AD8073JR各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号AD8073JR的概述

芯片AD8073JR的概述 AD8073JR是一款高性能的运算放大器，由Analog Devices公司研发。作为一款以速度和精度为重点的运算放大器，AD8073JR通常被应用于各种消费类电子、仪器设备和工业控制系统中。该芯片以其低噪声特性、宽带宽和高输入阻抗，受到广泛的关注和使用。 AD8073JR的设计着重于提供优秀的动态性能，适用于高频率信号处理。其核心优势在于能够提供高度准确性的信号放大，同时尽可能减少信号失真和噪声。这使得AD8073JR在需要高精度运算的应用中，表现得尤为突出。芯片AD8073JR的详细参数 AD8073JR的技术参数涉及多个维度，包括电气特性、频率响应、输入输出特性等。以下是AD8073JR的关键参数： 1. 工作电压范围：±5 V至±15 V，支持单电源操作。 2. 增益带宽积：约45 MHz，适合用于高频应用。 3. 失调电压：最大为2 mV，是处理...

产品型号AD8073JR的Datasheet PDF文件预览

Low Cost, Dual/Triple

Video Amplifiers

AD8072/AD8073

FEATURES

Very Low Cost

FUNCTIONAL BLOCK DIAGRAMS

8-Lead Plastic (N), SOIC (R), and ␮SOIC (RM) Packages

Good Video Specifications (R_L= 150 ⍀)

Gain Flatness of 0.1 dB to 10 MHz

0.05% Differential Gain Error

0.1؇ Differential Phase Error

Low Power

3.5 mA/Amplifier Supply Current

Operates on Single +5 V to +12 V Supply

High Speed

OUT1

–IN1

؉V

OUT2

–IN2

؉IN1

100 MHz, –3 dB Bandwidth (G = +2)

500 V/␮s Slew Rate

–V

؉IN2

AD8072

Fast Settling Time of 25 ns (0.1%)

Easy to Use

30 mA Output Current

14-Lead Plastic (N), and SOIC (R) Packages

Output Swing to 1.3 V of Rails on Single +5 V Supply

APPLICATIONS

Video Line Driver

Computer Video Plug-In Boards

RGB or S-Video Amplifier in Component Systems

OUT2

–IN2

12 ؉IN2

–V

PRODUCT DESCRIPTION

AD8073

AD8072

؉V

The AD8072 (dual) and AD8073 (triple) are low cost, current

feedback amplifiers intended for high volume, cost sensitive

applications. In addition to being low cost, these amplifiers

deliver solid video performance into a 150 Ω load while consuming

only 3.5 mA per amplifier of supply current. Furthermore, the

AD8073 is three amplifiers in a single 14-lead narrow-body

SOIC package. This makes it ideal for applications where small

size is essential. Each amplifier’s inputs and output are acces-

sible providing added gain setting flexibility.

؉IN1

؉IN3

–IN3

–IN1

OUT1

OUT3

NC = NO CONNECT

These devices provide 30 mA of output current per amplifier,

and are optimized for driving one back terminated video load

(150 Ω) each. These current feedback amplifiers feature gain

flatness of 0.1 dB to 10 MHz while offering differential gain and

phase error of 0.05% and 0.1°. This makes the AD8072 and

AD8073 ideal for business and consumer video electronics.

6.1

6.0

5.9

5.8

5.7

5.6

5.5

Both will operate from a single +5 V to +12 V power supply.

The outputs of each amplifier swing to within 1.3 volts of either

supply rail to accommodate video signals on a single +5 V supply.

= ؎5V

= 2V p-p

1 dB

DIV

= R = 1k⍀

The high bandwidth of 100 MHz, 500 V/µs of slew rate, along

with settling to 0.1% in 25 ns, make the AD8072 and AD8073

useful in many general purpose, high speed applications where a

single +5 V or dual power supplies up to 6 V are needed. The

AD8072 is available in 8-lead plastic DIP, SOIC, and µSOIC

packages while the AD8073 is available in 14-lead plastic DIP and

SOIC packages. Both operate over the commercial temperature

range of 0°C to +70°C. Additionally, the AD8072ARM oper-

ates over the industrial temperature range of –40°C to +85°C.

= 150⍀

= ؉2

0.1 dB

DIV

5.4

5.3

–1

500

0.1

100

FREQUENCY – MHz

Figure 1. Large Signal Frequency Response

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD8072/AD8073–SPECIFICATIONS

(@ T = +25؇C, V = ؎5 V, R = 150 ⍀, unless otherwise noted)

ELECTRICAL CHARACTERISTICS

AD8072/AD8073

Typ

Parameter

Conditions

Min

Max

Units

DYNAMIC PERFORMANCE

–3 dB Bandwidth, Small Signal

0.1 dB Bandwidth, Small Signal

Slew Rate

R_F= 1 kΩ

No Peaking, G = +2

V_O= 4 V Step

100

500

MHz

V/µs

Settling Time to 0.1%

V_O= 2 V Step

DISTORTION/NOISE PERFORMANCE R_F= 1 kΩ

Differential Gain

Differential Phase

Crosstalk

f = 3.58 MHz, G = +2

0.05

0.1

0.15

0.3

Degrees

nV/√Hz

pA/√Hz

f = 3.58 MHz, G = +2

f = 5 MHz

Input Voltage Noise

Input Current Noise

f = 10 kHz

f = 10 kHz ( I_IN)

DC PERFORMANCE

Transimpedance

Input Offset Voltage

0.3

MΩ

T_MINto T_MAX

Offset Drift

Input Bias Current ( )

Input Bias Current Drift ( )

µV/°C

µA

nA/°C

INPUT CHARACTERISTICS

–Input Resistance

+Input Resistance

Input Capacitance

Common-Mode Rejection Ratio

Input Common-Mode Voltage Range

120

1.6

Ω

MΩ

V_CM= –3.8 V to +3.8 V

3.8

OUTPUT CHARACTERISTICS

+Output Voltage Swing

–Output Voltage Swing

Output Current

2.25

3.3

R_L= 10 Ω

Short Circuit Current

POWER SUPPLY

Operating Range

Power Supply Rejection Ratio

Quiescent Current per Amplifier

2.5 to

3.5

V_S= 4 V to 6 V

OPERATING TEMPERATURE RANGE

+70

°C

Specifications subject to change without notice.

–2–

REV. A

AD8072/AD8073

(@ T_A= +25؇C, V_S= +5 V, R_L= 150 ⍀ to 2.5 V, unless otherwise noted)

ELECTRICAL CHARACTERISTICS

AD8072/AD8073

Typ

Parameter

Conditions

Min

Max

Units

DYNAMIC PERFORMANCE

–3 dB Bandwidth, Small Signal

0.1 dB Bandwidth, Small Signal

Slew Rate

R_F= 1 kΩ

No Peaking, G = +2

V_O= 2 V Step

7.8

100

350

MHz

V/µs

Settling Time to 0.1%

V_O= 2 V Step

DISTORTION/NOISE PERFORMANCE R_F= 1 kΩ

Differential Gain

Differential Phase

Crosstalk

Input Voltage Noise

Input Current Noise

f = 3.58 MHz, G = +2, R_Lto 1.5 V

0.1

Degrees

nV/√Hz

pA/√Hz

f = 3.58 MHz, G = +2, R_Lto 1.5 V

f = 5 MHz

f = 10 kHz

f = 10 kHz ( I_IN)

DC PERFORMANCE

Transimpedance

Input Offset Voltage

0.25

1.5

MΩ

T_MINto T_MAX

Offset Drift

Input Bias Current ( )

Input Bias Current Drift ( )

µV/°C

µA

nA/°C

INPUT CHARACTERISTICS

–Input Resistance

+Input Resistance

Input Capacitance

Common-Mode Rejection Ratio

Input Common-Mode Voltage Range

120

1.6

Ω

MΩ

V_CM= +1.2 V to +3.8 V

+1.2 to +3.8

OUTPUT CHARACTERISTICS

Output Voltage Swing

Output Current

+1.5 to +3.5 +1.3 to +3.7

R_L= 10 Ω

Short Circuit Current

POWER SUPPLY

Operating Range

Power Supply Rejection Ratio

2.5 to

V_S= +4 V to +6 V

Quiescent Current per Amplifier

4.5

OPERATING TEMPERATURE RANGE

+70

°C

–3–

REV. A

AD8072/AD8073

ABSOLUTE MAXIMUM RATINGS¹

MAXIMUM POWER DISSIPATION

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.2 V

The maximum power that can be safely dissipated by the

AD8072 and AD8073 is limited by the associated rise in junc-

tion temperature. The maximum safe junction temperature for

plastic encapsulated devices is determined by the glass transition

temperature of the plastic, approximately +150°C. Exceeding

this limit temporarily may cause a shift in parametric perfor-

mance due to a change in the stresses exerted on the die by the

package. Exceeding a junction temperature of +175°C for an

extended period can result in device failure.

Internal Power Dissipation²

AD8072 8-Lead Plastic (N) . . . . . . . . . . . . . . . . . 1.3 Watts

AD8072 8-Lead Small Outline (SO-8) . . . . . . . . . 0.9 Watts

AD8072 8-Lead µSOIC (RM) . . . . . . . . . . . . . . . 0.6 Watts

AD8073 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts

AD8073 14-Lead Small Outline (R) . . . . . . . . . . . 1.0 Watts

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . V_S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . 1.25 V

Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . .

Observe Power Derating Curves

While the AD8072 and AD8073 are internally short circuit pro-

tected, this may not be sufficient to guarantee that the maximum

junction temperature (+150°C) is not exceeded under all condi-

tions. To ensure proper operation, it is necessary to observe the

maximum power derating curves shown in Figures 2 and 3.

Storage Temperature Range

N, R, RM Packages . . . . . . . . . . . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . .+300°C

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²Specification is for device in free air:

2.0

8-LEAD MINI-DIP PACKAGE

= ؉150؇C

1.5

8-Lead Plastic Package: θ_JA= 90°C/W

8-LEAD SOIC PACKAGE

8-Lead SOIC Package: θ_JA= 140°C/W

1.0

0.5

8-Lead µSOIC Package: θ_JA= 214°C/W

14-Lead Plastic Package: θ_JA= 75°C/W

14-Lead SOIC Package: θ_JA= 120°C/W

␮SOIC

ORDERING GUIDE

Temperature

Range

Package

Description

Package

Option

Model

–50 –40 –30 –20 –10

10 20 30 40 50 60 70 80 90

AMBIENT TEMPERATURE – ؇C

AD8072ARM

–40°C to +85°C 8-Lead µSOIC

RM-8

AD8072ARM-REEL –40°C to +85°C 13" Reel 8-Lead µSOIC RM-8

AD8072ARM-REEL7 –40°C to +85°C 7" Reel 8-Lead µSOIC RM-8

Figure 2. AD8072 Maximum Power Dissipation vs.

Temperature

AD8072JN

0°C to +70°C

8-Lead Plastic DIP

8-Lead SOIC

13" Reel 8-Lead SOIC SO-8

7" Reel 8-Lead SOIC

14-Lead Plastic DIP

14-Lead Narrow SOIC R-14

13" Reel 14-Lead SOIC R-14

7" Reel 14-Lead SOIC R-14

N-8

AD8072JR

SO-8

2.5

AD8072JR-REEL

AD8072JR-REEL7

AD8073JN

AD8073JR

AD8073JR-REEL

= ؉150؇C

SO-8

N-14

2.0

14-LEAD DIP PACKAGE

AD8073JR-REEL7

1.5

1.0

0.5

14-LEAD SOIC

–50 –40 –30 –20 –10

10 20 30 40 50 60 70 80 90

AMBIENT TEMPERATURE – ؇C

Figure 3. AD8073 Maximum Power Dissipation vs.

Temperature

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD8072 and AD8073 feature proprietary ESD protection circuitry, permanent

damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. A

AD8072/AD8073

6.1

6.0

5.9

5.8

5.7

5.6

5.5

0؇C, 25؇C

= ؎5V

70؇C

= 1k⍀

= ؉5V

= 1k⍀

= 150⍀ TO 2.5V

= ؉2

= 150⍀

= ؉2

= 100mV p-p

0؇C

= 100mV p-p

70؇C

5.4

5.3

25؇C

0.1

1.0

FREQUENCY – MHz

100

1000

0.1

1.0

FREQUENCY – MHz

100

500

Figure 7. 0.1 dB Flatness vs. Frequency Over Tempera-

ture; V_S= 5 V

Figure 4. Frequency Response Over Temperature; V_S=+5V

MIN = 0.00

MAX = 0.09

p-p/MAX = 0.09

0.00 0.03 0.07 0.08 0.08 0.08 0.09 0.08 0.08 0.07 0.06

0.12

0.10

0.08

0.06

0.04

0.02

0.00

–0.02

= ؉5V, R = 1k⍀, R = 150⍀ TO 1.5V, A = ؉2

MIN = 0.00

MAX = 0.10

p-p = 0.10

0.00 0.05 0.09 0.10 0.09 0.08 0.06 0.06 0.05 0.04 0.02

= ؎5V

= 1k⍀

= 150⍀

= ؉2

= 100mV p-p

0؇C

0.12

0.10

0.08

0.06

0.04

0.02

0.00

–0.02

= ؉5V, R = 1k⍀, R = 150⍀ TO 1.5V, A = ؉2

70؇C

25؇C

0.1

6TH

1ST

4TH

5TH

7TH

8TH

9TH 10TH 11TH

1.0

FREQUENCY – MHz

100

1000

MODULATING RAMP LEVEL – IRE

Figure 8. Differential Gain and Phase, V_S= +5 V

Figure 5. Frequency Response Over Temperature; V_S= 5 V

MIN = –0.03

MAX = 0.00

p-p/MAX = 0.03

6.1

6.0

5.9

5.8

0.00 0.00 0.00 –0.00 0.00 –0.01 –0.01 –0.02 –0.03 –0.03 –0.03

0.00

–0.01

–0.02

= ؎5V,

= 1k⍀

= 150⍀

= ؉2

–0.03

5.7

5.6

5.5

= ؉5V

= 1k⍀

= 150⍀ TO 2.5V

= ؉2

= 100mV p-p

MIN = –0.10

MAX = 0.00

p-p = 0.10

0.00 0.00 –0.00 –0.02 –0.03 –0.05 –0.07 –0.08 –0.10 –0.10 –0.10

0.02

0.00

0؇C, 25؇C

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

= ؎5V,

= 1k⍀

= 150⍀

= ؉2

70؇C

5.4

5.3

6TH

1ST

4TH

5TH

7TH

8TH

9TH 10TH 11TH

0.1

1.0

100

500

MODULATING RAMP LEVEL – IRE

FREQUENCY – MHz

Figure 9. Differential Gain and Phase, V_S= 5 V

Figure 6. 0.1 dB Flatness vs. Frequency Over Tempera-

ture; V_S= +5 V

–5–

REV. A

AD8072/AD8073

100k

10k

AMP 2 OUTPUT

–10

–20

SOIC PACKAGE

DRIVE AMP 2

RECEIVE AMPS 1, 3 AD8073

RECEIVE AMP 1 AD8072

OHMS (⍀)

–20

–30

–40

–50

–60

–40

–60

= ؉5V, ؎5V

DEGREES

= 1k⍀, R = 150⍀

= ؉2

–80

= 1V p-p

–100

–120

–140

–160

–180

–70

–80

100

–90

0.1

10k

100k

10M

100M

0.1

1.0

FREQUENCY – MHz

100

500

FREQUENCY – Hz

Figure 10. Crosstalk vs. Frequency

Figure 13. Open-Loop Transimpedance vs. Frequency

–40

؉3

؉2

= ؎5V

= 1k⍀

= 150⍀

= ؉2

–50

–60

–70

–80

= ؉1

؉1

= 2V p-p

OUT

3RD

HARMONIC

–1

–2

–3

= ؎5V

= 1k⍀

= 150⍀

= ؉2

= ؉10

2ND

HARMONIC

= 200mV p-p

OUT

–4

–5

–6

–90

= ؉5

–100

0.1

FREQUENCY – MHz

100

FREQUENCY – MHz

Figure 11. Distortion vs. Frequency; V_S= 5 V

Figure 14. Normalized Frequency Response; V_S= 5 V

–40

6.1

6.0

5.9

5.8

5.7

5.6

5.5

= ؉5V

= 1k⍀

= 150⍀ TO 2.5V

= ؉2

= 2V p-p

–50

–60

–70

–80

3RD

HARMONIC

OUT

= ؉5V

1 dB

DIV

= 2V p-p

2ND

= R = 1k⍀

HARMONIC

0.1 dB

DIV

= 150⍀ TO 2.5V

= ؉2

–90

5.4

5.3

–100

–1

500

0.1

100

FREQUENCY – MHz

Figure 15. Large Signal Frequency Response

Figure 12. Distortion vs. Frequency; V_S= +5 V

–6–

REV. A

AD8072/AD8073

100

= ؎5V

= 1k⍀

= ؉2

100

0.1

100

10k

100k

100

500

FREQUENCY – Hz

FREQUENCY – MHz

Figure 16. Output Resistance vs. Frequency; V_S= 5 V

Figure 18. Noise vs. Frequency; V_S= 5 V

؉10

= ؎5V

= 1k⍀

= 150⍀

= ؉2

–10

–20

–30

–40

–50

–PSRR

100mV p-p ON TOP

OF V

؉PSRR

–60

–70

100

10k

100k

0.1

100

500

0.02

FREQUENCY – Hz

FREQUENCY – MHz

Figure 17. Noise vs. Frequency; V_S= 5 V

Figure 19. PSRR vs. Frequency

–5

1k⍀

V_IN

2V p-p

–10

V_OUT

150⍀

–15

154⍀

60.4⍀

154⍀

–20

–25

–30

–35

–40

–45

–50

–55

0.1

100

500

0.02

FREQUENCY – MHz

Figure 20. CMRR vs. Frequency; V_S= 5 V

–7–

REV. A

AD8072/AD8073

1k⍀

OUT

150⍀

؉V

50⍀

0.1␮F

0.001␮F

10␮F

–V

Figure 21. Test Circuit; Gain = +2

20ns

250mV

10ns

Figure 22. 2 V Step Response; G = +2, V_S= 5 V

Figure 25. 2 V Step Response; G = +2, V_S= 2.5 V

50mV

20ns

Figure 23. 200 mV Step Response; G = +2, V_S= 5 V

Figure 26. 200 mV Step Response; G = +2, V_S= 2.5 V

250mV

20ns

Figure 24. Sine Response; G = +2, V_S= 5 V

Figure 27. Sine Response; G = +2, V_S= 2.5 V

Note: V_S= 2.5 V operation is identical to V_S= +5 V single supply operation.

–8–

REV. A

AD8072/AD8073

APPLICATIONS

Capacitive Load Drive

Overdrive Recovery

When an op amp output drives a capacitive load, extra phase

shift due to the pole formed by the op amp’s output impedance

and the capacitor can cause peaking or even oscillation. The top

trace of Figure 30, R_S= 0 Ω, shows the output of one of the am-

plifiers of the AD8072/AD8073 when driving a 50 pF capacitor

as shown in the schematic of Figure 31.

Overdrive of an amplifier occurs when the output and/or input

range are exceeded. The amplifier must recover from this overdrive

condition and resume normal operation. As shown in Figure 28,

the AD8072 and AD8073 recover within 75 ns from positive

overdrive and 30 ns from negative overdrive.

The amount of peaking can be significantly reduced by adding

a resistor in series with the capacitor. The lower trace of Fig-

ure 30 shows the same capacitor being driven with a 25 Ω resis-

tor in series with it. In general, the resistor value will have to be

experimentally determined, but from 10 Ω to 50 Ω is a practical

range of values to experiment with for capacitive loads of up to a

few hundred pF.

OUT

= 0Ω

= 25Ω

25ns

Figure 28. Overload Recovery; V_S= 5 V, V_IN= 8 V p-p,

R_F= 1 kΩ, R_L= 150 Ω, G = +2

Bandwidth vs. Feedback Resistor Value

The closed-loop frequency response of a current feedback am-

plifier is a function of the feedback resistor. A smaller feedback

resistor will produce a wider bandwidth response. However, if

the feedback resistance becomes too small, the gain flatness can

be affected. As a practical consideration, the minimum value of

feedback resistance for the AD8072/AD8073 was found to be

649 Ω. For resistances below this value, the gain flatness will be

affected and more significant lot to lot variations in device per-

formance will be noticed. Figure 29 shows a plot of the frequency

response of an AD8072/AD8073 at a gain of two with both feed-

back and gain resistors equal to 649 Ω.

50mV

20ns

Figure 30. Capacitive Low Drive

1k⍀

= 100mV p-p

50pF

1k⍀

50⍀

On the other hand, the bandwidth of a current feedback ampli-

fier can be decreased by increasing the feedback resistance. This

can sometimes be useful where it is desired to reduce the noise

bandwidth of a system. As a practical matter, the maximum

value of feedback resistor was found to be 2 kΩ. Figure 29

shows the frequency response of an AD8072/AD8073 at a gain

of two with both feedback and gain resistors equal to 2 kΩ.

Figure 31. Capacitive Load Drive Circuit

6.1

6.0

5.9

5.8

5.7

= 649⍀

0.1 dB

DIV

= ؎5V

= ؉2

5.6

5.5

5.4

1 dB

DIV

= 150⍀

= 0.2V p-p

= 2k⍀

0.1

FREQUENCY – MHz

100

500

Figure 29. Frequency Response vs. R_F

–9–

REV. A

AD8072/AD8073

Crosstalk

Layout Considerations

Crosstalk between internal amplifiers may vary depending on

which amplifier is being driven and how many amplifiers are

being driven. This variation typically stems from pin location on

the package and the internal layout of the IC itself. Table I

illustrates the typical crosstalk results for a combination of

conditions.

The specified high speed performance of the AD8072 and

AD8073 require careful attention to board layout and compo-

nent selection. Proper RF design techniques and low parasitic

component selection are mandatory.

The PCB should have a ground plane covering all unused portions

of the component side of the board to provide a low impedance

ground path. The ground plane should be removed from the

area near the input pins to reduce stray capacitance.

Table I. AD8073JR Crosstalk Table (dB)

Chip capacitors should be used for supply bypassing. One end

of the capacitor should be connected to the ground plane and

the other within 1/8 inches of each power pin. An additional

large (4.7 µF–10 µF) tantalum electrolytic capacitor should be

connected in parallel, but not necessarily as close to the supply

pins, to provide current for fast large-signal changes at the

device’s output.

Receive Amplifier

AD8073JR

–60

–56

–60

–54

–53

–60

Drive

Amplifier

–60

–55

All Hostile

–54

The feedback resistor should be located close to the inverting

input pin in order to keep the stray capacitance at this node to a

minimum. Capacitance variations of less than 1 pF at the invert-

ing input will affect high speed performance.

CONDITIONS

V_S= 5 V

R_F= 1 kΩ, R_L= 150 Ω

Stripline design techniques should be used for long signal traces

(greater than about 1 inch). These should be designed with a

characteristic impedance of 50 Ω or 75 Ω and be properly termi-

nated at each end.

A_V= +2

_OUT= 2 V p-p on Drive Amplifier

–10–

REV. A

AD8072/AD8073

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP

(N-8)

14-Lead Plastic DIP

(N-14)

0.430 (10.92)

0.348 (8.84)

0.795 (20.19)

0.725 (18.42)

0.280 (7.11)

0.240 (6.10)

0.280 (7.11)

0.240 (6.10)

0.325 (8.25)

0.300 (7.62)

0.325 (8.25)

0.300 (7.62)

0.195 (4.95)

0.115 (2.93)

0.060 (1.52)

0.015 (0.38)

PIN 1

0.060 (1.52)

0.015 (0.38)

PIN 1

0.210 (5.33)

MAX

0.195 (4.95)

0.115 (2.93)

0.210 (5.33)

MAX

0.130

(3.30)

MIN

0.130

(3.30)

MIN

0.160 (4.06)

0.115 (2.93)

0.160 (4.06)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

0.015 (0.381)

0.008 (0.204)

SEATING

PLANE

0.022 (0.558)

0.014 (0.356)

0.100 0.070 (1.77)

SEATING

PLANE

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

(2.54)

BSC

0.045 (1.15)

8-Lead Plastic SOIC

(SO-8)

14-Lead SOIC

(R-14)

0.1968 (5.00)

0.1890 (4.80)

0.3444 (8.75)

0.3367 (8.55)

0.1574 (4.00)

0.1497 (3.80)

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.0688 (1.75)

0.0532 (1.35)

0.0688 (1.75)

0.0532 (1.35)

PIN 1

0.0196 (0.50)

0.0099 (0.25)

0.0196 (0.50)

0.0099 (0.25)

x 45°

0.0098 (0.25)

0.0040 (0.10)

0.0098 (0.25)

0.0040 (0.10)

8°

0°

8°

0°

0.0500

(1.27)

BSC

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0192 (0.49)

0.0138 (0.35)

SEATING

PLANE

SEATING

PLANE

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

0.0500 (1.27)

0.0160 (0.41)

0.0099 (0.25)

0.0075 (0.19)

8-Lead ␮SOIC

(RM-8)

0.122 (3.10)

0.114 (2.90)

0.122 (3.10)

0.114 (2.90)

0.199 (5.05)

0.187 (4.75)

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.120 (3.05)

0.112 (2.84)

0.043 (1.09)

0.037 (0.94)

0.006 (0.15)

0.002 (0.05)

33؇

0.018 (0.46)

0.008 (0.20)

27؇

0.028 (0.71)

0.016 (0.41)

0.011 (0.28)

0.003 (0.08)

SEATING

PLANE

–11–

REV. A

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AD8073JR产品参数

型号:	AD8073JR
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	SOIC
包装说明：	SOIC-14
针数：	14
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
风险等级：	5.41
其他特性：	IT CAN ALSO OPERATE WITH 5V TO 12V SINGLE SUPPLY
标称带宽：	100000 kHz
商用集成电路类型：	VIDEO AMPLIFIER
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e0
长度：	8.65 mm
湿度敏感等级：	1
信道数量：	3
功能数量：	1
端子数量：	14
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240
认证状态：	Not Qualified
座面最大高度：	1.75 mm
最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2.5 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	3.9 mm
Base Number Matches：	1

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