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产品型号AD8131ARM的概述

芯片AD8131ARM的概述 AD8131ARM是一款由美国Analog Devices（ADI）公司生产的高性能运算放大器。该芯片以其较高的带宽、优秀的线性度和良好的电流驱动能力在许多高频和精密的电子应用中得到了广泛的应用。AD8131ARM常用于视频信号处理、仪器仪表、数据采集系统以及需要高增益带宽的放大应用。 AD8131ARM的设计极为注重低失真，可以在较高的信号频率下提供稳定、线性的运算，从而非常适合于处理高频信号。其内部结构经过优化，以减少增益偏移和温度漂移，进一步提高了其在复杂应用中的可靠性和稳定性。芯片AD8131ARM的详细参数 AD8131ARM的主要参数特性如下： 1. 增益带宽积（GBP）：AD8131的增益带宽积为 1.5 GHz。这意味着在信号传输中能够提供较高增益的同时保持较宽频率范围的使用。 2. 输出驱动能力：AD8131具有较强的负载驱动能力，可驱...

产品型号AD8131ARM的Datasheet PDF文件预览

Low-Cost, High-Speed

Differential Driver

AD8131

FUNCTIONAL BLOCK DIAGRAM

FEATURES

High Speed

400 MHz –3 dB Full Power Bandwidth

2000 V/␮s Slew Rate

Fixed Gain of 2 with No External Components

Internal Common-Mode Feedback to Improve Gain

and Phase Balance

–D

750⍀

OCM

V+

V–

1.5k⍀

–60 dB @10 MHz

+OUT

–OUT

Separate Input to Set the Common-Mode Output

Voltage

AD8131

NC = NO CONNECT

Low Distortion

68 dB SFDR @ 5 MHz 200 ⍀ Load

Low Power 7.5 mA @ 3 V

Power Supply Range +2.7 V to ؎5 V

–20

–30

–40

–50

–60

–70

–80

⌬V

,dm = 2V p-p

OUT

APPLICATIONS

Video Line Driver

Digital Line Driver

Low Power Differential ADC Driver

Differential In/Out Level Shifting

Single-Ended Input to Differential Output Driver

,cm/⌬V

, dm

OUT

= +5V

= ؎5V

100

1000

FREQUENCY – MHz

Figure 1. Output Balance Error vs. Frequency

GENERAL DESCRIPTION

The AD8131 is a differential or single-ended input to differen-

tial output driver requiring no external components for a ﬁxed

gain of 2. The AD8131 is a major advancement over op amps

for driving signals over long lines or for driving differential input

ADCs. The AD8131 has a unique internal feedback feature that

provides output gain and phase matching that are balanced to

–60 dB at 10 MHz, reducing radiated EMI and suppressing

harmonics. Manufactured on ADI’s next generation XFCB

bipolar process, the AD8131 has a –3 dB bandwidth of 400 MHz

and delivers a differential signal with very low harmonic distortion.

The AD8131 can replace transformers in a variety of applica-

tions preserving low frequency and dc information. The AD8131

does not have the susceptibility to magnetic interference and

hysteresis of transformers, while being smaller in size, easier

to work with, and has the high reliability associated with ICs.

The AD8131’s differential output also helps balance the input

for differential ADCs, optimizing the distortion performance of

the ADCs. The common-mode level of the differential output

is adjustable by a voltage on the V_OCMpin, easily level-shifting

the input signals for driving single supply ADCs with dual supply

signals. Fast overload recovery preserves sampling accuracy.

The AD8131 is a differential driver for the transmission of

high-speed signals over low-cost twisted pair or coax cables.

The AD8131 can be used for either analog or digital video

signals or for other high-speed data transmission. The AD8131

driver is capable of driving either Cat3 or Cat5 twisted pair or coax

with minimal line attenuation. The AD8131 has considerable

cost and performance improvements over discrete line driver

solutions.

The AD8131 will be available in both SOIC and µSOIC packages

for operation over –40؇C to +85؇C.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(@ 25؇C, V_S= ؎5 V, V_OCM= 0, G = 2, R_L,dm= 200 ⍀, unless otherwise noted. Refer to

Figures 2 and 37 for test setup and label descriptions. All speciﬁcations refer to single-ended input and differential outputs unless noted.)

AD8131–SPECIFICATIONS

Parameter

Conditions

Min

Typ

Max

Unit

؎D_INto ؎OUT Speciﬁcations

DYNAMIC PERFORMANCE

–3 dB Large Signal Bandwidth

–3 dB Small Signal Bandwidth

Bandwidth for 0.1 dB Flatness

Slew Rate

V_OUT= 2 V p-p

400

320

2000

MHz

V/µs

_OUT= 0.2 V p-p

V_OUT= 2 V p-p, 10% to 90%

0.1%, V_OUT= 2 V p-p

V_IN= 5 V to 0 V Step

Settling Time

Overdrive Recovery Time

NOISE/HARMONIC PERFORMANCE

Second Harmonic

V_OUT= 2 V p-p, 5 MHz, R_L,dm= 200 Ω

–68

–63

–95

–79

–94

–70

–101

–77

–54

dBc

_OUT= 2 V p-p, 20 MHz, R_L,dm= 200 Ω

_OUT= 2 V p-p, 5 MHz, R_L,dm= 800 Ω

_OUT= 2 V p-p, 20 MHz, R_L,dm= 800 Ω

_OUT= 2 V p-p, 5 MHz, R_L,dm= 200 Ω

Third Harmonic

V_OUT= 2 V p-p, 20 MHz, R_L,dm= 200 Ω

_OUT= 2 V p-p, 5 MHz, R_L,dm= 800 Ω

_OUT= 2 V p-p, 20 MHz, R_L,dm= 800 Ω

IMD

IP3

20 MHz, R_L,dm= 800 Ω

f = 20 MHz

NTSC, R_L,dm= 150 Ω

dBc

dBm

nV/√Hz

Voltage Noise (RTO)

Differential Gain Error

Differential Phase Error

0.01

0.06

Degrees

INPUT CHARACTERISTICS

Offset Voltage

V_OS,dm= V_OUT,dm; V_DIN+= V_DIN–= V_OCM= 0 V

±2

±8

±4

±10

1.125

1.5

±7

µV/°C

kΩ

_MINto T_MAXVariation

_OCM= Float

_MINto T_MAXVariation

Input Resistance

Single-Ended Input

Differential Input

kΩ

Input Capacitance

Input Common-Mode Voltage

CMRR

–7.0 to +5.0

–70

∆V_OUT,dm/∆V_IN,cm; ∆V_IN,cm= ±0.5 V

OUTPUT CHARACTERISTICS

Output Voltage Swing

Linear Output Current

Gain

Maximum ∆V_OUT; Single-Ended Output

–3.6 to +3.6

–70

V/V

∆V_OUT,dm/∆V_IN,dm; ∆V_IN,dm= ± 0.5 V

∆V_OUT,cm/∆V_OUT,dm; ∆V_OUT,dm= 1 V

1.97

2.03

Output Balance Error

V_OCMto ؎OUT Speciﬁcations

DYNAMIC PERFORMANCE

–3 dB Bandwidth

Slew Rate

∆V_OCM= 600 mV

V_OCM= –1 V to +1 V

210

500

MHz

V/µs

DC PERFORMANCE

Input Voltage Range

Input Resistance

±3.6

120

±1.5

±2.5

0.5

kΩ

µA

V/V

Input Offset Voltage

_OS,cm= V_OUT,cm; V_DIN+= V_DIN–= V_OCM= 0 V

_OCM= Float

±7

Input Bias Current

V_OCMCMRR

Gain

[∆V_OUT,dm/∆V_OCM]; ∆V_OCM= ± 0.5 V

∆V_OUT,cm/∆V_OCM; ∆V_OCM= ±1 V

–60

0.988

1.012

POWER SUPPLY

Operating Range

Quiescent Current

±1.4

10.5

±5.5

12.5

_DIN+= V_DIN–= V_OCM= 0 V

_MINto T_MAXVariation

11.5

–70

µA/°C

Power Supply Rejection Ratio

∆V_OUT,dm/∆V_S; ∆V_S= ±1 V

–56

OPERATING TEMPERATURE RANGE

Speciﬁcations subject to change without notice.

–40

+85

°C

REV. 0

–2–

AD8131

(@ 25؇C, V_S= 5 V, V_OCM= 2.5 V, G = 2, R_L,dm= 200 ⍀, unless otherwise noted. Refer to Figures 2 and 37

for test setup and label descriptions. All speciﬁcations refer to single-ended input and differential outputs unless noted.)

SPECIFICATIONS

Parameter

Conditions

Min

Typ

Max

Unit

؎D_INto ؎OUT Speciﬁcations

DYNAMIC PERFORMANCE

–3 dB Large Signal Bandwidth

–3 dB Small Signal Bandwidth

Bandwidth for 0.1 dB Flatness

Slew Rate

V_OUT= 2 V p-p

V_OUT= 0.2 V p-p

385

285

1600

MHz

V/µs

_OUT= 2 V p-p, 10% to 90%

Settling Time

Overdrive Recovery Time

0.1%, V_OUT= 2 V p-p

V_IN= 5 V to 0 V Step

NOISE/HARMONIC PERFORMANCE

Second Harmonic

V_OUT= 2 V p-p, 5 MHz, R_L,dm= 200 Ω

V_OUT= 2 V p-p, 20 MHz, R_L,dm= 200 Ω

–67

–56

–94

–77

–74

–67

–95

–74

–51

dBc

_OUT= 2 V p-p, 5 MHz, R_L,dm= 800 Ω

V_OUT= 2 V p-p, 20 MHz, R_L,dm= 800 Ω

V_OUT= 2 V p-p, 5 MHz, R_L,dm= 200 Ω

V_OUT= 2 V p-p, 20 MHz, R_L,dm= 200 Ω

V_OUT= 2 V p-p, 5 MHz, R_L,dm= 800 Ω

Third Harmonic

_OUT= 2 V p-p, 20 MHz, R_L,dm= 800 Ω

IMD

IP3

20 MHz, R_L,dm= 800 Ω

f = 20 MHz

NTSC, R_L,dm= 150 Ω

dBc

dBm

nV/√Hz

Voltage Noise (RTO)

Differential Gain Error

Differential Phase Error

0.02

0.08

Degrees

INPUT CHARACTERISTICS

Offset Voltage

V_OS,dm= V_OUT,dm; V_DIN+= V_DIN–= V_OCM= 2.5 V

T_MINto T_MAXVariation

V_OCM= Float

±3

±8

±4

±10

1.125

1.5

±7

µV/°C

kΩ

_MINto T_MAXVariation

Input Resistance

Single-Ended Input

Differential Input

kΩ

Input Capacitance

Input Common-Mode Voltage

CMRR

–1.0 to +4.0

–70

∆V_OUT,dm/∆V_IN,cm; ∆V_IN,cm= ±0.5 V

OUTPUT CHARACTERISTICS

Output Voltage Swing

Linear Output Current

Gain

Maximum ∆V_OUT; Single-Ended Output

1.0 to 3.7

V/V

∆V_OUT,dm/∆V_IN,dm; ∆V_IN,dm= ± 0.5 V

∆V_OUT,cm/∆V_OUT,dm; ∆V_OUT,dm= 1 V

1.96

2.04

Output Balance Error

–62

V_OCMto ؎OUT Speciﬁcations

DYNAMIC PERFORMANCE

–3 dB Bandwidth

Slew Rate

∆V_OCM= 600 mV

V_OCM= 1.5 V to 3.5 V

200

450

MHz

V/µs

DC PERFORMANCE

Input Voltage Range

Input Resistance

1.0 to 3.7

±5

±10

0.5

–60

kΩ

µA

V/V

Input Offset Voltage

V_OS,cm= V_OUT,cm; V_DIN+= V_DIN–= V_OCM= 2.5 V

V_OCM= Float

±12

Input Bias Current

V_OCMCMRR

Gain

[∆V_OUT,dm/∆V_OCM]; ∆V_OCM= 2.5 V ± 0.5 V

∆V_OUT,cm/∆V_OCM; ∆V_OCM= 2.5 V ± 1 V

0.985

1.015

POWER SUPPLY

Operating Range

Quiescent Current

2.7

9.25

11.25

V_DIN+= V_DIN= V_OCM= 2.5 V

T_MINto T_MAXVariation

∆V_OUT,dm/∆V_S; ∆V_S= ±0.5 V

10.25

–70

µA/°C

Power Supply Rejection Ratio

–56

OPERATING TEMPERATURE RANGE

–40

+85

°C

Speciﬁcations subject to change without notice.

REV. 0

–3–

AD8131

ABSOLUTE MAXIMUM RATINGS¹

PIN FUNCTION DESCRIPTIONS

Pin No. Name Function

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5.5 V

V_OCM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V_S

Internal Power Dissipation². . . . . . . . . . . . . . . . . . . . 250 mW

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C

–D_IN

V_OCM

Negative Input.

Voltage applied to this pin sets the common-

mode output voltage with a ratio of 1:1. For

example, 1 V dc on V_OCMwill set the dc bias

level on +OUT and –OUT to 1 V.

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only, functional operation of the

device at these or any other conditions above listed in the operational section of this

speciﬁcation is not implied. Exposure to Absolute Maximum Ratings for any

extended periods may affect device reliability.

V+

Positive Supply Voltage.

+OUT Positive Output. Note: the voltage at –D_INis

inverted at +OUT.

²Thermal resistance measured on SEMI standard 4-layer board.

8-Lead SOIC θ_JA= 121°C/W

–OUT Negative Output. Note: the voltage at +D_IN

is inverted at –OUT.

8-Lead µSOIC θ_JA= 142°C/W

V–

+D_IN

Negative Supply Voltage.

No Connect.

Positive Input

PIN CONFIGURATION

–D

750⍀

OCM

V+

V–

1.5k⍀

+OUT

–OUT

AD8131

NC = NO CONNECT

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD8131AR

–40°C to +85°C

8-Lead SOIC

SO-8

AD8131AR-REEL

AD8131AR-REEL7

AD8131ARM

–40°C to +85°C

8-Lead µSOIC

RM-8

AD8131ARM-REEL

AD8131ARM-REEL7

AD8131-EVAL

Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD8131 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–4–

AD8131

= 200mV p-p

= ؎5V

= 200mV p-p

OUT

1500⍀

␮SO

= ؎5V

750⍀

49.9⍀

24.9⍀

,dm = 200⍀

AD8131

= 5V

SOIC

100

1500⍀

–3

1000

100

1000

FREQUENCY – MHz

Figure 2. Basic Test Circuit

Figure 3. Small Signal Frequency

Response

Figure 4. Small Signal Frequency

Response

= 2V p-p

= ؎5V

OUT

= 2V p-p

OUT

1500⍀

AD8131

1500⍀

2:1 TRANSFORMER

␮SO

= ؎5V

750⍀

300⍀

HPF

LPF

= 50⍀

49.9⍀

24.9⍀

SOIC

= 5V

–3

100

1000

100

1000

FREQUENCY – MHz

Figure 5. Large Signal Frequency

Response

Figure 6. Large Signal Frequency

Response

Figure 7. Harmonic Distortion Test

Circuit (R_L,dm= 800 Ω)

–50

–55

–40

= ؎5V

R ,dm = 800⍀

HD3 (V = ؎5V)

R ,dm = 800⍀

,dm = 1V p-p

,dm = 2V p-p

OUT

–50

–60

–65

–75

–85

–60

–70

–80

HD3 (V = 3V)

HD3 (F = 20MHz)

HD3 (V = 5V)

–70

HD3 (V = 5V)

HD2 (F = 20MHz)

–80

HD2 (V = 3V)

HD2 (V = ؎5V)

–95

–105

–115

–90

–100

–110

–90

HD2 (V = 5V)

–100

–110

HD3 (F = 5MHz)

HD2 (F = 5MHz)

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

FREQUENCY – MHz

Figure 10. Harmonic Distortion vs.

Differential Output Voltage

Figure 8. Harmonic Distortion vs.

Frequency

Figure 9. Harmonic Distortion vs.

Frequency

REV. 0

–5–

AD8131

–50

= ؎5V

= 3V

= 5V

HD3 (F = 5MHz)

,dm = 2V p-p

R ,dm = 800⍀

OUT

–60

–70

–60

–70

–60

–70

HD3 (F = 20MHz)

HD2 (F = 20MHz)

–80

–90

–80

–90

–80

–90

HD2 (F = 20MHz)

HD3 (F = 5MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz)

–100

HD2 (F = 5MHz)

HD3 (F = 5MHz)

–110

0.25

0.50

0.75

1.0

1.25

1.5

1.75

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

200 300 400 500 600 700 800 900 1000

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

– ⍀

LOAD

Figure 12. Harmonic Distortion vs.

Differential Output Voltage

Figure 11. Harmonic Distortion vs.

Differential Output Voltage

Figure 13. Harmonic Distortion vs.

R_LOAD

–50

= 3V

= 5V

= 50MHz

–10

–20

–30

–40

–50

,dm = 1V p-p

,dm = 2V p-p

HD3 (F = 20MHz)

OUT

= ؎5V

–60

–70

–60

–70

R ,dm = 800⍀

HD2 (F = 20MHz)

HD3 (F = 20MHz)

–80

–90

–80

–90

–60

–70

–80

–90

HD2 (F = 5MHz)

–100

HD3 (F = 5MHz)

–100

–110

49.5

–110

200 300 400 500 600 700 800 900 1000

FREQUENCY – MHz

50.5

– ⍀

LOAD

Figure 16. Intermodulation Distortion

Figure 15. Harmonic Distortion vs.

R_LOAD

Figure 14. Harmonic Distortion vs.

R_LOAD

R ,dm = 800⍀

= 5V

= ؎5V

,dm

OUT

= ؎5V

OUT+

OUT–

+DIN

= ؎5V

= 5V

40mV

5ns

60 70

FREQUENCY – MHz

Figure 17. Third Order Intercept vs.

Frequency

Figure 19. Small Signal Transient

Response

Figure 18. Large Signal Transient

Response

REV. 0

–6–

AD8131

= 1.5V p-p

= 5V

= 2V p-p

OUT

= 3V

V = ؎5V

2mV/DIV

,dm

OUT

= ؎5V

+DIN

300mV

400mV

5ns

4ns

1V/DIV

Figure 21. Large Signal Transient

Response

Figure 20. Large Signal Transient

Response

Figure 22. 0.1% Settling Time

= 5pF

⌬V

,dm

OUT

= 0pF

C = 20pF

⌬V

–10

–20

–30

–40

–50

–60

–70

–80

1500⍀

+PSRR

(V = ؎5V, +5V)

750⍀

24.9⍀

49.9⍀

150⍀

AD8131

750⍀

–PSRR

(V = ؎5V)

= ؎5V

24.9⍀

1500⍀

400mV

1.25ns

100

1000

FREQUENCY – MHz

Figure 25. PSRR vs. Frequency

Figure 23. Capacitor Load Drive Test

Circuit

Figure 24. Large Signal Transient

Response for Various Capacitor

Loads

–20

100

= ؎5V

,cm = 1V p-p

SINGLE-ENDED OUTPUT

–30

1500⍀

–40

–50

–60

750⍀

100⍀

⌬V

,dm/

OUT

,cm

OUT

⌬V ,cm

,dm

AD8131

OUT

24.9⍀

100⍀

= 5V

⌬V

,cm/⌬V ,cm

1500⍀

–70

–80

OUT

= ؎5V

0.1

100

1000

100

FREQUENCY – MHz

Figure 27. CMRR vs. Frequency

Figure 28. Single-Ended Z_OUTvs.

Frequency

Figure 26. CMRR Test Circuit

REV. 0

–7–

AD8131

–20

–30

⌬V

,dm = 2V p-p

OUT

,cm/⌬V

,dm

OUT

1500⍀

AD8131

1500⍀

= ؎5V

–40

–50

–60

750⍀

100⍀

49.9⍀

24.9⍀

= 5V

–70

–80

= +3V(V

= 0V)

OCM

= ؎5V

–1

100

1000

–50 –30 –10

FREQUENCY – MHz

TEMPERATURE – ؇C

Figure 29. Output Balance Error Test

Circuit

Figure 30. Output Balance Error vs.

Frequency

Figure 31. Output Offset Voltage vs.

Temperature

110

⌬V

,cm

= ؎5V

OUT

= ؎5V

⌬V

OCM

⌬V

= 600mV p-p

OCM

= ؎5V

–3

= 5V

= 3V

⌬V

= 2V p-p

OCM

–6

–9

100

1000

–50

–30 –10

0.1k

10k

100k

10M 100M

TEMPERATURE – ؇C

FREQUENCY – MHz

FREQUENCY – Hz

Figure 32. Quiescent Current vs.

Temperature

Figure 34. V_OCMGain Response

Figure 33. Voltage Noise vs.

Frequency

–20

⌬V

,dm

OCM

= ؎5V

OUT

⌬V

OCM

–30

–40

–50

–60

–70

⌬V

= 600mV p-p

,cm

OUT

⌬V

= 2V p-p

OCM

= ؎5V

–80

–90

= –1V TO +1V

OCM

400mV

5ns

100

1000

FREQUENCY – MHz

Figure 35. V_OCMCMRR vs. Frequency

Figure 36. V_OCMTransient Response

REV. 0

–8–

AD8131

OPERATIONAL DESCRIPTION

Deﬁnition of Terms

The AD8131 uses two feedback loops to separately control the

differential and common-mode output voltages. The differential

feedback, set by internal resistors, controls only the differential

output voltage. The common-mode feedback controls only the

common-mode output voltage. This architecture makes it easy

to arbitrarily set the output common-mode level. It is forced, by

internal common-mode feedback, to be equal to the voltage

applied to the V_OCMinput, without affecting the differential

output voltage.

+IN

–IN

–OUT

L,dm

AD8131

,dm

OUT

OCM

+OUT

–D

+OUT

The AD8131 architecture results in outputs that are very highly

balanced over a wide frequency range without requiring external

components or adjustments. The common-mode feedback loop

forces the signal component of the output common-mode voltage

to be zeroed. The result is nearly perfectly balanced differential

outputs, of identical amplitude and exactly 180 degrees apart

in phase.

Figure 37. Circuit Deﬁnitions

Differential voltage refers to the difference between two node

voltages. For example, the output differential voltage (or

equivalently output differential-mode voltage) is deﬁned as:

_OUT,dm= (V_+OUT– V_–OUT

)

_+OUTand V_–OUTrefer to the voltages at the +OUT and –OUT

Analyzing an Application Circuit

terminals with respect to a common reference.

The AD8131 uses high open-loop gain and negative feedback to

force its differential and common-mode output voltages in such

a way as to minimize the differential and common-mode error

voltages. The differential error voltage is deﬁned as the voltage

between the differential inputs labeled +IN and –IN in Figure

37. For most purposes, this voltage can be assumed to be zero.

Similarly, the difference between the actual output common-

mode voltage and the voltage applied to V_OCMcan also be

assumed to be zero. Starting from these two assumptions, any

application circuit can be analyzed.

Common-mode voltage refers to the average of two node volt-

ages. The output common-mode voltage is deﬁned as:

_OUT,cm= (V_+OUT+ V_–OUT)/2

Balance is a measure of how well differential signals are matched

in amplitude and exactly 180 degrees apart in phase. Balance

is most easily determined by placing a well-matched resistor

divider between the differential voltage nodes and comparing

the magnitude of the signal at the divider’s midpoint with the

magnitude of the differential signal. By this deﬁnition, output

balance is the magnitude of the output common-mode voltage

divided by the magnitude of the output differential-mode

voltage:

Closed-Loop Gain

The differential mode gain of the circuit in Figure 37 can be

determined to be described by the following equation:

V_{OUT ,dm}

V_{IN ,dm}

R_F

R_G

= 2

V_OUT,cm

Output Balance Error =

V_OUT,dm

where R_F= 1.5 kΩ and R_G= 750 Ω nominally.

THEORY OF OPERATION

Estimating the Output Noise Voltage

The AD8131 differs from conventional op amps in that it has

two outputs whose voltages move in opposite directions. Like

an op amp, it relies on high open-loop gain and negative feed-

back to force these outputs to the desired voltages. The AD8131

behaves much like a standard voltage feedback op amp and

makes it easy to perform single-ended-to-differential conversion,

common-mode level-shifting, and ampliﬁcation of differential

signals.

Similar to the case of a conventional op amp, the differential

output errors (noise and offset voltages) can be estimated by

multiplying the input referred terms, at +IN and –IN, by the

circuit noise gain. The noise gain is deﬁned as:

R_F

G_N= 1 +

= 3

R_G

The total output referred noise for the AD8131, including the

contributions of R_F, R_G, and op amp, is nominally 25 nV/√Hz

at 20 MHz.

Previous differential drivers, both discrete and integrated

designs, have been based on using two independent ampliﬁers,

and two independent feedback loops, one to control each of the

outputs. When these circuits are driven from a single-ended

source, the resulting outputs are typically not well balanced.

Achieving a balanced output has typically required exceptional

matching of the ampliﬁers and feedback networks.

Calculating an Application Circuit’s Input Impedance

The effective input impedance of a circuit such as that in Figure

37, at +D_INand –D_IN, will depend on whether the ampliﬁer is

being driven by a single-ended or differential signal source. For

balanced differential input signals, the input impedance (R_IN,_dm

between the inputs (+D_INand –D_IN) is simply:

)

DC common-mode level-shifting has also been difﬁcult with

previous differential drivers. Level-shifting has required the use

of a third ampliﬁer and feedback loop to control the output

common-mode level. Sometimes the third ampliﬁer has also

been used to attempt to correct an inherently unbalanced

circuit. Excellent performance over a wide frequency range has

proven difﬁcult with this approach.

_IN,dm= 2 × R_G= 1.5 kΩ

In the case of a single-ended input signal (for example if –D_INis

grounded and the input signal is applied to +D_IN), the input

impedance becomes:

REV. 0

–9–

AD8131

In this case, the input signal is provided by a signal generator

with an output impedance of 50 Ω. This is terminated with a

49.9 Ω resistor near +D_INof the AD8131. The effective parallel

resistance of the source and termination is 25 Ω. The 24.9 Ω

resistor from –D_INto ground matches the +D_INsource impedance

and minimizes any dc and gain errors.

R_G

R_F

R_{IN ,dm}

= 1.125 kΩ

1 −

2 × R_G+ R_F

(

)

If +D_INis driven by a low-impedance source over a short dis-

tance, such as the output of an op amp, then no termination

resistor is required at +D_IN. In this case, the –D_INcan be

directly tied to ground.

The circuit’s input impedance is effectively higher than it would

be for a conventional op amp connected as an inverter because

a fraction of the differential output voltage appears at the inputs

as a common-mode signal, partially bootstrapping the voltage

across the input resistor R_G.

+3 V Supply Differential A-to-D Driver

Many newer A-to-D converters can run from a single +3 V

supply, which can save signiﬁcant system power. In order to

increase the dynamic range at the analog input, they have differ-

ential inputs, which doubles the dynamic range with respect to a

single-ended input. An added beneﬁt of using a differential

input is that the distortion can be improved.

Input Common-Mode Voltage Range in Single Supply

Applications

The AD8131 is optimized for level-shifting “ground” referenced

input signals. For a single-ended input this would imply, for

example, that the voltage at –D_INin Figure 37 would be zero

volts when the ampliﬁer’s negative power supply voltage (at V–)

was also set to zero volts.

The low distortion and ability to run from a single +3 V supply

make the AD8131 suited as an A-to-D driver for some 10-bit,

single supply applications. Figure 39 shows a schematic for a

circuit for an AD8131 driving an AD9203, a 10-bit, 40 MSPS

A-to-D converter.

Setting the Output Common-Mode Voltage

The AD8131’s V_OCMpin is internally biased at a voltage

approximately equal to the midsupply point (average value of

the voltages on V+ and V–). Relying on this internal bias will

result in an output common-mode voltage that is within about

25 mV of the expected value.

The common mode of the AD8131 output is set at midsupply

by the voltage divider connected to V_OCM, and ac bypassed with

a 0.1 µF capacitor. This provides for maximum dynamic range

between the supplies at the output of the AD8131. The 110 Ω

resistors at the AD8131 output, along with the shunt capacitors

form a one pole, low-pass ﬁlter for lowering noise and antialiasing.

In cases where more accurate control of the output common-

mode level is required, it is recommended that an external

source, or resistor divider (made up of 10 kΩ resistors), be used.

Driving a Capacitive Load

Figure 40 shows an FFT plot that was taken from the combined

devices at an analog input frequency of 2.5 MHz and a 40 MSPS

sampling rate. The performance of the AD8131 compares very

favorably with a center-tapped transformer drive, which has

typically been the best way to drive this A-to-D converter. The

AD8131 has the advantage of maintaining dc performance,

which a transformer solution cannot provide.

A purely capacitive load can react with the pin and bondwire

inductance of the AD8131 resulting in high frequency ringing in

the pulse response. One way to minimize this effect is to place a

small resistor in series with the ampliﬁer’s outputs as shown in

Figure 23.

APPLICATIONS

Unity-Gain, Single-Ended-to-Differential Driver

If it is not necessary to offset the output common-mode volt-

age (via the V_OCMpin), then the AD8131 can make a simple

unity-gain single-ended-to-differential ampliﬁer that does not

require any external components. Figure 41 shows the schematic

for this circuit.

Twisted-Pair Line Driver

The AD8131 has on-chip resistors that provide for a gain-of-

two without any external parts. Several on-chip resistors are

trimmed to ensure that the gain is accurate, the common-mode

rejection is good, and the output is well balanced. This makes

the AD8131 very suitable as a single-ended-to-differential

twisted-pair line driver.

Referring to Figure 2, when –D_INis left floating, there is 100

percent feedback of +OUT to –IN via the internal feedback

resistor. This contrasts with the typical gain-of-two operation

where –D_INis grounded and one third of the +OUT is fed back

to –IN. The result is a closed-loop differential gain of one.

Figure 38 shows a circuit of an AD8131 driving a twisted-pair

line, like a Category 3 or Category 5 (Cat3 or Cat5), that are

already installed in many buildings for telephony and data com-

munications. The characteristic impedance of such transmission

lines is usually about 100 Ω. The outstanding balance of the

AD8131 output will minimize the common-mode signal and there-

fore the amount of EMI generated by driving the twisted pair.

Upon careful observation, it can be seen that only +D_INand

V_OCMare referenced to ground. It is the case that the ground

voltage at V_OCMis the reference for this circuit. In this unity

gain conﬁguration, if a dc voltage is applied to V_OCMto shift the

common-mode voltage, a differential dc voltage will be created

at the output, along with the common-mode voltage change.

Thus, this conﬁguration cannot be used when it is desired to

offset the common-mode voltage of the output with respect to

the input at +D_IN.

The two resistors in series with each output terminate the line at

the transmit end. Since the impedances of the outputs of the

AD8131 are very low, they can be thought of as a short circuit,

and the two terminating resistors form a 100 Ω termination at

the transmit end of the transmission line. The receive end is

directly terminated by a 100 Ω resistor across the line.

This back-termination of the transmission line divides the out-

put signal by two. The ﬁxed gain of two of the AD8131 will

create a net unity gain for the system from end to end.

REV. 0

–10–

AD8131

–10

–20

+5V

–30

–40

10␮F

0.1␮F

49.9⍀

–50

–60

–70

–80

–90

49.9⍀

100⍀

AD8131

24.9⍀

–100

–110

RECEIVER

49.9⍀

0.1␮F

–120

10␮F

2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0

–5V

FREQUENCY – MHz

Figure 38. Single-Ended-to-Differential 100 Ω Line Driver

Figure 40. FFT Plot for AD8131/AD9203

+5V

INPUT

10␮F

0.1␮F

10␮F

0.1␮F

110⍀

0.1␮F

DRVDD

AVDD

AINN

–OUT

+OUT

20pF

LPF

AD8131

49.9⍀

DIGITAL

OUTPUTS

AD9203

49.9⍀

OCM

0.1␮F

20pF

+3V

AINP

AVSS

24.9⍀

110⍀

DRVSS

10␮F

0.1␮F

10k⍀

–5V

Figure 41. Unity Gain, Single-Ended-to-Differential

Ampliﬁer

Figure 39. Test Circuit for AD8131 Driving an AD9203,

10 Bit, 40 Msps A-to-D Converter

REV. 0

–11–

AD8131

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead SOIC

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

BSC

45؇

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0040 (0.10)

8؇

0؇

0.0500 (1.27)

0.0160 (0.41)

0.0192 (0.49)

0.0138 (0.35)

0.0098 (0.25)

0.0075 (0.19)

SEATING

PLANE

8-Lead ␮SOIC

(RM-8)

0.122 (3.10)

0.114 (2.90)

0.122 (3.10)

0.114 (2.90)

0.199 (5.05)

0.187 (4.75)

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.120 (3.05)

0.112 (2.84)

0.043 (1.09)

0.037 (0.94)

0.006 (0.15)

0.002 (0.05)

33؇

27؇

0.018 (0.46)

0.008 (0.20)

0.028 (0.71)

0.016 (0.41)

0.011 (0.28)

0.003 (0.08)

SEATING

PLANE

–12–

REV. 0

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AD8131ARM产品参数

型号:	AD8131ARM
Brand Name：	Analog Devices Inc
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP8,.19
针数：	8
制造商包装代码：	RM-8
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	7.62
放大器类型：	OPERATIONAL AMPLIFIER
标称共模抑制比：	70 dB
最大输入失调电压：	7000 µV
JESD-30 代码：	S-PDSO-G8
JESD-609代码：	e0
长度：	3 mm
湿度敏感等级：	1
负供电电压上限：	-5.5 V
标称负供电电压 (Vsup)：	-5 V
功能数量：	1
端子数量：	8
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP8,.19
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240
电源：	5/+-5 V
认证状态：	Not Qualified
座面最大高度：	1.1 mm
标称压摆率：	2000 V/us
子类别：	Operational Amplifier
最大压摆率：	12.5 mA
供电电压上限：	5.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	AUTOMOTIVE
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	3 mm
Base Number Matches：	1

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