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Low Noise, Low Gain Drift, G = 2000

Instrumentation Amplifier

Data Sheet

AD8428

FEATURES

FUNCTIONAL BLOCK DIAGRAM

+V

–FIL

S

Fixed gain of 2000

Access to internal nodes provides flexibility

Low noise: 1.5 nV/√Hz input voltage noise

High accuracy dc performance

Gain drift: 5 ppm/°C

Offset drift: 0.3 μV/°C

Gain accuracy: 0.05%

–IN

6kΩ

120kΩ

3kΩ

30.15Ω

3kΩ

OUT

REF

6kΩ

120kΩ

CMRR: 140 dB min

+IN

Excellent ac specifications

Bandwidth: 3.5 MHz

AD8428

–V

S

Slew rate: 40 V/μs

+FIL

Power supply range: 4 V to 18 V

8-lead SOIC package

ESD protection: 5000 V (HBM)

Temperature range for specified performance:

−40°C to +85°C

Figure 1.

Table 1. Instrumentation Amplifiers by Category¹

General-

Purpose

Zero

Drift

Military

Grade

Low

Power

Low

Noise

AD8220

AD8221

AD8222

AD8224

AD8228

AD8295

AD8231

AD8290

AD8293

AD8553

AD8556

AD8557

AD620

AD621

AD524

AD526

AD624

AD627

AD623

AD8428

AD8429

Operational up to 125°C

APPLICATIONS

AD8235

AD8236

AD8426

AD8226

AD8227

AD8420

Sensor interface

Medical instrumentation

Patient monitoring

¹See www.analog.com for the latest instrumentation amplifiers.

The AD8428 is one of the fastest instrumentation amplifiers

available. The circuit architecture is designed for high bandwidth

at high gain. The AD8428 uses a current feedback topology for

the initial preamplifier gain stage of 200, followed by a difference

amplifier stage of 10. This architecture results in a 3.5 MHz

bandwidth at a gain of 2000 for an equivalent gain bandwidth

product of 7 GHz.

GENERAL DESCRIPTION

The AD8428 is an ultralow noise instrumentation amplifier

designed to accurately measure tiny, high speed signals. It

delivers industry-leading gain accuracy, noise, and bandwidth.

All gain setting resistors for the AD8428 are internal to the part

and are precisely matched. Care is taken in both the chip pinout

and layout. This results in excellent gain drift and quick settling

to the final gain value after the part is powered on.

The AD8428 pinout allows access to internal nodes between the

first and second stages. This feature can be useful for modifying

the frequency response between the two amplification stages,

thereby preventing unwanted signals from contaminating the

output results.

The high CMRR of the AD8428 prevents unwanted signals

from corrupting the signal of interest. The pinout of the AD8428

is designed to avoid parasitic capacitance mismatches that can

degrade CMRR at high frequencies.

The performance of the AD8428 is specified over the industrial

temperature range of −40°C to +85°C. It is available in an 8-lead

plastic SOIC package.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD8428

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Filter Terminals........................................................................... 13

Reference Terminal .................................................................... 13

Input Voltage Range................................................................... 14

Layout .......................................................................................... 14

Input Bias Current Return Path ............................................... 15

Input Protection ......................................................................... 15

Radio Frequency Interference (RFI)........................................ 16

Calculating the Noise of the Input Stage................................. 16

Applications Information.............................................................. 18

Effect of Passive Network Across the Filter Terminals.......... 18

Circuits Using the Filter Terminals.......................................... 18

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 13

Architecture................................................................................. 13

REVISION HISTORY

4/12—Rev. 0 to Rev. A

Changes to Features Section and Table 1 ...................................... 1

Added B Grade Column to Table 2................................................ 3

Changes to Figure 3, Figure 4, Figure 5, Figure 6, Figure 7,

and Figure 8....................................................................................... 7

Changes to Filter Terminals Section ............................................ 13

Added Applications Information Section ................................... 18

Changes to Ordering Guide .......................................................... 20

10/11—Revision 0: Initial Version

Rev. A | Page 2 of 20

Data Sheet

AD8428

SPECIFICATIONS

V_S= 15 V, V_REF= 0 V, T_A= 25°C, G = 2000, R_L= 10 kΩ, unless otherwise noted.

Table 2.

Test Conditions/

Comments

A Grade

Typ

B Grade

Typ

Parameter

Min

Max

Min

Max

Unit

COMMON-MODE REJECTION RATIO RTI, V_CM

(CMRR)

= 10 V

DC to 60 Hz

At 50 kHz

130

110

140

120

dB

NOISE (RTI)

Voltage Noise

V_IN+, V_IN− = 0 V

f = 1 kHz

1.3

40

1.5

150

1.5

50

1.3

40

1.5

150

1.5

50

nV/√Hz

nV p-p

pA/√Hz

pA p-p

f = 0.1 Hz to 10 Hz

f = 1 kHz

f = 0.1 Hz to 10 Hz

Current Noise

VOLTAGE OFFSET

Input Offset, V_OSI

Average TC

Offset RTI vs. Supply (PSRR)

INPUT CURRENT

100

1

25

0.3

μV

μV/°C

dB

T_A= −40°C to +85°C

120

130

Input Bias Current

Over Temperature

Input Offset Current

Over Temperature

DYNAMIC RESPONSE

−3 dB Small Signal Bandwidth

Settling Time to 0.01%

Settling Time to 0.001%

Slew Rate

200

50

10

nA

pA/°C

nA

T_A= −40°C to +85°C

250

20

250

20

pA/°C

3.5

0.75

1.4

50

3.5

0.75

1.4

50

MHz

μs

10 V step

40

V/μs

GAIN

First Stage Gain

Subtractor Stage Gain

Total Gain Error

Total Gain Nonlinearity

Gain Drift

200

10

200

10

V/V

%

ppm

ppm/°C

V_OUT= −10 V to +10 V

0.2

5

10

0.05

5

INPUT

Impedance (Pin to Ground)¹

Input Operating Voltage Range

Over Temperature

OUTPUT

1||2

GΩ||pF

V

V_S= 4 V to 18 V

T_A= −40°C to +85°C

−V_S+ 2.5

+V_S− 2.5 −V_S+ 2.5

+V_S− 2.5

Output Voltage Swing

Over Temperature

R_L= 2 kΩ

−V_S+ 1.7

−V_S+ 2.0

−V_S+ 1.6

−V_S+ 1.7

−V_S+ 1.8

−V_S+ 1.4

+V_S− 1.2 −V_S+ 1.7

+V_S− 1.3 −V_S+ 2.0

+V_S− 1.1 −V_S+ 1.6

+V_S− 1.0 −V_S+ 1.7

+V_S− 1.2 −V_S+ 1.8

+V_S− 0.9 −V_S+ 1.4

+V_S− 1.2

+V_S− 1.3

+V_S− 1.1

+V_S− 1.0

+V_S− 1.2

+V_S− 0.9

V

T_A= −40°C

T_A= +85°C

R_L= 10 kΩ

T_A= −40°C

T_A= +85°C

Output Voltage Swing

Over Temperature

Short-Circuit Current

REFERENCE INPUT

Input Impedance, R_IN

Input Current, I_IN

30

mA

132

6.5

132

6.5

kΩ

μA

V

V_IN+, V_IN− = 0 V

Voltage Range

−V_S

+V_S

−V_S

+V_S

Reference Gain to Output

Reference Gain Error

1

0.01

1

0.01

V/V

%

Rev. A | Page 3 of 20

AD8428

Data Sheet

Test Conditions/

Comments

A Grade

Typ

B Grade

Typ

Parameter

Min

Max

Min

Max

Unit

FILTER TERMINALS

Input Impedance, R_IN

Voltage Range

2

6

kΩ

V

−V_S

4

+V_S

−V_S

4

+V_S

POWER SUPPLY

Operating Range

Quiescent Current

Over Temperature

18

6.8

8

18

6.8

8

V

mA

6.5

T_A= −40°C to +85°C

¹The differential and common-mode input impedances can be calculated from the pin impedance: Z_DIFF= 2(Z_PIN); Z_CM= Z_PIN/2.

²To calculate the actual impedance, see Figure 1.

Rev. A | Page 4 of 20

Data Sheet

AD8428

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 3.

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Parameter

Rating

Supply Voltage

18 V

Output Short-Circuit Current Duration Indefinite

Table 4. Thermal Resistance

Maximum Voltage at −IN, +IN¹

Maximum Voltage at −FIL, +FIL

Differential Input Voltage¹

Maximum Voltage at REF

Storage Temperature Range

Specified Temperature Range

Maximum Junction Temperature

ESD

V_S

1 V

V_S

Package

θ_JA

Unit

8-Lead SOIC_N

121

°C/W

−65°C to +150°C

−40°C to +85°C

140°C

ESD CAUTION

Human Body Model

Charged Device Model

Machine Model

5000 V

1250 V

400 V

¹For voltages beyond these limits, use input protection resistors. See the

Input Protection section for more information.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. A | Page 5 of 20

AD8428

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8428

–IN

–FIL

+FIL

+IN

1

2

3

4

8

7

6

5

+V

S

OUT

REF

–V

S

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

5

6

7

8

−IN

Negative Input Terminal.

Negative Filter Terminal.

Positive Filter Terminal.

Positive Input Terminal.

−FIL

+FIL

+IN

−V_S

REF

Negative Power Supply Terminal.

Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output.

Output Terminal.

Positive Power Supply Terminal.

OUT

+V_S

Rev. A | Page 6 of 20

Data Sheet

AD8428

TYPICAL PERFORMANCE CHARACTERISTICS

V_S= 15 V, V_REF= 0 V, T_A= 25°C, G = 2000, R_L= 10 kΩ, unless otherwise noted.

1600

1400

1200

1000

800

600

400

200

0

POSITIVE INPUT I

BIAS

N = 5170

MEAN = 2.12

SD = 7.332

1400

1200

1000

800

600

400

200

0

NEGATIVE INPUT I

BIAS

N = 5171

MEAN = –10.8

SD = 6.67496

N = 5171

MEAN = –10.2

SD = 6.52901

–60

–40

–20

0

20

40

60

–60

–40

–20

0

20

40

60

I

(nA)

V

(µV)

BIAS

OSI

Figure 3. Typical Distribution of Input Offset Voltage, V_S= 5 V

Figure 6. Typical Distribution of Input Bias Current

1600

1400

1200

1000

800

600

400

200

0

N = 5171

N = 5169

1400

MEAN = –0.53

MEAN = –2.57

SD = 1.41655

SD = 7.31066

1200

1000

800

600

400

200

0

–8

–6

–4

–2

0

2

4

6

8

–60

–40

–20

0

20

40

60

I

(nA)

V

(µV)

OS

OSI

Figure 7. Typical Distribution of Input Offset Current

Figure 4. Typical Distribution of Input Offset Voltage, V_S= 15 V

1600

1400

1200

1000

800

600

400

200

0

1600

N = 5166

N = 3487

1400

MEAN = 0.398

MEAN = –53.9

SD = 86.7774

SD = 0.42707

1200

1000

800

600

400

200

0

–3

–2

–1

0

1

2

3

–600

–400

–200

0

200

400

600

V

DRIFT (µV/°C)

GAIN ERROR (µV/V)

OSI

Figure 5. Typical Distribution of Input Offset Voltage Drift

Figure 8. Typical Distribution of Gain Error, Gain = 2000,

V_S= 15 V, R_L= 10 kΩ

Rev. A | Page 7 of 20

AD8428

Data Sheet

15

72

66

60

54

48

42

36

30

24

18

12

6

V

= ±15V

S

10

V

= ±12V

S

5

0

V

= ±5V

S

–5

–10

0

–6

–15

–12

100

–10

–5

0

5

10

15

1k

10k

100k

1M

10M

100M

OUTPUT VOLTAGE (V)

FREQUENCY (Hz)

Figure 9. Input Common-Mode Voltage vs. Output Voltage,

V_S= 5 V, V_S= 12 V, V_S= 15 V

Figure 12. Gain vs. Frequency

18

170

160

150

140

130

120

110

100

90

V

= –11.8V

GAIN = 2000

CM

16

14

12

10

8

6

4

2

0

V

= +12V

CM

80

1

10

100

1k

10k

100k

1M

–14 –12 –10 –8 –6 –4 –2

0

2

4

6

8

10 12 14

FREQUENCY (Hz)

COMMON-MODE VOLTAGE (V)

Figure 10. Input Bias Current vs. Common-Mode Voltage,

V_S= 15 V

Figure 13. CMRR vs. Frequency

140

120

110

100

90

GAIN = 2000

120

100

80

60

40

20

0

+PSRR

–PSRR

80

70

60

50

40

30

20

10

0

0.1

1

10

100

1k

10k

100k

1M

1

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 11. PSRR vs. Frequency

Figure 14. CMRR vs. Frequency, 1 kΩ Source Imbalance

Rev. A | Page 8 of 20

Data Sheet

AD8428

5

70

60

REPRESENTATIVE DATA

NORMALIZED AT 25°C

4

50

3

40

30

2

20

1

10

0

–10

–20

–30

–1

–2

0

10 20 30 40 50 60 70 80 90 100 110 120

WARM-UP TIME (Seconds)

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 15. Change in Input Offset Voltage (V_OSI) vs. Warm-Up Time

Figure 18. CMRR vs. Temperature, Normalized at 25°C

15

10

1.2

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

I

OS

I

0.8

BIAS+

5

0.4

I

BIAS–

0

–0.4

–0.8

–1.2

–1.6

–2.0

–5

–10

–15

–20

–25

NORMALIZED AT 25°C

–30

–2.4

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 16. Input Bias Current and Input Offset Current vs. Temperature,

Normalized at 25°C

Figure 19. Supply Current vs. Temperature

50

40

250

200

150

100

50

I

SHORT+

30

20

10

0

–10

–20

–30

–40

–50

–100

–150

I

SHORT–

REPRESENTATIVE DATA

NORMALIZED AT 25°C

80 95 110 125

–200

–40 –25 –10

5

20

35

50

65

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 20. Short-Circuit Current vs. Temperature

Figure 17. Gain Error vs. Temperature, Normalized at 25°C

Rev. A | Page 9 of 20

AD8428

Data Sheet

100

90

80

70

60

50

40

30

20

10

+V

S

–40°C

+25°C

+85°C

+125°C

–0.4

–0.8

–1.2

–SR

+2.0

+1.6

+1.2

+0.8

+0.4

+SR

0

–V

S

–40 –25 –10

5

20

35

50

65

80

95 110 125

4

5

6

7

8

9

10 11 12 13 14 15 16 17

TEMPERATURE (°C)

SUPPLY VOLTAGE (±V )

S

Figure 21. Slew Rate vs. Temperature, V_S= 15 V

Figure 24. Output Voltage Swing vs. Supply Voltage, R_L= 10 kΩ

100

90

80

70

60

50

40

30

20

10

+V

S

–40°C

+25°C

+85°C

+125°C

–0.4

–0.8

–1.2

–SR

+SR

+2.0

+1.6

+1.2

+0.8

+0.4

0

–V

S

–40 –25 –10

5

20

35

50

65

80

95 110 125

4

5

6

7

8

9

10 11 12 13 14 15 16 17

TEMPERATURE (°C)

SUPPLY VOLTAGE (±V )

S

Figure 22. Slew Rate vs. Temperature, V_S= 5 V

Figure 25. Output Voltage Swing vs. Supply Voltage, R_L= 2 kΩ

+V

15

S

–40°C

–0.5

–1.0

–1.5

–2.0

–2.5

–40°C

+25°C

+85°C

+125°C

+25°C

+85°C

+125°C

10

5

0

–5

+2.5

+2.0

+1.5

+1.0

+0.5

–10

–15

–V

S

4

6

8

10

12

14

16

18

100

1k

10k

100k

SUPPLY VOLTAGE (±V )

LOAD RESISTANCE (Ω)

S

Figure 23. Input Voltage Limit vs. Supply Voltage

Figure 26. Output Voltage Swing vs. Load Resistance, V_S= 15 V

Rev. A | Page 10 of 20

Data Sheet

AD8428

+V

S

–40°C

+25°C

+85°C

+125°C

–0.5

–1.0

–1.5

+1.5

+1.0

+0.5

20nV/DIV

1s/DIV

–V

S

0.01

0.1

1

10

OUTPUT CURRENT (mA)

Figure 27. Output Voltage Swing vs. Output Current, V_S= 15 V

Figure 30. RTI Voltage Noise, 0.1 Hz to 10 Hz

20

16

15

14

13

12

11

10

9

GAIN = 2000

15

10

5

0

8

7

–5

6

5

–10

–15

–20

4

3

2

1

–10

–8

–6

–4

–2

0

2

4

6

8

10

1

10

100

1k

10k

100k

OUTPUT VOLTAGE (V)

FREQUENCY (Hz)

Figure 31. Current Noise Spectral Density vs. Frequency

Figure 28. Gain Nonlinearity, R_L= 10 kΩ

100

GAIN = 2000

10

1

50pA/DIV

1s/DIV

0.1

1

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 29. RTI Voltage Noise Spectral Density vs. Frequency

Figure 32. Current Noise, 0.1 Hz to 10 Hz

Rev. A | Page 11 of 20

AD8428

Data Sheet

5V/DIV

752ns TO 0.01%

1408ns TO 0.001%

NO LOAD

= 500pF

0.002%/DIV

C

L

C

= 770pF

L

1µs/DIV

50mV/DIV

1µs/DIV

TIME (µs)

Figure 33. Large Signal Pulse Response and Settling Time,

10 V Step, V_S= 15 V

Figure 35. Small Signal Pulse Response with Various Capacitive Loads,

No Resistive Load

1800

1600

GAIN = 2000

1400

1200

SETTLED TO 0.001%

1000

800

600

SETTLED TO 0.01%

400

200

0

20mV/DIV

1µs/DIV

2

4

6

8

10

12

14

16

18

20

STEP SIZE (V)

Figure 36. Settling Time vs. Step Size

Figure 34. Small Signal Pulse Response, R_L= 10 kΩ, C_L= 100 pF

Rev. A | Page 12 of 20

Data Sheet

AD8428

THEORY OF OPERATION

I

V

B

–FIL

I

B

2

COMPENSATION

120kΩ

R7

A1

A2

+V

–V

S

+V

–V

C1

C2

S

R3

R4

6kΩ

NODE 1

7

6

OUT

REF

A3

NODE 2

+V

S

+V

–V

S

R5

6kΩ

R6

6kΩ

S

R1

3kΩ

R2

3kΩ

120kΩ

R8

S

1

4

+V

–V

S

Q1

Q2

–IN

+IN

3

+FIL

30.15Ω

–V

S

–V

S

–RG

+RG

S

R

G

Figure 37. Simplified Schematic

ARCHITECTURE

REFERENCE TERMINAL

The AD8428 is based on the classic 3-op-amp topology. This

topology has two stages: a gain stage (preamplifier) to provide

differential amplification by a factor of 200, followed by a differ-

ence amplifier (subtractor) stage to remove the common-mode

voltage and provide additional amplification by a factor of 10.

Figure 37 shows a simplified schematic of the AD8428.

The output voltage of the AD8428 is developed with respect to

the potential on the reference terminal. This is useful when the

output signal must be offset to a precise midsupply level. For

example, a voltage source can be tied to the REF pin to level-

shift the output so that the AD8428 can drive a single-supply

ADC. The REF pin is protected with ESD diodes and should

not exceed either +V_Sor −V_S.

The first stage works as follows. To keep its two inputs matched,

Amplifier A1 must keep the collector of Q1 at a constant voltage.

It does this by forcing −RG to be a constant diode drop from −IN.

Similarly, A2 forces +RG to be a constant diode drop from +IN.

Therefore, a replica of the differential input voltage is placed across

the gain setting resistor, R_G. The current that flows across this

resistor must also flow through the R1 and R2 resistors, creating

a gained differential signal between the A2 and A1 outputs.

For best performance, the source impedance to the REF

terminal should be kept well below 1 ꢀ. As shown in Figure 37,

the reference terminal, REF, is at one end of a 120 kΩ resistor.

Additional impedance at the REF terminal adds to this 120 kΩ

resistor and results in amplification of the signal connected to

the positive input. The amplification from the additional R_REF

can be calculated as follows:

The second stage is a G = 10 difference amplifier, composed of

Amplifier A3 and Resistors R3 through R8. This stage removes

the common-mode signal from the amplified differential signal.

2 × (120 kΩ + R_REF)/(240 kΩ + R_REF)

Only the positive signal path is amplified; the negative path is

unaffected. This uneven amplification degrades the CMRR of

the amplifier.

The transfer function of the AD8428 is

INCORRECT

CORRECT

V

_OUT= 2000 × (V_IN+− V_IN−) + V_REF

FILTER TERMINALS

The −FIL and +FIL terminals allow access between R3 and R4,

and between R5 and R6, respectively. Adding a filter between

these two terminals modifies the gain that is applied to the signal

before it reaches the second amplifier stage (see the Applications

Information section).

AD8428

REF

V

+

OP1177

–

Figure 38. Driving the Reference Pin

Rev. A | Page 13 of 20

AD8428

Data Sheet

Power Supplies and Grounding

INPUT VOLTAGE RANGE

Use a stable dc voltage to power the instrumentation amplifier.

Noise on the supply pins can adversely affect performance. See

the PSRR performance curves in Figure 11 for more information.

The 3-op-amp architecture of the AD8428 applies gain in the

first stage before removing the common-mode voltage in the

difference amplifier stage. Internal nodes between the first and

second stages (Node 1 and Node 2 in Figure 37) experience a

combination of an amplified differential signal, a common-mode

signal, and a diode drop. This combined signal can be limited by

the voltage supplies even when the individual input and output

signals are not limited. Figure 9 shows the allowable input

common-mode voltage ranges for various output voltages and

supply voltages.

Place a 0.1 μF capacitor as close as possible to each supply pin.

Because the length of the bypass capacitor leads is critical at

high frequency, surface-mount capacitors are recommended.

Parasitic inductance in the bypass ground trace works against

the low impedance created by the bypass capacitor.

As shown in Figure 40, a 10 μF capacitor can be used farther

away from the device. For larger value capacitors, which are

intended to be effective at lower frequencies, the current return

path distance is less critical. In most cases, the 10 μF capacitor

can be shared by other precision integrated circuits.

LAYOUT

To ensure optimum performance of the AD8428 at the PCB

level, care must be taken in the design of the board layout. The

pins of the AD8428 are especially arranged to simplify board

layout and to help minimize parasitic imbalance between the

inputs.

+V

S

0.1µF

10µF

AD8428

+IN

–IN

–FIL

+FIL

+IN

1

2

3

4

8

7

6

5

+V

S

OUT

LOAD

OUT

REF

AD8428

–V

S

REF

TOP VIEW

(Not to Scale)

Figure 39. Pinout Diagram

0.1µF

10µF

Common-Mode Rejection Ratio over Frequency

–V

S

Poor layout can cause some of the common-mode signals to

be converted to differential signals before reaching the in-amp.

Such conversions occur when one input path has a frequency

response that is different from the other.

Figure 40. Supply Decoupling, REF, and Output Referred to Local Ground

A ground plane layer is helpful to reduce undesired parasitic

inductances and to minimize voltage drops with changes in

current. The area of the current path is directly proportional

to the magnitude of parasitic inductances and, therefore, the

impedance of the path at high frequency. Large changes in

currents in an inductive decoupling path or ground return

create unwanted effects due to the coupling of such changes

into the amplifier inputs.

To maintain high CMRR over frequency, the input source

impedance and capacitance of each path should be closely

matched. Additional source resistance in the input paths (for

example, for input protection) should be placed close to the

in-amp inputs to minimize the interaction of the inputs with

parasitic capacitance from the PCB traces.

Because load currents flow from the supplies, the load should

be connected at the same physical location as the bypass capac-

itor grounds.

Parasitic capacitance at the filter pins can also affect CMRR over

frequency. If the board design has a component at the filter pins,

the component should be chosen so that the parasitic capacitance

is as small as possible.

Reference Pin

The output voltage of the AD8428 is developed with respect to

the potential on the reference terminal. Ensure that REF is tied

to the appropriate local ground.

Rev. A | Page 14 of 20

Data Sheet

AD8428

Input Voltages Beyond the Rails

INPUT BIAS CURRENT RETURN PATH

If voltages beyond the rails are expected, use an external resistor

in series with each input to limit current during overload condi-

tions. The limiting resistor at each input can be computed using

the following equation:

The input bias current of the AD8428 must have a return path

to ground. When the source, such as a thermocouple, cannot

provide a current return path, one should be created, as shown

in Figure 41.

INCORRECT

CORRECT

V

_IN−V_SUPPLY

+V

S

+V

S

R_PROTECT≥

I_MAX

Noise sensitive applications may require a lower protection

resistance. Low leakage diode clamps, such as the BAV199, can

be used at the inputs to shunt current away from the AD8428

inputs and, therefore, allow smaller protection resistor values.

To ensure that current flows primarily through the external

protection diodes, place a small value resistor, such as a 33 Ω

resistor, between the diodes and the AD8428.

AD8428

REF

–V

S

TRANSFORMER

+V

S

+V

S

R

+

IN+

–

R

+V

S

+V

S

PROTECT

I

33Ω

PROTECT

I

+

IN+

–

V

–V

+V

S

AD8428

S

R

PROTECT

33Ω

PROTECT

AD8428

+

IN–

–

+

IN–

–

REF

–V

S

–V

S

V

–V

S

10MΩ

SIMPLE METHOD

LOW NOISE METHOD

–V

S

Figure 42. Protection for Voltages Beyond the Rails

THERMOCOUPLE

Large Differential Input Voltage at High Gain

+V

S

If large differential voltages at high gain are expected, use

an external resistor in series with each input to limit current

during overload conditions. The limiting resistor at each input

can be computed using the following equation:

C

R

1

f_HIGH-PASS

=

AD8428

2πRC

AD8428

C

REF

⎛

⎜

⎞

⎟

V_DIFF− 1V

1

2

R_PROTECT

≥

×

− R_G

⎜

⎝

⎟

⎠

I_MAX

–V

S

CAPACITIVELY COUPLED

Noise sensitive applications may require a lower protection

resistance. Low leakage diode clamps, such as the BAV199,

can be used across the AD8428 inputs to shunt current away

from the inputs and, therefore, allow smaller protection resistor

values.

Figure 41. Creating an Input Bias Current Return Path

INPUT PROTECTION

Do not allow the inputs of the AD8428 to exceed the ratings

stated in the Absolute Maximum Ratings section. If these ratings

cannot be adhered to, add protection circuitry in front of the

AD8428 to limit the maximum current into the inputs (see the

R

PROTECT

I

+

V

DIFF

–

AD8428

I

_MAXsection).

R

PROTECT

I_MAX

Figure 43. Protection for Large Differential Voltages

The maximum current into the AD8428 inputs, I_MAX, depends

on time and temperature. At room temperature, the device can

withstand a current of 10 mA for at least one day. This time is

cumulative over the life of the device.

Rev. A | Page 15 of 20

AD8428

Data Sheet

For best results, place the RFI filter network as close to the

RADIO FREQUENCY INTERFERENCE (RFI)

amplifier as possible. Layout is critical to ensure that RF signals

are not picked up on the traces after the filter. If RF interference

is too strong to be filtered, shielding is recommended.

Because of its high gain and low noise properties, the AD8428

is a highly sensitive amplifier. Therefore, RF rectification can be

a problem if the AD8428 is used in applications that have strong

RF signal sources present. The problem is intensified if long leads

or PCB traces are required to connect the amplifier to the signal

source. The disturbance can appear as a dc offset voltage or as a

train of pulses.

Note that the resistors used for the RFI filter can be the same

as those used for input protection (see the Input Protection

section).

CALCULATING THE NOISE OF THE INPUT STAGE

High frequency signals can be filtered with a low-pass filter

network at the input of the instrumentation amplifier, as shown

in Figure 44.

The total noise of the amplifier front end depends on much

more than the specifications in this data sheet. The three main

contributors to noise are as follows:

+V

S

•

Source resistance

Voltage noise of the instrumentation amplifier

Current noise of the instrumentation amplifier

0.1µF

+IN

10µF

C

1nF

C

L*

R

In the following calculations, noise is referred to the input (RTI);

that is, all sources of noise are calculated as if the source appeared

at the amplifier input. To calculate the noise referred to the ampli-

fier output (RTO), multiply the RTI noise by the gain of the

instrumentation amplifier.

33Ω

OUT

C

D

AD8428

10nF

R

REF

–IN

33Ω

C

1nF

Source Resistance Noise

0.1µF

10µF

Any sensor connected to the AD8428 has some output resistance.

There may also be resistance placed in series with the inputs for

protection from either overvoltage or radio frequency interference.

This combined resistance is labeled R1 and R2 in Figure 45. Any

resistor, no matter how well made, has an intrinsic level of noise.

This noise is proportional to the square root of the resistor value.

At room temperature, the value is approximately equal to

4 nV/√Hz × √(resistor value in kΩ).

–V

S

*CHIP FERRITE BEAD.

Figure 44. RFI Suppression

The filter limits both the differential and common-mode band-

width, as shown in the following equations:

1

FilterFrequency_DIFF

=

2πR(2C_D+C_C)

SENSOR

1

FilterFrequency_CM

=

2πRC_C

R1

AD8428

where C_D≥ 10 C_C.

C_Daffects the differential signal, and C_Caffects the common-

mode signal. Choose values of R and C_Cthat minimize RFI. A

mismatch between R × C_Cat the positive input and R × C_Cat

the negative input degrades the CMRR of the AD8428. By using

a value of C_Done order of magnitude larger than C_C, the effect

of the mismatch is reduced, and performance is improved.

R2

Figure 45. Source Resistance from Sensor and Protection Resistors

For example, assuming that the combined sensor and protec-

tion resistance is 4 kΩ on the positive input and 1 kΩ on the

negative input, the total noise from the input resistance is

Resistors add noise; therefore, the choice of resistor and capac-

itor values depends on the desired trade-off between noise, input

impedance at high frequencies, and RFI immunity. To achieve

low noise and sufficient RFI filtering, the use of inductive ferrite

beads is recommended (see Figure 44). Using inductive ferrite

beads allows the value of the resistors to be reduced, which helps

to minimize the noise at the input.

2

(

4 × 4

)

+

(

4 × 1

)

= 64 +16 = 8.9 nV/ Hz

Rev. A | Page 16 of 20

Data Sheet

AD8428

Voltage Noise of the Instrumentation Amplifier

Total Noise Density Calculation

Unlike other instrumentation amplifiers in which an external

resistor is used to set the gain, the voltage noise specification

of the AD8428 already includes the input noise, output noise,

and the R_Gresistor noise.

To determine the total noise of the in-amp, referred to input,

combine the source resistance noise, voltage noise, and current

noise contribution by the sum of squares method.

For example, if the R1 source resistance in Figure 45 is 4 kΩ

and the R2 source resistance is 1 kΩ, the total noise, referred

to input, is

Current Noise of the Instrumentation Amplifier

The contribution of current noise to the input stage in nV/√Hz

is calculated by multiplying the source resistance in kΩ by the

specified current noise of the instrumentation amplifier in

pA/√Hz.

8.9²+1.5²+ 6.2²= 11.0 nV/ Hz

For example, if the R1 source resistance in Figure 45 is 4 kΩ

and the R2 source resistance is 1 kΩ, the total effect from the

current noise is calculated as follows:

2

(

4 × 1.5

)

+

(

1 × 1.5

)

=

36 + 2.25 = 6.2 nV/ Hz

Rev. A | Page 17 of 20

AD8428

Data Sheet

APPLICATIONS INFORMATION

The classic 3-op-amp topology used for instrumentation

amplifiers typically places all the gain in the first stage and

subtracts the common-mode signals only in the second stage.

When operated at high gain, any amplifier is sensitive to large

interfering signals that can saturate it, thus making it impossible

to recover the signal of interest.

Because this resistor appears inside the feedback of the subtractor

stage, it modifies the gain of the subtractor as well. The total gain

formula is a simplified version of the transfer function equation

(Equation 1).

2000 × R_G

G =

(2)

R_G+ 6000

The AD8428 splits the total gain of 2000 into two stages: 200 in the

preamplification stage and 10 in the subtractor stage. Reducing the

gain of the first stage helps to increase the common-mode range

vs. differential signal range by avoiding saturation of the preamps.

15

The R_Gunit is in ohms. The resistor value required to obtain the

desired gain can be calculated using the following formula:

6000 × G

R_G=

2000 − G

The AD8428 defaults to G = 2000 when no gain resistor is used.

When setting the amplifier to a different gain, the absolute gain

accuracy is only 10%. In addition, the temperature mismatch of

the external gain resistor increases the gain drift of the instrumen-

tation amplifier. Gain error and gain drift are at a guaranteed

minimum when a gain resistor is not used. For applications that

require accuracy at different gains, low noise, and wide bandwidth,

the AD8429 should be considered.

10

5

SINGLE STAGE GAIN, G = 2000

AD8428

0

–5

–10

–15

Low-Pass Filter

To help limit undesired differential signals, a first-order, low-pass

filter can be implemented by adding a capacitor across the filter

terminals of the AD8428, as shown in Figure 47.

–15

–10

–5

0

5

10

15

OUTPUT VOLTAGE (V)

Figure 46. AD8428 vs. Single Stage Gain Topology, G = 2000

+IN

+

+FIL

In addition, filtering between stages can help to attenuate signals

before they reach the second amplification stage. This filtering

helps to prevent saturation of the second stage amplifier as long

as the signals are located in frequencies other than the signal of

interest.

C

OUT

AD8428

–FIL

–

F

–IN

Figure 47. Differential Low-Pass Filter

This single-pole filter limits the signal bandwidth, as shown in

the following equation:

EFFECT OF PASSIVE NETWORK ACROSS THE

FILTER TERMINALS

1

f_C=

The AD8428 filter terminals allow access between the two

amplification stages. Adding a passive network between the two

terminals can shape the transfer function over the frequency of

the amplifier. The general expression for the transfer function is

represented by Equation 1.

2π(6 kΩ)C_F

The 6 kΩ factor comes from the internal resistor values. The

tolerance of these resistors is 10%; therefore, using capacitors

with a tolerance better than 5% does not provide a significant

improvement on the absolute tolerance of the cutoff frequency.

2000 × Z(s)

Z(s) + 6000

G(s) =

(1)

Limiting the bandwidth of the amplifier also helps to minimize

the amount of out-of-band noise present at the output.

where Z(s) is the frequency dependent impedance of the

network across the filter terminals.

Note that filtering common-mode signals by adding a capacitor

on each filter terminal to ground degrades the performance of

the amplifier. This practice is generally discouraged because it

degrades CMRR performance. In addition, filtering common-

mode signals has little effect on preventing the saturation of the

internal nodes. On the contrary, the load added to the preamplifiers

causes them to saturate with even smaller common-mode signals.

CIRCUITS USING THE FILTER TERMINALS

Setting the Amplifier to Different Gains

In its simplest form, the transfer function equation (Equation 1)

implies that the AD8428 can be configured for gains lower than

2000. This can be achieved by attaching a resistor across the filter

pins. Unlike the gain configuration of traditional instrumentation

amplifiers, this resistor attenuates the signal that was previously

amplified by the initial gain of 200.

Rev. A | Page 18 of 20

Data Sheet

AD8428

Notch Filter

In contrast, a small Q value increases the range for the same

attenuation, which relaxes the tolerance requirements between

the inductor and capacitor and the frequency uncertainty of the

undesired signal. However, the lower Q value has a significant

effect on signal bandwidth one decade before the notch

frequency.

In cases where the frequency of the interfering signal is well

known, a notch filter can be implemented to help minimize the

impact of the known signal on the measurement. The filter can

be realized by adding a series LC network between the filter

pins, as shown in Figure 48.

72

L

F

+

+FIL

Q = 1

66

OUT

AD8428

–FIL

–

–3dB

C

F

60

Q = 0.1

Figure 48. Notch Filter Example

54

48

The inductor and capacitor form a resonant circuit that rejects

frequencies near the notch. The center frequency can be

calculated using the following equation:

–20dB

1

42

f_N

=

2π L_FC_F

The Q factor of the filter is given by the following equation:

L_F

6000 C_F

36

0.01f

0.1f

f

10f

100f

N

FREQUENCY (Hz)

1

Q =

Figure 49. Notch Filter Attenuation with Q = 0.1 and Q = 1

Around the Center Frequency

The accuracy of the center frequency, f_N, depends only on the

tolerance of the capacitor and inductor values, not on the value

of the internal resistors. However, the Q of the circuit depends on

both the tolerance of the external components and the absolute

tolerance of the internal resistors, which is typically 10%.

The maximum attenuation that can be achieved with a notch

filter is at its center frequency, f_N. This maximum attenuation

(or depth of the notch) depends on the equivalent series

resistance of the inductor and capacitor at the center frequency.

Choosing components with high quality factors improves the

rejection at the filter’s center frequency. For information about

calculating the maximum allowed series resistance at the frequency

of interest to obtain the desired attenuation, see the Setting the

Amplifier to Different Gains section.

The Q factor is a filter parameter that indicates how narrow the

notch filter is. It is defined as follows:

f_N

Q =

f_B− f_A

Extracting the Common-Mode Voltage of the Input

where f_Aand f_Bare the frequencies at which there is −3 dB

attenuation on each side of the notch.

The common-mode signal present at the input terminals can be

extracted by inserting two resistors between the filter terminals

and tapping from the center, as shown in Figure 50. The common-

mode voltage, V_CM, is the average of the voltages present at the

two inputs minus a 0.6 V drop.

This equation indicates that the higher the Q, the narrower the

notch—that is, high values of Q increase the selectivity of the

notch. In other words, although high values of Q reduce the

effect of the notch on the amplitude and phase in neighboring

frequencies, the ability to reject the undesired frequency may

also be reduced due to mismatch between it and the actual

center frequency. This mismatch can be caused by frequency

variations on the affecting source and the tolerance of the filter

inductor and capacitor values.

+IN

+

+FIL

R

V

OUT

CM

AD8428

–FIL

–IN

–

Figure 50. Extracting the Common-Mode Voltage

Use resistor values that are high enough to minimize the impact

on gain accuracy. For example, resistor values of 2 MΩ introduce

an additional gain error of less than 0.2%. For information about

the impact of these resistors on the gain of the amplifier, see the

Effect of Passive Network Across the Filter Terminals section.

In contrast, low values of Q work better to ensure that the

interfering frequency is attenuated, but these low values also

affect the signal of interest if it is located close to the center

frequency of the notch.

For example, if the goal is to attenuate the interfering signal by

20 dB, a large Q value reduces the frequency range where the

notch is effective, as shown in Figure 49.

Rev. A | Page 19 of 20

AD8428

Data Sheet

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

8

1

5

4

6.20 (0.2441)

5.80 (0.2284)

4.00 (0.1574)

3.80 (0.1497)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

BSC

45°

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0098)

0.10 (0.0040)

8°

0°

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 51. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model¹

AD8428ARZ

AD8428ARZ-RL

AD8428BRZ

AD8428BRZ-RL

Temperature Range

−40°C to +85°C

Package Description

Package Option

8-Lead SOIC_N

8-Lead SOIC_N, 13”Tape and Reel

8-Lead SOIC_N

R-8

8-Lead SOIC_N, 13”Tape and Reel

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D09731-0-4/12(A)

Rev. A | Page 20 of 20

型号:	AD8428BRZ
Source Url Status Check Date：	2013-05-01 14:56:26.358
Brand Name：	Analog Devices Inc
是否无铅：	含铅
是否Rohs认证：	符合
生命周期：	Active
针数：	8
制造商包装代码：	R-8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
风险等级：	2.31
放大器类型：	INSTRUMENTATION AMPLIFIER
JESD-30 代码：	R-PDSO-G8
标称负供电电压 (Vsup)：	-15 V
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
电源：	+-15 V
认证状态：	Not Qualified
子类别：	Instrumentation Amplifiers
最大压摆率：	8 mA
标称供电电压 (Vsup)：	15 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
Base Number Matches：	1

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