AD9215BRUZ-105全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

10-Bit, 65/80/105 MSPS,

3 V A/D Converter

Data Sheet

AD9215

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

DRVDD

Single 3 V supply operation (2.7 V to 3.3 V)

SNR = 58 dBc (to Nyquist)

SFDR = 77 dBc (to Nyquist)

VIN+

VIN–

PIPELINE

ADC CORE

SHA

Low power ADC core: 96 mW at 65 MSPS, 104 mW

@ 80 MSPS, 120 mW at 105 MSPS

Differential input with 300 MHz bandwidth

On-chip reference and sample-and-hold amplifier

DNL = 0.25 LSB

REFT

REFB

AD9215

CORRECTION LOGIC

10

OR

OUTPUT BUFFERS

Flexible analog input: 1 V p-p to 2 V p-p range

Offset binary or twos complement data format

Clock duty cycle stabilizer

D9 (MSB)

D0

VREF

CLOCK

MODE

SELECT

DUTY CYCLE

STABLIZER

APPLICATIONS

SENSE

REF

SELECT

Ultrasound equipment

0.5V

IF sampling in communications receivers

Battery-powered instruments

Hand-held scopemeters

AGND

CLK

PDWN

MODE DGND

Figure 1.

Low cost digital oscilloscopes

PRODUCT DESCRIPTION

The AD9215 is a family of monolithic, single 3 V supply, 10-bit,

65/80/105 MSPS analog-to-digital converters (ADC). This family

features a high performance sample-and-hold amplifier (SHA)

and voltage reference. The AD9215 uses a multistage differential

pipelined architecture with output error correction logic to pro-

vide 10-bit accuracy at 105 MSPS data rates and to guarantee no

missing codes over the full operating temperature range.

Fabricated on an advanced CMOS process, the AD9215 is avail-

able in both a 28-lead surface-mount plastic package and a

32-lead chip scale package and is specified over the industrial

temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. The AD9215 operates from a single 3 V power supply and

features a separate digital output driver supply to accom-

modate 2.5 V and 3.3 V logic families.

2. Operating at 105 MSPS, the AD9215 core ADC consumes

a low 120 mW; at 80 MSPS, the power dissipation is 104

mW; and at 65 MSPS, the power dissipation is 96 mW.

3. The patented SHA input maintains excellent performance

for input frequencies up to 200 MHz and can be config-

ured for single-ended or differential operation.

4. The AD9215 is part of several pin compatible 10-, 12-, and

14-bit low power ADCs. This allows a simplified upgrade

from 10 bits to 12 bits for systems up to 80 MSPS.

The wide bandwidth, truly differential sample-and-hold ampli-

fier (SHA) allows for a variety of user-selectable input ranges

and offsets including single-ended applications. It is suitable for

multiplexed systems that switch full-scale voltage levels in

successive channels and for sampling single-channel inputs at

frequencies well beyond the Nyquist rate. Combined with pow-

er and cost savings over previously available ADCs, the AD9215

is suitable for applications in communications, imaging, and

medical ultrasound.

A single-ended clock input is used to control all internal conversion

cycles. A duty cycle stabilizer compensates for wide variations in the

clock duty cycle while maintaining excellent performance. The digital

output data is presented in straight binary or twos complement for-

mats. An out-of-range signal indicates an overflow condition, which

can be used with the MSB to determine low or high overflow.

5. The clock duty cycle stabilizer maintains converter per-

formance over a wide range of clock pulse widths.

6. The out of range (OR) output bit indicates when the signal

is beyond the selected input range.

Rev. B

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sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights ofthird parties that may result fromits use. Specifications subject to change without notice. No

licenseis granted byimplication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD9215

Data Sheet

TABLE OF CONTENTS

Specifications..................................................................................... 3

REVISION HISTORY

Absolute Maximum Ratings¹.......................................................... 6

Explanation of Test Levels........................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Equivalent Circuits....................................................................... 8

Definitions of Specifications ....................................................... 8

Typical Performance Characteristics ........................................... 10

Applying the AD9215 Theory of Operation............................... 14

Clock Input and Considerations .............................................. 15

Evaluation Board ........................................................................ 18

Outline Dimensions ....................................................................... 33

Ordering Guide........................................................................... 34

2/13—Data Sheet Changed from a REV. A to a REV. B

Changes to Figure 4 and Added EPAD Note to Pin Configura-

tions and Function Descriptions Section..................................... 7

Changes to Voltage Reference Section........................................ 17

Changes to Evaluation Board Section......................................... 18

Updated Outline Dimensions...................................................... 33

Changes to Ordering Guide......................................................... 34

2/04—Data Sheet Changed from a REV. 0 to a REV. A

Renumbered Figures and Tables ..............................UNIVERSAL

Changes to Product Title................................................................ 1

Changes to Features ........................................................................ 1

Changes to Product Description ................................................... 1

Changes to Product Highlights ..................................................... 1

Changes to Specifications............................................................... 2

Changes to Figure 2......................................................................... 4

Changes to Figures 9 to 11 ........................................................... 10

Added Figure 14 ............................................................................ 10

Added Figures 16 and 18.............................................................. 11

Changes to Figures 21 to 24 and 25 to 26................................... 12

Deleted Figure 25........................................................................... 12

Changes to Figures 28 and 29 ...................................................... 13

Changes to Figure 31..................................................................... 14

Changes t0 Figure 35..................................................................... 16

Changes to Figures 50 through 58............................................... 26

Added Table 11 .............................................................................. 31

Updated Outline Dimensions...................................................... 32

Changes to Ordering Guide......................................................... 33

5/03—Revision 0: Initial Version

Rev. B | Page 2 of 36

Data Sheet

AD9215

SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise

noted.

Table 1. DC Specifications

AD9215BRU-65/

AD9215BCP-65

AD9215BRU-80/

AD9215BCP-80

AD9215BRU-105/

AD9215BCP-105

Test

Temp Level Min Typ

Parameter

Max Min Typ

Max Min

Typ

Max

Unit

RESOLUTION

Full

VI

10

Bits

ACCURACY

No Missing Codes

Offset Error¹

Full

VI

Guaranteed

0.3

Guaranteed

0.3

Guaranteed

0.3

+1.5

2.0

+4.0

+1.2

1.2

% FSR

LSB

Gain Error¹

0

−1.0

+1.5

0.5

+4.0

+1.0

1.2

+1.5

+4.0

Differential Nonlinearity (DNL)²

Integral Nonlinearity (INL)²

TEMPERATURE DRIFT

Offset Error¹

−1.0

0.5

+1.0

−1.0

0.6

0.65

1.2

LSB

Full

V

+15

+30

230

+15

+30

230

+15

+30

230

ppm/°C

Gain Error¹

Reference Voltage (1 V Mode)

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode)

Load Regulation @ 1.0 mA

Output Voltage Error (0.5 V Mode)

Load Regulation @ 0.5 mA

INPUT REFERRED NOISE

VREF = 0.5 V

Full

VI

V

2

0.2

1

35

2

0.2

1

35

2

0.2

1

35

mV

V

0.2

25°C

V

0.8

0.4

0.8

0.4

0.8

0.4

LSB rms

VREF = 1.0 V

ANALOG INPUT

Input Span, VREF = 0.5 V

Input Span, VREF = 1.0 V

Input Capacitance³

REFERENCE INPUT RESISTANCE

POWER SUPPLIES

Full

IV

V

1

2

7

1

2

7

1

2

7

V p-p

pF

V

kΩ

Supply Voltage

AVDD

DRVDD

Full

IV

2.7

2.25 2.5

3.0

3.3

3.6

2.7

2.25 2.5

3.0

3.3

3.6

2.7

2.25

3.0

2.5

3.3

3.6

V

Supply Current

2

I_AVDD

Full

25°C

Full

VI

V

32

7.0

0.1

35

34.5

8.6

0.1

39

40

11.3

0.1

44

mA

% FSR

2

I_DRVDD

PSRR

POWER CONSUMPTION

Sine Wave Input²

2

I_AVDD

Full

25°C

VI

V

96

18

1.0

104

20

1.0

120

25

1.0

mW

2

I_DRVDD

Standby Power⁴

¹With a 1.0 V internal reference.

²Measured at f_IN= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.

³Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.

⁴Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).

Rev. B | Page 3 of 36

AD9215

Data Sheet

AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference,

AIN = −0.5 dBFS, MODE = AVDD/3 (duty cycle stabilizer [DCS] enabled), unless otherwise noted.

Table 2. AC Specifications

AD9215BRU-65/

AD9215BCP-65

AD9215BRU-80/

AD9215BCP-80

AD9215BRU-105/

AD9215BCP-105

Test

Temp Level

Parameter

Min Typ Max Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 2.4 MHz

Full

25°C

Full

25°C

VI

I

VI

I

V

56.0 58.5

57.0 59.0

56.0 58.0

56.5 58.5

56.0 58.5

57.0 59.0

56.0 58.0

56.5 58.5

58.0

57.5

56.6 58.5

57.5

56.4 58.0

57.8

dB

f_IN= Nyquist¹

f_IN= 70 MHz

f_IN= 100 MHz

57.5

57.7

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

f_IN= 2.4 MHz

Full

25°C

Full

25°C

VI

I

VI

I

V

55.8 58.5

56.5 59.0

55.8 58.0

56.3 58.5

55.7 58.5

56.8 58.5

55.5 58.0

56.3 58.5

56.0

57.6

56.5 58.2

57.3

56.1 57.8

57.7

dB

f_IN= Nyquist¹

f_IN= 70 MHz

f_IN= 100 MHz

55.5

57.4

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 2.4 MHz

Full

25°C

Full

25°C

VI

I

VI

I

V

9.1

9.2

9.1

9.5

9.6

9.4

9.5

9.0

9.3

9.0

9.5

9.4

9.5

9.1

9.0

9.3

Bits

9.2

9.1

9.5

9.4

9.3

f_IN= Nyquist¹

f_IN= 70 MHz

f_IN= 100 MHz

WORST HARMONIC (Second or Third)

f_IN= 2.4 MHz

Full

25°C

Full

25°C

VI

I

VI

I

V

−78 −64

−80 −65

−77 −64

−78 −65

−78 −64

−80 −65

−76 −63

−78 −65

−70

−78

dBc

−84 −70 dBc

−74 dBc

−75 −61 dBc

−75

−74

f_IN= Nyquist¹

f_IN= 70 MHz

f_IN= 100 MHz

dBc

−70

WORST OTHER (Excluding Second or Third)

f_IN= 2.4 MHz

Full

25°C

Full

25°C

VI

I

VI

I

V

−77 −67

−78 −68

−77 −67

−78 −68

−77 −66

−77 −68

−77 −66

−77 −68

−80

−73

dBc

−75 −66 dBc

−71 dBc

−75 −63 dBc

-75

−75

f_IN= Nyquist¹

f_IN= 70 MHz

f_IN= 100 MHz

dBc

−80

TWO-TONE SFDR (AIN = –7 dBFS)

f_IN1= 70.3 MHz, f_IN2= 71.3 MHz

f_IN1= 100.3 MHz, f_IN2= 101.3 MHz

ANALOG BANDWIDTH

25°C

V

75

74

75

74

dBc

MHz

300

¹Tested at f_IN= 35 MHz for AD9215-65; f_IN= 39 MHz for AD9215-80; and f_IN= 50 MHz for AD9215-105.

Rev. B | Page 4 of 36

Data Sheet

AD9215

Table 3. Digital Specifications

AD9215BRU-65/

AD9215BCP-65

AD9215BRU-80/

AD9215BCP-80

AD9215BRU-105/

AD9215BCP-105

Test

Temp Level Min

Parameter

Typ Max Min

2.0

Typ

Max

Min

Typ Max

Unit

LOGIC INPUTS (CLK, PDWN)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

Full

IV

V

2.0

V

µA

pF

0.8

+10

0.8

+10

2

−650

−70

+10 −650

+10 −70

−650

−70

2

LOGIC OUTPUTS¹

DRVDD = 2.5 V

High Level Output Voltage

Low Level Output Voltage

Full

IV

2.45

0.05

2.45

V

0.05

¹Output voltage levels measured with a 5 pF load on each output.

Table 4. Switching Specifications

AD9215BRU-65/

AD9215BCP-65

AD9215BRU-80/

AD9215BCP-80

AD9215BRU-105/

AD9215BCP-105

Test

Temp Level

Unit

Parameter

Min

Typ

Max Min

Typ

Max Min

Typ

Max

CLOCK INPUT PARAMETERS

Maximum Conversion Rate

Minimum Conversion Rate

CLOCK Period

Full

VI

V

65

80

105

MSPS

ns

5

15.4

2.5

12.5

2.5

9.5

DATA OUTPUT PARAMETERS

Output Delay¹(t_OD

)

Full

25°C

VI

V

4.8

5

2.4

0.5

7

6.5

4.8

5

2.4

0.5

7

6.5

2.5

4.8

5

2.4

0.5

7

6.5

ns

Cycles

ns

ps rms

ms

Pipeline Delay (Latency)

Aperture Delay

Aperture Uncertainty (Jitter)

Wake-Up Time²

OUT-OF-RANGE RECOVERY TIME

1

Cycles

N+1

N

N+2

N+8

N–1

N+3

t_A

ANALOG

INPUT

N+7

N+4

N+6

N+5

CLK

DATA

OUT

N–7

N–6

N–5

N–4

N–3

N–2

N–1

N

N+1

N+2

t

PD

Figure 2. Timing Diagram

¹Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.

²Wake-up time is dependent on the value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.

Rev. B | Page 5 of 36

AD9215

Data Sheet

ABSOLUTE MAXIMUM RATINGS¹

Table 5.

EXPLANATION OF TEST LEVELS

With

Test Level

Mnemonic

ELECTRICAL

AVDD

DRVDD

AGND

Respect to Min Max

Unit

I

100% production tested.

AGND

DRGND

DRVDD

DRGND

AGND

−0.3 +3.9

−0.3 +0.3

−3.9 +3.9

−0.3 DRVDD + 0.3

−0.3 AVDD + 0.3

V

II

100% production tested at 25°C and sample tested at spec-

ified temperatures.

AVDD

III Sample tested only.

Digital Outputs

CLK, MODE

VIN+, VIN−

VREF

SENSE

REFB, REFT

PDWN

IV Parameter is guaranteed by design and characterization

testing.

V

Parameter is a typical value only.

VI 100% production tested at 25°C; guaranteed by design and

characterization testing for industrial temperature range;

100% production tested at temperature extremes for mili-

tary devices.

ENVIRONMENTAL²

Operating Temperature

Junction Temperature

Lead Temperature (10 sec)

Storage Temperature

−40

+85

150

°C

300

−65

+150

NOTES

¹Absolute maximum ratings are limiting values to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional

operability is not necessarily implied. Exposure to absolute maximum rating

conditions for an extended period of time may affect device reliability.

²Typical thermal impedances 28-lead TSSOP: θ_JA= 67.7°C/W, 32-lead LFCSP:

θ_JA= 32.7°C/W; heat sink soldered down to ground plane.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. B | Page 6 of 36

Data Sheet

AD9215

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OR

MODE

SENSE

VREF

REFB

REFT

AVDD

AGND

VIN+

D9 (MSB)

D8

1

2

3

4

5

6

7

8

9

28

27

26

25

24

DNC

CLK

DNC

PDWN

DNC

1

2

3

4

5

6

7

8

24 VREF

23 SENSE

22 MODE

21 OR

20 D9 (MSB)

19 D8

D7

D6

AD9215

TOP VIEW

(Not to Scale)

DRVDD

23 DRGND

22

AD9215

DNC

18 D7

17 D6

TOP VIEW

D5

(Not to Scale)

21 D4

20 D3

VIN– 10

AGND 11

AVDD 12

D2

19

18

17

16

15

D1

NOTES

1. DNC = DO NOT CONNECT.

D0 (LSB)

DNC

2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED

TO THE GROUND PLANE FOR THE LFCSP PACKAGE. THERE IS

AN INCREASED RELIABILITY OF THE SOLDER JOINTS, AND

THE MAXIMUM THERMAL CAPABILITY OF THE PACKAGE IS

ACHIEVED WITH THE EXPOSED PAD SOLDERED TO THE

CUSTOMER BOARD.

13

14

CLK

PDWN

DNC = DO NOT CONNECT

Figure 4. LFCSP (CP-32-7)

Figure 3. TSSOP (RU-28)

Table 6. Pin Function Descriptions

TSSOP Pin No.

LFCSP Pin No. Mnemonic Description

1

21

OR

Out-of-Range Indicator.

2

3

4

5

22

23

24

25

26

27, 32

28, 31

29

MODE

SENSE

VREF

REFB

REFT

AVDD

AGND

VIN+

VIN−

CLK

Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.

Reference Mode Selection.

Voltage Reference Input/Output.

Differential Reference (Negative).

Differential Reference (Positive).

Analog Power Supply.

Analog Ground.

Analog Input Pin (+).

Analog Input Pin (−).

Clock Input Pin.

6

7, 12

8, 11

9

10

13

30

2

14

15 to 16

17 to 22,

25 to 28

4

PDWN

DNC

D0 (LSB) to

D9 (MSB)

Power-Down Function Selection (Active High).

Do not connect, recommend floating this pin.

Data Output Bits.

1, 3, 5 to 8

9 to 14,

17 to 20

23

24

15

16

DRGND

DRVDD

Digital Output Ground.

Digital Output Driver Supply. Must be decoupled to DRGND with a

minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF.

N/A

33

EP

Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane

for the LFCSP package. There is an increased reliability of the solder joints, and the

maximum thermal capability of the package is achieved with the exposed pad soldered

to the customer board.

Rev. B | Page 7 of 36

AD9215

Data Sheet

EQUIVALENT CIRCUITS

AVDD

no missing codes to 10-bit resolution indicate that all 1024

codes, respectively, must be present over all operating ranges.

Effective Number of Bits (ENOB)

MODE

For a sine wave, SINAD can be expressed in terms of the num-

ber of bits. Using the following formula, it is possible to obtain a

measure of performance expressed as N, the effective number of

bits

Figure 5. Equivalent Analog Input Circuit

AVDD

N = (SINAD – 1.76)/6.02

Thus, the effective number of bits for a device for sine wave

inputs at a given input frequency can be calculated directly

from its measured SINAD.

MODE

20kΩ

Gain Error

Figure 6. Equivalent MODE Input Circuit

The first code transition should occur at an analog value 1/2

LSB above negative full scale. The last transition should occur at

an analog value 1 1/2 LSB below the positive full scale. Gain

error is the deviation of the actual difference between the first

and last code transitions and the ideal difference between the

first and last code transitions.

DRVDD

D9–D0,

OR

Integral Nonlinearity (INL)

Figure 7. Equivalent Digital Output Circuit

INL refers to the deviation of each individual code from a line

drawn from “negative full scale” through “positive full scale.”

The point used as negative full scale occurs 1/2 LSB before the

first code transition. Positive full scale is defined as a level 1 1/2

LSB beyond the last code transition. The deviation is measured

from the middle of each particular code to the true straight line.

AVDD

2.6kΩ

CLK

2.6kΩ

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Minimum Conversion Rate

Figure 8. Equivalent Digital Input Circuit

The clock rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed

limit.

DEFINITIONS OF SPECIFICATIONS

Aperture Delay

Aperture delay is a measure of the sample-and-hold amplifier

(SHA) performance and is measured from the rising edge of the

clock input to when the input signal is held for conversion.

Offset Error

The major carry transition should occur for an analog value 1/2

LSB below VIN+ = VIN−. Zero error is defined as the deviation

of the actual transition from that point.

Aperture Jitter

Aperture jitter is the variation in aperture delay for successive

samples and can be manifested as frequency-dependent noise

on the input to the ADC.

Out-of-Range Recovery Time

Out-of-range recovery time is the time it takes for the ADC to

reacquire the analog input after a transient from 10% above

positive full scale to 10% above negative full scale, or from 10%

below negative full scale to 10% below positive full scale.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the clock

pulse should be left in the Logic 1 state to achieve rated perfor-

mance. Pulse width low is the minimum time the clock pulse

should be left in the low state. At a given clock rate, these speci-

fications define an acceptable clock duty cycle.

Output Propagation Delay

The delay between the clock logic threshold and the time when

all bits are within valid logic levels.

Power Supply Rejection

Differential Nonlinearity (DNL, No Missing Codes)

The specification shows the maximum change in full scale from

the value with the supply at the minimum limit to the value

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed

Rev. B | Page 8 of 36

Data Sheet

AD9215

with the supply at its maximum limit.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference in dB between the rms amplitude of the

input signal and the peak spurious signal.

Signal-to-Noise and Distortion (SINAD) Ratio

SINAD is the ratio of the rms value of the measured input sig-

nal to the rms sum of all other spectral components below the

Nyquist frequency, including harmonics but excluding dc. The

value for SINAD is expressed in decibels.

Temperature Drift

The temperature drift for zero error and gain error specifies the

maximum change from the initial (25°C) value to the value at

T

_MINor T_MAX.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured input signal to

the rms sum of all other spectral components below the Nyquist

frequency, excluding the first six harmonics and dc. The value

for SNR is expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic com-

ponents to the rms value of the measured input signal and is

expressed as a percentage or in decibels.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product. It may be reported in dBc

(i.e., degrades as signal levels are lowered) or in dBFS (always

related back to converter full scale).

Rev. B | Page 9 of 36

AD9215

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.0 V, DRVDD = 2.5 V with DCS enabled, T_A= 25°C, 2 V differential input, A_IN= −0.5 dBFS, VREF = 1.0 V, unless

otherwise noted.

0

80

75

70

65

60

55

50

2V p-p SFDR (dBc)

AIN = –0.5dBFS

A

= –0.5dBFS

IN

SNR = 58.0

ENOB = 9.4 BITS

SFDR = 75.5dB

–20

–40

1V p-p SFDR (dBc)

–60

2V p-p SNR (dB)

–80

–100

–120

1V p-p SNR (dB)

0

6.56

13.13 19.69 26.25 32.81 39.38 45.94 52.50

FREQUENCY (MHz)

5

15

25

35

45

55

65

75

85

ENCODE (MSPS)

Figure 12. AD9215-80 SNR/SFDR vs. f_SAMPLE, f_IN= 10.3 MHz

Figure 9. Single-Tone 32k FFT with f_IN= 10.3 MHZ, f_SAMPLE= 105 MSPS

80

75

70

65

0

AIN = –0.5dBFS

2V p-p SFDR (dBc)

A

= –0.5dBFS

IN

SNR = 57.8

ENOB = 9.4 BITS

SFDR = 75.0dB

–20

–40

1V p-p SFDR (dBc)

–60

60

55

50

2V p-p SNR (dB)

1V p-p SNR (dB)

–80

–100

–120

5

15

25

35

45

55

65

0

6.56

13.13 19.69 26.25 32.81 39.38 45.94 52.50

FREQUENCY (MHz)

ENCODE (MSPS)

Figure 10. Single-Tone 32k FFT with f_IN= 70.3 MHz, f_SAMPLE= 105 MSPS

Figure 13. AD9215-65 SNR/SFDR vs. f_SAMPLE, f_IN= 10.3 MHz

85

0

A

= –0.5dBFS

2V p-p SFDR

IN

SNR = 57.7

ENOB = 9.3 BITS

SFDR = 75dB

–20

–40

80

75

70

65

60

55

–60

–80

–100

–120

2V p-p SNR

60

0

6.56

13.13 19.69 26.25 32.81 39.38 45.94 52.50

FREQUENCY (MHz)

0

20

40

80

100

f_SAMPLE(MSPS)

Figure 11. Single-Tone 32k FFT with f_IN= 100.3 MHz, f_SAMPLE= 105 MSPS

Figure 14. AD9215-105 SNR/SFDR vs. f_SAMPLE, f_IN= 10.3 MHz

Rev. B | Page 10 of 36

Data Sheet

AD9215

80

70

60

80

75

70

65

60

55

50

SFDR

80dB REFERENCE LINE

1V p-p SFDR (dBc)

50

40

2V p-p SNR (dB)

1V p-p SNR (dB)

2V p-p SFDR (dBc)

30

20

SNR

10

0

50

100

150

200

250

300

–50 –45 –40 –35 –30 –25 –20 –15 –10

–5

0

FREQUENCY (MHz)

ANALOG INPUT LEVEL

Figure 15. AD9215-80 SNR/SFDR vs.

Analog Input Drive Level, f_SAMPLE= 80 MSPS, f_IN= 39.1 MHz

Figure 18. AD9215-105 SNR/SFDR vs.

f_IN, A_IN= −0.5 dBFS, f_SAMPLE= 105 MSPS

85

80

75

70

65

60

55

70

60

50

40

30

20

10

0

2 SFDR dBc

2V p-p SFDR (dBc)

2V p-p SNR (dB)

–70dBFS

REFERENCE LINE

1V p-p SFDR (dBc)

1V p-p SNR

50

2V p-p

SNR

0

50

100

150

200

250

300

f_IN(MHz)

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

ANALOG INPUT LEVEL (–dBFS)

Figure 19. AD9215-80 SNR/SFDR vs.

f_IN, A_IN= −0.5 dBFS, f_SAMPLE= 80 MSPS

Figure 16. AD9215-105 SNR/SFDR vs.

Analog Input Drive Level, f_SAMPLE= 105 MSPS, f_IN= 50.3 MHz

80

1V p-p SFDR (dBc)

70

75

70

60

50

2V p-p SFDR (dBc)

80dB REFERENCE LINE

2V p-p SNR (dB)

40

65

60

55

50

30

20

1V p-p SNR (dB)

2V p-p SFDR (dBc)

2V p-p SNR (dB)

10

0

–50 –45 –40 –35 –30 –25 –20 –15 –10

–5

0

50

100

150

200

250

300

ANALOG INPUT LEVEL

ANALOG INPUT (MHz)

Figure 17. AD9215-65 SNR/SFDR vs.

Analog Input Drive Level, f_SAMPLE= 65 MSPS, f_IN= 30.3 MHz

Figure 20. AD9215-65 SNR/SFDR vs.

f_IN, A_IN= −0.5 dBFS, f_SAMPLE= 65 MSPS

Rev. B | Page 11 of 36

AD9215

Data Sheet

0

80

70

60

50

40

30

20

10

0

A

, A

= –7dBFS

IN1

IN2

SFDR = 74dBc

–20

SFDR

–40

–60

80dBFS REFERENCE LINE

–80

–100

–120

0

13.125

26.250

39.375

52.500

–5

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5

(dBFS)

FREQUENCY (MHz)

A

IN

Figure 21. Two-Tone 32k FFT with f_IN1= 70.1 MHz,

and f_IN2= 71.1 MHz, f_SAMPLE= 105 MSPS

Figure 24. AD9215-80 Two-Tone SFDR vs. A_IN, f_IN1= 100.3 MHz, and f_IN2

101.3 MHz, f_SAMPLE= 105 MSPS

=

0

–20

80

A

, A

= –7dBFS

IN1

IN2

SFDR = 74dBc

SFDR DCS ON

75

70

SFDR DCS OFF

–40

65

SNR DCS ON

60

55

50

–60

–80

45

SNR DCS OFF

–100

40

35

30

–120

0

13.125

26.250

FREQUENCY (MHz)

39.375

20

30

40

50

60

70

80

CLOCK DUTY CYCLE HIGH (%)

Figure 22. Two-Tone 32k FFT with f_IN1= 100.3 MHz,

and f_IN2= 101.3 MHz, f_SAMPLE= 105 MSPS

Figure 25. SINAD, SFDR vs.

Clock Duty Cycle, f_SAMPLE= 105 MSPS, f_IN= 50.3 MH

80

70

60

50

40

30

20

10

80

2V p-p SFDR (dBc)

75

70

65

60

55

50

SFDR

1V p-p SFDR (dBc)

80dBFS REFERENCE LINE

2V p-p SINAD

1V p-p SINAD

0

–65

–55

–45

–35

–25

–15

–40

–20

0

20

40

60

80

AIN1, AIN2 (dBFS)

TEMPERATURE (C)

Figure 23. AD9215-105 Two-Tone SFDR vs. A_IN,

_IN1= 70.1 MHz, and f_IN2= 71.1 MHz, f_SAMPLE= 105 MSPS

Figure 26. SINAD, SFDR vs. Temperature,

f_SAMPLE= 105 MSPS, f_IN= 50 MHz

f

Rev. B | Page 12 of 36

Data Sheet

AD9215

0.6

0.4

40

30

20

10

0.2

0

–10

–20

–30

–40

–0.2

–0.4

–0.6

0

128

256

384

512

640

768

896

1024

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

CODE

Figure 27. Gain vs. Temperature External 1 V Reference

Figure 29. AD9215-105 Typical INL, f_SAMPLE= 105 MSPS, f_IN= 2.3 MHz

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

128

256

384

512

640

768

896

1024

CODE

Figure 28. AD9215-105 Typical DNL, f_SAMPLE= 105 MSPS, f_IN= 2.3 MHz

Rev. B | Page 13 of 36

AD9215

Data Sheet

APPLYING THE AD9215 THEORY OF OPERATION

placed across the inputs to provide dynamic charging currents.

This passive network creates a low-pass filter at the ADC’s in-

put; therefore, the precise values are dependent upon the appli-

cation. In IF undersampling applications, any shunt capacitors

should be removed. In combination with the driving source

impedance, they would limit the input bandwidth.

The AD9215 architecture consists of a front-end SHA followed

by a pipelined switched capacitor ADC. Each stage provides

sufficient overlap to correct for flash errors in the preceding

stages. The quantized outputs from each stage are combined

into a final 10-bit result in the digital correction logic. The pipe-

lined architecture permits the first stage to operate on a new

input sample, while the remaining stages operate on preceding

samples. Sampling occurs on the rising edge of the clock.

The analog inputs of the AD9215 are not internally dc biased.

In ac-coupled applications, the user must provide this bias ex-

ternally. V_CM= AVDD /2 is recommended for optimum perfor-

mance, but the device functions over a wider range with rea-

sonable performance (see Figure 31).

The input stage contains a differential SHA that can be config-

ured as ac-coupled or dc-coupled in differential or single-ended

modes. Each stage of the pipeline, excluding the last, consists of

a low resolution flash ADC connected to a switched capacitor

DAC and interstage residue amplifier (MDAC). The residue

amplifier magnifies the difference between the reconstructed

DAC output and the flash input for the next stage in the pipe-

line. Redundancy is used in each one of the stages to facilitate

digital correction of flash errors.

85

80

2V p-p SFDR

75

70

65

60

The output-staging block aligns the data, carries out the error

correction, and passes the data to the output buffers. The output

buffers are powered from a separate supply, allowing adjust-

ment of the output voltage swing. During power-down, the

output buffers go into a high impedance state.

2V p-p SNR

55

50

45

40

Analog Input and Reference Overview

0.25

0.75

1.25

1.75

2.25

2.75

ANALOG INPUT COMMON-MODE VOLTAGE (V)

The analog input to the AD9215 is a differential switched

capacitor SHA that has been designed for optimum perfor-

mance while processing a differential input signal. The SHA

input can support a wide common-mode range and maintain

excellent performance, as shown in Figure 31. An input com-

mon-mode voltage of midsupply minimizes signal-dependent

errors and provides optimum performance.

Figure 31. AD9215-105 SNR, SFDR vs. Common-Mode Voltage

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC.

An internal differential reference buffer creates positive and

negative reference voltages, REFT and REFB, respectively, that

define the span of the ADC core. The output common mode of

the reference buffer is set to midsupply, and the REFT and

REFB voltages and span are defined as

H

T

0.5pF

VIN+

VIN–

C

PAR

REFT = 1/2 (AVDD + VREF)

T

REFB = 1/2 (AVDD − VREF)

0.5pF

C

Span = 2 × (REFT − REFB) = 2 × VREF

PAR

T

It can be seen from the equations above that the REFT and

REFB voltages are symmetrical about the midsupply voltage

and, by definition, the input span is twice the value of the VREF

voltage.

H

Figure 30. Switched-Capacitor SHA Input

The clock signal alternatively switches the SHA between sample

mode and hold mode (see Figure 30). When the SHA is

switched into sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current required from the output

stage of the driving source. Also, a small shunt capacitor can be

The internal voltage reference can be pin-strapped to fixed val-

ues of 0.5 V or 1.0 V or adjusted within the same range as dis-

cussed in the Internal Reference Connection section. Maximum

SNR performance is achieved with the AD9215 set to the largest

input span of 2 V p-p. The relative SNR degradation is 3 dB

Rev. B | Page 14 of 36

Data Sheet

AD9215

when changing from 2 V p-p mode to 1 V p-p mode.

AVDD

VIN+

R

The SHA may be driven from a source that keeps the signal

peaks within the allowable range for the selected reference volt-

age. The minimum and maximum common-mode input levels

are defined as

C

2Vp-p

49.9Ω

AD9215

VIN–

AGND

AVDD

1kΩ

VCM_MIN= VREF/2

0.1µF

VCM_MAX= (AVDD + VREF)/2

Figure 33. Differential Transformer-Coupled Configuration

The minimum common-mode input level allows the AD9215 to

accommodate ground-referenced inputs.

The signal characteristics must be considered when selecting a

transformer. Most RF transformers saturate at frequencies

below a few MHz, and excessive signal power can also cause

core saturation, which leads to distortion.

Although optimum performance is achieved with a differential

input, a single-ended source may be driven into VIN+ or VIN−.

In this configuration, one input accepts the signal, while the

opposite input should be set to midscale by connecting it to an

appropriate reference. For example, a 2 V p-p signal may be

applied to VIN+ while a 1 V reference is applied to VIN−. The

AD9215 then accepts a signal varying between 2 V and 0 V. In

the single-ended configuration, distortion performance may

degrade significantly as compared to the differential case. How-

ever, the effect is less noticeable at lower input frequencies.

Single-Ended Input Configuration

A single-ended input may provide adequate performance in

cost-sensitive applications. In this configuration, there is a deg-

radation in SFDR and distortion performance due to the large

input common-mode swing. However, if the source impedances

on each input are kept matched, there should be little effect on

SNR performance. Figure 34 details a typical single-ended input

configuration.

Differential Input Configurations

10µF

AVDD

As previously detailed, optimum performance is achieved while

driving the AD9215 in a differential input configuration. For

baseband applications, the AD8138 differential driver provides

excellent performance and a flexible interface to the ADC. The

output common-mode voltage of the AD8138 is easily set to

AVDD/2, and the driver can be configured in a Sallen Key filter

topology to provide band limiting of the input signal.

1kΩ

R

VIN+

0.1µF

1kΩ

2V p-p

49.9Ω

C

AD9215

AVDD

R

1kΩ

VIN–

AGND

10µF

0.1µF

Figure 34. Single-Ended Input Configuration

1kΩ

CLOCK INPUT AND CONSIDERATIONS

499Ω

AVDD

R

1kΩ

0.1µF

523Ω

499Ω

VIN+

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals, and as a result may be sensi-

tive to clock duty cycle. Commonly, a 5% tolerance is required

on the clock duty cycle to maintain dynamic performance char-

acteristics. The AD9215 contains a clock duty cycle stabilizer

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9215. As shown in Figure 25, noise and distortion per-

formance are nearly flat over a 50% range of duty cycle. For best

ac performance, enabling the duty cycle stabilizer is recom-

mended for all applications.

C

AD8138

AD9215

V

CM

R

VIN–

AGND

1V p-p

49.9Ω

499Ω

Figure 32. Differential Input Configuration Using the AD8138

At input frequencies in the second Nyquist zone and above, the

performance of most amplifiers is not adequate to achieve the

true performance of the AD9215. This is especially true in IF

undersampling applications where frequencies in the 70 MHz to

200 MHz range are being sampled. For these applications, differ-

ential transformer coupling is the recommended input configura-

tion. The value of the shunt capacitor is dependant on the input

frequency and source impedance and should be reduced or re-

moved. An example of this is shown in Figure 33.

The duty cycle stabilizer uses a delay-locked loop (DLL) to cre-

ate the nonsampling edge. As a result, any changes to the sam-

pling frequency require approximately 100 clock cycles to allow

the DLL to acquire and lock to the new rate.

Rev. B | Page 15 of 36

AD9215

Data Sheet

Table 7. Reference Configuration Summary

External SENSE

Connection

Internal Op Amp

Configuration

Resulting VREF Resulting Differential Span

Selected Mode

(V)

N/A

0.5

(V p-p)

Externally Supplied Reference AVDD

N/A

2 × External Reference

1.0

Internal 0.5 V Reference

Programmed Variable

Reference

VREF

External Divider

Voltage Follower (G = 1)

Noninverting (1 < G < 2)

0.5 × (1 + R2/R1) 2 × VREF

Internally Programmed 1 V

Reference

AGND to 0.2 V

Internal Divider

1.0

2.0

Table 8. Digital Output Coding

Code VIN+ − VIN− Input Span = VIN+ − VIN− Input Span =

Digital Output Offset Binary

Digital Output Twos

2 V p-p (V)

1 V p-p (V)

(D9••••••D0)

Complement (D9••••••D0)

1023 1.000

0.500

0

−0.000978

−0.5000

11 1111 1111

10 0000 0000

01 1111 1111

00 0000 0000

01 1111 1111

00 0000 0000

11 1111 1111

10 0000 0000

512

511

0

−0.00195

−1.00

number of output bits switching, which are determined by the

encode rate and the characteristics of the analog input signal.

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR at a given full-scale

input frequency (f_INPUT) due only to aperture jitter (t_A) can be

calculated with the following equation

Digital power consumption can be minimized by reducing the

capacitive load presented to the output drivers. The data in Fig-

ure 35 was taken with a 5 pF load on each output driver.

SNR Degradation = 20 × log₁₀[2 × π × f_INPUT× t_A]

15

13

11

9

40

35

30

25

20

15

AD9215-105 I

In the equation, the rms aperture jitter, t_A, represents the root-

sum square of all jitter sources, which include the clock input,

analog input signal, and ADC aperture jitter specification.

Undersampling applications are particularly sensitive to jitter.

AVDD

AD9215-65/80 I

AVDD

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the

AD9215. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter, crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other

methods), it should be retimed by the original clock at the last

step.

7

5

3

I

1

DRVDD

–1

105

5

15

25

35

45

55

65

75

85

95

f_SAMPLE(MSPS)

Figure 35. Supply Current vs. f_SAMPLEfor f_IN= 10.3 MHz

Power Dissipation and Standby Mode

The analog circuitry is optimally biased so that each speed

grade provides excellent performance while affording reduced

power consumption. Each speed grade dissipates a baseline

power at low sample rates that increases linearly with the clock

frequency.

As shown in Figure 35, the power dissipated by the AD9215 is

proportional to its sample rate. The digital power dissipation

does not vary substantially between the three speed grades

because it is determined primarily by the strength of the digital

drivers and the load on each output bit. The maximum DRVDD

current can be calculated as

By asserting the PDWN pin high, the AD9215 is placed in

standby mode. In this state, the ADC typically dissipates 1 mW

if the CLK and analog inputs are static. During standby, the

output drivers are placed in a high impedance state. Reasserting

the PDWN pin low returns the AD9215 into its normal opera-

tional mode.

I_DRVDD= V_DRVDD× C_LOAD× f_CLOCK× N

where N is the number of output bits, 10 in the case of the

AD9215. This maximum current is for the condition of every

output bit switching on every clock cycle, which can only occur

for a full-scale square wave at the Nyquist frequency, f_CLOCK/2. In

practice, the DRVDD current is established by the average

In standby mode, low power dissipation is achieved by shutting

down the reference, reference buffer, and biasing networks. The

Rev. B | Page 16 of 36

Data Sheet

AD9215

decoupling capacitors on REFT and REFB are discharged when

entering standby mode and then must be recharged when

returning to normal operation. As a result, the wake-up time is

related to the time spent in standby mode, and shorter standby

cycles result in proportionally shorter wake-up times. With the

recommended 0.1 μF and 10 μF decoupling capacitors on REFT

and REFB, it takes approximately one second to fully discharge

the reference buffer decoupling capacitors and 7 ms to restore

full operation.

R2

R1











VREF  0.5 1



VIN+

VIN–

REFT

0.1F

REFB

ADC

CORE

10F

0.1F

VREF

Digital Outputs

+

7k

The AD9215 output drivers can be configured to interface with

2.5 V or 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic. The output drivers are sized to

provide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fanouts may require external buffers or latches.

10F

0.1F

0.5V

SELECT

LOGIC

SENSE

7k

AD9215

Figure 36. Internal Reference Configuration

Timing

In all reference configurations, REFT and REFB drive the ADC

conversion core and establish its input span. The input range of

the ADC always equals twice the voltage at the reference pin for

either an internal or an external reference.

The AD9215 provides latched data outputs with a pipeline delay

of five clock cycles. Data outputs are available one propagation

delay (t_OD) after the rising edge of the clock signal. Refer to Fig-

ure 2 for a detailed timing diagram.

VIN+

The length of the output data lines and loads placed on them

should be minimized to reduce transients within the AD9215;

these transients can detract from the converter’s dynamic per-

formance.

VIN–

REFT

0.1F

ADC

CORE

0.1F

10F

REFB

The lowest typical conversion rate of the AD9215 is 5 MSPS. At

clock rates below 5 MSPS, dynamic performance may degrade.

0.1F

VREF

+

10F

0.1F

0.5V

R2

Voltage Reference

SELECT

LOGIC

A stable and accurate 0.5 V voltage reference is built into the

AD9215. The input range can be adjusted by varying the refer-

ence voltage applied to the AD9215, using either the internal

reference or an externally applied reference voltage. The input

span of the ADC tracks reference voltage changes linearly. Max-

imum SNR and DNL performance is achieved with the AD9215

set to the largest input span of 2 V p-p.

SENSE

R1

AD9215

Figure 37. Programmable Reference Configuration

If the internal reference of the AD9215 is used to drive multiple

converters to improve gain matching, the loading of the refer-

ence by the other converters must be considered. Figure 38 de-

picts how the internal reference voltage is affected by loading.

Internal Reference Connection

A comparator within the AD9215 detects the potential at the

SENSE pin and configures the reference into four possible

states, which are summarized in Table 1. If SENSE is grounded,

the reference amplifier switch is connected to the internal resis-

tor divider (see Figure 36), setting VREF to 1 V. Connecting the

SENSE pin to the VREF pin switches the amplifier output to the

SENSE pin, configuring the internal op amp circuit as a voltage

follower and providing a 0.5 V reference output. If an external

resistor divider is connected as shown in Figure 37, the switch is

again set to the SENSE pin. This puts the reference amplifier in a

noninverting mode with the VREF output defined as

Rev. B | Page 17 of 36

AD9215

Data Sheet

0.05

Operational Mode Selection

As discussed earlier, the AD9215 can output data in either offset

binary or twos complement format. There is also a provision for

enabling or disabling the clock duty cycle stabilizer (DCS). The

MODE pin is a multilevel input that controls the data format

and DCS state. For best ac performance, enabling the duty cycle

stabilizer is recommended for all applications. The input

threshold values and corresponding mode selections are out-

lined in Table 9.

0

VREF = 0.5V

–0.05

–0.10

–0.15

–0.20

VREF = 1.0V

As detailed in Table 9, the data format can be selected for either

offset binary or twos complement.

–0.25

0

0.5

1.0

1.5

(mA)

2.0

2.5

3.0

Table 9. Mode Selection

I

LOAD

MODE Voltage

Data Format

Duty Cycle Stabilizer

Disabled

Enabled

Disabled

Figure 38. VREF Accuracy vs. Load

External Reference Operation

AVDD

2/3 AVDD

1/3 AVDD

AGND (Default)

Twos Complement

Offset Binary

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. When multiple ADCs track one another, a single refer-

ence (internal or external) may be necessary to reduce gain

matching errors to an acceptable level. A high precision external

reference may also be selected to provide lower gain and offset

temperature drift. Figure 39 shows the typical drift characteris-

tics of the internal reference in both 1 V and 0.5 V modes.

0.6

Offset Binary

The MODE pin is internally pulled down to AGND by a 20 kΩ

resistor.

EVALUATION BOARD

The AD9215 evaluation board is no longer in production. The

following evaluation board documentation is provided for in-

formational purposes only.

The AD9215 evaluation board provides all of the support cir-

cuitry required to operate the ADC in its various modes and

configurations. The converter can be driven differentially

through an AD8351 driver, a transformer, or single-ended. Sep-

arate power pins are provided to isolate the DUT from the sup-

port circuitry. Each input configuration can be selected by

proper connection of various jumpers (refer to the schematics).

Figure 40 shows the typical bench characterization setup used

to evaluate the ac performance of the AD9215. It is critical that

signal sources with very low phase noise (<1 ps rms jitter) be

used to realize the ultimate performance of the converter. Prop-

er filtering of the input signal, to remove harmonics and lower

the integrated noise at the input, is also necessary to achieve the

specified noise performance.

0.5

VREF = 0.5V

0.4

0.3

VREF = 1.0V

0.2

0.1

0

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 39. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7 kΩ load. The internal buffer still generates the positive and

negative full-scale references, REFT and REFB, for the ADC

core. The input span is always twice the value of the reference

voltage; therefore, the external reference must be limited to a

maximum of 1 V.

Complete schematics and layout plots follow that demonstrate

the proper routing and grounding techniques that should be

applied at the system level.

3.0V

2.5V

5.0V

–

+

–

+

–

+

–

+

AVDD GND DRVDD GND

V

VAMP

P12

DL

R AND S SMG, 2V p-p

SIGNAL SYNTHESIZER

BAND-PASS

FILTER

XFMR

INPUT

REFIN

DATA

CAPTURE

AND

AD9215

EVALUATION BOARD

10MHz

REFOUT

PROCESSING

R AND S SMG, 2V p-p

SIGNAL SYNTHESIZER

CLK

Figure 40. Evaluation Board Connections

Rev. B | Page 18 of 36

Data Sheet

AD9215

P 2

5 . 0 V

2 . 5 V

V A M P

V D L

G N D

2 . 5 V

3 . 0 V

D R V D D

G N D

A V D D

D 6

D 7

D 8

D 9

O R

1 7

1 8

8

D N C

7

D N C

1 9

2 0

2 1

2 2

2 3

6

D N C

5

P D W N

4

D N C

M O D E

3

C L K

2

S E N S E

V R E F

D N C

2 4

1

Figure 41. LFCSP Evaluation Board Schematic, Analog Inputs and DUT

Rev. B | Page 19 of 36

AD9215

Data Sheet

Figure 42. LFCSP Evaluation Board, Digital Path

Rev. B | Page 20 of 36

Data Sheet

AD9215

Figure 43. LFCSP Evaluation Board Schematic, Clock Input

Rev. B | Page 21 of 36

AD9215

Data Sheet

Figure 44. LFCSP Evaluation Board Layout, Primary Side

Figure 45. LFCSP Evaluation Board Layout, Secondary Side

Rev. B | Page 22 of 36

Data Sheet

AD9215

Figure 47. LFCSP Evaluation Board Layout, Power Plane

Figure 46. LFCSP Evaluation Board Layout, Ground Plane

Rev. B | Page 23 of 36

AD9215

Data Sheet

Figure 48. LFCSP Evaluation Board Layout, Primary Silkscreen

Figure 49. LFCSP Evaluation Board Layout, Secondary Silkscreen

Rev. B | Page 24 of 36

Data Sheet

AD9215

Table 10. LFCSP Evaluation Board Bill of Materials (BOM)

Recommended Vendor/

Part Number

Item Qty Omit¹Reference Designator

Device

Package

Value

1

18

C1, C5, C7, C8, C9, C11,

Chip Capacitor

0603

0.1 μF

C12, C13, C15, C16, C31, C33,

C34, C36, C37, C41, C43, C47

8

2

C6, C18, C27, C17,

C28, C35, C45, C44

2

8

C2, C3, C4, C10,

C20, C22, C25, C29

Tantalum Capacitor

TAJD

10 μF

C46, C24,

3

4

C14, C30, C32, C38,

C39 C40, C48, C49

Chip Capacitor

0603

0.001

μF

1

2

1

9

C19

10 pF

C21, C23

C26

5

6

Chip Capacitor

Header

0603

10 pF

E31, E35, E43, E44,

E50, E51, E52, E53

EHOLE

Jumper Blocks

2

E1, E45

J1, J2

L1

7

8

2

1

SMA Connector/50 Ω

Inductor

SMA

0603

10 nH

Coilcraft/0603CS-

10NXGBU

9

1

5

P2

Terminal Block

TB6

Wieland/25.602.2653.0

z5-530-0625-0

10

11

P12

Header Dual 20-Pin RT

Angle

HEADER40

0603

Digi-Key S2131-20-ND

R3, R12, R23, R18, RX

R37, R22, R42, R16, R17, R27

R4, R15

Chip Resistor

0 Ω

6

1

12

13

2

Chip Resistor

0603

33 Ω

1 Ω

14

R5, R6, R7, R8, R13, R20, R21, R24,

R25, R26, R30, R31, R32, R36

14

15

2

1

R10, R11

R29

Chip Resistor

0603

36 Ω

50 Ω

R19

16

2

RP1, RR2

Resistor Pack

ADT1-1WT

R_742

220 Ω

Digi-Key

CTS/742C163220JTR

17

18

1

T1

AWT1-T1

TSSOP-48

Mini-Circuits

U1

74LVTH162374 CMOS

Register

19

20

21

22

23

24

25

26

27

28

1

U4

AD9215BCP ADC (DUT) CSP-32

Analog Devices, Inc.

Fairchild

U5

74VCX86M

SOIC-14

PCB

AD9XXBCP/PCB

AD8351 Op Amp

MACOM Transformer

Chip Resistor

Analog Devices, Inc.

MACOM/ETC1-1-13

1

5

3

2

1

U3

MSOP-8

T2

ETC1-1-13 1-1 TX

R9, R1, R2, R38, R39

R18, R14, R35

R40, R41

0603

Select

25 Ω

Chip Resistor

10 kΩ

1.2 kΩ

110 Ω

R34

Chip Resistor

R33

Chip Resistor

¹These items are included in the PCB design but are omitted at assembly.

Rev. B | Page 25 of 36

AD9215

Data Sheet

P 2

0 - 4 A 8

0 2 8 7 4 -

V A M P

5 . 0 V

3 . 0 V

V D L

G N D

3 . 0 V

V C L K

G N D

D R V D D 2 . 5 V

G N D

A V D D

3 . 0 V

E 2 8

E 2 6

E 2 9

E 2 5

E 2 7

E 2 4

E 2 1

E 2 0

E 1 8

E 2 2

E 2 3

E 1 9

E 1 6

E 1 7

Figure 50. TSSOPP Evaluation Board Schematic, Analog Inputs and DUT

Rev. B | Page 26 of 36

Data Sheet

AD9215

0 2

+

Figure 51. TSSOP Evaluation Board, Digital Path

Rev. B | Page 27 of 36

AD9215

Data Sheet

0 - 5 0

0 2 8 7 4 - A

Figure 52. TSSOP Evaluation Board Schematic, Clock Input

Rev. B | Page 28 of 36

Data Sheet

AD9215

Figure 53. TSSOP Evaluation Board Layout, Primary Side

Figure 55. TSSOP Evaluation Board Layout, Ground Plane

Figure 56. TSSOP Evaluation Board Layout, Power Plane

Figure 54. TSSOP Evaluation Board Layout, Secondary Side

Rev. B | Page 29 of 36

AD9215

Data Sheet

Figure 57. TSSOP Evaluation Board Layout, Primary Silkscreen

Figure 58. TSSOP Evaluation Board Layout, Secondary Silkscreen

Rev. B | Page 30 of 36

Data Sheet

AD9215

Table 11. TSSOP Evaluation Board Bill of Materials (BOM)

Recommended

Vendor/Part No.

Item Qty. Omit Reference Designator

Device

Package

Value

1

11

C2 to C4, C10, C20,

C25, C27, C29,

C47, C50, C52

Tantalum Capacitor

TAJD

10 μF

C47

2

3

2

C5,C8

C31

Chip Capacitor

0603

10 pF

0.1 μF

1

15

C6, C9, C13,

C15 to C18, C21, C24,

C26, C30, C32, C34, C36,

C40, C46, C48, C51

4

5

3

6

C12, C14, C23, C28

Chip Capacitor

0603

Select

8

C7, C19, C35, C19,

C37 to C39, C49

0.001 μF

6

C1,C33, C41 to C42,

C44 to C5

BCAP0402

0402

0.1 μF

7

8

9

1

C43

C11

BCAP0402

BCAP0603

BRES603

0402

0603

0.001 μF

Select

1 kΩ

11

4

R2, R8 to R11, R24,

R26, R29, R39, R41 to R45

0603A

2

8

R48, R49

10

11

R6, R25, R34, R37

BRES603

0603A

0 Ω

R5, R35, R17 to R18,

R27 to R28, R38, R52

2

R7, R40

50 Ω

1

R14

12

13

14

15

16

17

18

19

20

21

22

23

2

1

2

R19, R21

BRES603

RES0603

0603A

0603

33 Ω

R32, R33

36 Ω

R16

BRES603

Potentiometer

Resister Pack

Select

10 kΩ

Select

1 kΩ

R4, R15,

0603

4

2

4

1

R20, R22 to R23, R47

0603A

0603

R48, R49

R36, R46, R50 to R51

0603

25 Ω

R31

0603

100 Ω

1.2 kΩ

5 kΩ

R30

0603

R3

0603

R1

RJ24FW

220Ω

10 kΩ

742C163221

4

RP1 to RP4

Rev. B | Page 31 of 36

AD9215

Data Sheet

Recommended

Vendor/Part No.

Item Qty. Omit Reference Designator

Device

Package

Value

24

25

26

27

1

L1

Chip Inductor

0603

10 nH

Coilcraft/0603CS-

10NXGBU

T1

U1

U2

1:1 RF Transformer

ADC

CD542

Mini-Circuits

AWT1-1T

28TSSOP

Analog Devices, Inc.

AD9215

Right Angle 40-Pin Header

Samtec

TSW-120-08-T-D-RA

28

29

30

2

1

U3, U4

U5

Octal D-Type Flip-Flop

Quad XOR Gate

Fairchild 74LVT57MSA

Fairchild 74VCX86M

SO14

1

U6

High Speed Amplifier

SOMB10

Analog Devices, Inc.

AD8351ARM

31

32

2

J1, J3

J4

SMB Connecter

SMBP

P1, P2

Power Connector

PTMICRO4

Weiland

Z5.531.3425.0 Posts

25.602.5453.0 Top

33

34

26

E1/E5, E2/E3, E4/E8,

E9/E11, E6/E7, E16/E17,

E19/E22, E18/E23, E21/20,

E35/E51, E36/E50, E43/E53,

E44/E52

Headers/Jumper Blocks

TSW-120-07-G-S

SMT-100-BK-G

12

E24/E27, E25/E26, E28/E29,

E13/E14/E30, E12/E32/E45

Wirehole

Rev. B | Page 32 of 36

Data Sheet

AD9215

OUTLINE DIMENSIONS

9.80

9.70

9.60

28

15

4.50

4.40

4.30

6.40 BSC

1

14

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

8°

0°

0.75

0.60

0.45

0.30

0.19

0.20

0.09

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AE

Figure 59. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

25

24

32

1

INDICATOR

0.50

BSC

3.25

3.10 SQ

2.95

EXPOSED

PAD

17

16

8

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

Figure 60. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-7)

Dimensions shown in millimeters

Rev. B | Page 33 of 36

AD9215

Data Sheet

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +85°C

Package Description

Package Option

RU-28

CP-32-7

AD9215BRUZ-65

AD9215BRUZ-80

AD9215BRUZ-105

AD9215BRUZRL7-65

AD9215BRUZRL7-80

AD9215BRUZRL7-105

AD9215BCPZ-65

AD9215BCPZ-80

AD9215BCPZ-105

28-Lead Thin Shrink Small Outline Package (TSSOP)

32-Lead Lead Frame Chip Scale Package (LFCSP_WQ)

¹Z = RoHS Compliant Part.

Rev. B | Page 34 of 36

Data Sheet

NOTES

AD9215

Rev. B | Page 35 of 36

AD9215

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D02874-0-2/13(B)

Rev. B | Page 36 of 36

型号:	AD9215BRUZ-105
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	ROCHESTER ELECTRONICS LLC
零件包装代码：	TSSOP
包装说明：	PLASTIC, MO-153AE, TSSOP-28
针数：	28
Reach Compliance Code：	unknown
风险等级：	5.82
转换器类型：	ADC, FLASH METHOD
JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3
长度：	9.7 mm
最大线性误差 (EL)：	0.1172%
湿度敏感等级：	1
模拟输入通道数量：	1
位数：	10
功能数量：	1
端子数量：	28
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出位码：	OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：	PARALLEL, WORD
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
采样速率：	105 MHz
采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	1.2 mm
标称供电电压：	3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	4.4 mm

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