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  • AD9224ARSZ图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
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  • 深圳市芯福林电子有限公司

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  • 深圳市芯鹏泰科技有限公司

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  • AD9224ARSZ
  • 数量7536 
  • 厂家Analog Devices Inc. 
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  • AD9224ARSZ
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  • AD9224ARSZRL
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  • 深圳市羿芯诚电子有限公司

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  • 深圳市和诚半导体有限公司

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  • AD9224ARSZ
  • 数量5600 
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  • 深圳市得捷芯城科技有限公司

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  • AD9224ARSZ
  • 数量4250 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • AD9224ARSZ
  • 数量28000 
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  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • AD9224ARSZ
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  • 集好芯城

     该会员已使用本站13年以上
  • AD9224ARSZ
  • 数量15252 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • AD9224ARSZ
  • 数量15862 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • AD9224ARSZ
  • 数量15862 
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  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
  • AD9224ARSZ
  • 数量2015 
  • 厂家ADI 
  • 封装SOP/DIP 
  • 批号18998 
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • AD9224ARSZ
  • 数量13497 
  • 厂家ADI(亚德诺) 
  • 封装SSOP28 
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  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
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  • 数量98622 
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  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • AD9224ARSZ
  • 数量26700 
  • 厂家ADI(亚德诺) 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • AD9224ARSZ
  • 数量12500 
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     该会员已使用本站12年以上
  • AD9224ARSZ
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产品型号AD9224ARSZ的概述

AD9224ARSZ芯片概述 AD9224ARSZ是一款高性能、广泛应用的逐次逼近型模数转换器(ADC),由Analog Devices公司设计和生产。该芯片以其高分辨率和快速转换速率在音频、通信、仪器仪表及图像处理等领域展现出优异的性能。AD9224ARSZ使用先进的工艺技术,保证了其在多种应用中的可靠性和优越性。 AD9224是一款12位ADC,具有高达20 MSPS的采样率,适合处理高频信号。其输入范围和动态范围设计适合多种信号源。高效的电源管理设计使得该芯片在性能和功耗之间达成了良好的平衡,用户可以根据需求灵活选择工作模式。 芯片AD9224ARSZ的详细参数 在详细的技术规格中,AD9224ARSZ拥有许多值得注意的参数。以下是该芯片的主要特点: 1. 分辨率:12位 2. 采样率:最高20 MSPS 3. 输入电压范围:0 to 2V 4. 信噪比:68 dB 5. 功耗:...

产品型号AD9224ARSZ的Datasheet PDF文件预览

Complete 12-Bit, 40 MSPS  
Monolithic A/D Converter  
a
AD9224  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Monolithic 12-Bit, 40 MSPS A/D Converter  
Low Power Dissipation: 415 mW  
Single +5 V Supply  
No Missing Codes Guaranteed  
Differential Nonlinearity Error: ؎0.33 LSB  
Complete On-Chip Sample-and-Hold Amplifier and  
Voltage Reference  
DRVDD  
AVDD  
CLK  
SHA  
VINA  
VINB  
MDAC1  
GAIN = 16  
MDAC2  
GAIN = 4  
MDAC3  
GAIN = 4  
5
3
3
A/D  
A/D  
A/D  
A/D  
CML  
CAPT  
CAPB  
5
3
4
3
DIGITAL CORRECTION LOGIC  
Signal-to-Noise and Distortion Ratio: 68.3 dB  
Spurious-Free Dynamic Range: 81 dB  
Out-of-Range Indicator  
Straight Binary Output Data  
28-Lead SSOP Package  
12  
VREF  
OUTPUT BUFFERS  
OTR  
SENSE  
BIT 1  
(MSB)  
1V  
MODE  
SELECT  
BIT 12  
(LSB)  
AD9224  
DRVSS  
REFCOM  
AVSS  
Compatible with 3 V Logic  
PRODUCT DESCRIPTION  
A single clock input is used to control all internal conversion  
cycles. The digital output data is presented in straight binary  
output format. An out-of-range signal indicates an overflow  
condition which can be used with the most significant bit to  
determine low or high overflow.  
The AD9224 is a monolithic, single supply, 12-bit, 40 MSPS,  
analog-to-digital converter with an on-chip, high performance  
sample-and-hold amplifier and voltage reference. The AD9224  
uses a multistage differential pipelined architecture with output  
error correction logic to provide 12-bit accuracy at 40 MSPS  
data rates, and guarantees no missing codes over the full operat-  
ing temperature range.  
PRODUCT HIGHLIGHTS  
The AD9224 is fabricated on a very cost effective CMOS  
process. High speed precision analog circuits are now combined  
with high density logic circuits.  
The AD9224 combines a low cost high speed CMOS process  
and a novel architecture to achieve the resolution and speed of  
existing bipolar implementations at a fraction of the power  
consumption and cost.  
The AD9224 offers a complete single-chip sampling 12-bit,  
40 MSPS analog-to-digital conversion function in 28-lead  
SSOP package.  
The input of the AD9224 allows for easy interfacing to both  
imaging and communications systems. With a truly differential  
input structure, the user can select a variety of input ranges and  
offsets, including single-ended applications. The dynamic per-  
formance is excellent.  
Low Power—The AD9224 at 415 mW consumes a fraction of  
the power of presently available in existing monolithic solutions.  
On-Board Sample-and-Hold (SHA)—The versatile SHA  
input can be configured for either single-ended or differential  
inputs.  
The sample-and-hold (SHA) amplifier is well suited for both  
multiplexed systems that switch full-scale voltage levels in suc-  
cessive channels and sampling single-channel inputs at frequen-  
cies up to and well beyond the Nyquist rate.  
Out of Range (OTR)—The OTR output bit indicates when  
the input signal is beyond the AD9224’s input range.  
Single Supply—The AD9224 uses a single +5 V power supply  
simplifying system power supply design. It also features a sepa-  
rate digital driver supply line to accommodate 3 V and 5 V logic  
families.  
The AD9224’s wideband input, combined with the power and  
cost savings over previously available monolithics, is suitable for  
applications in communications, imaging and medical ultrasound.  
The AD9224 has an onboard programmable reference. An  
external reference can also be chosen to suit the dc accuracy  
and temperature drift requirements of the application.  
Pin Compatibility—The AD9224 is pin compatible with the  
AD9220, AD9221, AD9223 and AD9225 ADCs.  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1999  
AD9224–SPECIFICATIONS  
DC SPECIFICATIONS  
Parameter  
(AVDD = +5 V, DRVDD = +3 V, fSAMPLE = 40 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, TMIN to TMAX unless otherwise noted)  
Min  
12  
Typ  
Max  
Units  
Bits  
RESOLUTION  
MAX CONVERSION RATE  
40  
MHz  
INPUT REFERRED NOISE  
VREF = 1.0 V  
VREF = 2.0 V  
0.35  
0.17  
LSB rms  
LSB rms  
ACCURACY  
Integral Nonlinearity (INL)  
Differential Nonlinearity (DNL)  
No Missing Codes Guaranteed  
Zero Error (@ +25°C)  
±1.5  
±0.33  
±2.5  
±1.0  
LSB  
LSB  
Bits  
% FSR  
% FSR  
% FSR  
12  
±0.12  
±0.3  
±0.4  
±0.3  
±2.2  
±1.6  
Gain Error (@ +25°C)1  
Gain Error (@ +25°C)2  
TEMPERATURE DRIFT  
Zero Error  
±2  
±26  
±0.4  
ppm/°C  
ppm/°C  
ppm/°C  
Gain Error1  
Gain Error2  
POWER SUPPLY REJECTION  
AVDD (+5 V ± 0.25 V)  
±0.07  
±0.24  
% FSR  
ANALOG INPUT  
Input Span (VREF = 1 V)  
(VREF = 2 V)  
2
4
V p-p  
V p-p  
V
Input (VINA or VINB) Range  
0
AVDD  
Input Capacitance  
10  
pF  
INTERNAL VOLTAGE REFERENCE  
Output Voltage (1 V Mode)  
1.0  
V
Output Voltage Tolerance (1 V Mode)  
Output Voltage (2.0 V Mode)  
Output Voltage Tolerance (2.0 V Mode)  
Output Current (Available for External Loads)  
Load Regulation3  
±5  
2.0  
±10  
1.0  
±1.0  
±17  
±35  
±3.4  
mV  
V
mV  
mA  
mV  
REFERENCE INPUT RESISTANCE  
5
kΩ  
POWER SUPPLIES  
Supply Voltages  
AVDD  
4.75  
2.85  
5
5.25  
5.25  
V (±5% AVDD Operating)  
V (±5% DRVDD Operating)  
DRVDD  
Supply Current  
IAVDD  
IDRVDD  
82  
4.3  
87  
5
mA (2 V Internal VREF)  
mA (2 V Internal VREF)  
POWER CONSUMPTION  
415  
425  
445  
450  
mW (1 V Internal Ref)  
mW (2 V Internal Ref)  
NOTES  
1Includes internal voltage reference error.  
2Excludes internal voltage reference error.  
3Load regulation with 1 mA load current (in addition to that required by the AD9224).  
Specifications subject to change without notice.  
–2–  
REV. A  
AD9224  
AC SPECIFICATIONS (AVDD = +5 V, DRVDD = +3 V, fSAMPLE = 40 MSPS, VREF= 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted)  
Parameter  
Min  
Typ  
Max  
Units  
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)  
fINPUT = 2.5 MHz  
fINPUT = 10 MHz  
65  
63.5  
68.3  
68.0  
dB  
dB  
SIGNAL-TO-NOISE RATIO (SNR)  
fINPUT = 2.5 MHz  
fINPUT = 10 MHz  
65.3  
64.6  
69.1  
68.4  
dB  
dB  
TOTAL HARMONIC DISTORTION (THD)  
f
INPUT = 2.5 MHz  
–80  
–78  
–71  
–67.4  
dB  
dB  
fINPUT = 10 MHz  
SPURIOUS FREE DYNAMIC RANGE  
f
INPUT = 2.5 MHz  
71.1  
67.9  
81  
79  
120  
120  
1
dB  
dB  
MHz  
MHz  
ns  
fINPUT = 10 MHz  
Full Power Bandwidth  
Small Signal Bandwidth  
Aperture Delay  
Aperture Jitter  
4
ps rms  
Specifications subject to change without notice.  
(AVDD = +5 V, DRVDD = +5 V, unless otherwise noted)  
DIGITAL SPECIFICATIONS  
Parameters  
Symbol  
Min  
Typ  
Max  
Units  
LOGIC INPUTS  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current (VIN = DRVDD)  
Low Level Input Current (VIN = 0 V)  
Input Capacitance  
VIH  
VIL  
IIH  
IIL  
CIN  
+3.5  
V
V
µA  
µA  
pF  
+1.0  
+10  
+10  
–10  
–10  
5
LOGIC OUTPUTS (With DRVDD = 5 V)  
High Level Output Voltage (IOH = 50 µA)  
High Level Output Voltage (IOH = 0.5 mA)  
Low Level Output Voltage (IOL = 1.6 mA)  
Low Level Output Voltage (IOL = 50 µA)  
Output Capacitance  
VOH  
VOH  
VOL  
VOL  
COUT  
+4.5  
+2.4  
V
V
V
V
+0.4  
+0.1  
5
pF  
LOGIC OUTPUTS (With DRVDD = 3 V)  
High Level Output Voltage (IOH = 50 µA)  
High Level Output Voltage (IOH = 0.5 mA)  
Low Level Output Voltage (IOL = 1.6 mA)  
Low Level Output Voltage (IOL = 50 µA)  
VOH  
VOH  
VOL  
VOL  
+2.95  
+2.80  
V
V
V
V
+0.4  
+0.05  
Specifications subject to change without notice.  
(TMIN to TMAX with AVDD = + 5 V, DRVDD = +5 V, CL = 20 pF)  
SWITCHING SPECIFICATIONS  
Parameters  
Symbol  
Min  
Typ  
Max  
Units  
Clock Period1  
tC  
25  
ns  
ns  
ns  
ns  
CLOCK Pulsewidth High2  
CLOCK Pulsewidth Low  
Output Delay  
tCH  
tCL  
tOD  
12.37  
12.37  
13  
Pipeline Delay (Latency)  
3
Clock Cycles  
NOTES  
1The clock period may be extended to 1 ms without degradation in specified performance @ +25°C.  
2For operation at 40 MHz, the clock must be held to 50% duty cycle. See section on clock shaping in text.  
Specifications subject to change without notice.  
REV. A  
–3–  
AD9224  
ABSOLUTE MAXIMUM RATINGS*  
PIN CONFIGURATION  
28-Lead SSOP  
With  
Pin Name  
Respect to Min  
Max  
Units  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
CLK  
(LSB) BIT 12  
BIT 11  
BIT 10  
BIT 9  
DRVDD  
DRVSS  
AVDD  
AVDD  
DRVDD  
AVSS  
AVDD  
REFCOM  
CLK  
Digital Outputs DRVSS  
VINA, VINB  
VREF  
SENSE  
CAPB, CAPT  
Junction Temperature  
Storage Temperature  
Lead Temperature (10 sec)  
AVSS  
–0.3  
–0.3  
–0.3  
–6.5  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
+6.5  
+6.5  
+0.3  
+6.5  
V
V
V
V
V
V
V
V
V
V
V
°C  
°C  
°C  
DRVSS  
DRVSS  
DRVDD  
AVSS  
3
4
AVSS  
5
VINB  
+0.3  
6
BIT 8  
VINA  
AD9224  
AVSS  
AVDD + 0.3  
DRVDD + 0.3  
AVDD + 0.3  
AVDD+ 0.3  
AVDD+ 0.3  
AVDD+ 0.3  
+150  
7
BIT 7  
CML  
TOP VIEW  
(Not to Scale)  
8
BIT 6  
CAPT  
AVSS  
AVSS  
AVSS  
AVSS  
9
BIT 5  
CAPB  
10  
11  
12  
13  
14  
BIT 4  
REFCOM (AVSS)  
VREF  
BIT 3  
BIT 2  
SENSE  
AVSS  
(MSB) BIT 1  
OTR  
–65  
+150  
+300  
AVDD  
*Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum  
ratings for extended periods may affect device reliability.  
PIN FUNCTION DESCRIPTIONS  
Pin  
Number  
Name  
Description  
S1  
S2  
1
2
3–12  
13  
CLK  
Clock Input Pin  
Least Significant Data Bit (LSB)  
Data Output Bit  
ANALOG  
INPUT  
S4  
tC  
BIT 12  
BIT 11–2  
BIT 1  
S3  
tCH  
tCL  
Most Significant Data Bit (MSB)  
INPUT  
CLOCK  
14  
OTR  
AVDD  
AVSS  
SENSE  
VREF  
Out of Range  
+5 V Analog Supply  
Analog Ground  
Reference Select  
Input Span Select (Reference I/O)  
tOD  
15, 26  
16, 25  
17  
DATA  
OUTPUT  
DATA 1  
Figure 1. Timing Diagram  
18  
19  
REFCOM Reference Common  
(AVSS)  
20  
21  
22  
23  
24  
27  
28  
CAPB  
CAPT  
CML  
VINA  
VINB  
DRVSS  
DRVDD  
Noise Reduction Pin  
Noise Reduction Pin  
Common-Mode Level (Midsupply)  
Analog Input Pin (+)  
Analog Input Pin (–)  
Digital Output Driver Ground  
+3 V to +5 V Digital Output  
Driver Supply  
ORDERING GUIDE  
Package Description  
Model  
Temperature Range  
Package Option  
AD9224ARS  
AD9224-EB  
–40°C to +85°C  
28-Lead Shrink Small Outline (SSOP)  
Evaluation Board  
RS-28  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the AD9224 features proprietary ESD protection circuitry, permanent damage may  
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD  
precautions are recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
–4–  
REV. A  
AD9224  
DEFINITIONS OF SPECIFICATION  
APERTURE JITTER  
INTEGRAL NONLINEARITY (INL)  
Aperture jitter is the variation in aperture delay for successive  
samples and is manifested as noise on the input to the A/D.  
INL refers to the deviation of each individual code from a line  
drawn from “negative full scale” through “positive full scale.”  
The point used as “negative full scale” occurs 1/2 LSB before  
the first code transition. “Positive full scale” is defined as a level  
1 1/2 LSB beyond the last code transition. The deviation is  
measured from the middle of each particular code to the true  
straight line.  
APERTURE DELAY  
Aperture delay is a measure of the sample-and-hold amplifier  
(SHA) performance and is measured from the rising edge of the  
clock input to when the input signal is held for conversion.  
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)  
RATIO  
S/N+D is the ratio of the rms value of the measured input signal  
to the rms sum of all other spectral components below the  
Nyquist frequency, including harmonics but excluding dc. The  
value for S/N+D is expressed in decibels.  
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING  
CODES)  
An ideal ADC exhibits code transitions that are exactly 1 LSB  
apart. DNL is the deviation from this ideal value. Guaranteed  
no missing codes to 12-bit resolution indicates that all 4096  
codes, respectively, must be present over all operating ranges.  
EFFECTIVE NUMBER OF BITS (ENOB)  
ZERO ERROR  
For a sine wave, SINAD can be expressed in terms of the num-  
ber of bits. Using the following formula,  
The major carry transition should occur for an analog value  
1/2 LSB below VINA = VINB. Zero error is defined as the  
deviation of the actual transition from that point.  
N = (SINAD – 1.76)/6.02  
it is possible to get a measure of performance expressed as N,  
the effective number of bits.  
GAIN ERROR  
The first code transition should occur at an analog value  
1/2 LSB above negative full scale. The last transition should  
occur at an analog value 1 1/2 LSB below the nominal full scale.  
Gain error is the deviation of the actual difference between first  
and last code transitions and the ideal difference between first  
and last code transitions.  
Thus, effective number of bits for a device for sine wave inputs  
at a given input frequency can be calculated directly from its  
measured SINAD.  
TOTAL HARMONIC DISTORTION (THD)  
THD is the ratio of the rms sum of the first six harmonic com-  
ponents to the rms value of the measured input signal and is  
expressed as a percentage or in decibels.  
TEMPERATURE DRIFT  
The temperature drift for zero error and gain error specifies the  
maximum change from the initial (+25°C) value to the value at  
SIGNAL-TO-NOISE RATIO (SNR)  
T
MIN or TMAX.  
SNR is the ratio of the rms value of the measured input signal to  
the rms sum of all other spectral components below the Nyquist  
frequency, excluding the first six harmonics and dc. The value  
for SNR is expressed in decibels.  
POWER SUPPLY REJECTION  
The specification shows the maximum change in full scale from  
the value with the supply at the minimum limit to the value with  
the supply at its maximum limit.  
SPURIOUS FREE DYNAMIC RANGE (SFDR)  
SFDR is the difference in dB between the rms amplitude of the  
input signal and the peak spurious signal.  
REV. A  
–5–  
AD9224  
Typical Performance Characteristics  
(AVDD, DVDD = +5 V, FS = 40 MHz [50% duty cycle] unless otherwise noted.)  
1.00  
2.00  
1.50  
0.75  
0.50  
1.00  
0.25  
0.50  
0.00  
0.00  
–0.25  
–0.50  
–0.50  
–1.00  
–1.50  
–2.00  
–0.75  
–1.00  
0
511  
1022  
1533  
2044  
2555  
3066  
3577  
4095  
0
511  
1022  
1533 2044  
CODE  
2555  
3066  
3577  
4095  
CTOitDleE  
Figure 2. Typical DNL  
Figure 5. Typical INL  
70  
65  
60  
75  
70  
–0.5dB  
–6.0dB  
–0.5dB  
–6.0dB  
65  
60  
55  
50  
55  
50  
45  
–20.0dB  
–20.0dB  
45  
40  
40  
0.5  
10  
20  
30  
40  
50  
60  
70  
0.5  
5
10 15 20 25 30 35 40 45 50 55 60 65 70  
INPUT FREQUENCY – MHz  
INPUT FREQUENCY – MHz  
Figure 6. SINAD vs. Input Frequency (Input Span =  
2.0 V p-p, VCM = 2.5 V Differential Input)  
Figure 3. SINAD vs. Input Frequency (Input Span =  
4.0 V p-p, VCM = 2.5 V Differential Input)  
–40  
–45  
–50  
–55  
–20  
–30  
–40  
–20.0dB  
–50  
–60  
–20.0dB  
–65  
–60  
–70  
–0.5dB  
–0.5dB  
–70  
–75  
–5.0dB  
–6.0dB  
–80  
–80  
–90  
0.5  
–85  
0.5  
5
10 15 20 25 30 35 40 45 50 55 60 65 70  
INPUT FREQUENCY – MHz  
5
10 15 20 25 30 35 40 45 50 55 60 65 70  
INPUT FREQUENCY – MHz  
Figure 7. THD vs. Input Frequency (Input Span =  
2.0 V p-p, VCM = 2.5 V Differential Input)  
Figure 4. THD vs. Input Frequency (Input Span =  
4.0 V p-p, VCM = 2.5 V Differential Input)  
–6–  
REV. A  
AD9224  
80  
70  
60  
50  
90  
80  
70  
SFDR  
40  
30  
20  
10  
0
60  
50  
40  
SNR  
30  
10  
–0.5  
–20  
–40  
–60  
20  
30  
40  
50  
60  
SAMPLE RATE – MHz  
INPUT AMPLITUDE  
Figure 8. SNR/SFDR vs. AIN (Input Amplitude) (fIN = 20 MHz,  
Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input)  
Figure 11. THD vs. Sample Rate (AIN = –0.5 dB, VCM = 2.5 V  
Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input)  
90  
80  
90  
THD  
80  
SNR  
70  
70  
SNR  
60  
60  
THD  
50  
40  
30  
50  
40  
30  
20  
10  
0
20  
10  
0
0.5  
5
10 15 20 25 30 35 40 45 50 55 60 65 70  
INPUT FREQUENCY  
0.5  
5
10  
15  
20  
25  
30  
INPUT FREQUENCY  
Figure 9. +SNR/–THD vs. Input Frequency (Input Span =  
4.0 V p-p, VCM = 2.5 V Single-Ended Input)  
Figure 12. +SNR/–THD vs. Input Frequency (FS = 32 MHz,  
Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input)  
167819  
2857  
N+1  
2093  
N–1  
N
BIN  
Figure 10. “Grounded-Input” Histogram (Input Span =  
2 V p-p)  
REV. A  
–7–  
AD9224  
INTRODUCTION  
converter. Specifically, the input to the A/D core is the differ-  
ence of the voltages applied at the VINA and VINB input pins.  
Therefore, the equation,  
The AD9224 is a high performance, complete single-supply 12-  
bit ADC. The analog input range of the AD9224 is highly flex-  
ible allowing for both single-ended or differential inputs of  
varying amplitudes that can be ac or dc coupled.  
V
CORE = VINA VINB  
(1)  
defines the output of the differential input stage and provides  
the input to the A/D core.  
It utilizes a four-stage pipeline architecture with a wideband  
input sample-and-hold amplifier (SHA) implemented on a cost-  
effective CMOS process. Each stage of the pipeline, excluding  
the last stage, consists of a low resolution flash A/D connected  
to a switched capacitor DAC and interstage residue amplifier  
(MDAC). The residue amplifier amplifies the difference be-  
tween the reconstructed DAC output and the flash input for the  
next stage in the pipeline. One bit of redundancy is used in each  
of the stages to facilitate digital correction of flash errors. The  
last stage simply consists of a flash A/D.  
The voltage, VCORE, must satisfy the condition,  
VREF VCORE VREF  
(2)  
where VREF is the voltage at the VREF pin.  
While an infinite combination of VINA and VINB inputs exist  
that satisfy Equation 2, an additional limitation is placed on the  
inputs by the power supply voltages of the AD9224. The power  
supplies bound the valid operating range for VINA and VINB.  
The condition,  
The pipeline architecture allows a greater throughput rate at the  
expense of pipeline delay or latency. This means that while the  
converter is capable of capturing a new input sample every clock  
cycle, it actually takes three clock cycles for the conversion to be  
fully processed and appear at the output. This latency is not a  
concern in most applications. The digital output, together with  
the out-of-range indicator (OTR), is latched into an output  
buffer to drive the output pins. The output drivers of the  
AD9224 can be configured to interface with +5 V or +3.3 V  
logic families.  
AVSS – 0.3 V < VINA < AVDD + 0.3 V  
AVSS – 0.3 V < VINB < AVDD + 0.3 V  
(3)  
where AVSS is nominally 0 V and AVDD is nominally +5 V,  
defines this requirement. The range of valid inputs for VINA  
and VINB is any combination that satisfies both Equations 2  
and 3.  
For additional information showing the relationship between  
VINA, VINB, VREF and the digital output of the AD9224, see  
Table IV.  
The AD9224 uses both edges of the clock in its internal timing  
circuitry (see Figure 1 and specification page for exact timing  
requirements). The A/D samples the analog input on the rising  
edge of the clock input. During the clock low time (between the  
falling edge and rising edge of the clock), the input SHA is in  
the sample mode; during the clock high time it is in hold. Sys-  
tem disturbances just prior to the rising edge of the clock and/or  
excessive clock jitter may cause the input SHA to acquire the  
wrong value, and should be minimized.  
Refer to Table I and Table II at the end of this section for a  
summary of both the various analog input and reference  
configurations.  
ANALOG INPUT OPERATION  
Figure 14 shows the equivalent analog input of the AD9224  
which consists of a differential sample-and-hold amplifier  
(SHA). The differential input structure of the SHA is highly  
flexible, allowing the devices to be easily configured for either a  
differential or single-ended input. The dc offset, or common-  
mode voltage, of the input(s) can be set to accommodate either  
single-supply or dual-supply systems. Note also, that the analog  
inputs, VINA and VINB, are interchangeable, with the excep-  
tion that reversing the inputs to the VINA and VINB pins re-  
sults in a polarity inversion.  
ANALOG INPUT AND REFERENCE OVERVIEW  
Figure 13 is a simplified model of the AD9224. It highlights the  
relationship between the analog inputs, VINA, VINB, and the  
reference voltage, VREF. Like the voltage applied to the top of  
the resistor ladder in a flash A/D converter, the value VREF  
defines the maximum input voltage to the A/D core. The mini-  
mum input voltage to the A/D core is automatically defined to  
be –VREF.  
C
H
Q
S2  
+
C
C
PIN  
PAR  
C
Q
S
AD9224  
S1  
+VREF  
VINA  
VINA  
VINB  
Q
C
Q
H1  
S
S1  
12  
V
CORE  
A/D  
C
C
CORE  
PIN  
PAR  
Q
S2  
–VREF  
VINB  
C
H
Figure 13. Equivalent Functional Input Circuit  
Figure 14. Simplified Input Circuit  
The addition of a differential input structure gives the user an  
additional level of flexibility that is not possible with traditional  
flash converters. The input stage allows the user to easily config-  
ure the inputs for either single-ended operation or differential  
operation. The A/D’s input structure allows the dc offset of the  
input signal to be varied independently of the input span of the  
The AD9224 has a wide input range. The input peaks may be  
moved to AVDD or AVSS before performance is compromised.  
This allows for much greater flexibility when selecting single-  
ended drive schemes. Op amps and ac coupling clamps can be  
set to available reference levels rather than be dictated by what  
the ADC “needs.”  
–8–  
REV. A  
AD9224  
V
Due to the high degree of symmetry within the SHA topology,  
a significant improvement in distortion performance for differ-  
ential input signals with frequencies up to and beyond Nyquist  
can be realized. This inherent symmetry provides excellent  
cancellation of both common-mode distortion and noise.  
Also, the required input signal voltage span is reduced by a  
half which further reduces the degree of RON modulation and  
its effects on distortion.  
CC  
AD9224  
R
S
VINA  
R
S
VINB  
V
EE  
VREF  
10F  
0.1F  
SENSE  
REFCOM  
The optimum noise and dc linearity performance for either  
differential or single-ended inputs is achieved with the largest  
input signal voltage span (i.e., 4 V input span) and matched  
input impedance for VINA and VINB. Only a slight degrada-  
tion in dc linearity performance exists between the 2 V and  
4 V input spans.  
Figure 15. Series Resistor Isolates Switched-Capacitor  
SHA Input from Op Amp. Matching Resistors Improve  
SNR Performance  
The optimum size of this resistor is dependent on several fac-  
tors, including the ADC sampling rate, the selected op amp,  
and the particular application. In most applications, a 30 to  
100 resistor is sufficient. However, some applications may  
require a larger resistor value to reduce the noise bandwidth or  
possibly limit the fault current in an overvoltage condition.  
Other applications may require a larger resistor value as part of  
an antialiasing filter. In any case, since the THD performance is  
dependent on the series resistance and the above mentioned  
factors, optimizing this resistor value for a given application is  
encouraged.  
Referring to Figure 14, the differential SHA is implemented  
using a switched-capacitor topology. Its input impedance and  
its switching effects on the input drive source should be consid-  
ered in order to maximize the converter’s performance. The  
combination of the pin capacitance, CPIN, parasitic capacitance  
C
PAR, and the sampling capacitance, CS, is typically less than  
5 pF. When the SHA goes into track mode, the input source  
must charge or discharge the voltage stored on CS to the new  
input voltage. This action of charging and discharging CS,  
averaged over a period of time and for a given sampling fre-  
quency, FS, makes the input impedance appear to have a be-  
nign resistive component. However, if this action is analyzed  
within a sampling period (i.e., T = 1/FS), the input impedance  
is dynamic and hence certain precautions on the input drive  
source should be observed.  
The source impedance driving VINA and VINB should be  
matched. Failure to provide that matching will result in the  
degradation of the AD9224’s SNR, THD and SFDR.  
For noise sensitive applications, the very high bandwidth of the  
AD9224 may be detrimental and the addition of a series resistor  
and/or shunt capacitor can help limit the wideband noise at the  
A/D’s input by forming a low-pass filter. Note, however, that  
the combination of this series resistance with the equivalent  
input capacitance of the AD9224 should be evaluated for those  
time domain applications that are sensitive to the input signal’s  
absolute settling time. In applications where harmonic distor-  
tion is not a primary concern, the series resistance may be  
selected in combination with the nominal 10 pF of input  
capacitance to set the filter’s 3 dB cutoff frequency.  
The resistive component to the input impedance can be com-  
puted by calculating the average charge drawn by CH from the  
input drive source. It can be shown that if CS is allowed to  
fully charge up to the input voltage before switches QS1 are  
opened, the average current into the input is the same as if  
there were a resistor of 1/(CS FS) ohms connected between the  
inputs. This means that the input impedance is inversely pro-  
portional to the converter’s sample rate. Since CS is only 5 pF,  
this resistive component is typically much larger than that of  
the drive source (i.e., 5 kat FS = 40 MSPS).  
A better method of reducing the noise bandwidth, while possi-  
bly establishing a real pole for an antialiasing filter, is to add  
some additional shunt capacitance between the input (i.e.,  
VINA and/or VINB) and analog ground. Since this additional  
shunt capacitance combines with the equivalent input capaci-  
tance of the AD9224, a lower series resistance can be selected to  
establish the filter’s cutoff frequency while not degrading the  
distortion performance of the device. The shunt capacitance  
also acts like a charge reservoir, sinking or sourcing the addi-  
tional charge required by the hold capacitor, CH, further reduc-  
ing current transients seen at the op amp’s output.  
The SHA’s input impedance over a sampling period appears as  
a dynamic input impedance to the input drive source. When the  
SHA goes into the track mode, the input source should ideally  
provide the charging current through RON of switch QS1 in an  
exponential manner. The requirement of exponential charging  
means that the most common input source, an op amp, must  
exhibit a source impedance that is both low and resistive up to  
and beyond the sampling frequency.  
The output impedance of an op amp can be modeled with a  
series inductor and resistor. When a capacitive load is switched  
onto the output of the op amp, the output will momentarily  
drop due to its effective output impedance. As the output re-  
covers, ringing may occur. To remedy the situation, a series  
resistor can be inserted between the op amp and the SHA  
input as shown in Figure 15. The series resistance helps isolate  
the op amp from the switched-capacitor load.  
The effect of this increased capacitive load on the op amp driv-  
ing the AD9224 should be evaluated. To optimize performance  
when noise is the primary consideration, increase the shunt  
capacitance as much as the transient response of the input signal  
will allow. Increasing the capacitance too much may adversely  
affect the op amp’s settling time, frequency response and distor-  
tion performance.  
REV. A  
–9–  
AD9224  
The actual reference voltages used by the internal circuitry of  
the AD9224 appear on the CAPT and CAPB pins. For proper  
operation when using the internal or an external reference, it is  
necessary to add a capacitor network to decouple these pins.  
Figure 17 shows the recommended decoupling network. This  
capacitive network performs the following three functions: (1)  
along with the reference amplifier, A2, it provides a low source  
impedance over a large frequency range to drive the A/D inter-  
nal circuitry, (2) it provides the necessary compensation for A2,  
and (3) it bandlimits the noise contribution from the reference.  
The turn-on time of the reference voltage appearing between  
CAPT and CAPB is approximately 15 ms and should be evalu-  
ated in any power-down mode of operation.  
REFERENCE OPERATION  
The AD9224 contains an onboard bandgap reference that  
provides a pin strappable option to generate either a 1 V or 2 V  
output. With the addition of two external resistors, the user can  
generate reference voltages other than 1 V and 2 V. Another  
alternative is to use an external reference for designs requiring  
enhanced accuracy and/or drift performance. See Table II for a  
summary of the pin-strapping options for the AD9224 refer-  
ence configurations.  
Figure 16 shows a simplified model of the internal voltage  
reference of the AD9224. A pin strappable reference ampli-  
fier buffers a 1 V fixed reference. The output from the refer-  
ence amplifier, A1, appears on the VREF pin. The voltage on  
the VREF pin determines the full-scale input span of the A/D.  
This input span equals,  
0.1F  
CAPT  
10F  
Full-Scale Input Span = 2 × VREF  
0.1F  
AD9224  
The voltage appearing at the VREF pin as well as the state of  
the internal reference amplifier, A1, are determined by the  
voltage appearing at the SENSE pin. The logic circuitry con-  
tains two comparators which monitor the voltage at the SENSE  
pin. The comparator with the lowest set point (approximately  
0.3 V) controls the position of the switch within the feedback  
path of A1. If the SENSE pin is tied to AVSS (AGND), the  
switch is connected to the internal resistor network thus provid-  
ing a VREF of 2.0 V. If the SENSE pin is tied to the VREF pin  
via a short or resistor, the switch will connect to the SENSE  
pin. This short will provide a VREF of 1.0 V. An external resis-  
tor network will provide an alternative VREF between 1.0 V  
and 2.0 V. The other comparator controls internal circuitry  
that will disable the reference amplifier if the SENSE pin is tied  
AVDD. Disabling the reference amplifier allows the VREF pin  
to be driven by an external voltage reference.  
CAPB  
0.1F  
Figure 17. Recommended CAPT/CAPB Decoupling Network  
The A/D’s input span may be varied dynamically by changing  
the differential reference voltage appearing across CAPT and  
CAPB symmetrically around 2.5 V (i.e., midsupply). To change  
the reference at speeds beyond the capabilities of A2, it will be  
necessary to drive CAPT and CAPB with two high speed, low  
noise amplifiers. In this case, both internal amplifiers (i.e., A1  
and A2) must be disabled by connecting SENSE to AVDD,  
connecting VREF to AVSS and removing the capacitive decou-  
pling network. The external voltages applied to CAPT and  
CAPB must be 2.0 V + Input Span/4 and 2.0 V – Input Span/4  
respectively in which the input span can be varied between 2 V  
and 4 V. Note that those samples within the pipeline A/D dur-  
ing any reference transition will be corrupted and should be  
discarded.  
AD9224  
TO  
A/D  
5k  
CAPT  
5k⍀  
A2  
5k⍀  
CAPB  
5k⍀  
DISABLE  
LOGIC  
A2  
VREF  
A1  
1V  
6.25k⍀  
SENSE  
DISABLE  
LOGIC  
6.25k⍀  
A1  
REFCOM  
Figure 16. Equivalent Reference Circuit  
–10–  
REV. A  
AD9224  
Table I. Analog Input Configuration Summary  
Input  
Connection  
Input  
Coupling Span (V)  
Input Range (V)  
VINA1 VINB1  
Figure  
#
Comments  
Single-Ended  
DC  
2
0 to 2  
1
19, 20  
19, 20  
Best for stepped input response applications, requires ±5 V op amp.  
2 × VREF  
0 to  
2 × VREF  
VREF  
Same as above but with improved noise performance due to  
increase in dynamic range. Headroom/settling time require-  
ments of ±5 op amp should be evaluated.  
4
0 to 4  
2.0  
2.0  
19, 20  
30  
Optimum noise performance, excellent SNR performance, often  
requires low distortion op amp with VCC > +5 V due to its head-  
room issues.  
2 × VREF  
2.0 – VREF  
to  
Optimum THD performance with VREF = 1. Single supply  
operation (i.e., +5 V) for many op amps.  
2.0 + VREF  
Single-Ended  
AC  
2 or  
2 × VREF  
0 to 1 or  
0 to 2 × VREF  
1 or VREF  
2.5  
21, 22  
22  
4
0.5 to 4.5  
Optimum noise performance, excellent THD performance,  
ability to use ±5 V op amp.  
2 × VREF  
2.0 – VREF  
to  
2.0  
21  
Flexible input range, Optimum THD performance with  
VREF = 1. Ability to use either +5 V or ±5 V op amp.  
2.0 + VREF  
Differential  
(via Transformer)  
or Amplifier  
AC/DC  
2
2 to 3  
3 to 2  
23, 24  
Optimum full-scale THD and SFDR performance well beyond  
the A/Ds Nyquist frequency. Preferred mode for undersampling  
applications.  
2 × VREF  
2.0 – VREF/2 2.0 + VREF/2 23, 24  
to to  
2.0 + VREF/2 2.0 – VREF/2  
Same as above with the exception that full-scale THD and SFDR  
performance can be traded off for better noise performance.  
4.0  
1.5 to 3.5  
3.5 to 1.5  
23, 24  
Optimum noise performance.  
NOTE  
1VINA and VINB can be interchanged if signal inversion is required.  
Table II. Reference Configuration Summary  
Input Span (VINA–VINB)  
Reference  
Operating Mode  
(V p-p)  
Required VREF (V)  
Connect  
To  
INTERNAL  
INTERNAL  
INTERNAL  
2
4
1
2
SENSE  
SENSE  
R1  
VREF  
REFCOM  
VREF AND SENSE  
SENSE AND REFCOM  
2 SPAN 4 AND  
SPAN = 2  
1 VREF 2.0 AND  
VREF = (1 + R1/R2)  
×
VREF  
R2  
EXTERNAL  
(NONDYNAMIC)  
2 SPAN 4  
1 VREF 2.0  
SENSE  
VREF  
AVDD  
EXT. REF.  
EXTERNAL  
(DYNAMIC)  
2 SPAN 4  
CAPT and CAPB  
Externally Driven  
SENSE  
VREF  
EXT. REF.  
EXT. REF.  
AVDD  
AVSS  
CAPT  
CAPB  
REV. A  
–11–  
AD9224  
OPTIONAL  
AC COUPLING  
CAPACITOR  
DRIVING THE ANALOG INPUTS  
AVDD  
D2  
The AD9224 has a highly flexible input structure allowing it to  
interface with single-ended or differential input interface cir-  
cuitry. The applications shown in Driving the Analog Inputs and  
Reference Configurations sections, along with the information  
presented in Input and Reference Overview of this data sheet,  
give examples of both single-ended and differential operation.  
Refer to Tables I and II for a list of the different possible input  
and reference configurations and their associated figures in the  
data sheet.  
V
CC  
R
30  
R
20⍀  
S1  
S2  
AD9224  
D1  
V
EE  
Figure 18. Simple Clamping Circuit  
SINGLE-ENDED MODE OF OPERATION  
The AD9224 can be configured for single-ended operation  
using dc or ac coupling. In either case, the input of the A/D  
must be driven from an operational amplifier that will not de-  
grade the A/D’s performance. Because the A/D operates from a  
single supply, it will be necessary to level shift ground-based  
bipolar signals to comply with its input requirements. Both dc  
and ac coupling provide this necessary function, but each method  
results in different interface issues which may influence the  
system design and performance.  
The optimum mode of operation, analog input range, and asso-  
ciated interface circuitry will be determined by the particular  
applications performance requirements as well as power supply  
options. For example, a dc-coupled single-ended input would be  
appropriate for most data acquisition and imaging applications.  
Also, many communication applications that require a dc coupled  
input for proper demodulation can take advantage of the  
single-ended distortion performance of the AD9224. The input  
span should be configured so the system’s performance objec-  
tives and the headroom requirements of the driving op amp are  
simultaneously met.  
Single-ended operation is often limited by the availability driv-  
ing op amps. Very low distortion op amps that provide great  
performance out to the Nyquist frequency of the converter are  
hard to find. Compounding the problem, for dc coupled single-  
ended applications, is the inability of the many high perfor-  
mance amplifiers to maintain low distortions as their outputs  
approach their positive output voltage limit (i.e., 1 dB compres-  
sion point). For this reason, it is recommended that applications  
requiring high performance dc coupling use the single-ended-to-  
differential circuit shown in Figure 23.  
Differential modes of operation (ac or dc coupled input) provide  
the best THD and SFDR performance over a wide frequency  
range. Differential operation should be considered for the most de-  
manding spectral based applications (e.g., direct IF-to-digital con-  
version). See Figures 23, 24 and section on Differential Mode of  
Operation. Differential input characterization was performed for  
this data sheet using the configuration shown in Figure 24.  
Single-ended operation requires that VINA be ac or dc coupled  
to the input signal source, while VINB of the AD9224 be biased  
to the appropriate voltage corresponding to a midscale code transi-  
tion. Note that signal inversion may be easily accomplished by  
transposing VINA and VINB. Most of the single-ended specifi-  
cations for the AD9224 were characterized using Figure 21  
circuitry with input spans of 4 V and 2 V as well as VCM = 2.5 V.  
DC COUPLING AND INTERFACE ISSUES  
Many applications require the analog input signal to be dc coupled  
to the AD9224. An operational amplifier can be configured to  
rescale and level shift the input signal so that it is compatible  
with the selected input range of the A/D. The input range to the  
A/D should be selected on the basis of system performance  
objectives as well as the analog power supply availability since  
this will place certain constraints on the op amp selection.  
Differential operation requires that VINA and VINB be simulta-  
neously driven with two equal signals that are in and out of  
phase versions of the input signal. Differential operation of the  
AD9224 offers the following benefits: (1) Signal swings are  
smaller and therefore linearity requirements placed on the input  
signal source may be easier to achieve, (2) Signal swings are  
smaller and therefore may allow the use of op amps which may  
otherwise have been constrained by headroom limitations, (3)  
Differential operation minimizes even-order harmonic products,  
and (4) Differential operation offers noise immunity based on  
the device’s common-mode rejection.  
Many of the new high performance op amps are specified for  
only ±5 V operation and have limited input/output swing capa-  
bilities. The selected input range of the AD9224 should be consid-  
ered with the headroom requirements of the particular op amp to  
prevent clipping of the signal. Also, since the output of a dual  
supply amplifier can swing below absolute minimum (–0.3 V),  
clamping its output should be considered in some applications.  
In some applications, it may be advantageous to use an op amp  
specified for single supply +5 V operation since it will inherently  
limit its output swing to within the power supply rails. Ampli-  
fiers like the AD8041 and AD8011 are useful for this purpose  
but their low bandwidths will limit the AD9224’s performance.  
High performance amplifiers (±5 V) such as the AD9631,  
AD9632, AD8056 or AD8055 allow the AD9224 to be config-  
ured for larger input spans which will improve the ADC’s noise  
performance.  
As is typical of most IC devices, exceeding the supply limits will  
turn on internal parasitic diodes resulting in transient currents  
within the device. Figure 18 shows a simple means of clamping  
an ac or dc coupled single-ended input with the addition of two  
series resistors and two diodes. An optional capacitor is shown  
for ac coupled applications. Note that a larger series resistor  
could be used to limit the fault current through D1 and D2 but  
should be evaluated since it can cause a degradation in overall  
performance. A similar clamping circuit could also be used for  
each input if a differential input signal is being applied. The  
diodes might cause nonlinearity in the signal. Careful evaluation  
should be performed on the diodes used.  
Op amp circuits using a noninverting and inverting topologies  
are discussed in the next section. Although not shown, the non-  
inverting and inverting topologies can be easily configured as  
part of an antialiasing filter by using a Sallen-Key or Multiple-  
Feedback topology. An additional R-C network can be inserted  
between the op amp’s output and the AD9224 input to provide  
a filter pole.  
–12–  
REV. A  
AD9224  
AC COUPLING AND INTERFACE ISSUES  
Simple Op Amp Buffer  
For applications where ac coupling is appropriate, the op amp’s  
output can be easily level-shifted via a coupling capacitor. This  
has the advantage of allowing the op amp’s common-mode level  
In the simplest case, the input signal to the AD9224 will already  
be biased at levels in accordance with the selected input range.  
It is simply necessary to provide an adequately low source imped-  
ance for the VINA and VINB analog pins of the A/D. Figure 19  
shows the recommended configuration a single-ended drive  
using an op amp. In this case, the op amp is shown in a nonin-  
verting unity gain configuration driving the VINA pin. The  
internal reference drives the VINB pin. Note that the addi-  
tion of a small series resistor of 30 to 100 connected to  
VINA and VINB will be beneficial in nearly all cases. Refer to  
the Analog Input Operation section for a discussion on resistor  
selection. Figure 19 shows the proper connection for a 0 V to  
4 V input range. Alternative single ended ranges of 0 V to 2 ×  
VREF can also be realized with the proper configuration of  
VREF (refer to the Using the Internal Reference section). Head-  
room limitations of the op amp must always be considered.  
to be symmetrically biased to its midsupply level (i.e. (VCC  
+
V
EE)/2). Op amps that operate symmetrically with respect to  
their power supplies typically provide the best ac performance as  
well as greatest input/output span. Various high speed/perfor-  
mance amplifiers that are restricted to +5 V/–5 V operation and/  
or specified for +5 V single-supply operation can be easily  
configured for the 4 V or 2 V input span of the AD9224. A  
differential input connection should be considered for opti-  
mum ac performance.  
Simple AC Interface  
Figure 21 shows a typical example of an ac-coupled, single-  
ended configuration. The bias voltage shifts the bipolar, ground-  
referenced input signal to approximately AVDD/2. The value  
for C1 and C2 will depend on the size of the resistor, R. The  
capacitors, C1 and C2, are a 0.1 µF ceramic and 10 µF tanta-  
lum capacitor in parallel to achieve a low cutoff frequency while  
maintaining a low impedance over a wide frequency range. The  
combination of the capacitor and the resistor form a high-pass filter  
with a high-pass –3 dB frequency determined by the equation,  
+V  
4V  
0V  
AD9224  
R
S
U1  
–V  
VINA  
R
S
VINB  
2.0V  
10F  
VREF  
0.1F  
f
–3 dB = 1/(2 × π × R × (C1 + C2))  
SENSE  
The low impedance VREF voltage source both biases the VINB  
input and provides the bias voltage for the VINA input. Figure  
21 shows the VREF configured for 2.0 V thus the input range  
of the A/D is 0 V to 4 V. Other input ranges could be selected  
by changing VREF.  
Figure 19. Single-Ended AD9224 Op Amp Drive Circuit  
Op Amp with DC Level-Shifting  
Figure 20 shows a dc-coupled level-shifting circuit employing  
an op amp, A1, to sum the input signal with the desired dc set.  
Configuring the op amp in the inverting mode with the given  
resistor values results in an ac signal gain of –1. If the signal  
inversion is undesirable, interchange the VINA and VINB con-  
nections to reestablish the original signal polarity. The dc volt-  
age at VREF sets the common-mode voltage of the AD9224.  
For example, when VREF = 1.0 V, the input level from the op  
amp will also be centered around 1.0 V. The use of ratio matched,  
thin-film resistor networks will minimize gain and offset errors.  
Also, an optional pull-up resistor, RP, may be used to reduce  
the output load on VREF to less than 1 mA maximum.  
C1  
10F  
+V  
+V  
+5V  
–5V  
AD9631  
4.5  
2.5  
0.5  
R
R
+2V  
0V  
–2V  
AD9224  
VINA  
V
R
IN  
S
C2  
0.1F  
R
S
VINB  
SENSE  
0.1F  
10F  
R
R
500*  
Figure 21. AC-Coupled Input  
+V  
CC  
0.1F  
NC  
1
+VREF  
–VREF  
500*  
7
0V  
2
3
DC  
R
S
6
A1  
VINA  
R **  
500*  
0.1F  
P
5
+V  
4
500*  
NC  
AD9224  
R
S
VREF  
VINB  
NC = NO CONNECT  
*OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D  
**OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE  
Figure 20. Single-Ended Input with DC-Coupled Level Shift  
REV. A  
–13–  
AD9224  
Alternative AC Interface  
Figure 22 shows a flexible ac-coupled circuit that can be con-  
figured for different input spans. Since the common-mode  
AD8055: f–3 dB = 300 MHz.  
Low cost. Best used for driving single-ended ac  
coupled configuration.  
voltage of VINA and VINB are biased to midsupply (VCM  
)
Limit: THD is compromised when output is not  
swinging about 0 V.  
independent of VREF, VREF can be pin strapped or reconfig-  
ured to achieve input spans between 2 V and 4 V p-p. The  
AD9224’s CMRR, along with the symmetrical coupling R-C  
networks, will reject both power supply variations and noise.  
VCM establishes the common-mode voltage. VCM’s source im-  
pedance is 5 k. The capacitors, C1 and C2, are typically a  
0.1 µF ceramic and 10 µF tantalum capacitor in parallel to  
achieve a low cutoff frequency while maintaining a low imped-  
ance over a wide frequency range. RS isolates the buffer ampli-  
fier from the A/D input. The optimum performance is preserved  
because VINA and VINB are driven via symmetrical R-C net-  
works. The f–3 dB point can be approximated by the equation,  
AD8056: Dual Version of above amp.  
Perfect for single-ended to differential configuration  
(see Figure 23). Harmonics cancel each other in  
differential drive, making this amplifier highly recom-  
mended for a single-ended input signal source. Handles  
input signals past the 20 MHz Nyquist frequency.  
AD9631: f–3 dB = 250 MHz.  
Moderate cost.  
Good for single-ended drive applications when signal  
is anywhere between 0 V and 3 V.  
Limits: THD is compromised above 8 MHz.  
1
f 3dB  
=
DIFFERENTIAL MODE OF OPERATION  
2 π ×6K +(C1+C2)  
Since not all applications have a signal preconditioned for differ-  
ential operation, there is often a need to perform a single-ended-  
to-differential conversion. In systems that do not need to be dc  
coupled, an RF transformer with a center tap is the best method  
to generate differential inputs for the AD9224. It provides all  
the benefits of operating the A/D in the differential mode with-  
out contributing additional noise or distortion. An RF transformer  
also has the added benefit of providing electrical isolation be-  
tween the signal source and the A/D.  
C2  
0.1F  
C1  
10F  
AD9224  
R
S
V
IN  
VINA  
1k⍀  
1k⍀  
VCM  
C3  
0.1F  
VINB  
An improvement in THD and SFDR performance can be real-  
ized by operating the AD9224 in the differential mode. The  
performance enhancement between the differential and single-  
ended mode is most noteworthy as the input frequency approaches  
and goes beyond the Nyquist frequency (i.e., fIN > FS /2).  
C1  
10F  
C2  
0.1F  
R
S
Figure 22. AC-Coupled Input-Flexible Input Span,  
CM = 2.5 V  
V
OP AMP SELECTION GUIDE  
The circuit shown in Figure 23 is an ideal method of applying a  
differential dc drive to the AD9224. We have used this configu-  
ration to drive the AD9224 from 2 V to 4 V spans at frequencies  
approaching Nyquist, with performance numbers matching  
those shown on the Specification pages of this data sheet (gath-  
ered through a transformer). The dc input is shifted to a dc  
point swinging symmetrically about the reference voltage. The  
optional resistor will provide additional current if more refer-  
ence drive is required.  
Op amp selection for the AD9224 is highly dependent on a  
particular application. In general, the performance requirements  
of any given application can be characterized by either time  
domain or frequency domain parameters. In either case, one  
should carefully select an op amp that preserves the perfor-  
mance of the A/D. This task becomes challenging when one  
considers the AD9224’s high performance capabilities coupled  
with other extraneous system level requirements such as power  
consumption and cost.  
500  
The ability to select the optimal op amp may be further compli-  
cated by either limited power supply availability and/or limited  
acceptable supplies for a desired op amp. Newer, high perfor-  
mance op amps typically have input and output range limita-  
tions in accordance with their lower supply voltages. As a result,  
some op amps will be more appropriate in systems where ac-  
coupling is allowable. When dc-coupling is required, op amps  
without headroom constraints such as rail-to-rail op amps or  
ones where larger supplies can be used should be considered.  
The following section describes some op amps currently avail-  
able from Analog Devices. The system designer is always en-  
couraged to contact the factory or local sales office to be  
updated on Analog Devices latest amplifier product offerings.  
Highlights of the areas where the op amps excel and where they  
may limit the performance of the AD9224 is also included.  
500⍀  
50⍀  
VREF  
VINA  
500⍀  
0V  
500⍀  
500⍀  
AD9224  
500⍀  
500⍀  
50⍀  
+V  
VINB  
CML  
R*  
500⍀  
10F  
0.1F  
*OPTIONAL  
Figure 23. Direct Coupled Drive Circuit with AD8056 Dual  
Op Amps  
When single-ended, dc coupling is needed. The use of the  
AD8056 in a differential configuration (Figure 23) is highly  
recommended.  
–14–  
REV. A  
AD9224  
Transformers with other turns ratios may also be selected to  
optimize the performance of a given application. For example, a  
given input signal source or amplifier may realize an improve-  
ment in distortion performance at reduced output power levels  
and signal swings. For example, selecting a transformer with a  
higher impedance ratio (e.g., Minicircuits T16-6T with a 1:16  
impedance ratio) effectively “steps up” the signal level thus  
further reducing the driving requirements of signal source.  
The driver circuit shown in Figure 23 is optimized for dc cou-  
pling applications requiring optimum distortion performance.  
This differential op amp driver circuit is configured to convert  
and level shift a 2 V p-p single-ended, ground referenced signal  
to a 4 V p-p differential signal centered at the VREF level of the  
ADC. The circuit is based on two op amps that are configured  
as matched unity gain difference amplifiers. The single-ended  
input signal is applied to opposing inputs of the difference am-  
plifiers, thus providing differential drive. The common-mode  
offset voltage is applied to the noninverting resistor leg of each  
difference amplifier providing the required offset voltage. The  
common-mode offset can be varied over a wide span without  
any serious degradation in distortion performance as shown in  
Figure 25a, thus providing some flexibility in improving output  
compression distortion from some ±5 V op amps with limited  
positive voltage swing.  
Referring to Figure 24, a series resistor, RS, was inserted between  
the AD9224 and the secondary of the transformer. The value of  
33 was selected to specifically optimize both the THD and  
SNR performance of the A/D. RS and the internal capacitance  
help provide a low-pass filter to block high frequency noise.  
The AD9224 can be easily configured for either a 2 V p-p input  
span or 4.0 V p-p input span by setting the internal reference  
(see Table II). Other input spans can be realized with two exter-  
nal gain setting resistors as shown in Figure 28 of this data  
sheet. Figure 25a demonstrates the AD9224’s high degree of  
linearity and THD over a wide range of common-mode  
voltages.  
To protect the AD9224 from an undervoltage fault condition  
from op amps specified for ±5 V operation, two diodes to AGND  
can be inserted between each op amp output and the AD9224  
inputs. The AD9224 will inherently be protected against any  
overvoltage condition if the op amps share the same positive  
power supply (i.e., AVDD) as the AD9224. Note, the gain  
accuracy and common-mode rejection of each difference ampli-  
fier in this driver circuit can be enhanced by using a matched thin-  
film resistor network (i.e., Ohmtek ORNA5000F) for the op  
amps. The AD9224’s small signal bandwidth is 120 MHz, hence  
any noise falling within the baseband bandwidth of the AD9224  
will degrade its overall noise performance.  
84  
f
= 10MHz  
IN  
82  
80  
f
= 20MHz  
IN  
78  
76  
74  
72  
The noise performance of each unity gain differential driver  
circuit is limited by its inherent noise gain of two. For unity gain  
op amps ONLY, the noise gain can be reduced from two to one  
beyond the input signal’s passband by adding a shunt capacitor,  
CF, across each op amp’s feedback resistor. This will essentially  
establish a low-pass filter, which reduces the noise gain to one  
beyond the filter’s f–3 dB while simultaneously bandlimiting the  
input signal to f–3 dB. Note, the pole established by this filter  
can also be used as the real pole of an antialiasing filter.  
0.5  
1
2
2.5  
3
4
4.5  
COMMON-MODE VOLTAGE – V  
Figure 25a. THD vs. Common-Mode Voltage (AIN = 2 V  
Differential)  
Figure 24 shows the schematic of the suggested transformer  
circuit. The circuit uses a Minicircuits RF transformer, model  
T4-1T, which has an impedance ratio of four (turns ratio of 2).  
The schematic assumes that the signal source has a 50 source  
impedance. The 1:4 impedance ratio requires the 200 sec-  
ondary termination for optimum power transfer and VSWR.  
The center tap of the transformer provides a convenient  
means of level shifting the input signal to a desired common-  
mode voltage.  
10  
FUND  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
R
S
33⍀  
VINA  
CML  
–80  
–90  
3RD  
49.9⍀  
2ND  
5TH  
7TH  
9TH  
8TH  
6TH  
0.1F  
–100  
–110  
–120  
200⍀  
AD9224  
VINB  
MINICIRCUITS  
T4-1T  
0
8
17.25 26.5 35.7 45E6 54.25 63.5 72.75 82  
COMMON-MODE VOLTAGE – V  
R
S
33⍀  
Figure 25b. Frequency Domain Plot FIN = 5 MHz, FS =  
40 MHz (AIN = 2 V Differential)  
Figure 24. Transformer Coupled Input  
This (Figure 24) configuration was used to gather all of the  
differential data on the Specifications pages.  
REV. A  
–15–  
AD9224  
REFERENCE CONFIGURATIONS  
Figure 26b illustrates the relation between reference voltage and  
THD. Note that optimal performance occurs when the refer-  
ence voltage is set to 1.5 V (input span = 3 V).  
The figures associated with this section on internal and external  
reference operation do not show recommended matching series  
resistors for VINA and VINB for the purpose of simplicity.  
Please refer to the Driving the Analog Inputs section for a dis-  
cussion of this topic. Also, the figures do not show the decou-  
pling network associated with the CAPT and CAPB pins.  
Please refer to the Reference Operation section for a discussion  
of the internal reference circuitry and the recommended decou-  
pling network shown in Figure 17.  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
USING THE INTERNAL REFERENCE  
Single-Ended Input with 0 to 2 
؋
 VREF Range  
Figure 26a shows how to connect the AD9224 for a 0 V to 2 V  
or 0 V to 4 V input range via pin strapping the SENSE pin. An  
intermediate input range of 0 to 2 × VREF can be established  
using the resistor programmable configuration in Figure 28.  
In either case, both the midscale voltage and input span are  
directly dependent on the value of VREF. More specifically, the  
midscale voltage is equal to VREF while the input span is equal  
to 2 × VREF. Thus, the valid input range extends from 0 to 2 ×  
VREF. When VINA is 0 V, the digital output will be 000 Hex;  
when VINA is 2 × VREF, the digital output will be FFF Hex.  
1.2  
1.4  
1.6  
1.8  
2.2  
1.0  
2.0  
REFERENCE VOLTAGE – V  
Figure 26b. THD vs. Reference Voltage, FS = 40 MHz,  
FIN = 10 MHz (Differential)  
Figure 27 shows the single-ended configuration that gives good  
dynamic performance (SINAD, SFDR). To optimize dynamic  
specifications, center the common-mode voltage of the analog  
input at approximately by 2.5 V by connecting VINB to a low  
impedance 2.5 V source. As described above, shorting the  
VREF pin directly to the SENSE pin results in a 1 V reference  
voltage and a 2 V p-p input span. The valid range for input  
signals is 1.5 V to 3.5 V. The VREF pin should be bypassed to  
the REFCOM pin with a 10 µF tantalum capacitor in parallel  
with a low-inductance 0.1 µF ceramic capacitor.  
Shorting the VREF pin directly to the SENSE pin places the  
internal reference amplifier in unity-gain mode and the resultant  
VREF output is 1 V. Therefore, the valid input range is 0 V to  
2 V. However, shorting the SENSE pin directly to the REFCOM  
pin configures the internal reference amplifier for a gain of 2.0  
and the resultant VREF output is 2.0 V. Thus, the valid input  
range becomes 0 V to 4 V. The VREF pin should be bypassed to  
the REFCOM pin with a 10 µF tantalum capacitor in parallel  
with a low-inductance 0.1 µF ceramic capacitor.  
This reference configuration could also be used for a differential  
input in which VINA and VINB are driven via a transformer as  
shown in Figure 24. In this case, the common-mode voltage,  
VCM, is set at midsupply by connecting the transformer’s center  
tap to CML of the AD9224. VREF can be configured for 1.0 V or  
2.0 V by connecting SENSE to either VREF or REFCOM re-  
spectively. Note that the valid input range for each of the  
differential inputs is one half of the single-ended input and thus  
becomes VCM – VREF/2 to VCM + VREF/2.  
2 
؋
 VREF  
VINA  
0V  
VINB  
10F  
0.1F  
VREF  
AD9224  
SHORT FOR 0V TO 2V  
INPUT SPAN  
SENSE  
SHORT FOR 0V TO 4V  
INPUT SPAN  
REFCOM  
3.5V  
VINA  
1.5V  
VCM AD9224  
VINB  
Figure 26a. Internal Reference—2 V p-p Input Span,  
VCM = 1 V, or 4 V p-p Input Span  
1V  
VREF  
SENSE  
0.1F  
10F  
REFCOM  
Figure 27. Internal Reference—2 V p-p Input Span,  
VCM = 2.5 V  
–16–  
REV. A  
AD9224  
Resistor Programmable Reference  
The AD9224 contains an internal reference buffer, A2 (see  
Figure 16), that simplifies the drive requirements of an external  
reference. The external reference must be able to drive about  
5 k(±20%) load. Note that the bandwidth of the reference  
buffer is deliberately left small to minimize the reference noise  
contribution. As a result, it is not possible to change the refer-  
ence voltage rapidly in this mode.  
Figure 28 shows an example of how to generate a reference  
voltage other than 1.0 V or 2.0 V with the addition of two exter-  
nal resistors and a bypass capacitor. Use the equation,  
VREF = 1 V × (1 + R1/R2),  
to determine appropriate values for R1 and R2. These resistors  
should be in the 2 kto 100 krange. For the example shown,  
R1 equals 2.5 kand R2 equals 5 k. From the equation  
above, the resultant reference voltage on the VREF pin is 1.5 V.  
This sets the input span to be 3 V p-p. To assure stability, place  
a 0.1 µF ceramic capacitor in parallel with R1.  
2.5V+VREF  
2.5V  
2.5V–VREF  
VINA  
VINB  
AD9224  
2.5V  
REF  
+5V  
0.1F  
22F  
0.1F  
R1  
R2  
4V  
VINA  
A1  
VREF  
1V  
AD9224  
0.1F  
2.5V  
VINB  
SENSE  
1.5V  
C1  
+5V  
VREF  
R1  
2.5k⍀  
0.1F  
10F  
0.1F  
Figure 29. External Reference  
SENSE  
R2  
5k⍀  
Variable Input Span with VCM = 2.5 V  
Figure 29 shows an example of the AD9224 configured for an  
input span of 2 × VREF centered at 2.5 V. An external 2.5 V  
reference drives the VINB pin thus setting the common-mode  
voltage at 2.5 V. The input span can be independently set by a  
voltage divider consisting of R1 and R2 which generates the  
VREF signal. A1 buffers this resistor network and drives  
VREF. Choose this op amp based on accuracy requirements. It  
is essential that a minimum of a 10 µF capacitor in parallel with  
a 0.1 µF low inductance ceramic capacitor decouple the A1’s  
output to ground.  
REFCOM  
Figure 28. Resistor Programmable Reference—3 V p-p  
Input Span, VCM = 2.5 V  
The midscale voltage can be set to VREF by connecting VINB  
to VREF to provide an input span of 0 to 2 × VREF. Alterna-  
tively, the midscale voltage can be set to 2.5 V by connecting  
VINB to a low impedance 2.5 V source. For the example shown,  
the valid input single-ended range for VINA is 1 V to 4 V since  
VINB is set to an external, low impedance 2.5 V source. The  
VREF pin should be bypassed to the REFCOM pin with a  
10 µF tantalum capacitor in parallel with a low inductance  
0.1 µF ceramic capacitor.  
Single-Ended Input with 0 to 2 
؋
 VREF Range  
Figure 30 shows an example of an external reference driving  
both VINB and VREF. In this case, both the common-mode  
voltage and input span are directly dependent on the value of  
VREF. More specifically, the common-mode voltage is equal to  
VREF while the input span is equal to 2 × VREF. Thus, the  
valid input range extends from 0 to 2 × VREF. For example, if  
the REF191, a 2.048 V external reference was selected, the  
valid input range extends from 0 to 4.096 V. In this case, 1 LSB  
of the AD9224 corresponds to 1 mV. It is essential that a mini-  
mum of a 10 µF capacitor in parallel with a 0.1 µF low inductance  
ceramic capacitor decouple the reference output to ground.  
USING AN EXTERNAL REFERENCE  
Using an external reference may enhance the dc performance  
of the AD9224 by improving drift and accuracy. Figures 29 and  
30 show examples of how to use an external reference with the  
A/D. Table III is a list of suitable voltage references from Ana-  
log Devices. To use an external reference, the user must disable  
the internal reference amplifier and drive the VREF pin.  
Connecting the SENSE pin to AVDD disables the internal  
reference amplifier.  
2 
؋
 REF  
VINA  
0V  
Table III. Suitable Voltage References  
Initial  
+5V  
VINB  
VREF  
0.1F  
10F  
0.1F  
AD9224  
Output  
Voltage  
Drift  
(ppm/؇C)  
Accuracy  
% (max)  
Operating  
Current  
VREF  
0.1F  
Internal  
AD589  
AD1580 1.225  
REF191 2.048  
1.00  
1.235  
26  
1.4  
1 mA  
50 µA  
50 µA  
45 µA  
1 mA  
+5V  
SENSE  
10–100  
50–100  
5–25  
26  
1.2–2.8  
0.08–0.8  
0.1–0.5  
1.4  
Figure 30. Input Range = 0 V to 2 × VREF  
Internal  
2.0  
REV. A  
–17–  
AD9224  
DIGITAL INPUTS AND OUTPUTS  
Digital Output Driver Considerations (DRVDD)  
Digital Outputs  
The AD9224 output drivers can be configured to interface with  
+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V  
respectively. The output drivers are sized to provide sufficient  
output current to drive a wide variety of logic families. However,  
large drive currents tend to cause glitches on the supplies and  
may affect SINAD performance. Applications requiring the  
ADC to drive large capacitive loads or large fanout may require  
additional decoupling capacitors on DRVDD. In extreme cases,  
external buffers or latches may be required.  
The AD9224 output data is presented in positive true straight  
binary for all input ranges. Table IV indicates the output data  
formats for various input ranges regardless of the selected input  
range. A twos complement output data format can be created  
by inverting the MSB.  
Table IV. Output Data Format  
I
nput (V)  
Condition (V)  
Digital Output  
OTR  
Clock Input and Considerations  
VINA–VINB  
VINA–VINB  
VINA–VINB  
VINA–VINB  
VINA–VINB  
< – VREF  
= – VREF  
= 0  
= + VREF – 1 LSB 1111 1111 1111  
+ VREF 1111 1111 1111  
0000 0000 0000  
0000 0000 0000  
1000 0000 0000  
1
0
0
0
1
The AD9224 internal timing uses the two edges of the clock  
input to generate a variety of internal timing signals. The clock  
input must meet or exceed the minimum specified pulse width  
high and low (tCH and tCL) specifications for the given A/D as  
defined in the Switching Specifications at the beginning of the  
data sheet to meet the rated performance specifications. For  
example, the clock input to the AD9224 operating at 40 MSPS  
may have a duty cycle between 49% to 51% to meet this timing  
requirement since the minimum specified tCH and tCL is 12.37 ns.  
For low clock rates below 40 MSPS, the duty cycle may deviate  
from this range to the extent that both tCH and tCL are satisfied.  
+FS –1 1/2 LSB  
OTR DATA OUTPUTS  
1111 1111 1111  
1111 1111 1111  
1111 1111 1110  
OTR  
1
0
0
–FS+1/2 LSB  
0000 0000 0001  
0000 0000 0000  
0000 0000 0000  
0
0
1
High speed high resolution A/Ds are sensitive to the quality of  
the clock input. The degradation in SNR at a given full-scale  
input frequency (fIN) due only to aperture jitter (tA) can be cal-  
culated with the following equation:  
–FS  
–FS –1/2 LSB  
+FS  
+FS –1/2 LSB  
Figure 31. Output Data Format  
SNR = 20 log10 [1/2 π fIN tA]  
Out of Range (OTR)  
In the equation, the rms aperture jitter, tA, represents the root-  
sum square of all the jitter sources, which include the clock in-  
put, analog input signal, and A/D aperture jitter specification.  
Undersampling applications are particularly sensitive to jitter.  
An out-of-range condition exists when the analog input voltage  
is beyond the input range of the converter. OTR is a digital out-  
put that is updated along with the data output corresponding to  
the particular sampled analog input voltage. Hence, OTR has  
the same pipeline delay (latency) as the digital data. It is LOW  
when the analog input voltage is within the analog input range.  
It is HIGH when the analog input voltage exceeds the input  
range as shown in Figure 31. OTR will remain HIGH until the  
analog input returns within the input range and another conver-  
sion is completed. By logical ANDing OTR with the MSB  
and its complement, overrange high or underrange low con-  
ditions can be detected. Table V is a truth table for the over/  
underrange circuit in Figure 32 which uses NAND gates. Sys-  
tems requiring programmable gain conditioning of the AD9224  
input signal can immediately detect an out-of-range condition,  
thus eliminating gain selection iterations. Also, OTR can be  
used for digital offset and gain calibration.  
Clock input should be treated as an analog signal in cases where  
aperture jitter may affect the dynamic range of the AD9224.  
Power supplies for clock drivers should be separated from the  
A/D output driver supplies to avoid modulating the clock signal  
with digital noise. Low jitter crystal controlled oscillators make  
the best clock sources. If the clock is generated from another  
type of source (by gating, dividing or other method), it should  
be retimed by the original clock at the last step.  
The clock input is referred to the analog supply. Its logic thresh-  
old is AVDD/2. If the clock is being generated by 3 V logic, it  
will have to be level shifted into 5 V CMOS logic levels. This  
can also be accomplished by ac-coupling and level-shifting the  
clock signal.  
Table V. Out-of-Range Truth Table  
The AD9224 has a very tight clock tolerance at 40 MHz. One  
way to minimize the tolerance of a 50% duty cycle clock is to  
divide down a clock of higher frequency, as shown in Figure 33.  
OTR  
MSB  
Analog Input Is  
0
0
1
1
0
1
0
1
In Range  
In Range  
Underrange  
Overrange  
+5V  
R
D
Q
MSB  
OTR  
MSB  
OVER = “1”  
40MHz  
80MHz  
Q
S
UNDER = “1”  
+5V  
Figure 32. Overrange or Underrange Logic  
Figure 33. Divide-by-Two Clock Circuit  
–18–  
REV. A  
AD9224  
In this case an 80 MHz clock is divided by two to produce the  
40 MHz clock input for the AD9224. In this configuration, the  
duty cycle of the 80 MHz clock is irrelevant.  
The AD9224 is well suited for various IF sampling applications.  
The AD9224’s low distortion input SHA has a full-power  
bandwidth extending beyond 120 MHz, thus encompassing  
many popular IF frequencies. A DNL of ±0.7 LSB (typ) com-  
bined with low thermal input referred noise allows the AD9224  
in the 2 V span to provide 69 dB of SNR for a baseband input  
sine wave. Also, its low aperture jitter of 4 ps rms ensures  
minimum SNR degradation at higher IF frequencies. In fact,  
the AD9224 is capable of still maintaining 64.5 dB of SNR at  
an IF of 71 MHz with a 2 V input span. Note, although the  
AD9224 can yield a 1 dB to 2 dB improvement in SNR when  
configured for the larger 4 V span, the 2 V span achieves the  
optimum full- scale distortion performance at these higher input  
frequencies. Also, the 2 V span reduces the performance re-  
quirements of the input driver circuitry (i.e., IP3) and thus may  
also be more attractive from a system implementation perspective.  
The input circuitry for the CLOCK pin is designed to accom-  
modate CMOS inputs. The quality of the logic input, particu-  
larly the rising edge, is critical in realizing the best possible jitter  
performance of the part: the faster the rising edge, the better the  
jitter performance.  
As a result, careful selection of the logic family for the clock  
driver, as well as the fanout and capacitive load on the clock  
line, is important. Jitter-induced errors become more predomi-  
nant at higher frequency, large amplitude inputs, where the  
input slew rate is greatest.  
Most of the power dissipated by the AD9224 is from the analog  
power supplies. However, lower clock speeds will reduce digital  
current. Figure 34 shows the relationship between power and  
clock rate.  
Figure 35 shows a simplified schematic of the AD9224 config-  
ured in an IF sampling application. To reduce the complexity of  
the digital demodulator in many quadrature demodulation ap-  
plications, the IF frequency and/or sample rate are strategically  
selected such that the bandlimited IF signal aliases back into the  
center of the ADC’s baseband region (i.e., FS/4). For example,  
if an IF signal centered at 45 MHz is sampled at 36 MSPS, an  
image of this IF signal will be aliased back to 9.0 MHz, which  
corresponds to one quarter of the sample rate (i.e., FS/4). This  
demodulation technique typically reduces the complexity of the  
post digital demodulator ASIC which follows the ADC.  
460  
440  
420  
2V INTERNAL REFERENCE  
400  
380  
1V INTERNAL REFERENCE  
360  
OPTIONAL  
BANDPASS  
FILTER  
HIGH  
LINEARITY  
RF AMPLIFIER  
SAW  
FILTER  
340  
AD9224  
MINICIRCUITS  
T4-6T  
FROM  
PREVIOUS  
STAGES  
MIXER  
20  
200⍀  
20⍀  
VINA  
320  
300  
RF2317  
RF2312  
VINB  
CML  
15  
20  
25  
30  
35  
40  
45  
50  
SAMPLE RATE – MHz  
0.1F  
Figure 34. Power Consumption vs. Clock Rate  
VREF  
SENSE  
Direct IF Down Conversion Using the AD9224  
0.1F  
10F  
Sampling IF signals above an ADC’s baseband region (i.e., dc  
to FS/2) is becoming increasingly popular in communication  
applications. This process is often referred to as Direct IF Down  
Conversion or Undersampling. There are several potential ben-  
efits in using the ADC to alias (or mix) down a narrowband or  
wideband IF signal. First and foremost is the elimination of a  
complete mixer stage with its associated baseband amplifiers  
and filters, reducing cost and power dissipation. Second is the  
ability to apply various DSP techniques to perform such func-  
tions as filtering, channel selection, quadrature demodulation,  
data reduction, detection, etc. A detailed discussion on using  
this technique in digital receivers can be found in Analog De-  
vices Application Notes AN-301 and AN-302.  
REFCOM  
Figure 35. Example of AD9224 IF Sampling Circuit  
To maximize its distortion performance, the AD9224 is config-  
ured in the differential mode with a 2 V span using a transformer.  
The center-tap of the transformer is biased at midsupply via the  
CML output of the AD9224. Preceding the AD9224 and trans-  
former is an optional bandpass filter as well as a gain stage. A  
low Q passive bandpass filter can be inserted to reduce out-  
of-band distortion and noise which lies within the AD9224’s  
130 MHz bandwidth. A large gain stage(s) is often required to  
compensate for the high insertion losses of a SAW filter used for  
channel selection and image rejection. The gain stage will also  
provide adequate isolation for the SAW filter from the charge  
“kick back” currents associated with the AD9224’s switched  
capacitor input stage.  
In Direct IF Down Conversion applications, one exploits the  
inherent sampling process of an ADC in which an IF signal  
lying outside the baseband region can be aliased back into the  
baseband region in a similar manner that a mixer will down-  
convert an IF signal. Similar to the mixer topology, an image  
rejection filter is required to limit other potential interfering  
signals from also aliasing back into the ADC’s baseband region.  
A tradeoff exists between the complexity of this image rejection  
filter and the ADC’s sample rate as well as dynamic range.  
REV. A  
–19–  
AD9224  
The distortion and noise performance of an ADC at the given  
IF frequency is of particular concern when evaluating an ADC  
for a narrowband IF sampling application. Both single tone and  
dual tone SFDR vs. amplitude are very useful in assessing an  
ADC’s dynamic and static nonlinearities. SNR vs. amplitude  
performance at the given IF is useful in assessing the ADC’s  
noise performance and noise contribution due to aperture jitter.  
In any application, one is advised to test several units of the  
same device under the same conditions to evaluate the given  
applications sensitivity to that particular device.  
100  
90  
80  
SFDR-SINGLE  
TONE (dBFS)  
SFDR-DUAL  
TONE (dBFS)  
70  
60  
50  
40  
30  
20  
SNR-SINGLE  
TONE (dBc)  
Figures 36–39 combine the dual tone SFDR as well as single  
tone SFDR and SNR performances at IF frequencies of 35 MHz,  
45 MHz, 71 MHz, and 85 MHz. Note, the SFDR vs. amplitude  
data is referenced to dBFS while the single tone SNR data is  
referenced to dBc. The performance characteristics in these  
figures are representative of the AD9224 without any preceding  
gain stage. The AD9224 was operated in the differential mode  
(via transformer) with a 2 V span and a sample rate between  
28 MSPS and 36 MSPS. The analog supply (AVDD) and the  
digital supply (DRVDD) were set to +5 V and +3.3 V respectively.  
10  
0
–0.5  
–5  
–10  
–15  
–20  
–25  
–30  
A
– dBFS  
IN  
Figure 37. IF Undersampling at 45 MHz (F1 = 44.53 MHz,  
F2 = 45.55 MHz, fCLOCK = 36 MSPS)  
100  
90  
100  
90  
80  
SFDR-DUAL  
TONE (dBFS)  
SFDR-SINGLE  
TONE (dBFS)  
70  
60  
50  
40  
30  
20  
80  
SFDR-SINGLE  
TONE (dBFS)  
SFDR-DUAL  
TONE (dBFS)  
70  
60  
SNR-SINGLE  
TONE (dBc)  
SNR-SINGLE  
TONE (dBc)  
50  
40  
30  
20  
10  
0
10  
0
–0.5  
–5  
–10  
–15  
– dBFS  
–20  
–25  
–30  
A
IN  
Figure 38. IF Undersampling at 70 MHz (F1 = 70.46 MHz,  
F2 = 71.36 MHz, fCLOCK = 31.5 MSPS)  
–15  
–0.5  
–5  
–10  
–20  
–25  
–30  
A
– dBFS  
IN  
Figure 36. IF Undersampling at 35 MHz (F1 = 34.64 MHz,  
F2 = 35.43 MHz, fCLOCK = 28 MSPS)  
100  
SFDR-SINGLE  
TONE (dBFS)  
90  
80  
70  
60  
50  
40  
30  
SFDR-DUAL  
TONE (dBFS)  
SNR-SINGLE  
TONE (dBc)  
20  
10  
0
–0.5  
–5  
–10  
–15  
– dBFS  
–20  
–25  
30  
A
IN  
Figure 39. IF Undersampling at 85 MHz (F1 = 84.46 MHz,  
F2 = 85.36 MHz, fCLOCK = 31 MSPS)  
–20–  
REV. A  
AD9224  
GROUNDING AND DECOUPLING  
Analog and Digital Driver Supply Decoupling  
Analog and Digital Grounding  
The AD9224 features separate analog and digital supply and  
ground pins, helping to minimize digital corruption of sensitive  
analog signals. In general, AVDD, the analog supply, should be  
decoupled to AVSS, the analog common, as close to the chip as  
physically possible. Figure 41 shows the recommended decou-  
pling for the analog supplies; 0.1 µF ceramic chip and 10 µF  
tantalum capacitors should provide adequately low impedance  
over a wide frequency range. Note that the AVDD and AVSS  
pins are colocated on the AD9224 to simplify the layout of the  
decoupling capacitors and provide the shortest possible PCB  
trace lengths. The AD9224/AD9225EB power plane layout,  
shown in Figure 48 depicts a typical arrangement using a multi-  
layer PCB.  
Proper grounding is essential in any high speed, high resolution  
system. Multilayer printed circuit boards (PCBs) are recom-  
mended to provide optimal grounding and power schemes. The  
use of ground and power planes offers distinct advantages:  
1. The minimization of the loop area encompassed by a signal  
and its return path.  
2. The minimization of the impedance associated with ground  
and power paths.  
3. The inherent distributed capacitor formed by the power  
plane, PCB insulation and ground plane.  
These characteristics result in both a reduction of electromag-  
netic interference (EMI) and an overall improvement in  
performance.  
AVDD  
10F  
AD9224  
0.1F  
It is important to design a layout that prevents noise from cou-  
pling onto the input signal. Digital signals should not be run in  
parallel with input signal traces and should be routed away from  
the input circuitry. While the AD9224 features separate analog  
and driver ground pins, it should be treated as an analog com-  
ponent. The AVSS and DRVSS pins must be joined together  
directly under the AD9224. A solid ground plane under the A/D  
is acceptable if the power and ground return currents are care-  
fully managed. Alternatively, the ground plane under the A/D  
may contain serrations to steer currents in predictable directions  
where cross coupling between analog and digital would other-  
wise be unavoidable. The AD9224/AD9225EB ground layout,  
shown in Figure 47, depicts the serrated type of arrangement.  
AVSS  
Figure 41. Analog Supply Decoupling  
The CML is an internal analog bias point used internally by the  
AD9224. This pin must be decoupled with at least a 0.1 µF  
capacitor as shown in Figure 42. The dc level of CML is ap-  
proximately AVDD/2. This voltage should be buffered if it is to  
be used for any external biasing.  
CML  
0.1F  
AD9224  
The evaluation board is primarily built over a common ground  
plane. It has a “slit” to route currents near the clock driver. Figure  
40 illustrates a general scheme of ground and power implementa-  
tion in and around the AD9224.  
Figure 42. CML Decoupling  
The digital activity on the AD9224 chip falls into two general  
categories: correction logic, and output drivers. The internal  
correction logic draws relatively small surges of current, mainly  
during the clock transitions. The output drivers draw large  
current impulses while the output bits are changing. The size  
and duration of these currents are a function of the load on the  
output bits: large capacitive loads are to be avoided. Note, the  
internal correction logic of the AD9224 is referenced to AVDD  
while the output drivers are referenced to DRVDD.  
LOGIC  
SUPPLY  
AVDD  
DVDD  
A
A
D
ADC  
IC  
DIGITAL  
LOGIC  
ICs  
C
C
STRAY  
The decoupling shown in Figure 43, a 0.1 µF ceramic chip and  
10 µF tantalum capacitors are appropriate for a reasonable  
capacitive load on the digital outputs (typically 20 pF on each  
pin). Applications involving greater digital loads should consider  
increasing the digital decoupling proportionally, and/or using  
external buffers/latches.  
ANALOG  
CIRCUITS  
DIGITAL  
CIRCUITS  
V
IN  
B
A
A
STRAY  
I
I
A
D
GND  
D
AVSS  
DVSS  
= ANALOG  
= DIGITAL  
A
V  
A
A
DRVDD  
D
10F  
AD9224  
0.1F  
Figure 40. Ground and Power Consideration  
DRVSS  
Figure 43. Digital Supply Decoupling  
A complete decoupling scheme will also include large tantalum  
or electrolytic capacitors on the PCB to reduce low frequency  
ripple to negligible levels. Refer to the AD9224/AD9225EB  
schematic and layouts in Figures 44-50 for more information  
regarding the placement of decoupling capacitors.  
REV. A  
–21–  
AD9224  
U5  
REF43  
6
TP38  
R34  
50⍀  
1
2
1
2
TP34  
1
L2  
FBEAD  
J4  
VOUT  
VCC  
VIN  
GND  
DUTAVDD  
1
2
JP22  
JP23  
JP24  
JP25  
1
2
AVDDIN1  
2
1
C18  
1
2
C30  
2
2
+
1
1
1
2
AVDD  
JP26  
1
2
P3  
P3  
C39  
10F  
10V  
1
4
0.1F  
1
2
R31  
1
+
0.001F  
1
TP31  
1
TP30  
R25  
2.49k⍀  
2
C47  
C22  
10F  
10V  
+
820⍀  
C52  
0.1F  
JP21  
22F  
20V  
1
2
2
2
2
1
C36  
0.1F  
JP19  
1
AGND  
1
1
1
1
2
2
1
2
C57  
0.1F  
R3  
+
2
C28  
1
+
10k⍀  
1
C2  
2
1
2
0.1F  
2
1
C29  
0.1F  
2
AVDD  
1
10F  
10V  
2
R26  
4.99k⍀  
2
7
3
2
14  
13  
12  
11  
10  
9
8
7
6
5
R4  
15  
IN  
AVDD2  
AVSS2  
SENSE  
VREF  
OTR  
D11  
D10  
D9  
OTR  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
2
8
R29  
3
1
10k⍀  
1
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
JP20  
+V  
U4  
AD187  
1
1k⍀  
2
C21  
10F  
10V  
+
1
2
N2  
OUT  
C35  
0.1F  
6
2
1
2
Q1  
2N2222  
2
2
R28  
50⍀  
N1  
1
2
C27  
0.1F  
2
REFCOM  
CAPB  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
–V  
IN  
4
1
2
R27  
4.99k⍀  
1
C34  
0.1F  
1
2
1
2
2
1
C20  
10F  
10V  
CAPT  
CML  
VINA  
VINB  
AVSS1  
AVDD1  
DRVSS  
DRVDD  
C26  
C33  
U3  
1
2
1
+
0.1F  
0.1F  
VEE  
R30  
316⍀  
1
2
2
C19  
10F  
10V  
1
C31  
0.1F  
2
+
4
3
2
1
2
1
1
C32  
D2  
D1  
D0  
CLK  
0.1F  
TP37  
L3  
FBEAD  
TP29  
1
TP37  
D0  
R32  
50⍀  
VCCIN  
AGND  
1
1
2
CLK  
1
1
1
VCC  
1
P4  
2
J3  
1
+
1
2
C48  
1
2
C24  
0.1F  
JP27  
AD9224  
2
C53  
0.1F  
22F  
2
1
TP27  
DRVDD  
20V  
2
JP18  
R21  
200⍀  
1
TP33  
1
DUTDRVDD  
1
1
2
1
1
2
P4  
C1  
10F  
10V  
+
C37  
0.1F  
C40  
0.001F  
1
1
2
2
2
1
1
C42  
15pF  
R23  
200⍀  
TP28  
1
R22  
200⍀  
TP32  
1
2
DUTAUDD  
2
T1  
4
5
6
2
1
1
+
J1  
1
2
1
2
C23  
10F  
10V  
C41  
0.001F  
C38  
0.1F  
2
3
1
2
1
2
1
1
1
2
C46  
15pF  
C45  
15pF  
C44  
15pF  
C43  
15pF  
R24  
50⍀  
2
1
2
C25  
0.1F  
2
2
T4-6T  
TP36  
L6  
FBEAD  
L4  
FBEAD  
L1  
TP40  
TP5  
1
DUTAVDDIN  
2
FBEAD  
1
1
2
VEEIN  
1
1
2
DVDDIN  
DGND  
1
2
P6  
P6  
DUTAVDD  
3
P4  
VEE  
1
P2  
DVDD  
1
+
1
+
2
1
C58  
1
C49  
22F  
20V  
1
2
C59  
1
2
22F  
20V  
AGND  
C6  
C54  
0.1F  
+
C14  
0.1F  
0.1F  
22F  
2
2
20V  
2
1
C12  
0.1F  
2
P2  
TP6  
U9  
1
2
JP10  
JP4  
2
R17 22⍀  
10  
11  
1
TP25  
TP24  
TP23  
TP22  
TP21  
TP20  
TP19  
TP26  
TP18  
TP17  
TP16  
TP15  
1
1
1
2
2
2
1
1
1
1
1
2
1
P1  
P1  
P1  
P1  
P1  
2
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
C4  
TP7  
L7404  
U9  
JP1  
2
R5 22⍀  
10V 10F  
JP11  
JP12  
8
9
1
2
2
2
1
2
+ 1  
3
5
7
9
4
R6 22⍀  
TP8  
JP5  
2
U9  
1
1
1
1
1
1
1
1
1
1
1
1
L7404  
6
5
6
1
R7 22⍀  
1
20  
10  
1
1
G1  
G2  
VCC  
GND  
8
L7404  
DRVDD  
L5  
FBEAD  
19  
U9  
R8 22⍀  
JP16  
DRVDDIN  
DGND  
1
2
2
1
13  
12  
3
U6  
1
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
P5  
B
A
D11  
2
18  
17  
16  
15  
14  
13  
12  
11  
74541  
A1  
A2  
A3  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
2
1
+
R9 22⍀  
1
2
3
4
5
6
7
8
9
C51  
22F  
20V  
L7404  
1
1
2
C56  
0.1F  
11 P1  
13 P1  
D10  
D9  
D8  
D7  
D6  
D5  
R10 22⍀  
2
DVDD  
1
+
1
2
2
P5  
A4  
A5  
A6  
A7  
A8  
C7  
C15  
0.1F  
10F  
R11 22⍀  
10V  
TP39  
1
2
2
2
R35  
50⍀  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
P1  
R12 22⍀  
1
2
1
1
U1  
REF43  
U9  
1
2
J5  
DECOUPLING  
C11  
0.1F  
2
R13 22⍀  
1
2
VOUT  
VIN  
GND  
AVDD  
2
1
1
R14 22⍀  
C8  
1
2
1
2
1
2
C9  
+
3
+
C16  
0.1F  
C17  
0.1F  
1
2
10F  
10V  
10F  
10V  
JP3  
JP2  
C5  
10V 10F  
2
1
2
R15 22⍀  
1
20  
1
2
+
1
2
G1  
G2  
VCC  
GND  
2
1
19  
10  
R19  
4k⍀  
R2  
R18  
5k⍀  
1k⍀  
2
2
1
1
1
2
18  
D4  
D3  
D2  
D1  
D0  
A1  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
CW  
CCV  
3
4
5
6
7
8
9
JP17  
17  
16  
15  
14  
13  
12  
11  
2
A2  
A3  
A4  
A5  
A6  
A7  
A8  
3
1
U7  
A
B
2
74541  
C13  
0.1F  
1
TP4  
U8  
U8  
JP9  
1
3
1
2
3
1
2
4
9
8
J2  
CLK  
OTR  
1
R16  
2
L7404  
JP14  
L7404  
1
2
R1  
TP14  
TP13  
TP12  
TP11  
22⍀  
2
JP15  
3
1
2
1
1
50⍀  
1
B
A
B
A
2
1
JP32  
U9  
2
1
1
1
TP9  
1
U9  
1
TP10  
1
U8  
2
3
4
JP13  
1
16  
1
2
5
6
VCC  
CLR  
JP28  
JP30  
15  
14  
13  
12  
11  
10  
R20  
2
3
4
5
6
7
8
TP1  
L7404  
L7404  
RCO  
QA  
1
2
CLK  
A
B
C
D
U8  
22⍀  
L7404  
JP6  
2
11  
1
1
2
10  
JP29  
U2  
1
2
AVDD  
QB  
QC  
QD  
1
TP2  
74LS161  
1
U8  
C3  
10F  
10V  
+
L7404  
C10  
DVDD  
JP7  
1
1
2
13  
12  
1
2
1
+
0.1F  
1
2
C50  
2
2
C55  
0.1F  
ENT  
JP31  
ENP  
GND  
TP3  
1
10F  
U8  
L7404  
2
9
1
U8  
JP8  
10V  
2
LOAD  
1
2
1
2
DECOUPLING  
R33  
1k⍀  
2
1
L7404  
DVDD  
Figure 44. Evaluation Board Schematic  
–22–  
REV. A  
AD9224  
Figure 48. Evaluation Board Solder Side Layout (Not to  
Scale)  
Figure 45. Evaluation Board Component Side Layout (Not  
to Scale)  
Figure 49. Evaluation Board Power Plane Layout  
Figure 46. Evaluation Board Ground Plane Layout (Not to  
Scale)  
Figure 50. Evaluation Board Solder Side Silkscreen (Not  
to Scale)  
Figure 47. Evaluation Board Component Side Silkscreen  
(Not to Scale)  
REV. A  
–23–  
AD9224  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
28-Lead Shrink Small Outline (SSOP)  
(RS-28)  
0.407 (10.34)  
0.397 (10.08)  
28  
15  
1
14  
0.07 (1.79)  
0.066 (1.67)  
0.078 (1.98)  
0.068 (1.73)  
PIN 1  
0.03 (0.762)  
0.022 (0.558)  
8°  
0°  
0.0256 0.015 (0.38)  
0.008 (0.203)  
0.002 (0.050)  
SEATING  
PLANE  
0.009 (0.229)  
0.005 (0.127)  
(0.65)  
0.010 (0.25)  
BSC  
–24–  
REV. A  
配单直通车
AD9224ARSZRL产品参数
型号:AD9224ARSZRL
Brand Name:Analog Devices Inc
是否无铅:含铅
是否Rohs认证:符合
生命周期:Active
IHS 制造商:ANALOG DEVICES INC
零件包装代码:SSOP
包装说明:SSOP, SSOP28,.3
针数:28
制造商包装代码:RS-28
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:1.27
Is Samacsys:N
最大模拟输入电压:5.25 V
最小模拟输入电压:
转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:R-PDSO-G28
JESD-609代码:e3
长度:10.2 mm
最大线性误差 (EL):0.061%
湿度敏感等级:1
模拟输入通道数量:1
位数:12
功能数量:1
端子数量:28
最高工作温度:85 °C
最低工作温度:-40 °C
输出位码:BINARY, 2'S COMPLEMENT BINARY
输出格式:PARALLEL, WORD
封装主体材料:PLASTIC/EPOXY
封装代码:SSOP
封装等效代码:SSOP28,.3
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260
电源:3/5,5 V
认证状态:Not Qualified
采样速率:40 MHz
采样并保持/跟踪并保持:SAMPLE
座面最大高度:2 mm
子类别:Analog to Digital Converters
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:30
宽度:5.3 mm
Base Number Matches:1
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