AD9235BRUZ-65中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

12-Bit, 20/40/65 MSPS

3 V A/D Converter

AD9235

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

DRVDD

Single 3 V supply operation (2.7 V to 3.6 V)

SNR = 70 dBc to Nyquist at 65 MSPS

SFDR = 85 dBc to Nyquist at 65 MSPS

Low power: 300 mW at 65 MSPS

Differential input with 500 MHz bandwidth

On-chip reference and SHA

VIN+

VIN–

8-STAGE

1 1/2-BIT

PIPELINE

SHA

A/D

MDAC1

4

16

3

REFT

REFB

A/D

DNL = 0.4 LSB

CORRECTION LOGIC

12

Flexible analog input: 1 V p-p to 2 V p-p range

Offset binary or twos complement data format

Clock duty cycle stabilizer

OUTPUT BUFFERS

OTR

D11

AD9235

VREF

D0

CLOCK

DUTY CYCLE

STABILIZER

APPLICATIONS

Ultrasound equipment

IF sampling in communications receivers

IS-95, CDMA-One, IMT-2000

Battery-powered instruments

Hand-held scopemeters

MODE

SELECT

SENSE

REF

SELECT

0.5V

AGND

CLK

PDWN

MODE

DGND

Figure 1.

Low cost digital oscilloscopes

GENERAL DESCRIPTION

can be used with the most significant bit to determine low or

high overflow.

The AD9235 is a family of monolithic, single 3 V supply, 12-bit,

20/40/65 MSPS analog-to-digital converters (ADCs). This

family features a high performance sample-and-hold amplifier

(SHA) and voltage reference. The AD9235 uses a multistage

differential pipelined architecture with output error correction

logic to provide 12-bit accuracy at 20/40/65 MSPS data rates

and guarantee no missing codes over the full operating

temperature range.

Fabricated on an advanced CMOS process, the AD9235 is avail-

able in a 28-lead TSSOP and a 32-lead LFCSP and is specified

over the industrial temperature range (–40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9235 operates from a single 3 V power supply and

features a separate digital output driver supply to accommo-

date 2.5 V and 3.3 V logic families.

2. Operating at 65 MSPS, the AD9235 consumes a low 300 m W.

3. The patented SHA input maintains excellent performance for

input frequencies up to 100 MHz and can be configured for

single-ended or differential operation.

4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,

65 MSPS ADC. This allows a simplified upgrade path from

10 bits to 12 bits for 65 MSPS systems.

The wide bandwidth, truly differential SHA allows a variety of

user-selectable input ranges and offsets including single-ended

applications. It is suitable for multiplexed systems that switch

full-scale voltage levels in successive channels and for sampling

single-channel inputs at frequencies well beyond the Nyquist rate.

Combined with power and cost savings over previously available

ADCs, the AD9235 is suitable for applications in communica-

tions, imaging, and medical ultrasound.

5. The clock DCS maintains overall ADC performance over a

wide range of clock pulse widths.

6. The OTR output bit indicates when the signal is beyond the

selected input range.

A single-ended clock input is used to control all internal

conversion cycles. A duty cycle stabilizer (DCS) compensates

for wide variations in the clock duty cycle while maintaining

excellent overall ADC performance. The digital output data is

presented in straight binary or twos complement formats. An

out-of-range (OTR) signal indicates an overflow condition that

Rev. D

Information furnishedby Analog Devices is believedto be accurate andreliable. However, nore-

sponsibility is assumed by Analog Devices for its use, nor for anyinfringements of patentsor other

rightsofthird partiesthat may result from its use. Specifications subject to change without notice. No

license isgrantedbyimplication or otherwise under anypatent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9235

Data Sheet

TABLE OF CONTENTS

Specifications..................................................................................... 3

Applying the AD9235 .................................................................... 15

Theory of Operation .................................................................. 15

Analog Input ............................................................................... 15

Clock Input Considerations...................................................... 16

Power Dissipation and Standby Mode .................................... 17

Digital Outputs ........................................................................... 18

Voltage Reference ....................................................................... 18

Operational Mode Selection..................................................... 19

TSSOP Evaluation Board .......................................................... 19

LFCSP Evaluation Board........................................................... 20

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 37

DC Specifications ......................................................................... 3

Digital Specifications ................................................................... 4

Switching Specifications .............................................................. 4

AC Specifications.......................................................................... 5

Absolute Maximum Ratings............................................................ 7

Explanation of Test Levels........................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Definitions of Specifications ........................................................... 9

Equivalent Circuits ......................................................................... 10

Typical Performance Characteristics ........................................... 11

REVISION HISTORY

Changes to TPCs 1 to 12 ..................................................................9

Changes to Theory of Operation Section.....................................13

Changes to Analog Input Section..................................................13

Changes to Single-ended Input Configuration Section .............14

Replaced Figure 8 ............................................................................14

Changes to Clock Input Considerations Section ........................14

Changes to Table I ...........................................................................15

Changes to Power Dissipation and Standby Mode Section.......15

Changes to Digital Outputs Section..............................................15

Changes to Timing Section............................................................15

Changes to Figure 13.......................................................................16

Changes to Figures 16 to 26 ...........................................................17

Added LFCSP Evaluation Board Section .....................................17

Inserted Figures 27 to 35 ................................................................25

Added Table III................................................................................30

Updated Outline Dimensions........................................................31

10/12—Rev. C to Rev. D

Changes to Figure 4 and Table 6 ................................................................8

Updated Outline Dimensions (Changed CP-32-2 to CP-32-7)..... 36

Changes to Ordering Guide .......................................................... 37

10/04—Data Sheet changed from Rev. B to Rev. C

Changes to Format .............................................................Universal

Changes to Specifications .................................................................3

Changes to the Ordering Guide.................................................... 37

5/03—Data Sheet changed from Rev. A to Rev. B

Added CP-32 Package (LFCSP)........................................Universal

Changes to Several Pin Names..........................................Universal

Changes to Features...........................................................................1

Changes to Product Description .....................................................1

Changes to Product Highlights........................................................1

Changes to Specifications .................................................................2

Replaced Figure 1 ..............................................................................3

Changes to Absolute Maximum Ratings........................................5

Changes to Ordering Guide .............................................................5

Changes to Pin Function Descriptions...........................................6

New Definitions of Specifications Section .....................................7

8/02—Data Sheet changed from Rev. 0 to Rev. A

Updated RU-28 Package................................................................ 24

Rev. D | Page 2 of 40

Data Sheet

AD9235

SPECIFICATIONS

DC SPECIFICATIONS

AV DD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, T_MINto T_MAX

,

unless otherwise noted.

Table 1.

AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65

Test

Temp Level Min Typ

Parameter

Max

Min Typ

Max

Min Typ

Max

Unit

RESOLUTION

Full

VI

12

Bits

ACCURACY

No Missing Codes Guaranteed

Offset Error

Full

25°C

Full

25°C

VI

IV

I

12

Bits

0.30

0.35

0.45

0.40

1.20

2.40

0.65

0.50

1.20

2.50

0.75

0.50

1.20 % FSR

2.60 % FSR

0.80 LSB

LSB

1.30 LSB

LSB

Gain Error¹

0.50

0.35

0.50

0.40

0.50

0.40

0.35

0.70

0.45

Differential Nonlinearity (DNL)²

Integral Nonlinearity (INL)²

IV

I

0.80

0.90

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

V

2

12

2

12

3

12

ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode)

Load Regulation @ 1.0 mA

Full

VI

V

5

35

5

35

5

35

mV

0.8

2.5

0.1

0.8

2.5

0.1

0.8

2.5

0.1

Output Voltage Error (0.5 V Mode) Full

Load Regulation @ 0.5 mA

INPUT REFERRED NOISE

VREF = 0.5 V

Full

V

25°C

V

0.54

0.27

0.54

0.27

0.54

0.27

LSB rms

VREF = 1.0 V

ANALOG INPUT

Input Span, VREF = 0.5 V

Input Span, VREF = 1.0 V

Input Capacitance³

REFERENCE INPUT RESISTANCE

POWER SUPPLIES

Supply Voltages

AVDD

Full

IV

V

1

2

7

1

2

7

1

2

7

V p-p

pF

V

kΩ

Full

IV

2.7

3.0

2.25 3.0

3.6

2.7

3.0

2.25 3.0

3.6

2.7

3.0

2.25 3.0

3.6

V

DRVDD

Supply Current

IAVDD²

Full

V

30

2

0.01

55

5

0.01

100

7

0.01

mA

% FSR

IDRVDD²

PSRR

POWER CONSUMPTION

DC Input⁴

Sine Wave Input²

Standby Power⁵

Full

V

VI

V

90

95

1.0

165

180

1.0

300

320

1.0

mW

110

205

350

¹Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).

²Measured at maximum clock rate, f_IN= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.

³Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.

⁴Measured with dc input at maximum clock rate.

⁵Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).

Rev. D | Page 3 of 40

AD9235

Data Sheet

DIGITAL SPECIFICATIONS

Table 2.

AD9235BRU/BCP-20

AD9235BRU/BCP-40

AD9235BRU/BCP-65

Test

Temp Level Min

Parameter

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

LOGIC INPUTS

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

LOGIC OUTPUTS¹

Full

IV

V

2.0

V

µA

pF

0.8

+10

0.8

+10

0.8

+10

–10

2

DRVDD = 3.3 V

High-Level Output Voltage

(IOH = 50 µA)

High-Level Output Voltage

(IOH = 0.5 mA)

Low-Level Output Voltage

(IOL = 1.6 mA)

Low-Level Output Voltage

(IOL = 50 µA)

Full

IV

3.29

3.25

3.29

3.25

3.29

3.25

V

0.2

0.05

DRVDD = 2.5 V

High-Level Output Voltage

(IOH = 50 µA)

High-Level Output Voltage

(IOH = 0.5 mA)

Low-Level Output Voltage

(IOL = 1.6 mA)

Low-Level Output Voltage

(IOL = 50 µA)

Full

IV

2.49

2.45

2.49

2.45

2.49

2.45

V

0.2

0.05

¹Output voltage levels measured with 5 pF load on each output.

SWITCHING SPECIFICATIONS

Table 3.

AD9235BRU/BCP-20

AD9235BRU/BCP-40

AD9235BRU/BCP-65

Test

Parameter

Temp Level Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Maximum Conversion Rate

Minimum Conversion Rate

CLK Period

CLK Pulse-Width High¹

CLK Pulse-Width Low¹

DATA OUTPUT PARAMETERS

Output Delay²(t_PD)

Pipeline Delay (Latency)

Aperture Delay (t_A)

Aperture Uncertainty Jitter (t_J)

Wake-Up Time³

Full

VI

V

20

40

65

MSPS

ns

1

50.0

15.0

25.0

8.8

15.4

6.2

Full

V

3.5

7

1.0

0.5

3.0

1

3.5

7

1.0

0.5

3.0

1

3.5

7

1.0

0.5

3.0

2

ns

Cycles

ns

ps rms

ms

OUT-OF-RANGE RECOVERY TIME

Cycles

¹For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.

²Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.

³Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.

Rev. D | Page 4 of 40

Data Sheet

AD9235

N+1

t_A

N

N+2

N+8

N–1

N+3

ANALOG

INPUT

N+7

N+4

N+6

N+5

CLK

DATA

OUT

N–9

N–8

N–7

N–6

N–5

N–4

N–3

N–2

N–1

N

t_PD= 6.0ns MAX

2.0ns MIN

Figure 2. Timing Diagram

AC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, A_IN= –0.5 dBFS, 1.0 V internal reference, T_MINto T_MAX

,

unless otherwise noted.

Table 4.

AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65

Parameter

Temp Test Level Min Typ

Max

Min Typ

Max

Min Typ

Max

Unit

SIGNAL-TO-NOISE RATIO

f_INPUT= 2.4 MHz

f_INPUT= 9.7 MHz

25°C

Full

25°C

Full

25°C

Full

25°C

V

IV

I

IV

I

IV

I

V

70.8

70.0 70.4

70.6

70.5

dBc

f_INPUT= 19.6 MHz

f_INPUT= 32.5 MHz

f_INPUT= 100 MHz

69.9 70.3

70.4

68.7 69.7

70.1

68.7

68.5

70.5

68.3

SIGNAL-TO-NOISE RATIO

AND DISTORTION

f_INPUT= 2.4 MHz

f_INPUT= 9.7 MHz

25°C

Full

25°C

Full

25°C

Full

25°C

V

IV

I

IV

I

IV

I

V

70.6

69.9 70.3

70.5

70.4

dBc

f_INPUT= 19.6 MHz

f_INPUT= 32.5 MHz

69.7 70.2

70.3

68.3 69.5

69.9

f_INPUT= 100 MHz

68.6

68.3

67.8

TOTAL HARMONIC DISTORTION

f_INPUT= 2.4 MHz

f_INPUT= 9.7 MHz

25°C

Full

25°C

Full

25°C

Full

25°C

V

IV

I

IV

I

IV

I

V

–88.0

–86.0 –79.0

–87.4

–89.0

–87.5

dBc

f_INPUT= 19.6 MHz

f_INPUT= 32.5 MHz

f_INPUT= 100 MHz

–85.5 –79.0

–86.0

–81.8 –74.0 dBc

–82.0

–78.0

dBc

–84.0

–82.5

WORST HARMONIC

(SECOND OR THIRD)

f_INPUT= 9.7 MHz

f_INPUT= 19.6 MHz

f_INPUT= 32.5 MHz

Full

IV

–90.0 –80.0

dBc

–90.0 –80.0

–83.5 –74.0 dBc

Rev. D | Page 5 of 40

AD9235

Data Sheet

AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65

Parameter

Temp Test Level Min Typ

Max

Min Typ

Max

Min Typ

Max

Unit

SPURIOUS-FREE DYNAMIC RANGE

f_INPUT= 2.4 MHz

f_INPUT= 9.7 MHz

25°C

Full

25°C

Full

25°C

Full

25°C

V

IV

I

IV

I

IV

I

V

92.0

80.0 88.5

91.0

92.0

dBc

f_INPUT= 19.6 MHz

f_INPUT= 32.5 MHz

f_INPUT= 100 MHz

80.0 89.0

90.0

74.0 83.0

85.0

84.0

85.0

80.5

Rev. D | Page 6 of 40

Data Sheet

AD9235

ABSOLUTE MAXIMUM RATINGS

Table 5.

Absolute maximum ratings are limiting values to be applied

With

individually and beyond which the serviceability of the circuit

may be impaired. Functional operability is not necessarily

implied. Exposure to absolute maximum rating conditions for

an extended period of time may affect device reliability.

Pin Name

ELECTRICAL

AVDD

DRVDD

AGND

AVDD

Digital

Outputs

CLK, MODE

VIN+, VIN–

VREF

SENSE

REFB, REFT

PDWN

Respect to Min

Max

Unit

AGND

DGND

DRVDD

DGND

–0.3

–3.9

–0.3

+3.9

+0.3

+3.9

V

EXPLANATION OF TEST LEVELS

Test

Levels

DRVDD + 0.3

Description

I

100% production tested.

AGND

–0.3

AVDD + 0.3

V

II

100% production tested at 25°C and sample tested at

specified temperatures.

III

Sample tested only.

IV

Parameter is guaranteed by design and characteriza-

tion testing.

V

Parameter is a typical value only.

ENVIRONMENTAL¹

VI

100% production tested at 25°C; guaranteed by de-

sign and characterization testing for industrial tem-

perature range; 100% production tested at tempera-

ture extremes for military devices.

Operating Temperature

Junction Temperature

Lead Temperature (10 sec)

Storage Temperature

–40

–65

+85

150

300

°C

+150

¹Typical thermal impedances (28-lead TSSOP), θ_JA= 67.7°C/W; (32-lead

LFCSP), θ_JA= 32.5°C/W, θ_JC= 32.71°C/W. These measurements were taken on

a 4-layer board in still air, in accordance with EIA/JESD51-1.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-

trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation

or loss of functionality.

Rev. D | Page 7 of 40

AD9235

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

OTR

MODE

SENSE

VREF

REFB

REFT

AVDD

AGND

VIN+

D11 (MSB)

D10

3

D9

DNC 1

24 VREF

23

4

D8

2

CLK

SENSE

5

AD9235

TOP VIEW

(Not to Scale)

DRVDD

DGND

D7

DNC 3

PDWN 4

22 MODE

21 OTR

AD9235

6

TOP VIEW

5

6

7

8

20

19

18

DNC

D0 (LSB)

D1

D11 (MSB)

D10

D9

7

(Not to Scale)

8

D6

9

D5

17 D8

10

11

12

13

14

VIN–

D4

AGND

AVDD

CLK

D3

D2

D1

NOTES

PDWN

D0 (LSB)

1. DNC = DO NOT CONNECT.

2. IT IS RECOMMENDED THAT THE EXPOSED PADDLE

BE SOLDERED TO THE GROUND PLANE.

Figure 3. 28-Lead TSSOP Pin Configuration

Figure 4. 32-Lead LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

28-Lead TSSOP

Pin No.

32-Lead LFCSP Mnemonic

Description

1

21

OTR

Out-of-Range Indicator.

2

3

4

5

6

7, 12

8, 11

9

22

23

24

25

26

27, 32

28, 31

29

MODE

SENSE

VREF

REFB

REFT

AVDD

AGND

VIN+

VIN–

Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.

Reference Mode Selection.

Voltage Reference Input/Output.

Differential Reference (−).

Differential Reference (+).

Analog Power Supply.

Analog Ground.

Analog Input Pin (+).

Analog Input Pin (−).

10

30

13

2

CLK

Clock Input Pin.

14

4

PDWN

Power-Down Function Selection (Active High).

15 to 22, 25 to 28

7 to 14, 17 to 20

D0 (LSB) to D11 (MSB) Data Output Bits.

23

24

15

16

DGND

DRVDD

Digital Output Ground.

Digital Output Driver Supply. Must be decoupled to DGND with a minimum.

0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF.

Do Not Connect.

Exposed Pad. It is recommended that the exposed paddle be soldered to the

ground plane. There is an increased reliability of the solder joints and maxi-

mum thermal capability of the package is achieved with exposed paddle

soldered to the customer board.

1, 3, 5, 6

EP

DNC

EPAD

Rev. D | Page 8 of 40

Data Sheet

AD9235

DEFINITIONS OF SPECIFICATIONS

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Signal-to-Noise and Distortion (SINAD)¹

The ratio of the rms signal amplitude (set 0.5 dB below full

scale) to the rms value of the sum of all other spectral compo-

nents below the Nyquist frequency, including harmonics but

excluding dc.

Aperture Delay (t_A)

The delay between the 50% point of the rising edge of the clock

and the instant at which the analog input is sampled.

Effective Number of Bits (ENOB)

The ENOB for a device for sine wave inputs at a given input

frequency can be calculated directly from its measured SINAD

using the following formula

Aperture Jitter (t_J)

The sample-to-sample variation in aperture delay.

N = (SINAD − 1.76)/6.02

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from

negative full scale through positive full scale. The point used as

negative full scale occurs ½ LSB before the first code transition.

Positive full scale is defined as a level 1 ½ LSBs beyond the last

code transition. The deviation is measured from the middle of

each particular code to the true straight line.

Signal-to-Noise Ratio (SNR)¹

The ratio of the rms signal amplitude (set at 0.5 dB below full

scale) to the rms value of the sum of all other spectral compo-

nents below the Nyquist frequency, excluding the first six

harmonics and dc.

Spurious-Free Dynamic Range (SFDR)¹

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed

no missing codes to 12-bit resolution indicates that all 4096

codes must be present over all operating ranges.

The difference in dB between the rms amplitude of the input

signal and the peak spurious signal.

Two-Tone SFDR¹

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product.

Offset Error

The major carry transition should occur for an analog value

½ LSB below VIN+ = VIN–. Offset error is defined as the

deviation of the actual transition from that point.

Clock Pulse Width and Duty Cycle

Pulse-width high is the minimum amount of time that the

clock pulse should be left in the Logic 1 state to achieve rated

performance. Pulse-width low is the minimum time the clock

pulse should be left in the low state. At a given clock rate, these

specifications define an acceptable clock duty cycle.

Gain Error

The first code transition should occur at an analog value ½ LSB

above negative full scale. The last transition should occur at an

analog value 1 ½ LSB below the positive full scale. Gain error is

the deviation of the actual difference between first and last code

transitions and the ideal difference between first and last code

transitions.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the

guaranteed limit.

Temperature Drift

The temperature drift for offset error and gain error specifies

the maximum change from the initial (25°C) value to the value

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

at T_MINor T_MAX

.

Output Propagation Delay (t_PD

)

The delay between the clock logic threshold and the time when

all bits are within valid logic levels.

Power Supply Rejection Ratio

The change in full scale from the value with the supply

at the minimum limit to the value with the supply at its

maximum limit.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input

after a transition from 10% above positive full scale to 10%

above negative full scale, or from 10% below negative full scale

to 10% below positive full scale.

Total Harmonic Distortion (THD)¹

The ratio of the rms sum of the first six harmonic components

to the rms value of the measured input signal.

¹AC specifications may be reported in dBc (degrades as signal levels are

lowered) or in dBFS (always related back to converter full scale).

Rev. D | Page 9 of 40

AD9235

Data Sheet

EQUIVALENT CIRCUITS

AVDD

DRVDD

VIN+, VIN–

D11–D0,

OTR

Figure 5. Equivalent Analog Input Circuit

Figure 7. Equivalent Digital Output Circuit

AVDD

CLK,

MODE

PDWN

20kΩ

Figure 6. Equivalent MODE Input Circuit

Figure 8. Equivalent Digital Input Circuit

Rev. D | Page 10 of 40

Data Sheet

AD9235

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.0 V, DRVDD = 2.5 V, f_SAMPLE= 65 MSPS with DCS disabled, T_A= 25°C, 2 V differential input, A_IN= −0.5 dBFS, VREF = 1.0 V,

unless otherwise noted.

0

100

95

90

85

80

75

70

65

60

55

50

SNR = 70.3dBc

SFDR (2V DIFF)

SINAD = 70.2dBc

ENOB = 11.4 BITS

THD = –86.3dBc

SFDR = 89.9dBc

–20

–40

SNR (2V SE)

–60

–80

SNR (2V DIFF)

–100

–120

SFDR (2V SE)

45

0

6.5

13.0

19.5

26.0

32.5

40

50

55

60

65

FREQUENCY (MHz)

SAMPLE RATE (MSPS)

Figure 9. Single Tone 8K FFT with f_IN= 10 MHz

Figure 12. AD9235-65: Single Tone SNR/SFDR vs.

_CLKwith f_IN= Nyquist (32.5 MHz)

f

0

–20

100

95

90

85

80

75

70

65

60

55

50

SNR = 69.4dBc

SINAD = 69.1dBc

ENOB = 11.2 BITS

THD = –81.0dBc

SFDR = 83.8dBc

–40

SFDR (2V DIFF)

SNR (2V SE)

SNR (2V DIFF)

–60

–80

SFDR (2V SE)

–100

–120

65.0

71.5

78.0

84.5

91.0

20

25

30

SAMPLE RATE (MSPS)

35

40

FREQUENCY (MHz)

Figure 10. Single Tone 8K FFT with f_IN= 70 MHz

Figure 13. AD9235-40: Single Tone SNR/SFDR vs. f_CLKwith f_IN= Nyquist (20 MHz)

0

100

SNR = 68.5dBc

SFDR (2V DIFF)

95

SINAD = 66.5dBc

ENOB = 10.8 BITS

THD = –71.0dBc

SFDR = 71.2dBc

–20

90

85

–40

–60

SFDR (2V SE)

80

75

SNR (2V SE)

70

–80

65

SNR (2V DIFF)

60

55

50

–100

–120

97.5

104.0

110.5

117.0

123.5

130.0

0

5

10

15

20

FREQUENCY (MHz)

SAMPLE RATE (MSPS)

Figure 11. Single Tone 8K FFT with f_IN= 100 MHz

Figure 14. AD9235-20: Single Tone SNR/SFDR vs. f_CLKwith f_IN= Nyquist (10 MHz)

Rev. D | Page 11 of 40

AD9235

Data Sheet

100

95

90

85

80

75

70

65

SFDR

DIFFERENTIAL (dBFS)

SINGLE-ENDED (dBFS)

90

SFDR

DIFFERENTIAL (dBc)

SFDR

SNR

DIFFERENTIAL (dBFS)

80

70

60

50

40

SNR

SINGLE-ENDED (dBFS)

SFDR

SINGLE-ENDED (dBc)

SNR

SINGLE-ENDED (dBc)

SNR

DIFFERENTIAL (dBc)

–30

–25

–20

–15

–10

–5

0

25

50

75

100

125

A

(dBFS)

INPUT FREQUENCY (MHz)

IN

Figure 18. AD9235-65: SNR/SFDR vs. f_IN

Figure 15. AD9235-65: Single Tone SNR/SFDR vs.

_INwith f_IN= Nyquist (32.5 MHz)

A

95

90

85

80

75

70

65

100

90

80

70

60

50

40

SFDR

DIFFERENTIAL (dBFS)

SFDR

SINGLE-ENDED

(dBFS)

SFDR

DIFFERENTIAL

(dBc)

SNR

DIFFERENTIAL

(dBFS)

SNR

SINGLE-ENDED

(dBFS)

SFDR

SINGLE-ENDED (dBc)

SNR

DIFFERENTIAL (dBc)

SNR

SINGLE-ENDED (dBc)

0

25

50

75

100

125

–30

–25

–20

–15

–10

–5

0

INPUT FREQUENCY (MHz)

A

(dBFS)

IN

Figure 19. AD9235-40: SNR/SFDR vs. f_IN

Figure 16. AD9235-40: Single Tone SNR/SFDR vs. A_INwith f_IN= Nyquist (20 MHz)

95

90

85

80

75

70

65

100

SFDR DIFFERENTIAL (dBFS)

SFDR

90

DIFFERENTIAL (dBc)

SFDR

SINGLE-ENDED (dBFS)

SFDR

80

70

60

50

40

SNR

SINGLE-ENDED(dBc)

DIFFERENTIAL (dBFS)

SNR

SINGLE-ENDED (dBFS)

SNR

DIFFERENTIAL(dBc)

SNR

SINGLE-ENDED (dBc)

0

25

50

75

100

125

–30

–25

–20

–15

–10

–5

0

INPUT FREQUENCY (MHz)

A

(dBFS)

IN

Figure 20. AD9235-20: SNR/SFDR vs. f_IN

Figure 17. AD9235-20: Single Tone SNR/SFDR vs. A_INwith f_IN= Nyquist (10 MHz)

Rev. D | Page 12 of 40

Data Sheet

AD9235

0

95

90

85

80

75

70

65

60

SNR = 64.6dBFS

SFDR = 81.6dBFS

2V SFDR

1V SFDR

–20

–40

–60

–80

2V SNR

1V SNR

–100

–120

32.5

39.0

45.5

52.0

58.5

65.0

–24

–21

–18

–15

(dBFS)

–12

–9

–6

FREQUENCY (MHz)

A

IN

Figure 21. Dual Tone 8K FFT with f_IN1= 45 MHz and f_IN2= 46 MHz

Figure 24. Dual Tone SNR/SFDR vs. A_INwith f_IN1= 45 MHz and f_IN2= 46 MHz

95

0

SNR = 64.3dBFS

2V SFDR

SFDR = 81.1dBFS

90

–20

1V SFDR

85

80

75

–40

–60

–80

2V SNR

1V SNR

70

–100

65

60

–24

–120

65.0

–21

–18

–15

–12

–9

–6

71.5

78.0

84.5

91.0

97.5

A

(dBFS)

FREQUENCY (MHz)

IN

Figure 22. Dual Tone 8K FFT with f_IN1= 69 MHz and f_IN2= 70 MHz

Figure 25. Dual Tone SNR/SFDR vs. A_INwith f_IN1= 69 MHz and f_IN2= 70 MHz

0

95

SNR = 62.5dBFS

SFDR = 75.6dBFS

2V SFDR

90

–20

–40

1V SFDR

85

80

75

–60

–80

2V SNR

1V SNR

70

–100

65

–120

130.0

60

–24

136.5

143.0

149.5

156.0

162.0

–21

–18

–15

–12

–9

–6

FREQUENCY (MHz)

A

(dBFS)

IN

Figure 23. Dual Tone 8K FFT with f_IN1= 144 MHz and f_IN2= 145 MHz

Figure 26. Dual Tone SNR/SFDR vs. A_INwith f_IN1= 144 MHz and f_IN2= 145 MHz

Rev. D | Page 13 of 40

AD9235

Data Sheet

20

15

75

12.2

11.7

11.2

10.7

10.2

9.7

AD9235-40:

2V SINAD

AD9235-65:

2V SINAD

AD9235-20:

2V SINAD

72

69

66

63

60

10

5

AD9235-20:

1V SINAD

AD9235-40:

1V SINAD

0

–5

AD9235-65:

1V SINAD

–10

–15

–20

0

10

20

30

40

50

60

–40

–20

0

20

40

60

80

SAMPLE RATE (MSPS)

TEMPERATURE (°C)

Figure 27. SINAD vs. f_CLKwith f_IN= Nyquist

Figure 30. A/D Gain vs. Temperature Using an External Reference

90

1.0

0.8

SFDR: DCS ON

80

70

60

50

40

30

0.6

SFDR: DCS OFF

SINAD: DCS ON

0.4

0.2

SINAD: DCS OFF

0

–0.2

–0.4

–0.6

–0.8

–1.0

35

40

45

50

55

60

65

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

DUTY CYCLE (%)

Figure 28. SINAD/SFDR vs. Clock Duty Cycle

Figure 31. Typical INL

90

85

80

75

70

65

60

55

50

1.0

0.8

SFDR 2V DIFF

0.6

0.4

SFDR 1V DIFF

SINAD 2V DIFF

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

SINAD 1V DIFF

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80

0

500

1000

1500 2000 2500

CODE

3000

3500

4000

SAMPLE RATE (MSPS)

Figure 29. SINAD/SFDR vs. Temperature with f_IN= 32.5 MHz

Figure 32. Typical DNL

Rev. D | Page 14 of 40

Data Sheet

AD9235

APPLYING THE AD9235

For best dynamic performance, the source impedances driving

VIN+ and VIN– should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC.

THEORY OF OPERATION

The AD9235 architecture consists of a front end SHA followed

by a pipelined switched capacitor ADC. The pipelined ADC is

divided into three sections, consisting of a 4-bit first stage

followed by eight 1.5-bit stages and a final 3-bit flash. Each stage

provides sufficient overlap to correct for flash errors in the

preceding stages. The quantized outputs from each stage are

combined into a final 12-bit result in the digital correction log-

ic. The pipelined architecture permits the first stage to operate

on a new input sample while the remaining stages operate on

preceding samples. Sampling occurs on the rising edge

of the clock.

H

T

5pF

VIN+

VIN–

C

PAR

T

PAR

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

T

H

Figure 33. Switched-Capacitor SHA Input

An internal differential reference buffer creates positive and

negative reference voltages, REFT and REFB, respectively, that

define the span of the ADC core. The output common mode of

the reference buffer is set to midsupply, and the REFT and

REFB voltages and span are defined as:

The input stage contains a differential SHA that can be ac- or

dc-coupled in differential or single-ended modes. The output-

staging block aligns the data, carries out the error correction,

and passes the data to the output buffers. The output buffers are

powered from a separate supply, allowing adjustment of the

output voltage swing. During power-down, the output buffers

go into a high impedance state.

REFT = ½(AVDD + VREF)

REFB = ½(AVDD − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

ANALOG INPUT

It can be seen from the equations above that the REFT and

REFB voltages are symmetrical about the midsupply voltage

and, by definition, the input span is twice the value of the

VREF voltage.

The analog input to the AD9235 is a differential switched

capacitor SHA that has been designed for optimum perfor-

mance while processing a differential input signal. The SHA

input can support a wide common-mode range and maintain

excellent performance, as shown in Figure 34. An input

common-mode voltage of midsupply minimizes signal-

dependent errors and provides optimum performance.

90

85

80

75

70

65

60

55

50

–90

–85

–80

–75

–70

–65

–60

–55

–50

THD 2.5MHz 2V DIFF

THD 35MHz 2V DIFF

SNR 2.5MHz 2V DIFF

Referring to Figure 33, the clock signal alternatively switches

the SHA between sample mode and hold mode. When the SHA

is switched into sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current required from the output

stage of the driving source. Also, a small shunt capacitor can be

placed across the inputs to provide dynamic charging currents.

This passive network creates a low-pass filter at the ADC’s

input; therefore, the precise values are dependent upon the

application. In IF undersampling applications, any shunt

capacitors should be removed. In combination with the driving

source impedance, they would limit the input bandwidth.

SNR 35MHz 2V DIFF

0

0.5

1.0

1.5

2.0

2.5

3.0

COMMON-MODE LEVEL (V)

Figure 34. AD9235-65: SNR, THD vs. Common-Mode Level

Rev. D | Page 15 of 40

AD9235

Data Sheet

The internal voltage reference can be pin-strapped to fixed

values of 0.5 V or 1.0 V, or adjusted within the same range as

discussed in the Internal Reference Connection section. Maxi-

mum SNR performance is achieved with the AD9235 set to the

largest input span of 2 V p-p. The relative SNR degradation is

3 dB when changing from 2 V p-p mode to 1 V p-p mode.

differential transformer coupling is the recommended input

configuration, as shown in Figure 36.

AVDD

22Ω

VIN+

15pF

AD9235

2Vp-p

49.9Ω

22Ω

The SHA may be driven from a source that keeps the signal

peaks within the allowable range for the selected reference volt-

age. The minimum and maximum common-mode input levels

are defined as:

VIN–

AGND

1kΩ

15pF

0.1µF

1kΩ

Figure 36. Differential Transformer-Coupled Configuration

VCM_MIN= VREF/2

The signal characteristics must be considered when selecting a

transformer. Most RF transformers saturate at frequencies

below a few MHz, and excessive signal power can also cause

core saturation, which leads to distortion.

VCM_MAX= (AVDD + VREF)/2

The minimum common-mode input level allows the AD9235 to

accommodate ground-referenced inputs.

Single-Ended Input Configuration

Although optimum performance is achieved with a differential

input, a single-ended source may be driven into VIN+ or VIN–.

In this configuration, one input accepts the signal, while the

opposite input should be set to midscale by connecting it to an

appropriate reference. For example, a 2 V p-p signal may be

applied to VIN+ while a 1 V reference is applied to VIN–. The

AD9235 then accepts an input signal varying between 2 V and

0 V. In the single-ended configuration, distortion performance

may degrade significantly as compared to the differential case.

However, the effect is less noticeable at lower input frequencies and

in the lower speed grade models (AD9235-40 and AD9235-20).

A single-ended input may provide adequate performance in

cost-sensitive applications. In this configuration, there is degra-

dation in SFDR and in distortion performance due to the large

input common-mode swing. However, if the source

impedances on each input are matched, there should be little

effect on SNR performance. Figure 37 details a typical single-

ended input configuration.

1kΩ

AVDD

VIN+

0.33µF

22Ω

2Vp-p

49.9Ω

1kΩ

15pF

Differential Input Configurations

AD9235

As previously detailed, optimum performance is achieved while

driving the AD9235 in a differential input configuration. For

baseband applications, the AD8138 differential driver provides

excellent performance and a flexible interface to the ADC. The

output common-mode voltage of the AD8138 is easily set to

AVDD/2, and the driver can be configured in a Sallen-Key filter

topology to provide band limiting of the input signal.

22Ω

VIN–

AGND

10µF

0.1µF

15pF

1kΩ

Figure 37. Single-Ended Input Configuration

CLOCK INPUT CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals, and as a result, may be sensi-

tive to clock duty cycle. Commonly a 5% tolerance is required

on the clock duty cycle to maintain dynamic performance char-

acteristics. The AD9235 contains a clock duty cycle stabilizer

(DCS) that retimes the nonsampling edge, providing an internal

clock signal with a nominal 50% duty cycle. This allows a wide

range of clock input duty cycles without affecting the perfor-

mance of the AD9235. As shown in Figure 30, noise and distor-

tion performance are nearly flat over a 30% range of duty cycle.

49.9Ω

1Vp-p

499Ω

AVDD

VIN+

22Ω

499Ω

523Ω

1kΩ

15pF

AD9235

AD8138

499Ω

22Ω

VIN–

AGND

0.1µF

1kΩ

15pF

Figure 35. Differential Input Configuration Using the AD8138

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately 100 clock cycles to

allow the DLL to acquire and lock to the new rate.

At input frequencies in the second Nyquist zone and above, the

performance of most amplifiers is not adequate to achieve the

true performance of the AD9235. This is especially true in IF

undersampling applications where frequencies in the 70 MHz to

100 MHz range are being sampled. For these applications,

Rev. D | Page 16 of 40

Data Sheet

AD9235

325

300

275

250

225

200

175

150

125

100

75

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given full-scale

input frequency (f_INPUT) due only to aperture jitter (t_J) can be

calculated by

AD9235-65

SNR Degradation = −20 × log₁₀[2π × f_INPUT× t_J]

In the equation, the rms aperture jitter, t_J, represents the root-

sum square of all jitter sources, which include the clock input,

analog input signal, and ADC aperture jitter specification.

Undersampling applications are particularly sensitive to jitter.

AD9235-40

AD9235-20

10

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the

AD9235. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter, crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other

methods), it should be retimed by the original clock at the last

step.

50

0

20

30

40

50

60

SAMPLE RATE (MSPS)

Figure 38. Total Power vs. Sample Rate with f_IN= 10 MHz

For the AD9235-20 speed grade, the digital power consumption

can represent as much as 10% of the total dissipation. Digital

power consumption can be minimized by reducing the capaci-

tive load presented to the output drivers. The data in Figure 38

was taken with a 5 pF load on each output driver.

POWER DISSIPATION AND STANDBY MODE

The analog circuitry is optimally biased so that each speed

grade provides excellent performance while affording reduced

power consumption. Each speed grade dissipates a baseline

power at low sample rates that increases linearly with the clock

frequency.

As shown in Figure 38, the power dissipated by the AD9235 is

proportional to its sample rate. The digital power dissipation

does not vary substantially between the three speed grades

because it is determined primarily by the strength of the digital

drivers and the load on each output bit. The maximum DRVDD

current can be calculated as

By asserting the PDWN pin high, the AD9235 is placed in

standby mode. In this state, the ADC typically dissipates 1 mW

if the CLK and analog inputs are static. During standby, the

output drivers are placed in a high impedance state. Reasserting

the PDWN pin low returns the AD9235 into its normal

operational mode.

I_DRVDD= V_DRVDD× C_LOAD× f_CLK× N

where N is the number of output bits, 12 in the case of the

AD9235. This maximum current occurs when every output bit

switches on every clock cycle, i.e., a full-scale square wave at the

Nyquist frequency, f_CLK/2. In practice, the DRVDD current is

established by the average number of output bits switching,

which is determined by the encode rate and the characteristics

of the analog input signal.

Low power dissipation in standby mode is achieved by shutting

down the reference, reference buffer, and biasing networks. The

decoupling capacitors on REFT and REFB are discharged when

entering standby mode and then must be recharged when

returning to normal operation. As a result, the wake-up time is

related to the time spent in standby mode, and shorter standby

cycles result in proportionally shorter wake-up times. With the

recommended 0.1 µF and 10 µF decoupling capacitors on REFT

and REFB, it takes approximately 1 sec to fully discharge the

reference buffer decoupling capacitors and 3 ms to restore full

operation.

Rev. D | Page 17 of 40

AD9235

Data Sheet

Table 7. Reference Configuration Summary

Selected Mode

SENSE Voltage Internal Switch Position

Resulting VREF (V)

Resulting Differential Span (V p-p)

External Reference

AVDD

N/A

2 × External Reference

Internal Fixed Reference

Programmable Reference

Internal Fixed Reference

VREF

0.2 V to VREF

AGND to 0.2 V

SENSE

Internal Divider

0.5

1.0

0.5 × (1 + R2/R1)

1.0

2 × VREF (See Figure 40)

2.0

SENSE pin. This puts the reference amplifier in a noninverting

mode with the VREF output defined as

DIGITAL OUTPUTS

The AD9235 output drivers can be configured to interface with

2.5 V or 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic. The output drivers are sized to

provide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fan-outs may require external buffers or latches.

VREF = 0.5 × (1 + R2/R1)

VIN+

VIN–

REFT

0.1µF

+

ADC

CORE

0.1µF

REFB

0.1µF

10µF

As detailed in Table 8, the data format can be selected for either

offset binary or twos complement.

VREF

0.1µF

+

Timing

10µF

0.5V

SELECT

LOGIC

The AD9235 provides latched data outputs with a pipeline delay

of seven clock cycles. Data outputs are available one propaga-

tion delay (t_PD) after the rising edge of the clock signal. Refer to

Figure 2 for a detailed timing diagram.

SENSE

The length of the output data lines and loads placed on them

should be minimized to reduce transients within the AD9235;

these transients can detract from the converter’s dynamic

performance.

AD9235

Figure 39. Internal Reference Configuration

In all reference configurations, REFT and REFB drive the A/D

conversion core and establish its input span. The input range of

the ADC always equals twice the voltage at the reference pin for

either an internal or an external reference.

The lowest typical conversion rate of the AD9235 is 1 MSPS. At

clock rates below 1 MSPS, dynamic performance may degrade.

VOLTAGE REFERENCE

VIN+

A stable and accurate 0.5 V voltage reference is built into the

AD9235. The input range can be adjusted by varying the refer-

ence voltage applied to the AD9235, using either the internal

reference or an externally applied reference voltage. The input

span of the ADC tracks reference voltage changes linearly.

VIN–

REFT

0.1µF

+

ADC

CORE

0.1µF

REFB

0.1µF

10µF

If the ADC is being driven differentially through a transformer,

the reference voltage can be used to bias the center tap

(common-mode voltage).

VREF

0.1µF

+

10µF

0.5V

R2

SELECT

LOGIC

Internal Reference Connection

A comparator within the AD9235 detects the potential at the

SENSE pin and configures the reference into one of four possi-

ble states, which are summarized in Table 7. If SENSE is

grounded, the reference amplifier switch is connected to the

internal resistor divider (see Figure 39), setting VREF to 1 V.

Connecting the SENSE pin to VREF switches the reference

amplifier output to the SENSE pin, completing the loop and

providing a 0.5 V reference output. If a resistor divider is

connected as shown in Figure 40, the switch is again set to the

SENSE

R1

AD9235

Figure 40. Programmable Reference Configuration

Rev. D | Page 18 of 40

Data Sheet

AD9235

External Reference Operation

OPERATIONAL MODE SELECTION

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or to improve thermal drift

characteristics. When multiple ADCs track one another, a single

reference (internal or external) may be necessary to reduce gain

matching errors to an acceptable level. A high precision external

reference may also be selected to provide lower gain and offset

temperature drift. Figure 41 shows the typical drift characteris-

tics of the internal reference in both 1 V and 0.5 V modes.

As discussed earlier, the AD9235 can output data in either offset

binary or twos complement format. There is also a provision for

enabling or disabling the clock DCS. The MODE pin is a multi-

level input that controls the data format and DCS state. The

input threshold values and corresponding mode selections are

outlined in Table 8.

Table 8. Mode Selection

MODE Voltage Data Format

Duty Cycle Stabilizer

Twos Complement Disabled

Twos Complement Enabled

1.2

AVDD

2/3 AVDD

1/3 AVDD

AGND (Default)

1.0

Offset Binary

Enabled

Disabled

VREF = 1.0V

0.8

The MODE pin is internally pulled down to AGND by a 20 kΩ

resistor.

VREF = 0.5V

0.6

TSSOP EVALUATION BOARD

0.4

0.2

0

The AD9235 evaluation board provides the support circuitry

required to operate the ADC in its various modes and configu-

rations. The converter can be driven differentially, through an

AD8138 driver or a transformer, or single-ended. Separate pow-

er pins are provided to isolate the DUT from the support cir-

cuitry. Each input configuration can be selected by proper con-

nection of various jumpers (refer to the schematics). Figure 43

shows the typical bench characterization setup used to evaluate

the ac performance of the AD9235. It is critical that signal

sources with very low phase noise (<1 ps rms jitter) be used to

realize the ultimate performance of the converter. Proper filter-

ing of the input signal, to remove harmonics and lower the inte-

grated noise at the input, is also necessary to achieve the speci-

fied noise performance.

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80

TEMPERATURE (°C)

Figure 41. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7 kΩ load. The internal buffer still generates the positive and

negative full-scale references, REFT and REFB, for the ADC

core. The input span is always twice the value of the reference

voltage; therefore, the external reference must be limited to a

maximum of 1 V.

The AUXCLK input should be selected in applications requiring

the lowest jitter and SNR performance, i.e., IF undersampling

characterization. It allows the user to apply a clock input signal

that is 4× the target sample rate of the AD9235. A low-jitter,

differential divide-by-4 counter, the MC100LVEL33D, provides

a 1× clock output that is subsequently returned back to the CLK

input via JP9. For example, a 260 MHz signal (sinusoid) is

divided down to a 65 MHz signal for clocking the ADC. Note

that R1 must be removed with the AUXCLK interface. Lower

jitter is often achieved with this interface since many RF signal

generators display improved phase noise at higher output

frequencies and the slew rate of the sinusoidal output signal is

4× that of a 1× signal of equal amplitude.

If the internal reference of the AD9235 is used to drive multiple

converters to improve gain matching, the loading of the refer-

ence by the other converters must be considered. Figure 42

depicts how the internal reference voltage is affected by loading.

0.05

0

–0.05

0.5V ERROR (%)

–0.10

1V ERROR (%)

Complete schematics and layout plots follow and demonstrate

the proper routing and grounding techniques that should be

applied at the system level.

–0.15

–0.20

–0.25

0

0.5

1.0

1.5

2.0

2.5

3.0

LOAD (mA)

Figure 42. VREF Accuracy vs. Load

Rev. D | Page 19 of 40

AD9235

Data Sheet

LFCSP EVALUATION BOARD

An alternative differential analog input path using an AD8351

op amp is included in the layout but is not populated in produc-

tion. Designers interested in evaluating the op amp with the

ADC should remove C15, R12, and R3 and populate the op amp

circuit. The passive network between the AD8351 outputs and

the AD9235 allows the user to optimize the frequency response

of the op amp for the application.

The typical bench setup used to evaluate the ac performance

of the AD9235 is similar to the TSSOP Evaluation Board

connections (refer to the schematics for connection details).

The AD9235 can be driven single-ended or differentially

through a transformer. Separate power pins are provided to

isolate the DUT from the support circuitry. Each input

configuration can be selected by proper connection of

various jumpers (refer to the schematics).

3V

+

–

AVDD GND DUT GND DUT

DVDD

J1

S4

AVDD

DRVDD

HP8644, 2V p-p

SIGNAL SYNTHESIZER

BAND-PASS

FILTER

REFIN

10MHz

XFMR

INPUT

DATA

CAPTURE

AND

AD9235

TSSOP EVALUATION BOARD

PROCESSING

HP8644, 2V p-p

CLOCK

S1

REFOUT CLOCK SYNTHESIZER

DIVIDER

CLOCK

Figure 43. TSSOP Evaluation Board Connections

Rev. D | Page 20 of 40

Data Sheet

AD9235

RP3 22Ω

RP5 22Ω

1

8

1

8

D0O

D1O

D2O

D3O

D0

D1

D2

D3

D8O

D9O

D8

RP3 22Ω

RP5 22Ω

2

7

2

7

D9

RP3 22Ω

RP5 22Ω

3

6

3

6

D10O

D11O

D10

D11

RP3 22Ω

RP5 22Ω

4

5

4

5

RP4 22Ω

RP6 22Ω

1

8

1

8

D4O

D5O

D6O

D7O

D4

D5

D6

RP4 22Ω

RP6 22Ω

2

7

2

7

RP4 22Ω

RP6 22Ω

3

6

3

6

WHT

TP5

JP23

JP22

RP4 22Ω

RP6 22Ω

DUTAVDD

C36

4

5

4

5

D7 OTRO

OTR

R3

10kΩ

C57

0.1µF

C22

10µF

10V

+

JP25

JP24

TP2

RED

0.1µF

FBEAD

L1

C39

0.001µF

DUTAVDDIN

TB1

JP12

DUTAVDD

2

1

2

3

+

R4

10kΩ

C21

10µF

10V

C58

22µF

25V

AD9235

+

C59

0.1µF

C35

0.1µF

7

8

1

WHT

TP17

AVDD

OTR

D11

D10

D9

OTRO

AGND

TB1

28

27

26

25

22

21

20

19

18

17

16

15

13

AGND

SENSE

VREF

PDWN

REFB

REFT

MODE

VIN+

D0O

3

D1O

4

D2O

C34

0.1µF

14

5

TP1

RED

D8

D3O

D7

D4O

FBEAD

L2

AVDDIN

TB1

6

AVDD

D6

D5O

C20

10µF

10V

C33

0.1µF

2

1

+

2

D5

D6O

C47

22µF

25V

SHEET 3

C50

0.1µF

+

C52

0.1µF

9

VIN+

VIN–

D4

D7O

U1

C32

0.1µF

10

11

12

23

24

VIN–

D3

D8O

AGND

AVDD

DGND

DRVDD

D2

D9O

JP13

AVDD

D1

D10O

D11O

DUTCLK

AVDD

D0

R27

5kΩ

R20

1kΩ

JP7

JP6

JP1

JP2

TP3

RED

CLK

FBEAD

L3

WHT

TP6

DRVDDIN

TB1

JP11

DUTDRVDD

2

1

5

4

R17

1kΩ

DUTAVDD

C23

DUTDRVDD

C48

22µF

25V

+

C53

0.1µF

C1

10µF

10V

AGND

TB1

+

C38

C41

0.001µF

C37

0.1µF

C40

0.001µF

R42

1kΩ

10µF

0.1µF

10V

TP4

RED

TP9

BLK

TP10

BLK

TP15

BLK

TP16

BLK

FBEAD

L4

DVDDIN

TB1

DVDD

2

1

6

C6

22µF

25V

+

TP11

BLK

TP12

BLK

TP13

BLK

TP14

BLK

C14

0.1µF

Figure 44. TSSOP Evaluation Board Schematic, DUT

Rev. D | Page 21 of 40

AD9235

Data Sheet

DVDD

C12

0.1µF

C4

R25

10kΩ

10µF

10V

2

AUXCLK

+

1

3

2

AVDD

1

S5

1

2

20

10

18

17

16

15

14

13

12

11

4

6

5

4

1

2

3

T1–1T

T2

G1

G2

A1

A2

A3

A4

A5

A6

A7

A8

VCC

GND

Y1

19

1N5712

5

6

D2

D1

R11

49.9Ω

RP2 22Ω

DD0

DD1

DD2

DD3

DD4

DD5

DD6

DD7

DD8

DD9

DD10

DD11

DOTR

2

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

7

8

D0

3

4

5

6

7

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

D1

D2

D3

D4

D5

D6

D7

Y2

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

Y3

MC100LVEL33D

U3

U6

74VHC541

R26

10kΩ

8

7

6

5

1

2

Y4

Y5

Y6

Y7

Y8

AVDD

VCC

OUT

REF

VEE

NC

INA

INB

3

4

INCOM

AVDD

9

AVDD

C28

10µ

10V

16

15

14

13

12

11

10

9

+

C24

0.1µF

F

C11

0.1µF

R12

113Ω

R13

113Ω

C27

0.1µF

U8 DECOUPLING

C26

0.1µF

C5

10µF

10V

2

R14

90Ω

R15

90Ω

+

1

20

10

18

17

16

15

14

13

12

11

DACLK

G1

G2

A1

A2

A3

A4

A5

A6

A7

A8

VCC

GND

Y1

19

JP9

2

D8

D9

3

4

5

6

7

Y2

R19

500Ω

R2

10Ω

R18

500Ω

HDR40RAM

J1

D10

D11

Y3

AVDD; 14

AVDD; 7

U7

74VHC541

AVDD

CW

C13

Y4

Y5

Y6

Y7

Y8

CLOCK

R7

WHT

TP7

1

S1

U8

0.1µF

22Ω DUTCLK

1

OTR

2

5

6

2

R1

49.9Ω

74VHC04 74VHC04

JP4

JP3

9

R9

22Ω

U8

3

13

11

9

4

74VHC04

U8

AVDD

12

C8

C10

74VHC04

10µF

10V

0.1µF

U8

U9 DECOUPLING

10

U8

8

74VHC04

Figure 45. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering

Rev. D | Page 22 of 40

Data Sheet

AD9235

AVDD

C7

R23

1kΩ

0.1µF

JP5

SINGLE INPUT

1

S3

2

C9

0.33µF

R5

49.9Ω

JP42

JP40

JP45

R41

1kΩ

C15

10µF

10V

AVDD

C44

15pF

AVDD

R21

22Ω

1

2

C69

VIN+

0.1µF

R32

1kΩ

C44B

C2

VAL

R22

JP46

JP41

JP43

22Ω

R33

1kΩ

C8

0.1µF

VIN–

R37

499Ω

C42

VAL

C43

15pF

R6

40Ω

R34

523Ω

VCC

3

–IN

1

8

4

VO+

AD8138

R35

499Ω

2

AMP INPUT

1

VOC

R10

40Ω

U2

5

S2

VO–

2

+IN

R31

49.9Ω

6

VEE

C45

VAL

C18

0.1µF

R36

499Ω

AVDD

R16

XFMR INPUT

1

C19

6

5

4

1

2

3

C17

VAL

T1–1T

T2

1kΩ

10µF

10V

2

S4

2

+

1

ALT VEE

R24

49.9Ω

TP8

RED

3

2

A

B

R8

1kΩ

C25

0.33µF

C16

0.1µF

1

JP8

Figure 46. TSSOP Evaluation Board Schematic, Analog Inputs

DACLK

AD9762

U4

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DD0

DD1

DD2

DD3

DD4

DD5

DD6

DD7

DD8

DD9

DD10

DD11

MSB-DB11 CLOCK

DVDD

C30

0.1µF

C31

0.01µF

DB10

DB19

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

NC1

NC2

DVDD

DCOM

NC3

3

C29

0.1µF

C46

0.01µF

4

5

AVDD

WHT

TP18

6

COMP2

IOUTA

IOUTB

ACOM

COMP1

FSADJ

REFIO

REFLO

SLEEP

S6

7

R29

49.9Ω

8

C56

0.1µF

9

C55

22pF

10

11

12

13

14

R28

49.9Ω

C51

0.1µF

C49

0.1µF 2kΩ

R30

C54

22pF

Figure 47. TSSOP Evaluation Board Schematic, Optional DAC

Rev. D | Page 23 of 40

AD9235

Data Sheet

Figure 48. TSSOP Evaluation Board Layout, Primary Side

Rev. D | Page 24 of 40

Data Sheet

AD9235

Figure 49. TSSOP Evaluation Board Layout, Secondary Side

Rev. D | Page 25 of 40

AD9235

Data Sheet

Figure 50. TSSOP Evaluation Board Layout, Ground Plane

Rev. D | Page 26 of 40

Data Sheet

AD9235

_

Figure 51. TSSOP Evaluation Board Power Plane

Rev. D | Page 27 of 40

AD9235

Data Sheet

Figure 52. TSSOP Evaluation Board Layout, Primary Silkscreen

Rev. D | Page 28 of 40

Data Sheet

AD9235

Figure 53. TSSOP Evaluation Board Layout, Secondary Silkscreen

Rev. D | Page 29 of 40

AD9235

Data Sheet

EXTREF

1V MAX E1

GND AVDD

C13

C22

R1

0.10µF

10µF

10kΩ

P9 P8 P11

P7

A

B

C

D

R9

10kΩ

C12

0.1µF

GND

E

AVDD

H1

MTHOLE6

P10

1

GND

P2

P6

R5

1kΩ

GND GND

1

2

3

4

5

6

H2

MTHOLE6

MODE

P5

H3

MTHOLE6

C29

10µF

2 2

C9

0.10µF

C11

0.1µF

P1

R7

1kΩ

C8

0.1µF

+

H4

MTHOLE6

GND

3

C7

0.1µF

GND

P3

R6

1kΩ

OVERRANGE BIT

(MSB)

GND

4

P4

1

2

3

4

5

6

7

8

16

DRX

15

24 23 22 21 20 19 18 17

D13X

14

D12X

13

C6

0.1µF

R42

0Ω

D11X

12

D10X

11

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

REFB

REFT

AVDD

AGND

VIN+

DRVDD

DGND

D7

D9X

10

AVDD

DRVDD

GND

D8X

9

AMPIN

GND

R36

1kΩ

R26

1kΩ

D7X

AVDD

RP2 220Ω

GND

VIN+

AD9235

D6

X

OUT

U4

D5

R12

0Ω

R4

33kΩ

C21

10pF

VIN–

T1

ADT 1–1 WT

VIN–

D4

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

C15

0.1µF

D6X

D5X

D4X

D3X

D2X

D1X

D0X

R10

36Ω

E 45

GND

AGND

AVDD

D3

J1

C26

10pF

XFRIN1

NC

GND

1

5

3

6

2

4

AVDD

D2

L1

10nH

CT

R2

XX

C19

(LSB)

C16

AMP

C5

0.1µF

GND

1

2

3

4

5

6

7

8

OR L1

0.1µF

PRI SEC

GND

15pF

FOR FILTER

GND

RP1 220Ω

CLK

P14

R11

36Ω

OPTIONAL XFR

T2

FT C1–1–13

R3

0Ω

R8

1kΩ

GND

C23

X

B

OUT

10pF

1

5

2

4

P13

AMPINB

X FRIN

X

OUT

AVDD

GND

R15

CT

X

33Ω

3

B

C18

OUT

SENSE PIN SOLDERABLE JUMPER

AVDD

PRI SEC

GND

0.1µF

R13

1kΩ

R25

1kΩ

GND

E TO A

E TO B

E TO C

E TO D

EXTERNAL VOLTAGE DIVIDER

R18

25Ω

INTERNAL 1V REFERENCE (DEFAULT)

EXTERNAL REFERENCE

R SINGLE ENDED

R3, R17, R18

ONLY ONE SHOULD BE

ON BOARD AT A TIME

INTERNAL 0.5V REFERENCE

GND

MODE PIN SOLDERABLE JUMPER

5 TO 1 TWOS COMPLEMENT/DCS OFF

5 TO 2 TWOS COMPLEMENT/DCS OFF

5 TO 3 OFFSET BINARY/DCS ON

5 TO 4 OFFSET BINARY/DCS OFF

Figure 54. LFCSP Evaluation Board Schematic, Analog Inputs and DUT

Rev. D | Page 30 of 40

Data Sheet

AD9235

74LVTH162374

U1

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

2CLK

2OE

2QB

2Q7

GND

2Q6

2Q5

CLKAT/DAC

MSB DRX

D13X

GND

HEADER 40

2DB

2D7

GND

2D6

2D5

DRY

2

4

6

1

3

5

7

9

2

1

3

GND

4

DR

GND

6

5

D12X

D11X

MSB GND

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

8

7

V

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

9

DRVDD

D10X

DRVDD

CC

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

2D4

2D3

GND

2D2

2D1

1D8

1D7

GND

1D6

1D5

2Q4

2Q3

GND

2Q2

2Q1

1Q8

1Q7

GND

1Q6

1Q5

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

D9X

GND

D8X

D7X

D6X

D5X

GND

D4X

D3X

8

7

V

DRVDD

D2X

DRVDD

CC

6

1D4

1Q4

1Q3

GND

1Q2

1Q1

1OE

5

1D3

D1X

DRY

4

GND

1D2

GND

LSB

GND

3

D0X

2

1D1

GND

1

1CLK

1

CLKLAT/DAC

IN

OUT

R38

R39

1kΩ

VAMP

GND

C44

0.1µF

C24

10µF

VAMP

POWER DOWN

USE R40 OR R41

+

C45

0.1µF

GND

VAMP

GND

R41

R40

AD8351

R41

10kΩ

R14

25Ω

10kΩ 10kΩ

U3

PWDN

RGP1

INHI

VOCM

1

2

3

4

5

10

9

VPOS

OPH1

OPLO

COMM

C28

0.1µF

C27

R16

0Ω

AMP IN

AMP

0.1µF

8

AMPINB

AMPIN

INLO

RPG2

7

R17

0Ω

C35

0.10µF

C17

R19

50Ω

R35

25Ω

6

0.1µF

R33

25Ω

GND

R34

1.2kΩ

GND GND

Figure 55. LFCSP Evaluation Board Schematic, Digital Path

Rev. D | Page 31 of 40

AD9235

Data Sheet

Figure 56. LFCSP Evaluation Board Schematic, Clock Input

Rev. D | Page 32 of 40

Data Sheet

AD9235

Figure 59. LFCSP Evaluation Board Layout, Ground Plane

Figure 57. LFCSP Evaluation Board Layout, Primary Side

Figure 58. LFCSP Evaluation Board Layout, Secondary Side

Figure 60. LFCSP Evaluation Board Layout, Power Plane

Rev. D | Page 33 of 40

AD9235

Data Sheet

Figure 61. LFCSP Evaluation Board Layout, Primary Silkscreen

Figure 62. LFCSP Evaluation Board Layout, Secondary Silkscreen

Rev. D | Page 34 of 40

Data Sheet

AD9235

Table 9. LFCSP Evaluation Board Bill of Materials (BOM)

Recommended Vendor/ Supplied

Item Qty. Omit¹Reference Designator

Device

Package Value Part Number

by ADI

1

18

C1, C5, C7, C8, C9, C11,

C12, C13, C15, C16, C31, C33,

C34, C36, C37, C41, C43, C47

Chip Capacitor

0603

0.1 µF

8

2

C6, C18, C27, C17,

C28, C35, C45, C44

2

3

8

C2, C3, C4, C10, C20,

C22, C25, C29

Tantalum Capacitor

Chip Capacitor

TAJD

0603

10 µF

C46, C24

C14, C30, C32, C38,

C39, C40, C48, C49

0.001 µF

4

5

6

3

1

9

C19, C21, C23

C26

Chip Capacitor

Header

0603

10 pF

0603

E31, E35, E43, E44,

E50, E51, E52, E53

EHOLE

Jumper Blocks

2

1

E1, E45

J1, J2

L1

7

8

2

1

SMA Connector/50 Ω

Inductor

SMA

0603

10 nH Coilcraft/

0603CS-10NXGBU

9

P2

Terminal Block

TB6

Wieland/25.602.2653.0,

z5-530-0625-0

10

11

1

5

P12

Header Dual 20-Pin RT Angle HEADER40

Digi-Key S2131-20-ND

R3, R12, R23, R28, RX

R37, R22, R42, R16, R17, R27

R4, R15

Chip Resistor

0603

0 Ω

6

1

12

13

2

Chip Resistor

0603

33 Ω

1 k Ω

14

R5, R6, R7, R8, R13, R20,

R21, R24, R25, R26,

R30, R31, R32, R36

14

15

2

1

R10, R11

R29

Chip Resistor

0603

36 Ω

50 Ω

R19

16

2

RP1, RP2

Resistor Pack

ADT1-1WT

R_742

220 Ω Digi-Key

CTS/742C163220JTR

17

18

1

T1

AWT1-1T

TSSOP-48

Mini-Circuits

U1

74LVTH162374

CMOS Register

19

20

21

22

23

24

25

26

27

28

1

U4

AD9235BCP ADC (DUT)

74VCX86M

LFCSP-32

SOIC-14

PCB

Analog Devices, Inc.

Fairchild

X

U5

PCB

AD92XXBCP/PCB

AD8351 Op Amp

MACOM Transformer

Chip Resistor

Analog Devices, Inc.

X

1

U3

MSOP-8

1

T2

ETC1-1-13 1-1 TX M/A-COM/ETC1-1-13

5

R9, R1, R2, R38, R39

R18, R14, R35

R40, R41

0603

SELECT

25 Ω

3

Chip Resistor

2

Chip Resistor

10 k Ω

1.2 k Ω

100 Ω

1

R34

Chip Resistor

1

R33

Chip Resistor

Total 82

34

¹These items are included in the PCB design but are omitted at assembly.

Rev. D | Page 35 of 40

AD9235

Data Sheet

OUTLINE DIMENSIONS

9.80

9.70

9.60

28

15

4.50

4.40

4.30

6.40 BSC

1

14

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

8°

0°

0.75

0.60

0.45

0.30

0.19

0.20

0.09

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AE

Figure 63. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

25

24

32

1

INDICATOR

0.50

BSC

3.25

3.10 SQ

2.95

EXPOSED

PAD

17

16

8

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

Figure 64. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 × 5 mm Body, Very Very Thin Quad

(CP-32-7)

Dimensions shown in millimeters

Rev. D | Page 36 of 40

Data Sheet

AD9235

ORDERING GUIDE

Model^{1, 2}

Temperature Range

–40°C to +85°C

Package Description

Package Option

AD9235BRU-20

28-Lead Thin Shrink Small Outline Package (TSSOP)

32-Lead Lead Frame Chip Scale Package (LFCSP_WQ)

RU-28

CP-32-7

AD9235BRURL7-20

AD9235BRUZ-20

AD9235BRUZRL7-20

AD9235BRU-40

AD9235BRURL7-40

AD9235BRUZ-40

AD9235BRUZRL7-40

AD9235BRU-65

AD9235BRURL7-65

AD9235BRUZ-65

AD9235BRUZRL7-65

AD9235BCPZ-20

AD9235BCPZRL7-20

AD9235BCPZ-40

AD9235BCPZRL7-40

AD9235BCPZ-65

AD9235BCPZRL7-65

¹Z = RoHS Compliant Part.

²It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of

the package is achieved with exposed paddle soldered to the customer board.

Rev. D | Page 37 of 40

AD9235

NOTES

Data Sheet

Rev. D | Page 38 of 40

Data Sheet

NOTES

AD9235

Rev. D | Page 39 of 40

AD9235

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D02461-0-10/12(D)

Rev. D | Page 40 of 40

电子百科

产品导航

产品型号AD9235BRUZ-65的概述

产品型号AD9235BRUZ-65的Datasheet PDF文件预览

AD9235BRUZ-65相关产品

AD9235BRUZ-65相关文章

IC37:专业IC行业平台