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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • 深圳市芯达科技有限公司

     该会员已使用本站9年以上
  • AD9238BSTZ-20 现货库存
  • 数量18700 
  • 厂家ADI 
  • 封装ADI一级代理商绝对进口原装假一赔十 
  • 批号2019+ 
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • AD9238BSTZ-20 现货库存
  • 数量12500 
  • 厂家AD 
  • 封装64LQFP 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • AD9238BSTZ-20 现货库存
  • 数量5000 
  • 厂家AD 
  • 封装QFP 
  • 批号24+ 
  • 原装假一赔百,深圳现货,北美、新加坡可发货
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  • 755-83950019 QQ:800888908
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • AD9238BSTZ-20 现货库存
  • 数量26980 
  • 厂家ADI 
  • 封装QFP# 
  • 批号21+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
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  • 北京奕芯科技有限公司

     该会员已使用本站12年以上
  • AD9238BSTZ-20 现货库存
  • 数量
  • 厂家ADI 
  • 封装QFP 
  • 批号23+ 
  • 当天发货原装正品
  • QQ:335885516QQ:335885516 复制
  • 010-81030386 QQ:335885516
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  • 深圳市广百利电子有限公司

     该会员已使用本站6年以上
  • AD9238BSTZ-20 现货库存
  • 数量18500 
  • 厂家ADI(亚德诺) 
  • 封装LQFP-64 
  • 批号23+ 
  • ★★全网低价,原装原包★★
  • QQ:1483430049QQ:1483430049 复制
  • 0755-83235525 QQ:1483430049
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • AD9238BSTZ-20 现货库存
  • 数量98500 
  • 厂家ADI/亚德诺 
  • 封装QFP 
  • 批号23+ 
  • 真实库存全新原装正品!专业配单
  • QQ:308365177QQ:308365177 复制
  • 0755-13418564337 QQ:308365177
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • AD9238BSTZ-20 热卖库存
  • 数量3000 
  • 厂家ADI 
  • 封装LQFP64 
  • 批号23+ 
  • 全新原装正品现货
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82723761 QQ:867789136QQ:1245773710
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  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • AD9238BSTZ-20
  • 数量98622 
  • 厂家ADI/亚德诺 
  • 封装LQFP-64 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
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  • 0755-23611557【陈妙华 QQ:GTY82dX7
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  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • AD9238BSTZ-20
  • 数量5600 
  • 厂家ADI/亚德诺 
  • 封装QFP 
  • 批号23+ 
  • 100%深圳原装现货库存
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • AD9238BSTZ-20
  • 数量108 
  • 厂家ADI/亚德诺 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
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  • 0755-82546830 QQ:3007977934QQ:3007947087
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • AD9238BSTZ-20
  • 数量7800 
  • 厂家 
  • 封装QFP 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应
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  • 0755-82865294 QQ:198857245
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  • 集好芯城

     该会员已使用本站13年以上
  • AD9238BSTZ-20
  • 数量13293 
  • 厂家ADI/亚德诺 
  • 封装QFP 
  • 批号最新批次 
  • 原装原厂 现货现卖
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    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • AD9238BSTZ-20
  • 数量7586 
  • 厂家ADI(亚德诺) 
  • 封装64LQFP 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
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    QQ:3007947087QQ:3007947087 复制
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • AD9238BSTZ-20
  • 数量30000 
  • 厂家ADI/亚德诺 
  • 封装QFP 
  • 批号23+ 
  • 只做原装现货假一罚十
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    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • AD9238BSTZ-20
  • 数量6500 
  • 厂家ADI 
  • 封装64LQFP 
  • 批号23+ 
  • 只做原装正品 现货销售
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82723761 QQ:867789136QQ:1245773710
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • AD9238BSTZ-20
  • 数量3000 
  • 厂家ADI 
  • 封装LQFP64 
  • 批号23+ 
  • 全新原装公司现货销售!
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82772189 QQ:867789136QQ:1245773710
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  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • AD9238BSTZ-20
  • 数量6500 
  • 厂家ADI/亚德诺 
  • 封装LQFP-64 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
  • QQ:2885393494QQ:2885393494 复制
    QQ:2885393495QQ:2885393495 复制
  • 0755-83244680 QQ:2885393494QQ:2885393495
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  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • AD9238BSTZ-20EB
  • 数量500 
  • 厂家AD 
  • 封装 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 010-62565447 QQ:528164397QQ:1318502189
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  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • AD9238BSTZ-20
  • 数量3000 
  • 厂家ADI 
  • 封装LQFP64 
  • 批号23+ 
  • 全新原装正品现货
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • AD9238BSTz-20
  • 数量12300 
  • 厂家ADI/亚德诺 
  • 封装TQFP64 
  • 批号24+ 
  • ★原装真实库存★13点税!
  • QQ:2353549508QQ:2353549508 复制
    QQ:2885134615QQ:2885134615 复制
  • 0755-83201583 QQ:2353549508QQ:2885134615
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  • 深圳市芯达科技有限公司

     该会员已使用本站9年以上
  • AD9238BSTZ-20
  • 数量18700 
  • 厂家ADI 
  • 封装QFP 
  • 批号2017+ 
  • ADI一级代理商全新原装进口现货
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
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  • 深圳市正信鑫科技有限公司

     该会员已使用本站12年以上
  • AD9238BSTZ-20
  • 数量5062 
  • 厂家AD 
  • 封装原厂封装 
  • 批号22+ 
  • 原装正品★真实库存★价格优势★欢迎来电洽谈
  • QQ:1686616797QQ:1686616797 复制
    QQ:2440138151QQ:2440138151 复制
  • 0755-22655674 QQ:1686616797QQ:2440138151
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  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • AD9238BSTZ-20
  • 数量865000 
  • 厂家ADI/亚德诺 
  • 封装QFP 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • AD9238BSTZ-20
  • 数量75000 
  • 厂家AD 
  • 封装QFP 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • AD9238BSTZ-20
  • 数量5000 
  • 厂家AD 
  • 封装QFP 
  • 批号2021+ 
  • 原装假一赔十!可提供正规渠道证明!
  • QQ:3003818780QQ:3003818780 复制
    QQ:3003819484QQ:3003819484 复制
  • 755-83950019 QQ:3003818780QQ:3003819484
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  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • AD9238BSTZ-20
  • 数量2368 
  • 厂家ADI-亚德诺 
  • 封装QFP-64 
  • 批号▉▉:2年内 
  • ▉▉¥172元一有问必回一有长期订货一备货HK仓库
  • QQ:43871025QQ:43871025 复制
  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • AD9238BSTZ-20
  • 数量12500 
  • 厂家AD 
  • 封装64LQFP 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • AD9238BSTZ-20
  • 数量15300 
  • 厂家Analog Devices Inc. 
  • 封装64-LQFP(7x7) 
  • 批号24+ 
  • 只做原装★真实库存★含13点增值税票!
  • QQ:2885134615QQ:2885134615 复制
    QQ:2353549508QQ:2353549508 复制
  • 0755-83201583 QQ:2885134615QQ:2353549508
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  • 深圳市一呈科技有限公司

     该会员已使用本站9年以上
  • AD9238BSTZ-20
  • 数量3210 
  • 厂家ADI(亚德诺) 
  • 封装LQFP-64 
  • 批号23+ 
  • ▉原厂渠道▉支持实单
  • QQ:3003797048QQ:3003797048 复制
    QQ:3003797050QQ:3003797050 复制
  • 0755-82779553 QQ:3003797048QQ:3003797050
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  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • AD9238BSTZ-20
  • 数量54731 
  • 厂家AD 
  • 封装QFP 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
  • QQ:1091796029QQ:1091796029 复制
    QQ:916896414QQ:916896414 复制
  • 0755-82772151 QQ:1091796029QQ:916896414
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  • 深圳市誉兴微科技有限公司

     该会员已使用本站4年以上
  • AD9238BSTZ-20
  • 数量12600 
  • 厂家ADI/亚德诺 
  • 封装QFP 
  • 批号22+ 
  • 深圳原装现货,支持实单
  • QQ:2252757071QQ:2252757071 复制
  • 0755-82579431 QQ:2252757071
  • AD9238BSTZ-20图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • AD9238BSTZ-20
  • 数量1500 
  • 厂家ADI 
  • 封装QFP 
  • 批号24+ 
  • 原装假一赔十!可提供正规渠道证明!
  • QQ:3007947169QQ:3007947169 复制
    QQ:3007947210QQ:3007947210 复制
  • 755-83950895 QQ:3007947169QQ:3007947210
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • AD9238BSTZ-20
  • 数量15862 
  • 厂家AD 
  • 封装QFP 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • AD9238BSTZ-20
  • 数量1500 
  • 厂家ADI 
  • 封装QFP 
  • 批号24+ 
  • 原装假一赔十!可提供正规渠道证明!
  • QQ:3003818780QQ:3003818780 复制
    QQ:3003819484QQ:3003819484 复制
  • 0755-83950895 QQ:3003818780QQ:3003819484
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  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • AD9238BSTZ-20
  • 数量55000 
  • 厂家ADI(亚德诺) 
  • 封装LQFP-64 
  • 批号2年内 
  • 原厂渠道 正品保障 长期供应
  • QQ:2355734291QQ:2355734291 复制
  • -0755-88604592 QQ:2355734291
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  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • AD9238BSTZ-20
  • 数量8800 
  • 厂家ADI/亚德诺 
  • 封装QFP 
  • 批号新年份 
  • 羿芯诚只做原装,原厂渠道,价格优势可谈!
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  • 0755-82570683 QQ:2853992132
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • AD9238BSTZ-20
  • 数量500 
  • 厂家AD 
  • 封装QFP 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507168QQ:2355507168 复制
    QQ:2355507169QQ:2355507169 复制
  • 86-755-83219286 QQ:2355507168QQ:2355507169
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • AD9238BSTZ-20
  • 数量15862 
  • 厂家AD 
  • 封装QFP 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
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  • 深圳市迈锐达科技有限公司

     该会员已使用本站14年以上
  • AD9238BSTZ-20
  • 数量600 
  • 厂家ANA 
  • 封装 
  • 批号08+ 
  • 原装现货!冷门优势库存
  • QQ:603546486QQ:603546486 复制
    QQ:1181043992QQ:1181043992 复制
  • 86-0755 QQ:603546486QQ:1181043992
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  • 深圳市创芯联科技有限公司

     该会员已使用本站9年以上
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产品型号AD9238BSTZ-20的概述

AD9238BSTZ-20芯片概述及详细参数分析 概述 AD9238BSTZ-20是一款高性能的模数转换器(ADC),主要用于要求高精度和高速转换的应用场景,如医疗成像、通信和数字信号处理等。这款芯片由Analog Devices公司生产,凭借其出色的性能和灵活性,广泛应用于各种电子设备。 AD9238BSTZ-20是一个单通道、12位分辨率的ADC,具有20MHz的采样率,能够实现高达70dB的信噪比(SNR)。该芯片的架构采用了先进的插值和过采样技术,使得其在动态范围、线性度和响应速度上具备良好表现,适合应用于高速数据信号采集和处理。 详细参数 AD9238BSTZ-20的主要技术参数如下: 1. 分辨率: 12位 2. 采样率: 最高可达20 MSPS(百万次采样每秒) 3. 信噪比: 70dB 4. 失真: -78dBc(总谐波失真) 5. 输入范围: 适配不同电压范围的单端...

产品型号AD9238BSTZ-20的Datasheet PDF文件预览

12-Bit, 20 MSPS/40 MSPS/65 MSPS  
Dual A/D Converter  
AD9238  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Integrated dual 12-bit ADC  
AVDD AGND  
Single 3 V supply operation (2.7 V to 3.6 V)  
SNR = 70 dB (to Nyquist, AD9238-65)  
SFDR = 80.5 dBc (to Nyquist, AD9238-65)  
Low power: 300 mW/channel at 65 MSPS  
Differential input with 500 MHz, 3 dB bandwidth  
Exceptional crosstalk immunity > 85 dB  
Flexible analog input: 1 V p-p to 2 V p-p range  
Offset binary or twos complement data format  
Clock duty cycle stabilizer  
OTR_A  
VIN+_A  
VIN–_A  
12  
12  
D11_A TO D0_A  
OEB_A  
SHA  
ADC  
OUTPUT  
MUX/  
BUFFERS  
REFT_A  
REFB_A  
VREF  
MUX_SELECT  
CLK_A  
CLOCK  
DUTY CYCLE  
STABILIZER  
CLK_B  
DCS  
SENSE  
AGND  
SHARED_REF  
PWDN_A  
PWDN_B  
DFS  
0.5V  
Output datamux option  
MODE  
CONTROL  
REFT_B  
REFB_B  
VIN+_B  
VIN–_B  
APPLICATIONS  
Ultrasound equipment  
Direct conversion or IF sampling receivers  
WB-CDMA, CDMA2000, WiMAX  
Battery-powered instruments  
Hand-held scopemeters  
OTR_B  
12  
12  
OUTPUT  
MUX/  
BUFFERS  
SHA  
ADC  
D11_B TO D0_B  
OEB_B  
AD9238  
DRVDD  
DRGND  
Low cost, digital oscilloscopes  
Figure 1.  
GENERAL DESCRIPTION  
Fabricated on an advanced CMOS process, the AD9238 is  
available in a Pb-free, space saving, 64-lead LQFP or LFCSP and  
is specified over the industrial temperature range (−40°C to  
+85°C).  
The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS  
analog-to-digital converter (ADC). It features dual high  
performance sample-and-hold amplifiers (SHAs) and an  
integrated voltage reference. The AD9238 uses a multistage  
differential pipelined architecture with output error correction  
logic to provide 12-bit accuracy and to guarantee no missing  
codes over the full operating temperature range at up to  
65 MSPS data rates. The wide bandwidth, differential SHA  
allows for a variety of user-selectable input ranges and offsets,  
including single-ended applications. It is suitable for various  
applications, including multiplexed systems that switch full-  
scale voltage levels in successive channels and for sampling  
inputs at frequencies well beyond the Nyquist rate.  
PRODUCT HIGHLIGHTS  
1. Pin-compatible with the AD9248, 14-bit 20MSPS/  
40 MSPS/65 MSPS ADC.  
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS  
allow flexibility between power, cost, and performance to suit  
an application.  
3. Low power consumption:  
AD9238-65: 65 MSPS = 600 mW  
AD9238-40: 40 MSPS = 330 mW  
AD9238-20: 20 MSPS = 180 mW  
Dual single-ended clock inputs are used to control all internal  
conversion cycles. A duty cycle stabilizer is available and can  
compensate for wide variations in the clock duty cycle, allowing  
the converter to maintain excellent performance. The digital  
output data is presented in either straight binary or twos  
complement format. Out-of-range signals indicate an overflow  
condition, which can be used with the most significant bit to  
determine low or high overflow.  
4. Typical channel isolation of 85 dB @ fIN = 10 MHz.  
5. The clock duty cycle stabilizer (AD9238-20/AD9238-40/  
AD9238-65) maintains performance over a wide range of  
clock duty cycles.  
6. Multiplexed data output option enables single-port operation  
from either Data Port A or Data Port B.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
©2005 Analog Devices, Inc. All rights reserved.  
AD9238  
TABLE OF CONTENTS  
Specifications..................................................................................... 4  
Clock Circuitry........................................................................... 21  
Analog Inputs ............................................................................. 21  
Reference Circuitry.................................................................... 21  
Digital Control logic .................................................................. 21  
Outputs ........................................................................................ 21  
LQFP Evaluation Board Bill of Materials (BOM).................. 23  
LQFP Evaluation Board Schematics........................................ 24  
LQFP PCB Layers....................................................................... 28  
Dual ADC LFCSP PCB.................................................................. 34  
Power Connector........................................................................ 34  
Analog Inputs ............................................................................. 34  
Optional Operational Amplifier .............................................. 34  
Clock ............................................................................................ 34  
Voltage Reference ....................................................................... 34  
Data Outputs............................................................................... 34  
LFCSP Evaluation Board Bill of Materials (BOM) ................ 35  
LFCSP PCB Schematics............................................................. 36  
LFCSP PCB Layers..................................................................... 39  
Thermal Considerations............................................................ 44  
Outline Dimensions....................................................................... 45  
Ordering Guide .......................................................................... 46  
DC Specifications ......................................................................... 4  
AC Specifications.......................................................................... 5  
Digital Specifications ................................................................... 6  
Switching Specifications .............................................................. 6  
Absolute Maximum Ratings............................................................ 7  
Explanation of Test Levels........................................................... 7  
ESD Caution.................................................................................. 7  
Pin Configuration and Function Descriptions............................. 8  
Terminology .................................................................................... 10  
Typical Performance Characteristics ........................................... 11  
Equivalent Circuits......................................................................... 15  
Theory of Operation ...................................................................... 16  
Analog Input ............................................................................... 16  
Clock Input and Considerations .............................................. 17  
Power Dissipation and Standby Mode..................................... 18  
Digital Outputs ........................................................................... 18  
Timing.......................................................................................... 18  
Data Format ................................................................................ 19  
Voltage Reference....................................................................... 19  
AD9238 LQFP Evaluation Board ................................................. 21  
REVISION HISTORY  
4/05—Rev. A to Rev. B  
Changes to Pin Function Descriptions..........................................8  
Changes to Terminology Section .................................................10  
Changes to Figure 29......................................................................15  
Changes to Clock Input and Considerations Section................17  
Changes to Figure 33......................................................................18  
Changes to Data Format Section..................................................19  
Added AD9238 LQFP Evaluation Board Section ......................21  
Added Dual ADC LFCSP PCB Section.......................................34  
Added Thermal Considerations Section.....................................44  
Updated Outline Dimensions.......................................................45  
Changes to Ordering Guide..........................................................46  
Changes to Format and Layout........................................ Universal  
Added LFCSP..................................................................... Universal  
Changes to Features and Applications...........................................1  
Changes to General Description and Product Highlights ..........1  
Changes to Figure 1..........................................................................1  
Changes to Table 1............................................................................3  
Changes to Table 2............................................................................5  
Added Digital Specifications...........................................................6  
Moved Switching Specifications to.................................................6  
Rev. B | Page 2 of 48  
AD9238  
9/03—Rev. 0 to Rev. A  
2/03—Revision 0: Initial Version  
Changes to DC Specifications ........................................................ 2  
Changes to Switching Specifications ............................................. 3  
Changes to AC Specifications......................................................... 4  
Changes to Figure 1.......................................................................... 4  
Changes to Ordering Guide............................................................ 5  
Changes to TPCs 2, 3, and 6 ........................................................... 8  
Changes to Clock Input and Considerations Section................13  
Added Text to Data Format Section ............................................15  
Changes to Figure 9........................................................................16  
Added Evaluation Board Diagrams Section...............................17  
Update Outline Dimensions.........................................................24  
Rev. B | Page 3 of 48  
AD9238  
SPECIFICATIONS  
DC SPECIFICATIONS  
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,  
TMIN to TMAX, DCS enabled, unless otherwise noted.  
Table 1.  
Test  
AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65  
Parameter  
Temp Level Min Typ  
Max Min Typ  
Max Min Typ  
Max  
Unit  
RESOLUTION  
Full  
VI  
12  
12  
12  
12  
Bits  
ACCURACY  
No Missing Codes Guaranteed  
Offset Error  
Gain Error1  
Differential Nonlinearity (DNL)2  
Full  
Full  
Full  
Full  
2ꢀ°C  
Full  
2ꢀ°C  
VI  
VI  
IV  
V
I
12  
12  
Bits  
±±.3± ±1.2  
±±.3± ±2.2  
±±.3ꢀ  
±±.3ꢀ ±±.ꢁ  
±±.4ꢀ  
±±.4± ±1.4  
±±.ꢀ± ±1.1  
±±.ꢀ± ±2.4  
±±.3ꢀ  
±±.3ꢀ ±±.8  
±±.ꢂ±  
±±.ꢀ± ±1.1  
±±.ꢀ± ±2.ꢀ  
±±.3ꢀ  
±±.3ꢀ ±1.±  
±±.ꢃ±  
% FSR  
% FSR  
LSB  
LSB  
LSB  
Integral Nonlinearity (INL)2  
V
I
±±.ꢀ± ±1.4  
±±.ꢀꢀ ±1.ꢃꢀ LSB  
TEMPERATURE DRIFT  
Offset Error  
Gain Error  
Full  
Full  
V
V
±4  
±12  
±4  
±12  
±ꢂ  
±12  
µV/°C  
ppm/°C  
INTERNAL VOLTAGE REFERENCE  
Output Voltage Error (1 V Mode)  
Load Regulation @ 1.± mA  
Output Voltage Error (±.ꢀ V Mode)  
Load Regulation @ ±.ꢀ mA  
INPUT REFERRED NOISE  
Input Span = 1 V  
Input Span = 2.± V  
ANALOG INPUT  
Full  
Full  
Full  
Full  
VI  
V
V
±ꢀ  
±3ꢀ  
±ꢀ  
±3ꢀ  
±ꢀ  
±3ꢀ  
mV  
mV  
mV  
mV  
±.8  
±2.ꢀ  
±.1  
±.8  
±2.ꢀ  
±.1  
±.8  
±2.ꢀ  
±.1  
V
2ꢀ°C  
2ꢀ°C  
V
V
±.ꢀ4  
±.2ꢃ  
±.ꢀ4  
±.2ꢃ  
±.ꢀ4  
±.2ꢃ  
LSBrms  
LSBrms  
Input Span = 1.± V  
Input Span = 2.± V  
Input Capacitance3  
REFERENCE INPUT RESISTANCE  
POWER SUPPLIES  
Supply Voltages  
Full  
Full  
Full  
Full  
IV  
IV  
V
1
2
1
2
1
2
V p-p  
V p-p  
pF  
V
kΩ  
AVDD  
DRVDD  
Full  
Full  
IV  
IV  
2.ꢃ  
2.2ꢀ 3.±  
3.±  
3.ꢂ  
3.ꢂ  
2.ꢃ  
2.2ꢀ 3.±  
3.±  
3.ꢂ  
3.ꢂ  
2.ꢃ  
2.2ꢀ 3.±  
3.±  
3.ꢂ  
3.ꢂ  
V
V
Supply Current  
IAVDD2  
Full  
Full  
Full  
V
V
V
ꢂ±  
4
±±.±1  
11±  
1±  
±±.±1  
2±±  
14  
±±.±1  
mA  
mA  
% FSR  
IDRVDD2  
PSRR  
POWER CONSUMPTION  
DC Input4  
Sine Wave Input2  
Standby Powerꢀ  
Full  
Full  
Full  
V
VI  
V
18±  
1ꢁ±  
2.±  
33±  
3ꢂ±  
2.±  
ꢂ±±  
ꢂ4±  
2.±  
mW  
mW  
mW  
212  
3ꢁꢃ  
ꢂꢁ8  
MATCHING CHARACTERISTICS  
Offset Error  
Gain Error  
2ꢀ°C  
2ꢀ°C  
V
V
±±.1  
±±.±ꢀ  
±±.1  
±±.±ꢀ  
±±.1  
±±.±ꢀ  
% FSR  
% FSR  
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.± V external reference).  
2 Measured at maximum clock rate with a low frequency sine wave input and approximately ꢀ pF loading on each output bit.  
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 28 for the equivalent analog input structure.  
4 Measured with dc input at maximum clock rate.  
Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).  
Rev. B | Page 4 of 48  
 
 
 
 
 
 
AD9238  
AC SPECIFICATIONS  
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,  
TMIN to TMAX, DCS enabled, unless otherwise noted.  
Table 2.  
Test  
AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65  
Parameter  
Temp Level Min Typ  
Max Min Typ  
Max Min Typ  
Max Unit  
SIGNAL-TO-NOISE RATIO (SNR)  
fINPUT = 2.4 MHz  
fINPUT = ꢁ.ꢃ MHz  
2ꢀ°C  
Full  
2ꢀ°C  
Full  
2ꢀ°C  
Full  
2ꢀ°C  
2ꢀ°C  
V
V
IV  
V
IV  
V
ꢃ±.4  
ꢃ±.2  
ꢂꢁ.ꢃ ꢃ±.4  
ꢃ±.4  
ꢃ±.3  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
fINPUT = 1ꢁ.ꢂ MHz  
fINPUT = 32.ꢀ MHz  
fINPUT = 1±± MHz  
ꢃ±.1  
ꢂꢁ.ꢃ ꢃ±.3  
ꢂꢁ.3  
ꢂ8.ꢃ ꢃ±.±  
ꢂꢃ.ꢂ  
IV  
V
ꢂ8.ꢃ  
ꢂ8.3  
ꢃ±.2  
SIGNAL-TO-NOISE AND DISTORTION  
RATIO (SINAD)  
fINPUT = 2.4 MHz  
fINPUT = ꢁ.ꢃ MHz  
2ꢀ°C  
Full  
2ꢀ°C  
Full  
2ꢀ°C  
Full  
2ꢀ°C  
2ꢀ°C  
V
V
IV  
V
IV  
V
ꢃ±.2  
ꢃ±.1  
ꢂꢁ.3 ꢃ±.2  
ꢃ±.1  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
fINPUT = 1ꢁ.ꢂ MHz  
fINPUT = 32.ꢀ MHz  
ꢂꢁ.ꢁ  
ꢂꢁ.4 ꢃ±.1  
ꢂ8.ꢁ  
ꢂ8.1 ꢂꢁ.1  
ꢂꢂ.ꢂ  
IV  
V
fINPUT = 1±± MHz  
ꢂꢃ.ꢁ  
ꢂꢃ.ꢁ  
11.ꢀ  
EFFECTIVE NUMBER OF BITS (ENOB)  
fINPUT = 2.4 MHz  
fINPUT = ꢁ.ꢃ MHz  
2ꢀ°C  
Full  
2ꢀ°C  
Full  
2ꢀ°C  
Full  
2ꢀ°C  
2ꢀ°C  
V
V
IV  
V
IV  
V
11.ꢀ  
11.4  
11.3 11.ꢀ  
11.4  
Bits  
Bits  
Bits  
Bits  
Bits  
Bits  
Bits  
Bits  
fINPUT = 1ꢁ.ꢂ MHz  
fINPUT = 32.ꢀ MHz  
11.4  
11.3 11.4  
11.2  
11.1 11.3  
1±.ꢁ  
IV  
V
fINPUT = 1±± MHz  
11.1  
11.1  
WORST HARMONIC (SECOND or THIRD)  
fINPUT = ꢁ.ꢃ MHz  
fINPUT = 1ꢁ.ꢂ MHz  
Full  
Full  
Full  
V
V
V
−84.±  
dBc  
dBc  
dBc  
−8ꢀ.±  
fINPUT = 3ꢀ MHz  
−8±.±  
SPURIOUS-FREE DYNAMIC RANGE (SFDR)  
fINPUT = 2.4 MHz  
fINPUT = ꢁ.ꢃ MHz  
2ꢀ°C  
Full  
2ꢀ°C  
Full  
2ꢀ°C  
Full  
2ꢀ°C  
2ꢀ°C  
Full  
V
V
I
V
I
V
I
V
V
8ꢂ.±  
84.±  
ꢃꢂ.1 8ꢂ.±  
8ꢂ.±  
8ꢂ.±  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dB  
fINPUT = 1ꢁ.ꢂ MHz  
fINPUT = 32.ꢀ MHz  
8ꢀ.±  
ꢃꢂ.ꢃ 8ꢂ.±  
8±.±  
ꢃ2.ꢀ 8±.ꢀ  
ꢃꢀ.±  
fINPUT = 1±± MHz  
CROSSTALK  
−8ꢀ.±  
−8ꢀ.±  
−8ꢀ.±  
Rev. B | Page ꢀ of 48  
 
AD9238  
DIGITAL SPECIFICATIONS  
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,  
TMIN to TMAX, DCS enabled, unless otherwise noted.  
Table 3.  
Test  
AD9238BST/BCP-20  
AD9238BST/BCP-40  
AD9238BST/BCP-65  
Parameter  
Temp Level Min  
Typ Max Min  
Typ Max Min  
Typ Max Unit  
LOGIC INPUTS  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
Low Level Input Current  
Input Capacitance  
Full  
Full  
Full  
Full  
Full  
IV  
IV  
IV  
IV  
IV  
2.±  
2.±  
2.±  
V
V
µA  
µA  
pF  
±.8  
+1±  
+1±  
±.8  
+1±  
+1±  
±.8  
+1±  
+1±  
−1±  
−1±  
−1±  
−1±  
−1±  
−1±  
2
2
2
LOGIC OUTPUTS1  
High Level Output Voltage  
Full  
Full  
IV  
IV  
DRVDD −  
±.±ꢀ  
DRVDD −  
±.±ꢀ  
DRVDD −  
±.±ꢀ  
V
V
Low Level Output Voltage  
±.±ꢀ  
±.±ꢀ  
±.±ꢀ  
1 Output voltage levels measured with capacitive load only on each output.  
SWITCHING SPECIFICATIONS  
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,  
TMIN to TMAX, DCS enabled, unless otherwise noted.  
Table 4.  
Test  
AD9238BST/BCP-20  
AD9238BST/BCP-40  
AD9238BST/BCP-65  
Parameter  
Temp Level Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
SWITCHING PERFORMANCE  
Maximum Conversion Rate  
Minimum Conversion Rate  
CLK Period  
CLK Pulse-Width High1  
CLK Pulse-Width Low1  
DATA OUTPUT PARAMETER  
Output Delay2 (tPD)  
Pipeline Delay (Latency)  
Aperture Delay (tA)  
Aperture Uncertainty (tJ)  
Wake-Up Time3  
Full  
Full  
Full  
Full  
Full  
VI  
V
V
V
V
2±  
4±  
ꢂꢀ  
MSPS  
MSPS  
ns  
ns  
ns  
1
1
1
ꢀ±.±  
1ꢀ.±  
1ꢀ.±  
2ꢀ.±  
8.8  
8.8  
1ꢀ.4  
ꢂ.2  
ꢂ.2  
Full  
Full  
Full  
Full  
Full  
Full  
VI  
V
V
V
V
V
2
3.ꢀ  
1.±  
±.ꢀ  
2.ꢀ  
2
2
3.ꢀ  
1.±  
±.ꢀ  
2.ꢀ  
2
2
3.ꢀ  
1.±  
±.ꢀ  
2.ꢀ  
2
ns  
Cycles  
ns  
pS rms  
ms  
OUT-OF-RANGE RECOVERY TIME  
Cycles  
1 The ADꢁ238-ꢂꢀ model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 23).  
2 Output delay is measured from clock ꢀ±% transition to data ꢀ±% transition, with a ꢀ pF load on each output.  
3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with ±.1 µF and 1± µF capacitors on REFT and REFB.  
N+1  
N
N+8  
N+2  
N–1  
N+3  
ANALOG  
INPUT  
N+7  
N+4  
N+6  
N+5  
CLOCK  
DATA  
OUT  
N–9  
N–8  
N–7  
N–6  
N–5  
N–4  
N–3  
N–2  
N–1  
N
tPD = MIN 2.0ns,  
MAX 6.0ns  
Figure 2. Timing Diagram  
Rev. B | Page ꢂ of 48  
 
 
 
 
 
 
AD9238  
ABSOLUTE MAXIMUM RATINGS1  
Table 5.  
Parameter  
Rating  
Min  
Pin Name  
With Respect To  
Max  
Unit  
ELECTRICAL  
AVDD  
DRVDD  
AGND  
AVDD  
AGND  
DRGND  
DRGND  
DRVDD  
DRGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
−±.3  
−±.3  
−±.3  
−3.ꢁ  
−±.3  
−±.3  
−±.3  
−±.3  
−±.3  
−±.3  
−±.3  
+3.ꢁ  
+3.ꢁ  
+±.3  
+3.ꢁ  
DRVDD + ±.3  
AVDD + ±.3  
AVDD + ±.3  
AVDD + ±.3  
AVDD + ±.3  
AVDD + ±.3  
AVDD + ±.3  
V
V
V
V
V
V
V
V
V
V
V
Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF  
OEB, DFS  
VINA, VINB  
VREF  
SENSE  
REFB, REFT  
PDWN  
ENVIRONMENTAL2  
Operating Temperature  
Junction Temperature  
Lead Temperature (1± sec)  
Storage Temperature  
−4ꢀ  
+8ꢀ  
1ꢀ±  
3±±  
°C  
°C  
°C  
°C  
−ꢂꢀ  
+1ꢀ±  
1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is  
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.  
2 Typical thermal impedances: ꢂ4-lead LQFP, θJA = ꢀ4°C/W; ꢂ4-lead LFCSP, θJA = 2ꢂ.4°C/W with heat slug soldered to ground plane. These measurements were taken on a  
4-layer board in still air, in accordance with EIA/JESDꢀ1-ꢃ.  
EXPLANATION OF TEST LEVELS  
I
1±±% production tested.  
II  
1±±% production tested at 2ꢀ°C and sample tested at specified temperatures.  
III Sample tested only.  
IV Parameter is guaranteed by design and characterization testing.  
V
Parameter is a typical value only.  
VI 1±±% production tested at 2ꢀ°C; guaranteed by design and characterization testing for industrial temperature range; 1±±% production  
tested at temperature extremes for military devices.  
ESD CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate  
on the human body and test equipment and can discharge without detection. Although this product features  
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy  
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance  
degradation or loss of functionality.  
Rev. B | Page ꢃ of 48  
 
 
AD9238  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
48  
47  
46  
45  
44  
AGND  
D4_A  
PIN 1  
IDENTIFIER  
2
3
VIN+_A  
VIN–_A  
AGND  
D3_A  
D2_A  
4
D1_A  
5
AVDD  
D0_A (LSB)  
6
REFT_A  
REFB_A  
VREF  
43 DNC  
7
42  
DNC  
AD9238  
64-LEAD LQFP  
TOP VIEW  
8
41  
DRVDD  
40 DRGND  
9
SENSE  
REFB_B  
REFT_B  
AVDD  
10  
11  
12  
13  
14  
15  
16  
(Not to Scale)  
39  
38  
37  
36  
35  
34  
33  
OTR_B  
D11_B (MSB)  
D10_B  
AGND  
D9_B  
VIN–_B  
D8_B  
D7_B  
D6_B  
VIN+_B  
AGND  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
DNC = DO NOT CONNECT  
Figure 3. 64-Lead LQFP and LFCSP Pin Configuration  
Rev. B | Page 8 of 48  
 
AD9238  
Table 6. Pin Function Descriptions (64-Lead LQFP and 64-Lead LFCSP)  
Pin No.  
Mnemonic  
Description  
1, 4, 13, 1ꢂ  
AGND  
Analog Ground.  
2
3
VIN+_A  
VIN–_A  
AVDD  
Analog Input Pin (+) for Channel A.  
Analog Input Pin (−) for Channel A.  
Analog Power Supply.  
ꢀ, 12, 1ꢃ, ꢂ4  
8
REFT_A  
REFB_A  
VREF  
Differential Reference (+) for Channel A.  
Differential Reference (−) for Channel A.  
Voltage Reference Input/Output.  
SENSE  
REFB_B  
REFT_B  
VIN−_B  
VIN+_B  
CLK_B  
DCS  
Reference Mode Selection.  
1±  
11  
14  
1ꢀ  
18  
1ꢁ  
2±  
21  
Differential Reference (−) for Channel B.  
Differential Reference (+) for Channel B.  
Analog Input Pin (−) for Channel B.  
Analog Input Pin (+) for Channel B.  
Clock Input Pin for Channel B.  
Enable Duty Cycle Stabilizer (DCS) Mode (Tie High to Enable).  
Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement).  
Power-Down Function Selection for Channel B:  
Logic ± enables Channel B.  
DFS  
PDWN_B  
Logic 1 powers down Channel B. (Outputs static, not High-Z.)  
Output Enable Bit for Channel B:  
22  
OEB_B  
Logic ± enables Data Bus B.  
Logic 1 sets outputs to High-Z.  
23, 24, 42, 43 DNC  
Do Not Connect Pins. Should be left floating.  
2ꢀ to 2ꢃ,  
3± to 38  
D±_B (LSB) to Channel B Data Output Bits.  
D11_B (MSB)  
28, 4±, ꢀ3  
2ꢁ, 41, ꢀ2  
DRGND  
DRVDD  
Digital Output Ground.  
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum ±.1 µF capacitor.  
Recommended decoupling is ±.1 µF capacitor in parallel with 1± µF.  
3ꢁ  
OTR_B  
Out-of-Range Indicator for Channel B.  
44 to ꢀ1,  
ꢀ4 to ꢀꢃ  
D±_A (LSB) to Channel A Data Output Bits.  
D11_A (MSB)  
ꢀ8  
ꢀꢁ  
OTR_A  
OEB_A  
Out-of-Range Indicator for Channel A.  
Output Enable Bit for Channel A:  
Logic ± enables Data Bus A.  
Logic 1 sets outputs to High-Z.  
ꢂ±  
ꢂ1  
PDWN_A  
Power-Down Function Selection for Channel A:  
Logic ± enables Channel A.  
Logic 1 powers down Channel A. (Outputs static, not High-Z.)  
Data Multiplexed Mode.  
MUX_SELECT  
(See Data Format section for how to enable; high setting disables output data multiplexed mode).  
Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode).  
Clock Input Pin for Channel A.  
ꢂ2  
ꢂ3  
SHARED_REF  
CLK_A  
Rev. B | Page ꢁ of 48  
AD9238  
TERMINOLOGY  
frequency, including harmonics but excluding dc. The value for  
SINAD is expressed in dB.  
Aperture Delay  
SHA performance measured from the rising edge of the clock  
input to when the input signal is held for conversion.  
Effective Number of Bits (ENOB)  
Using the following formula  
Aperture Jitter  
The variation in aperture delay for successive samples, which is  
manifested as noise on the input to the ADC.  
ENOB = (SINAD − 1.76)/6.02  
ENOB for a device for sine wave inputs at a given input  
frequency can be calculated directly from its measured SINAD.  
Integral Nonlinearity (INL)  
Deviation of each individual code from a line drawn from  
negative full scale through positive full scale. The point used as  
negative full scale occurs ½ LSB before the first code transition.  
Positive full scale is defined as a level 1½ LSB beyond the last  
code transition. The deviation is measured from the middle of  
each particular code to the true straight line.  
Signal-to-Noise Ratio (SNR)  
The ratio of the rms value of the measured input signal to the  
rms sum of all other spectral components below the Nyquist  
frequency, excluding the first six harmonics and dc. The value  
for SNR is expressed in dB.  
Differential Nonlinearity (DNL, No Missing Codes)  
An ideal ADC exhibits code transitions that are exactly 1 LSB  
apart. DNL is the deviation from this ideal value. Guaranteed  
no missing codes to 12-bit resolution indicates that all 4,096  
codes must be present over all operating ranges.  
Spurious-Free Dynamic Range (SFDR)  
The difference in dB between the rms amplitude of the input  
signal and the peak spurious signal, which may or may not be a  
harmonic.  
Nyquist Sampling  
Offset Error  
When the frequency components of the analog input are below  
the Nyquist frequency (fCLOCK/2), this is often referred to as  
Nyquist sampling.  
The major carry transition should occur for an analog value  
½ LSB below VIN+ = VIN−. Offset error is defined as the  
deviation of the actual transition from that point.  
IF Sampling  
Gain Error  
Due to the effects of aliasing, an ADC is not limited to Nyquist  
sampling. Higher sampled frequencies are aliased down into the  
first Nyquist zone (DC − fCLOCK/2) on the output of the ADC.  
The bandwidth of the sampled signal should not overlap  
Nyquist zones and alias onto itself. Nyquist sampling  
performance is limited by the bandwidth of the input SHA and  
clock jitter (jitter adds more noise at higher input frequencies).  
The first code transition should occur at an analog value ½ LSB  
above negative full scale. The last transition should occur at an  
analog value 1½ LSB below the nominal full scale. Gain error is  
the deviation of the actual difference between first and last code  
transitions and the ideal difference between first and last code  
transitions.  
Temperature Drift  
Two-Tone SFDR  
The temperature drift for zero error and gain error specifies the  
maximum change from the initial (25°C) value to the value at  
The ratio of the rms value of either input tone to the rms value  
of the peak spurious component. The peak spurious component  
may or may not be an IMD product.  
TMIN or TMAX  
.
Power Supply Rejection  
Out-of-Range Recovery Time  
The specification shows the maximum change in full scale from  
the value with the supply at the minimum limit to the value  
with the supply at its maximum limit.  
The time it takes for the ADC to reacquire the analog input  
after a transient from 10% above positive full scale to 10% above  
negative full scale, or from 10% below negative full scale to 10%  
below positive full scale.  
Total Harmonic Distortion (THD)  
The ratio of the rms sum of the first six harmonic components  
to the rms value of the measured input signal, expressed as a  
percentage or in decibels relative to the peak carrier signal (dBc).  
Crosstalk  
Coupling onto one channel being driven by a (−0.5 dBFS) signal  
when the adjacent interfering channel is driven by a full-scale  
signal. Measurement includes all spurs resulting from both  
direct coupling and mixing components.  
Signal-to-Noise and Distortion (SINAD) Ratio  
The ratio of the rms value of the measured input signal to the  
rms sum of all other spectral components below the Nyquist  
Rev. B | Page 1± of 48  
 
AD9238  
TYPICAL PERFORMANCE CHARACTERISTICS  
AVDD, DRVDD = 3.0 V, T = 25°C, AIN differential drive, full scale = 2 V, unless otherwise noted.  
0
100  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
–20  
SFDR  
–40  
–60  
THIRD  
SECOND  
SNR  
HARMONIC  
HARMONIC  
–80  
CROSSTALK  
–100  
–120  
0
5
10  
15  
20  
25  
30  
40  
45  
50  
55  
60  
65  
FREQUENCY (MHz)  
ADC SAMPLE RATE (MSPS)  
Figure 4. Single-Tone FFT of Channel A Digitizing fIN = 12.5 MHz  
While Channel B Is Digitizing fIN = 10 MHz  
Figure 7. AD9238-65 Single-Tone SNR/SFDR vs. FS with fIN = 32.5 MHz  
100  
95  
0
–20  
90  
SFDR  
85  
80  
75  
70  
65  
60  
55  
50  
–40  
–60  
SECOND  
HARMONIC  
SNR  
CROSSTALK  
–80  
–100  
–120  
20  
25  
30  
ADC SAMPLE RATE (MSPS)  
35  
40  
0
5
10  
15  
20  
25  
30  
FREQUENCY (MHz)  
Figure 8. AD9238-40 Single-Tone SNR/SFDR vs. FS with fIN = 20 MHz  
Figure 5. Single-Tone FFT of Channel A Digitizing fIN = 70 MHz  
While Channel B Is Digitizing fIN = 76 MHz  
100  
95  
0
–20  
90  
SFDR  
85  
80  
75  
–40  
–60  
CROSSTALK  
SECOND  
HARMONIC  
SNR  
70  
–80  
65  
60  
55  
50  
–100  
–120  
0
5
10  
15  
20  
25  
30  
0
5
10  
15  
20  
FREQUENCY (MHz)  
ADC SAMPLE RATE (MSPS)  
Figure 6. Single-Tone FFT of Channel A Digitizing fIN = 120 MHz  
While Channel B is Digitizing fIN = 126 MHz  
Figure 9. AD9238-20 Single-Tone SNR/SFDR vs. FS with fIN = 10 MHz  
Rev. B | Page 11 of 48  
 
AD9238  
100  
95  
90  
90  
SFDR  
80  
70  
60  
50  
85  
80  
75  
SFDR  
SNR  
70  
65  
SNR  
40  
–35  
–30  
–25  
–20  
–15  
–10  
–5  
0
0
0
0
20  
40  
60  
80  
100  
120  
140  
140  
140  
INPUT AMPLITUDE (dBFS)  
INPUT FREQUENCY (MHz)  
Figure 10. AD9238-65 Single-Tone SNR/SFDR vs. AIN with fIN = 32.5 MHz  
Figure 13. AD9238-65 Single-Tone SNR/SFDR vs. fIN  
100  
90  
95  
90  
SFDR  
80  
70  
60  
85  
80  
75  
SFDR  
SNR  
SNR  
60  
50  
40  
70  
65  
–35  
–30  
–25  
–20  
–15  
–10  
–5  
0
20  
40  
80  
100  
120  
INPUT AMPLITUDE (dBFS)  
INPUT FREQUENCY (MHz)  
Figure 11. AD9238-40 Single-Tone SNR/SFDR vs. AIN with fIN = 20 MHz  
Figure 14. AD9238-40 Single-Tone SNR/SFDR vs. fIN  
100  
90  
95  
90  
85  
SFDR  
SFDR  
80  
70  
60  
80  
75  
SNR  
SNR  
50  
40  
70  
65  
–35  
–30  
–25  
–20  
–15  
–10  
–5  
0
20  
40  
60  
80  
100  
120  
INPUT FREQUENCY (MHz)  
INPUT AMPLITUDE (dBFS)  
Figure 12. AD9238-20 Single-Tone SNR/SFDR vs. AIN with fIN = 10 MHz  
Figure 15. AD9238-20 Single-Tone SNR/SFDR vs. fIN  
Rev. B | Page 12 of 48  
AD9238  
100  
95  
90  
85  
80  
75  
70  
0
SFDR  
–20  
–40  
–60  
–80  
SNR  
–18  
–100  
–120  
65  
60  
0
5
10  
15  
20  
25  
30  
–24  
–21  
–15  
–12  
–9  
–6  
FREQUENCY (MHz)  
INPUT AMPLITUDE (dBFS)  
Figure 16. Dual-Tone FFT with fIN1 = 45 MHz and fIN2 = 46 MHz  
Figure 19. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz  
0
100  
95  
90  
85  
80  
75  
70  
SFDR  
–20  
–40  
–60  
–80  
SNR  
–100  
–120  
65  
60  
0
5
10  
15  
20  
25  
30  
–24  
–21  
–18  
–15  
–12  
–9  
–6  
FREQUENCY (MHz)  
INPUT AMPLITUDE (dBFS)  
Figure 17. Dual-Tone FFT with fIN1 = 70 MHz and fIN2 = 71 MHz  
Figure 20. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 70 MHz and fIN2 = 71 MHz  
100  
95  
0
–20  
90  
SFDR  
–40  
–60  
85  
80  
75  
70  
–80  
SNR  
–18  
–100  
–120  
65  
60  
0
5
10  
15  
20  
25  
30  
–24  
–21  
–15  
–12  
–9  
–6  
FREQUENCY (MHz)  
INPUT AMPLITUDE (dBFS)  
Figure 18. Dual-Tone FFT with fIN1 = 200 MHz and fIN2 = 201 MHz  
Figure 21. Dual-Tone SNR/SFDR vs.  
AIN with fIN1 = 200 MHz and fIN2 = 201 MHz  
Rev. B | Page 13 of 48  
AD9238  
74  
12.0  
11.5  
11.0  
–65  
600  
500  
400  
72  
70  
–40  
SINAD –20  
300  
200  
100  
–20  
SINAD –40  
SINAD –65  
60  
68  
0
0
10  
20  
30  
40  
50  
60  
20  
40  
CLOCK FREQUENCY  
SAMPLE RATE (MSPS)  
Figure 25. Analog Power Consumption vs. FS  
Figure 22. SINAD vs. FS with Nyquist Input  
DCS ON (SFDR)  
1.0  
0.8  
0.6  
0.4  
0.2  
0
95  
90  
85  
80  
75  
70  
65  
60  
55  
DCS OFF (SFDR)  
DCS ON (SINAD)  
–0.2  
–0.4  
DCS OFF (SINAD)  
–0.6  
–0.8  
–1.0  
50  
30  
35  
40  
45  
50  
55  
60  
65  
0
500  
1000 1500  
2000  
2500  
3000 3500 4000  
DUTY CYCLE (%)  
CODE  
Figure 23. SINAD/SFDR vs. Clock Duty Cycle  
Figure 26. AD9238-65 Typical INL  
84  
82  
80  
78  
76  
74  
72  
70  
68  
1.0  
0.8  
0.6  
0.4  
0.2  
0
SFDR  
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
SINAD  
66  
–50  
0
50  
100  
0
500  
1000 1500  
2000  
2500  
3000 3500 4000  
TEMPERATURE (°C)  
CODE  
Figure 24. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz  
Figure 27. AD9238-65 Typical DNL  
Rev. B | Page 14 of 48  
 
AD9238  
EQUIVALENT CIRCUITS  
AVDD  
AVDD  
CLK_A, CLK_B  
DCS, DFS,  
MUX_SELECT,  
SHARED_REF  
VIN+_A, VIN–_A,  
VIN+_B, VIN–_B  
Figure 30. Equivalent Digital Input Circuit  
Figure 28. Equivalent Analog Input Circuit  
DRVDD  
Figure 29. Equivalent Digital Output Circuit  
Rev. B | Page 1ꢀ of 48  
 
AD9238  
THEORY OF OPERATION  
In IF undersampling applications, any shunt capacitors should  
be removed. In combination with the driving source  
impedance, they limit the input bandwidth. For best dynamic  
performance, the source impedances driving VIN+ and VIN−  
should be matched such that common-mode settling errors are  
symmetrical. These errors are reduced by the common-mode  
rejection of the ADC.  
The AD9238 consists of two high performance ADCs that are  
based on the AD9235 converter core. The dual ADC paths are  
independent, except for a shared internal band gap reference  
source, VREF. Each of the ADC paths consists of a proprietary  
front end SHA followed by a pipelined switched-capacitor  
ADC. The pipelined ADC is divided into three sections,  
consisting of a 4-bit first stage, followed by eight 1.5-bit stages,  
and a final 3-bit flash. Each stage provides sufficient overlap to  
correct for flash errors in the preceding stages. The quantized  
outputs from each stage are combined through the digital  
correction logic block into a final 12-bit result. The pipelined  
architecture permits the first stage to operate on a new input  
sample, while the remaining stages operate on preceding samples.  
Sampling occurs on the rising edge of the respective clock.  
H
T
T
5pF  
5pF  
VIN+  
C
PAR  
T
Each stage of the pipeline, excluding the last, consists of a low  
resolution flash ADC and a residual multiplier to drive the next  
stage of the pipeline. The residual multiplier uses the flash ADC  
output to control a switched-capacitor digital-to-analog  
converter (DAC) of the same resolution. The DAC output is  
subtracted from the stages input signal and the residual is  
amplified (multiplied) to drive the next pipeline stage. The  
residual multiplier stage is also called a multiplying DAC  
(MDAC). One bit of redundancy is used in each one of the  
stages to facilitate digital correction of flash errors. The last  
stage simply consists of a flash ADC.  
VIN–  
C
PAR  
T
H
Figure 31. Switched-Capacitor Input  
An internal differential reference buffer creates positive and  
negative reference voltages, REFT and REFB, respectively, that  
define the span of the ADC core. The output common mode of  
the reference buffer is set to midsupply, and the REFT and  
REFB voltages and span are defined as:  
The input stage contains a differential SHA that can be  
configured as ac- or dc-coupled in differential or single-ended  
modes. The output-staging block aligns the data, carries out the  
error correction, and passes the data to the output buffers. The  
output buffers are powered from a separate supply, allowing  
adjustment of the output voltage swing.  
REFT = ½(AVDD + VREF)  
REFB = ½ (AVDD + VREF)  
Span = 2 × (REFT REFB) = 2 × VREF  
ANALOG INPUT  
The equations above show that the REFT and REFB voltages are  
symmetrical about the midsupply voltage and, by definition, the  
input span is twice the value of the VREF voltage.  
The analog input to the AD9238 is a differential, switched-  
capacitor, SHA that has been designed for optimum perfor-  
mance while processing a differential input signal. The SHA  
input accepts inputs over a wide common-mode range. An  
input common-mode voltage of midsupply is recommended to  
maintain optimal performance.  
The internal voltage reference can be pin-strapped to fixed  
values of 0.5 V or 1.0 V or adjusted within the same range as  
discussed in the Internal Reference Connection section.  
Maximum SNR performance is achieved with the AD9238 set  
to the largest input span of 2 V p-p. The relative SNR  
degradation is 3 dB when changing from 2 V p-p mode to  
1 V p-p mode.  
The SHA input is a differential, switched-capacitor circuit. In  
Figure 31, the clock signal alternatively switches the SHA  
between sample mode and hold mode. When the SHA is  
switched into sample mode, the signal source must be capable  
of charging the sample capacitors and settling within one-half  
of a clock cycle. A small resistor in series with each input can  
help reduce the peak transient current required from the output  
stage of the driving source. Also, a small shunt capacitor can be  
placed across the inputs to provide dynamic charging currents.  
This passive network creates a low-pass filter at the ADC input;  
therefore, the precise values are dependant on the application.  
The SHA may be driven from a source that keeps the signal  
peaks within the allowable range for the selected reference  
voltage. The minimum and maximum common-mode input  
levels are defined as:  
VCMMIN = VREF/2  
VCMMAX = (AVDD + VREF)/2  
Rev. B | Page 1ꢂ of 48  
 
 
AD9238  
The minimum common-mode input level allows the AD9238 to  
accommodate ground-referenced inputs. Although optimum  
performance is achieved with a differential input, a single-  
ended source may be driven into VIN+ or VIN−. In this  
configuration, one input accepts the signal, while the opposite  
input should be set to midscale by connecting it to an  
appropriate reference. For example, a 2 V p-p signal may be  
applied to VIN+, while a 1 V reference is applied to VIN−. The  
AD9238 then accepts an input signal varying between 2 V and  
0 V. In the single-ended configuration, distortion performance  
may degrade significantly as compared to the differential case.  
However, the effect is less noticeable at lower input frequencies and  
in the lower speed grade models (AD9238-40 and AD9238-20).  
CLOCK INPUT AND CONSIDERATIONS  
Typical high speed ADCs use both clock edges to generate a  
variety of internal timing signals and, as a result, may be  
sensitive to the clock duty cycle. Commonly, a 5% tolerance is  
required on the clock duty cycle to maintain dynamic  
performance characteristics.  
The AD9238 provides separate clock inputs for each channel.  
The optimum performance is achieved with the clocks operated  
at the same frequency and phase. Clocking the channels  
asynchronously may degrade performance significantly. In  
some applications, it is desirable to skew the clock timing of  
adjacent channels. The AD9238’s separate clock inputs allow for  
clock timing skew (typically 1 ns) between the channels  
without significant performance degradation.  
Differential Input Configurations  
As previously detailed, optimum performance is achieved while  
driving the AD9238 in a differential input configuration. For  
baseband applications, the AD8138 differential driver provides  
excellent performance and a flexible interface to the ADC. The  
output common-mode voltage of the AD8138 is easily set to  
AVDD/2, and the driver can be configured in a Sallen-Key filter  
topology to provide band limiting of the input signal.  
The AD9238 contains two clock duty cycle stabilizers, one for  
each converter, that retime the nonsampling edge, providing an  
internal clock with a nominal 50% duty cycle. When proper  
track-and-hold times for the converter are required to maintain  
high performance, maintaining a 50% duty cycle clock is  
particularly important in high speed applications. It may be  
difficult to maintain a tightly controlled duty cycle on the input  
clock on the PCB (see Figure 23). DCS can be enabled by tying  
the DCS pin high.  
At input frequencies in the second Nyquist zone and above, the  
performance of most amplifiers is not adequate to achieve the  
true performance of the AD9238. This is especially true in IF  
under-sampling applications where frequencies in the 70 MHz  
to 200 MHz range are being sampled. For these applications,  
differential transformer coupling is the recommended input  
configuration, as shown in Figure 32.  
The duty cycle stabilizer uses a delay-locked loop to create the  
nonsampling edge. As a result, any changes to the sampling  
frequency require approximately 2 µs to 3 µs to allow the DLL  
to acquire and settle to the new rate.  
High speed, high resolution ADCs are sensitive to the quality of  
the clock input. The degradation in SNR at a given full-scale  
input frequency (fINPUT) due only to aperture jitter (tJ) can be  
calculated as  
AVDD  
50Ω  
VINA  
10pF  
2V p-p  
49.9Ω  
AD9238  
50Ω  
VINB  
AGND  
1
10pF  
1kΩ  
SNR = 20 × log  
(
2 × π × fINPUT × t j  
)
1kΩ  
0.1µF  
In the equation, the rms aperture jitter, tJ, represents the root-  
sum square of all jitter sources, which includes the clock input,  
analog input signal, and ADC aperture jitter specification.  
Undersampling applications are particularly sensitive to jitter.  
Figure 32. Differential Transformer Coupling  
The signal characteristics must be considered when selecting a  
transformer. Most RF transformers saturate at frequencies  
below a few MHz, and excessive signal power can also cause  
core saturation, which leads to distortion.  
For optimal performance, especially in cases where aperture  
jitter may affect the dynamic range of the AD9238, it is  
important to minimize input clock jitter. The clock input  
circuitry should use stable references; for example, use analog  
power and ground planes to generate the valid high and low  
digital levels for the AD9238 clock input. Power supplies for  
clock drivers should be separated from the ADC output driver  
supplies to avoid modulating the clock signal with digital noise.  
Low jitter, crystal-controlled oscillators make the best clock  
sources. If the clock is generated from another type of source  
Single-Ended Input Configuration  
A single-ended input may provide adequate performance in  
cost-sensitive applications. In this configuration, there is a  
degradation in SFDR and distortion performance due to the  
large input common-mode swing. However, if the source  
impedances on each input are matched, there should be little  
effect on SNR performance.  
Rev. B | Page 1ꢃ of 48  
 
 
AD9238  
(by gating, dividing, or other methods), it should be retimed by  
the original clock at the last step.  
discharged 0.1 µF and 10 µF decoupling capacitors on REFT  
and REFB.  
POWER DISSIPATION AND STANDBY MODE  
A single channel can be powered down for moderate power  
savings. The powered-down channel shuts down internal  
circuits, but both the reference buffers and shared reference  
remain powered on. Because the buffer and voltage reference  
remain powered on, the wake-up time is reduced to several  
clock cycles.  
The power dissipated by the AD9238 is proportional to its  
sampling rates. The digital (DRVDD) power dissipation is  
determined primarily by the strength of the digital drivers and  
the load on each output bit. The digital drive current can be  
calculated by  
I
DRVDD = VDRVDD × CLOAD × fCLOCK × N  
DIGITAL OUTPUTS  
where N is the number of bits changing, and CLOAD is the average  
load on the digital pins that changed.  
The AD9238 output drivers can be configured to interface with  
2.5 V or 3.3 V logic families by matching DRVDD to the digital  
supply of the interfaced logic. The output drivers are sized to  
provide sufficient output current to drive a wide variety of logic  
families. However, large drive currents tend to cause current  
glitches on the supplies that may affect converter performance.  
Applications requiring the ADC to drive large capacitive loads  
or large fanouts may require external buffers or latches.  
The analog circuitry is optimally biased so that each speed  
grade provides excellent performance while affording reduced  
power consumption. Each speed grade dissipates a baseline  
power at low sample rates that increases with clock frequency.  
Either channel of the AD9238 can be placed into standby mode  
independently by asserting the PDWN_A or PDWN_B pins.  
The data format can be selected for either offset binary or twos  
complement. See the Data Format section for more information.  
It is recommended that the input clock(s) and analog input(s)  
remain static during either independent or total standby, which  
results in a typical power consumption of 1 mW for the ADC.  
Note that if DCS is enabled, it is mandatory to disable the clock  
of an independently powered-down channel. Otherwise,  
significant distortion results on the active channel. If the clock  
inputs remain active while in total standby mode, typical power  
dissipation of 12 mW results.  
TIMING  
The AD9238 provides latched data outputs with a pipeline delay  
of seven clock cycles. Data outputs are available one propa-  
gation delay (tPD) after the rising edge of the clock signal. Refer  
to Figure 2 for a detailed timing diagram.  
The internal duty cycle stabilizer can be enabled on the AD9238  
using the DCS pin. This provides a stable 50% duty cycle to  
internal circuits.  
The minimum standby power is achieved when both channels  
are placed into full power-down mode (PDWN_A = PDWN_B  
= HI). Under this condition, the internal references are powered  
down. When either or both of the channel paths are enabled  
after a power-down, the wake-up time is directly related to the  
recharging of the REFT and REFB decoupling capacitors  
and to the duration of the power-down. Typically, it takes  
approximately 5 ms to restore full operation with fully  
The length of the output data lines and loads placed on them  
should be minimized to reduce transients within the AD9238.  
These transients can detract from the converter’s dynamic  
performance. The lowest typical conversion rate of the AD9238  
is 1 MSPS. At clock rates below 1 MSPS, dynamic performance  
may degrade.  
A
A
ANALOG INPUT  
ADC A  
A
1
0
8
A
2
A
–1  
A
7
A
3
A
A
6
4
A
5
B
B
B
1
0
8
B
ANALOG INPUT  
ADC B  
2
B
–1  
B
7
B
3
B
B
6
4
B
5
CLK_A = CLK_B =  
MUX_SELECT  
D0_A TO  
D11_A  
A
B
A
B
A
1
B
A
B
–7  
A
B
A
B
A
B
A
B
A
B
–1  
–1  
0
0
–8  
–7  
–6  
–6  
–5  
–5  
–4  
–4  
–3  
–3  
–2  
–2  
tPD  
tPD  
Figure 33. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT  
Rev. B | Page 18 of 48  
 
 
AD9238  
DATA FORMAT  
gain and offset matching performance. If the ADCs are to  
function independently, the reference decoupling can be  
treated independently and can provide superior isolation  
between the dual channels. To enable shared reference mode,  
the SHARED_REF pin must be tied high and the external  
differential references must be externally shorted. (REFT_A  
must be externally shorted to REFT_B, and REFB_A must be  
shorted to REFB_B.)  
The AD9238 data output format can be configured for either  
twos complement or offset binary. This is controlled by the data  
format select pin (DFS). Connecting DFS to AGND produces  
offset binary output data. Conversely, connecting DFS to AVDD  
formats the output data as twos complement.  
The output data from the dual ADCs can be multiplexed onto a  
single 12-bit output bus. The multiplexing is accomplished by  
toggling the MUX_SELECT bit, which directs channel data to  
the same or opposite channel data port. When MUX_SELECT  
is logic high, the Channel A data is directed to the Channel A  
output bus, and the Channel B data is directed to the Channel B  
output bus. When MUX_SELECT is logic low, the channel data  
is reversed, that is the Channel A data is directed to the  
Internal Reference Connection  
A comparator within the AD9238 detects the potential at the  
SENSE pin and configures the reference into four possible  
states, which are summarized in Table 7. If SENSE is grounded,  
the reference amplifier switch is connected to the internal  
resistor divider (see Figure 34), setting VREF to 1 V.  
Channel B output bus, and the Channel B data is directed to the  
Channel A output bus. By toggling the MUX_SELECT bit,  
multiplexed data is available on either of the output data ports.  
Connecting the SENSE pin to VREF switches the reference  
amplifier output to the SENSE pin, completing the loop and  
providing a 0.5 V reference output. If a resistor divider is  
connected, as shown in Figure 35, the switch is again set to the  
SENSE pin. This puts the reference amplifier in a noninverting  
mode with the VREF output defined as  
If the ADCs run with synchronized timing, this same clock can  
be applied to the MUX_SELECT pin. Any skew between  
CLK_A, CLK_B, and MUX_SELECT can degrade ac  
performance. It is recommended to keep the clock skew  
<100 pS. After the MUX_SELECT rising edge, either data port  
has the data for its respective channel; after the falling edge, the  
alternate channels data is placed on the bus. Typically, the other  
unused bus would be disabled by setting the appropriate OEB  
high to reduce power consumption and noise. Figure 33 shows  
an example of multiplex mode. When multiplexing data, the  
data rate is two times the sample rate. Note that both channels  
must remain active in this mode and that each channels power-  
down pin must remain low.  
VREF = 0.5 × (1 + R2/R1)  
In all reference configurations, REFT and REFB drive the ADC  
core and establish its input span. The input range of the ADC  
always equals twice the voltage at the reference pin for either an  
internal or an external reference.  
VIN+  
VIN–  
REFT  
VOLTAGE REFERENCE  
0.1µF  
ADC  
0.1µF  
A stable and accurate 0.5 V voltage reference is built into the  
AD9238. The input range can be adjusted by varying the  
reference voltage applied to the AD9238, using either the  
internal reference with different external resistor configurations  
or an externally applied reference voltage. The input span of the  
ADC tracks reference voltage changes linearly. If the ADC is  
being driven differentially through a transformer, the reference  
voltage can be used to bias the center tap (common-mode  
voltage).  
CORE  
10µF  
REFB  
0.1µF  
VREF  
10µF  
SELECT  
LOGIC  
0.1µF  
0.5V  
SENSE  
The shared reference mode allows the user to connect the  
references from the dual ADCs together externally for superior  
AD9238  
Figure 34. Internal Reference Configuration  
Table 7. Reference Configuration Summary  
Selected Mode  
SENSE Voltage  
Resulting VREF (V)  
Resulting Differential Span (V p-p)  
External Reference  
AVDD  
N/A  
2 × External Reference  
Internal Fixed Reference  
Programmable Reference  
Internal Fixed Reference  
VREF  
±.2 V to VREF  
AGND to ±.2 V  
±.ꢀ  
1.±  
±.ꢀ × (1 + R2/R1)  
1.±  
2 × VREF (See Figure 3ꢀ)  
2.±  
Rev. B | Page 1ꢁ of 48  
 
 
 
AD9238  
1.2  
1.0  
External Reference Operation  
The use of an external reference may be necessary to  
enhance the gain accuracy of the ADC or to improve thermal  
drift characteristics. When multiple ADCs track one another, a  
single reference (internal or external) may be necessary to  
reduce gain matching errors to an acceptable level. A high  
precision external reference may also be selected to provide  
lower gain and offset temperature drift. Figure 36 shows the  
typical drift characteristics of the internal reference in both  
1 V and 0.5 V modes. When the SENSE pin is tied to AVDD,  
the internal reference is disabled, allowing the use of an  
external reference. An internal reference buffer loads the  
external reference with an equivalent 7 kΩ load. The internal  
buffer still generates the positive and negative full-scale  
references, REFT and REFB, for the ADC core. The input span  
is always twice the value of the reference voltage; therefore, the  
external reference must be limited to a maximum of 1 V. If the  
internal reference of the AD9238 is used to drive multiple  
converters to improve gain matching, the loading of the  
reference by the other converters must be considered. Figure 37  
depicts how the internal reference voltage is affected by loading.  
VREF = 1V  
0.8  
0.6  
0.4  
VREF = 0.5V  
0.2  
0
0
30  
TEMPERATURE (°C)  
50 60 70 80  
–40 –30 –20 –10  
10 20  
40  
Figure 36. Typical VREF Drift  
0.05  
0
–0.05  
–0.10  
–0.15  
0.5V ERROR  
1V ERROR  
VIN+  
VIN–  
–0.20  
–0.25  
REFT  
0.1µF  
ADC  
CORE  
0.1µF  
0
0.5  
1.0  
1.5  
LOAD (mA)  
2.0  
2.5  
3.0  
10µF  
REFB  
0.1µF  
Figure 37. VREF Accuracy vs. Load  
VREF  
R2  
10µF  
10µF  
SELECT  
LOGIC  
0.5V  
SENSE  
R1  
AD9238  
Figure 35. Programmable Reference Configuration  
Rev. B | Page 2± of 48  
 
 
AD9238  
AD9238 LQFP EVALUATION BOARD  
The evaluation board supports both the AD9238 and AD9248  
and has five main sections: clock circuitry, inputs, reference  
circuitry, digital control logic, and outputs. A description of  
each section follows. Table 8 shows the jumper settings and  
notes assumptions in the comment column.  
The common-mode level for both input options is set to  
midsupply by a resistor divider off the AVDD supply but can  
also be overdriven with an external supply using the (test  
points) TP12, TP13 for the AD8138s and TP14, TP15 for the  
XFMRs. For low distortion of full-scale input signals when  
using an AD8138, put JP17 and JP22 in Position B and put an  
external negative supply on TP10 and TP11.  
Four supply connections to TB1 are necessary for the evaluation  
board: the analog supply of the DUT, the on-board analog  
circuitry supply, the digital driver DUT supply, and the on-  
board digital circuitry supply. Separate analog and digital  
supplies are recommended, and on each supply 3 V is nominal.  
Each supply is decoupled on-board, and each IC, including the  
DUT, is decoupled locally. All grounds should be tied together.  
For best performance, use low jitter input sources and a high  
performance band-pass filter after the signal source, before the  
evaluation board (see Figure 38). For XFMR inputs, use solder  
Jumpers JP13, JP14 for Channel A and JP20, JP21 for  
Channel B. For AD8138 inputs, use solder Jumpers JP15, JP16  
for Channel A and JP18, JP19 for Channel B. Remove all solder  
from the jumpers not being used.  
CLOCK CIRCUITRY  
The clock circuitry is designed for a low jitter sine wave source  
to be ac-coupled and level shifted before driving the 74VHC04  
hex inverter chips (U8 and U9) whose output provides the clock  
to the part. The POT (R32 and R31) on the level shifting  
circuitry allows the user to vary the duty cycle if desired. The  
amplitude of the sine wave must be large enough for the trip  
points of the hex inverter and within the supplies to avoid noise  
from clipping. To ensure a 50% duty cycle internal to the part,  
the AD9238-65 has an on-chip duty cycle stabilizer circuit that  
is enabled by putting in Jumper JP11. The duty cycle stabilizer  
circuitry should only be used at clock rates above 40 MSPS.  
REFERENCE CIRCUITRY  
The evaluation board circuitry allows the user to select a  
reference mode through a series of jumpers and provides an  
external reference if necessary. Refer to Table 9 to find the  
jumper settings for each reference mode. The external reference  
on the board is a simple resistor divider/zener diode circuit  
buffered by an AD822 (U4). The POT (R4) can be used to  
change the level of the external reference to fine adjust the ADC  
full scale.  
DIGITAL CONTROL LOGIC  
Each channel has its own clock circuitry, but normally both  
clock pins are driven by a single 74VHC04, and the solder  
Jumper JP24 is used to tie the clock pins together. When the  
clock pins are tied together and only one 74VHC04 is being  
used, the series termination resistor for the other channel must  
be removed (either R54 or R55, depending on which inverter is  
being used).  
The digital control logic on the evaluation board is a series of  
jumpers and pull-down resistors used as digital inputs for the  
following pins on the AD9238: the power-down and output  
enable bar for each channel, the duty cycle restore circuitry, the  
twos complement output mode, the shared reference mode, and  
the MUX_SELECT pin. Refer to Table 8 for normal operating  
jumper positions.  
A data capture clock for each channel is created and sent to the  
output buffers in order to be used in the data capture system if  
needed. Jumpers JP25 and JP26 are used to invert the data clock  
if necessary and can be used to debug data capture timing  
problems.  
OUTPUTS  
The outputs of the AD9238 (and the data clock discussed  
earlier) are buffered by 74VHC541s (U2, U3, U7, U10) to  
ensure the correct load on the outputs of the DUT, as well as the  
extra drive capability to the next part of the system. The  
74VHC541s are latches, but on this evaluation board, they are  
wired and function as buffers. JP30 can be used to tie the data  
clocks together if desired. If the data clocks are tied, R39 or R40  
must be removed, depending on which clock circuitry is being  
used.  
ANALOG INPUTS  
The AD9238 achieves the best performance with a differential  
input. The evaluation board has two input options for each  
channel, a transformer (XFMR) and an AD8138, both of which  
perform single-ended-to-differential conversions. The XFMR  
allows for the best high frequency performance, and the  
AD8138 is ideal for dc evaluation, low frequency inputs, and  
driving an ADC differentially without loading the single-ended  
signal.  
Rev. B | Page 21 of 48  
 
AD9238  
Table 8. PCB Jumpers  
Table 9. Reference Jumpers  
Normal  
Setting Comment  
Reference Mode  
1 V Internal  
±.ꢀ V Internal  
External  
JP1  
Out  
Out  
In  
JP2  
In  
Out  
Out  
JP3  
Out  
In  
JP4  
Out  
Out  
Out  
JP5  
Out  
Out  
In  
JP Description  
1
2
3
4
8
Reference  
Reference  
Reference  
Reference  
Out  
In  
1 V Reference Mode  
1 V Reference Mode  
1 V Reference Mode  
1 V Reference Mode  
1 V Reference Mode  
Out  
Out  
Out  
Out  
Out  
Out  
Out  
Out  
Out  
In  
SINE SOURCE  
LOW JITTER  
(HP8644)  
Reference  
Shared Reference  
Shared Reference  
PDWN B  
SINE SOURCES  
LOW JITTER  
(HP8644)  
AD9238  
PDWN A  
EVALUATION BOARD  
1± Shared Reference  
11 Duty Cycle  
CLOCK  
CIRCUITRY  
Duty Cycle Restore On  
12 Twos Complement Out  
13 Input  
14 Input  
In  
In  
Using XFMR Input  
Using XFMR Input  
Using XFMR Input  
Using XFMR Input  
Using XFMR Input  
Using XFMR Input  
OUTPUT  
BUFFERS  
INPUT  
BAND-PASS  
FILTERS  
AD9238  
CIRCUITRY  
1ꢀ Input  
1ꢂ Input  
1ꢃ AD8138 Supply  
18 Input  
1ꢁ Input  
Out  
Out  
A
Out  
Out  
In  
REFERENCE MODE  
SELECTION/EXTERNAL  
REFERENCE/CONTROL  
LOGIC  
2± Input  
21 Input  
Figure 38. PCB Test Setup  
In  
22 AD8138 Supply  
23 Mux Select  
24 Tie Clocks  
2ꢀ Data Clock  
2ꢂ Data Clock  
2ꢃ Mux Select  
28 OEB_A  
2ꢁ Mux Select  
3± Data Clock  
3ꢀ OEB_B  
A
Out  
In  
A
Out  
In  
Out  
Out  
Out  
Out  
Using One Signal for Clock  
Using One Signal for Clock  
Rev. B | Page 22 of 48  
AD9238  
LQFP EVALUATION BOARD BILL OF MATERIALS (BOM)  
Table 10.  
No. Quantity Reference Designator  
Device  
Package  
ACASE  
±8±ꢀ  
±ꢂ±3  
±ꢂ±3  
DCASE  
12±ꢂ  
ACASE  
±2±1  
±8±ꢀ  
±ꢂ±3  
Value  
1
2
3
18  
23  
C1, C2, C11, C12, C2ꢃ, C28, C33, C34, Cꢀ±, Cꢀ1, Cꢃ3 to Cꢃꢂ, C8ꢃ to Cꢁ±  
C3 to C1±, C2ꢁ to C31, Cꢀꢂ, Cꢂ1 to Cꢂꢀ, Cꢃꢃ, Cꢃꢁ, C8±, C84 to C8ꢂ  
C13, C1ꢀ, C18, C1ꢁ, C21, C23, C2ꢀ  
Capacitors  
Capacitors  
Capacitors  
Capacitors  
Capacitors  
Capacitors  
Capacitors  
Capacitors  
Capacitors  
Capacitors  
Capacitors  
AD1ꢀ8±  
1± µF  
±.1 µF  
±.±±1 µF  
±.1 µF  
22 µF  
±.1 µF  
ꢂ.3 V  
4
1ꢀ  
4
Cꢂ, C14, C1ꢂ, C1ꢃ, C2±, C22, C24, C2ꢂ, C32, C3ꢀ to C4±  
C41 to C44  
4
C4ꢀ to C48  
2
C4ꢁ, Cꢀ3  
8
2
Cꢀ2, Cꢀꢃ  
±.±1 µF  
4
Cꢀ4, Cꢀꢀ, Cꢂ8, Cꢂꢁ  
1±  
11  
12  
13  
14  
1ꢀ  
1ꢂ  
1ꢃ  
18  
1ꢁ  
2±  
21  
22  
23  
24  
2ꢀ  
2ꢂ  
2ꢃ  
28  
2ꢁ  
3±  
31  
32  
33  
34  
3ꢀ  
3ꢂ  
3ꢃ  
38  
3ꢁ  
4±  
41  
42  
43  
44  
4
2
1
1
14  
13  
4
4
1
1
8
2
4
2
4
2
2
2
1ꢂ  
Cꢀ8, Cꢀꢁ, Cꢃ±, Cꢃ1  
Cꢂ±, Cꢃ2  
D1  
J1  
JP1 to JPꢀ, JP8 to JP12, JP23, JP28, JP2ꢁ, JP3ꢀ  
JPꢂ, JPꢃ, JP13, JP14 to JP1ꢂ, JP18 to JP21, JP24, JP2ꢃ, JP3±  
JP1ꢃ, JP22, JP2ꢀ, JP2ꢂ  
L1 to L4  
R1, R2, R13, R14, R23, R2ꢃ  
R3  
DNP  
2± pF  
±ꢂ±3  
SOT-23CAN 1.2 V  
SAM±8±UPM  
JPRBLK±2  
JPRSLD±2  
JPRBLK±3  
LC121±  
12±ꢂ  
12±ꢂ  
RV32ꢁꢁUP  
±8±ꢀ  
12±ꢂ  
±8±ꢀ  
12±ꢂ  
12±ꢂ  
12±ꢂ  
RV32ꢁꢁW  
±8±ꢀ  
12±ꢂ  
±8±ꢀ  
IND121±  
Resistors  
Resistor  
1± µH  
33 Ω  
ꢀ.4ꢁ kΩ  
1± kΩ  
ꢀ kΩ  
4ꢁ.ꢁ Ω  
1 kΩ  
4ꢁꢁ Ω  
ꢀ23 Ω  
4± Ω  
1± kΩ  
ꢀ±± Ω  
1± kΩ  
22 Ω  
± Ω  
22 Ω  
R4  
Resistor  
Rꢀ, Rꢂ, R38, R41, R43, R44, Rꢀ1  
Rꢃ, R8, R1ꢁ, R2±, Rꢀ2, Rꢀ3  
Rꢁ, R18, R2ꢁ, R3±, R4ꢃ to Rꢀ±  
R1±, R12, R1ꢀ, R24, R2ꢀ, R28  
R11, R2ꢂ  
R1ꢂ, R1ꢃ, R21, R22  
R31, R32  
R33 to R3ꢀ, R42  
R3ꢂ, R3ꢃ  
R3ꢁ, R4±  
Rꢀ4, Rꢀꢀ  
RP1 to RP1ꢂ  
S1 to Sꢂ  
Resistors  
Resistors  
Resistors  
Resistors  
Resistors  
Resistors  
Resistors  
Resistors  
Resistors  
Resistors  
Resistors  
Resistor Pack  
12±ꢂ  
RCAꢃ42±4  
SMA2±±UP  
DIP±ꢂRCUP  
2
1
4
4
2
1
4
T1, T2  
TB1  
TP1, TP3, TPꢀ, TPꢃ  
TP2, TP4, TPꢂ, TP8  
TPꢁ, TP12 to TP1ꢃ  
TP1±, TP11  
T1-1T  
TBLK±ꢂREM  
RED  
BLK  
WHT  
LOOPTP  
LOOPTP  
LOOPMINI  
LOOPMINI  
ꢂ4LQFPꢃXꢃ  
SOL2±  
SOIC-8  
SO8NCꢃ  
TSSOP-14  
RED  
U1  
ADꢁ238  
ꢃ4VHCꢀ41  
AD822  
AD8138  
ꢃ4VHC±4  
U2, U3, Uꢃ, U1±  
U4  
Uꢀ, Uꢂ  
1
2
2
U8, Uꢁ  
Rev. B | Page 23 of 48  
 
AD9238  
LQFP EVALUATION BOARD SCHEMATICS  
Figure 39. Evaluation Board Schematic  
Rev. B | Page 24 of 48  
 
AD9238  
Figure 40. Evaluation Board Schematic (Continued)  
Rev. B | Page 2ꢀ of 48  
AD9238  
Figure 41. Evaluation Board Schematic (Continued)  
Rev. B | Page 2ꢂ of 48  
AD9238  
C28  
10µF  
6.3V  
C75  
10µF  
6.3V  
C8  
0.1µF  
C3  
0.1µF  
C10  
0.1µF  
C9  
0.1µF  
DVDD  
1
19  
20  
10  
R40  
22Ω  
G1  
G2  
VCC  
GND  
DATACLKA  
U10  
2
4
1
3
RP1 22Ω  
1
8
74VHC541  
1RP9 22Ω  
8
2
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
RP9  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
2
3
4
1
2
3
4
7
6
5
8
7
6
5
RP1  
RP1  
RP1  
RP2  
RP2  
RP2  
RP2  
RP3  
RP3  
RP3  
RP3  
RP4  
RP4  
RP4  
RP4  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
6
3
5
OTRA  
DA13  
DA12  
DA11  
DA10  
DA9  
RP9  
4
5
6
7
8
9
8
7
RP9  
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
9
RP10  
RP10  
RP10  
RP10  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
DA8  
20  
10  
1
19  
G1  
G2  
VCC  
GND  
U7  
74VHC541  
1
2
3
4
1
2
3
4
RP11  
RP11  
RP11  
RP11  
RP12  
RP12  
RP12  
RP12  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
8
2
18  
17  
16  
15  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
DA7  
DA6  
DA5  
DA4  
DA3  
DA2  
DA1  
DA0  
3
4
5
6
7
8
9
7
6
5
8
7
6
5
14  
13  
12  
11  
J1  
SAM080UPM  
JP30  
C27  
10µF  
6.3V  
C76  
C7  
0.1µF  
C6  
0.1µF  
C4  
0.1µF  
C5  
0.1µF  
10µF  
6.3V  
DVDD  
1
20  
10  
VCC  
GND  
G1  
G2  
41  
19  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
U2  
22Ω  
8
1 RP13  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
79  
74VHC541  
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
RP5  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
8
7
2
3
4
1
2
3
4
1
18  
RP13  
RP13  
RP13  
RP14  
RP14  
RP14  
RP14  
RP15  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
2
3
4
5
6
7
8
9
7
6
5
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Y1  
OTRB  
DA13  
DA12  
DA11  
DA10  
DA9  
17  
16  
15  
14  
13  
12  
11  
RP5  
RP5  
RP5  
RP6  
RP6  
RP6  
RP6  
RP7  
RP7  
RP7  
RP7  
RP8  
RP8  
RP8  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
6
5
8
7
6
5
8
7
6
5
8
7
6
8
7
6
5
DA8  
8
DA7  
20  
10  
1
G1  
G2  
VCC  
GND  
19  
U3  
74VHC541  
18  
17  
16  
15  
14  
13  
12  
11  
2
3
4
1
2
3
4
RP15  
RP15  
RP15  
RP16  
RP16  
RP16  
RP16  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
22Ω  
7
6
5
8
7
6
5
2
3
4
5
6
7
8
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
DA6  
DA5  
DA4  
DA3  
DA2  
DA1  
DA0  
4
RP8 225  
J1  
SAM080UPM  
Y7  
Y8  
9
R39  
22Ω  
DATACLKB  
Figure 42. Evaluation Board Schematic (Continued)  
Rev. B | Page 2ꢃ of 48  
AD9238  
LQFP PCB LAYERS  
Figure 43. PCB Top Side Silkscreen  
Rev. B | Page 28 of 48  
 
AD9238  
Figure 44. PCB Top Layer  
Rev. B | Page 2ꢁ of 48  
AD9238  
Figure 45. PCB Ground Plane  
Rev. B | Page 3± of 48  
AD9238  
Figure 46. PCB Split Power Plane  
Rev. B | Page 31 of 48  
AD9238  
Figure 47. PCB Bottom Layer  
Rev. B | Page 32 of 48  
AD9238  
Figure 48. PCB Bottom Silkscreen  
Rev. B | Page 33 of 48  
AD9238  
DUAL ADC LFCSP PCB1  
The PCB requires a low jitter clock source, analog sources, and  
power supplies. The PCB interfaces directly with ADIs standard  
dual-channel data capture board (HSC-ADC-EVAL-DC),  
which together with ADIs ADC Analyzer™ software allows for  
quick ADC evaluation.  
CLOCK  
The clock inputs are buffered on the board at U5 and U6. These  
gates provide buffered clocks to the on-board latches, U2 and  
U4, ADC input clocks, and DRA and DRB that are available at  
the output Connector P3, P8. The clocks can be inverted at the  
timing jumpers labeled with the respective clocks. The clock  
paths also provide for various termination options. The ADC  
input clocks can be set to bypass the buffers at P2 to P9 and  
P10, P12. An optional clock buffer U3, U7 can also be placed.  
The clock inputs can be bridged at TIEA, TIEB (R20, R40) to  
allow one to clock both channels from one clock source;  
however, optimal performance is obtained by driving J2 and J3.  
POWER CONNECTOR  
Power is supplied to the board via three detachable 4-lead  
power strips.  
Table 11. Power Connector  
Terminal  
VCC1 3.± V  
VDD1 3.± V  
VDL1 3.± V  
VREF  
Comments  
Analog supply for ADC  
Output supply for ADC  
Supply circuitry  
Optional external VREF  
Optional op amp supply  
Optional op amp supply  
Table 12. Jumpers  
Terminal  
Comments  
OEB A  
PDWN A  
MUX  
Output Enable for A Side  
Power-Down A  
Mux Input  
+ꢀ V  
−ꢀ V  
1VCC, VDD, and VDL are the minimum required power connections.  
SHARED REF  
DR A  
Shared Reference Input  
Invert DR A  
ANALOG INPUTS  
LATA  
ENC A  
OEB B  
PDWN B  
DFS  
Invert A Latch Clock  
Invert Encode A  
Output Enable for B Side  
Power-Down B  
Data Format Select  
Shared Reference Input  
Invert DR B  
The evaluation board accepts a 2 V p-p analog input signal  
centered at ground at two SMB connectors, Input A and  
Input B. These signals are terminated at their respective  
transformer primary side. T1 and T2 are wideband RF  
transformers that provide the single-ended-to-differential  
conversion, allowing the ADC to be driven differentially,  
minimizing even-order harmonics. The analog signals can be  
low-pass filtered at the transformer secondary to reduce high  
frequency aliasing.  
SHARED REF  
DR B  
LATB  
ENC B  
Invert B Latch Clock  
Invert Encode B  
VOLTAGE REFERENCE  
OPTIONAL OPERATIONAL AMPLIFIER  
The ADC SENSE pin is brought out to E41, and the internal  
reference mode is selected by placing a jumper from E41 to  
ground (E27). External reference mode is selected by placing a  
jumper from E41 to E25 and E30 to E2. R56 and R45 allow for  
programmable reference mode selection.  
The PCB has been designed to accommodate an optional  
AD8139 op amp that can serve as a convenient solution for  
dc-coupled applications. To use the AD8139 op amp, remove  
C14, R4, R5, C13, R37, and R36. Place R22, R23, R30, and R24.  
DATA OUTPUTS  
The ADC outputs are latched on the PCB at U2 and U4. The  
ADC outputs have the recommended series resistors in line to  
limit switching transient effects on ADC performance.  
1 The LFCSP PCB is in development.  
Rev. B | Page 34 of 48  
 
 
AD9238  
LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)  
Table 13.  
No. Quantity  
Reference Designator  
C1, C3  
C2, Cꢀ, Cꢃ, Cꢁ, C1±, C22, C3ꢂ  
C4, Cꢂ, C8, C11 to C1ꢀ, C2±, C21,  
C24 to C2ꢃ, C2ꢁ to C3ꢀ, C3ꢁ to Cꢂ1  
Device  
Package  
±2±1  
±8±ꢀ  
Value  
1
2
3
2
44  
Capacitors  
Capacitors  
Capacitors  
2± pF  
1± µF  
±.1 µF  
±4±2  
4
8
1±  
11  
12  
13  
14  
1ꢀ  
1ꢂ  
2
3
3
2
4
4
2
2ꢃ  
C1ꢂ to C1ꢁ, C3ꢃ, C38  
C23, C28  
J1 to Jꢂ  
P1, P4, P11  
P1, P4, P11  
P31, P8  
R1, R2, R32, R34  
R3, Rꢃ, R11, R14, Rꢀ1, Rꢂ1  
R4, Rꢀ, R3ꢂ, R3ꢃ  
Rꢁ, R1±, R12, R13, R2±, R3ꢀ, R38, R4±, R43  
R1ꢀ, R1ꢂ, R18, R2ꢂ, R2ꢁ, R31  
R1ꢃ, R2ꢀ  
Capacitors  
Capacitors  
SMBs  
Power Connector Posts  
Detachable Connectors  
Connectors  
Resistors  
Resistors  
Resistors  
Resistors  
Resistors  
TAJD  
±2±1  
1± µF  
±.1 µF  
Zꢀ.ꢀ31.342ꢀ.±  
2ꢀ.ꢂ±2.ꢀ4ꢀ3.±  
Wieland  
Wieland  
±4±2  
±4±2  
±4±2  
±4±2  
±4±2  
±4±2  
±4±2  
3ꢂ Ω  
ꢀ± Ω  
33 Ω  
± Ω  
4ꢁꢁ Ω  
ꢀ2ꢀ Ω  
1 kΩ  
Resistors  
Resistors  
R1ꢁ, R21, R2ꢃ, R28, R3ꢁ, R41, R44,  
R4ꢂ to R4ꢁ, Rꢀ2, Rꢀ4, Rꢀꢀ, Rꢀꢃ to Rꢂ±, Rꢂ2 to Rꢃ±  
1ꢃ  
18  
1ꢁ  
2±  
21  
22  
23  
24  
2ꢀ  
2ꢂ  
2ꢃ  
4
2
1
8
2
1
2
2
2
2
4
R22 to R24, R3±  
R4ꢀ, Rꢀꢂ  
Rꢀ±  
RZ1 to RZꢂ, RZꢁ, RZ1±  
T1, T2  
U1  
U2, U4  
U32, Uꢃ  
Uꢀ, Uꢂ  
U11, U12  
Rꢂ, R8, R33, R42  
Resistors  
Resistors  
Resistor  
Resistor Pack  
Transformers  
ADꢁ238  
SNꢃ4LVCH1ꢂ3ꢃ3A  
SNꢃ4LVC1G±4  
SNꢃ4VCX8ꢂ  
AD813ꢁ  
±4±2  
±4±2  
±4±2  
4± Ω  
1± kΩ  
22 Ω  
22± Ω  
AWT-1WT  
LFCSP-ꢂ4  
TSSOP-48  
SOT-ꢃ±  
SO-14  
Mini-Circuits®  
SO-8/EP  
±4±2  
Resistors  
1±± Ω  
1 P3 and P8 implemented as one 8±-pin connector SAMTEC TSW-14±-±8-L-D-RA.  
2 U3 and Uꢃ not placed.  
Rev. B| Page 3ꢀ of 48  
 
 
AD9238  
LFCSP PCB SCHEMATICS  
A D 7  
A D 8  
A D 9  
A _ D 7  
A _ D 8  
A _ D 9  
D D 2 D R V  
D R G N D 2  
A _ 0 D 1  
A _ 1 D 1  
A _ 2 D 1  
A _ 3 D 1  
O T R _ A  
O E B _ A  
_ A W N P D  
X _ S M E U L  
E F _ R S H  
B D 7  
B D 6  
B D 5  
4 9  
5 0  
5 1  
5 2  
5 3  
5 4  
5 5  
5 6  
5 7  
5 8  
5 9  
6 0  
6 1  
B _ D 7  
B _ D 6  
B _ D 5  
3 2  
3 1  
3 0  
D D D R V  
2 9  
D R G N D  
2 8  
A 0 D 1  
A 1 1 D  
A 2 1 D  
B D 4  
B D 3  
B D 2  
B D 1  
B D 0  
B _ D 4  
2 7  
2 6  
2 5  
2 4  
2 3  
B _ D 3  
B _ D 2  
B _ D 1  
B _ D 0  
A 3 D 1  
O T R A  
O E B _ B  
2 2  
_ B W N P D  
2 1  
D F S  
2 0  
D C S  
1 9  
6 2  
6 3  
6 4  
A
C L K _  
D D A 5 V  
N E C A  
N E C B  
V D  
B
C L K _  
1 8  
1 7  
V D  
D D A 3 V  
D
E P A  
6 5  
Figure 49. PCB Schematic (1 of 3)  
Rev. B | Page 3ꢂ of 48  
 
AD9238  
Figure 50. PCB Schematic (2 of 3)  
Rev. B | Page 3ꢃ of 48  
AD9238  
Figure 51. PCB Schematic (3 of 3)  
Rev. B | Page 38 of 48  
AD9238  
LFCSP PCB LAYERS  
Figure 52. PCB Top-Side Silkscreen  
Rev. B | Page 3ꢁ of 48  
 
AD9238  
Figure 53. PCB Top-Side Copper Routing  
Rev. B | Page 4± of 48  
AD9238  
Figure 54. PCB Ground Layer  
Rev. B | Page 41 of 48  
AD9238  
Figure 55. PCB Split Power Plane  
Rev. B | Page 42 of 48  
AD9238  
Figure 56. PCB Bottom-Side Copper Routing  
Rev. B | Page 43 of 48  
AD9238  
Figure 57. PCB Bottom-Side Silkscreen  
THERMAL CONSIDERATIONS  
The AD9238 LFCSP has an integrated heat slug that improves  
the thermal and electrical properties of the package when  
locally attached to a ground plane at the PCB. A thermal (filled)  
via array to a ground plane beneath the part provides a path for  
heat to escape the package, lowering junction temperature.  
Improved electrical performance also results from the reduction  
in package parasitics due to proximity of the ground plane.  
Recommended array is 0.3 mm vias on 1.2 mm pitch. θJA  
=
26.4°C/W with this recommended configuration. Soldering the  
slug to the PCB is a requirement for this package.  
Figure 58. Thermal Via Array  
Rev. B | Page 44 of 48  
 
AD9238  
OUTLINE DIMENSIONS  
0.75  
0.60  
0.45  
9.00  
BSC SQ  
1.60  
MAX  
64  
49  
1
48  
PIN 1  
7.00  
BSC SQ  
TOP VIEW  
(PINS DOWN)  
1.45  
1.40  
1.35  
0.20  
0.09  
7°  
3.5°  
0°  
0.15  
0.05  
16  
33  
SEATING  
32  
17  
0.10 MAX  
COPLANARITY  
PLANE  
VIEW A  
0.23  
0.18  
0.13  
0.40  
BSC  
LEAD PITCH  
VIEW A  
ROTATED 90° CCW  
COMPLIANT TO JEDEC STANDARDS MS-026-BBD  
Figure 59. 64-Lead Low Profile Quad Flat Package [LQFP]  
(ST-64-1)  
Dimensions shown in millimeters  
0.30  
0.25  
0.18  
9.00  
BSC SQ  
0.60 MAX  
0.60 MAX  
PIN 1  
INDICATOR  
64  
49  
48  
1
PIN 1  
INDICATOR  
*
4.85  
4.70 SQ  
4.55  
8.75  
BSC SQ  
TOP  
VIEW  
EXPOSED PAD  
(BOTTOM VIEW)  
0.45  
0.40  
0.35  
33  
32  
16  
17  
7.50  
REF  
0.80 MAX  
0.65 TYP  
1.00  
0.85  
0.80  
12° MAX  
0.05 MAX  
0.02 NOM  
0.50 BSC  
0.20 REF  
SEATING  
PLANE  
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD  
EXCEPT FOR EXPOSED PAD DIMENSION  
Figure 60. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
9 mm × 9 mm Body, Very Thin Quad  
(CP-64-1)  
Dimensions shown in millimeters  
Rev. B | Page 4ꢀ of 48  
 
AD9238  
ORDERING GUIDE  
Model  
ADꢁ238BST-2±  
Temperature Range  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
Package Description  
Package Option  
ST-ꢂ4-1  
ST-ꢂ4-1  
ST-ꢂ4-1  
ST-ꢂ4-1  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
Evaluation Board with ADꢁ238BSTZ-2±  
ADꢁ238BSTRL-2±  
ADꢁ238BSTZ-2±1  
ADꢁ238BSTZRL-2±1  
ADꢁ238BSTZ-2±EB1  
ADꢁ238BST-4±  
ADꢁ238BSTRL-4±  
ADꢁ238BSTZ-4±1  
ADꢁ238BSTZRL-1  
ADꢁ238BSTZ-4±EB1  
ADꢁ238BST-ꢂꢀ  
ADꢁ238BSTRL-ꢂꢀ  
ADꢁ238BSTZ-ꢂꢀ1  
ADꢁ238BSTZRL-ꢂꢀ1  
ADꢁ238BSTZ-ꢂꢀEB1  
ADꢁ238BCPZ-2±1  
ADꢁ238BCPZRL-2±1  
ADꢁ238BCPZ-2±EB1  
ADꢁ238BCPZ-4±1  
ADꢁ238BCPZRL-4±1  
ADꢁ238BCPZ-4±EB1  
ADꢁ238BCPZ-ꢂꢀ1  
ADꢁ238BCPZRL-ꢂꢀ1  
ADꢁ238BCPZ-ꢂꢀEB1  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
Evaluation Board with ADꢁ238BSTZ-4±  
ST-ꢂ4-1  
ST-ꢂ4-1  
ST-ꢂ4-1  
ST-ꢂ4-1  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
ꢂ4-Lead Low Profile Quad Flat Package (LQFP)  
Evaluation Board with ADꢁ238BSTZ-ꢂꢀ  
ST-ꢂ4-1  
ST-ꢂ4-1  
ST-ꢂ4-1  
ST-ꢂ4-1  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
ꢂ4-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
ꢂ4-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
Evaluation Board with ADꢁ238BCPZ-2±  
CP-ꢂ4-1  
CP-ꢂ4-1  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
ꢂ4-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
ꢂ4-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
Evaluation Board with ADꢁ238BCPZ-4±  
CP-ꢂ4-1  
CP-ꢂ4-1  
–4±°C to +8ꢀ°C  
–4±°C to +8ꢀ°C  
ꢂ4-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
ꢂ4-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
Evaluation Board with ADꢁ238BCPZ-ꢂꢀ  
CP-ꢂ4-1  
CP-ꢂ4-1  
1 Z = Pb-free part.  
Rev. B | Page 4ꢂ of 48  
 
 
 
AD9238  
NOTES  
Rev. B | Page 4ꢃ of 48  
AD9238  
NOTES  
©2005 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
C02640–0–4/05(B)  
Rev. B | Page 48 of 48  
配单直通车
AD9238BSTZ-20产品参数
型号:AD9238BSTZ-20
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
零件包装代码:QFP
包装说明:LFQFP,
针数:64
Reach Compliance Code:unknown
风险等级:5.61
最大模拟输入电压:2 V
最小模拟输入电压:1 V
转换器类型:ADC, FLASH METHOD
JESD-30 代码:S-PQFP-G64
JESD-609代码:e3
长度:7 mm
最大线性误差 (EL):0.0342%
湿度敏感等级:3
模拟输入通道数量:2
位数:12
功能数量:1
端子数量:64
最高工作温度:85 °C
最低工作温度:-40 °C
输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式:PARALLEL, WORD
封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP
封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260
采样速率:20 MHz
采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.6 mm
标称供电电压:3 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:MATTE TIN
端子形式:GULL WING
端子节距:0.4 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:40
宽度:7 mm
Base Number Matches:1
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