AD9411BSVZ-200全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

10-Bit, 170/200 MSPS

3.3 V A/D Converter

Data Sheet

AD9411

FEATURES

SNR = 60 dB @ f_INup to 70 MHz @ 200 MSPS

ENOB of 9.8 @ f_INup to 70 MHz @ 200 MSPS (–0.5 dBFS)

SFDR = 80 dBc @ f_INup to 70 MHz @ 200 MSPS (–0.5 dBFS)

Excellent linearity:

FUNCTIONAL BLOCK DIAGRAM

SENSE VREF AGND DRGND DRVDD AVDD

SCALABLE

REFERENCE

DNL = 0.15 LSB (typical)

AD9411

INL = 0.25 LSB (typical)

LVDS output levels

700 MHz full-power analog bandwidth

On-chip reference and track-and-hold

Power dissipation = 1.25 W typical @ 200 MSPS

1.5 V input voltage range

DATA,

OVERRANGE

IN LVDS

ADC

10-BIT

PIPELINE

CORE

VIN+

VIN–

10

/

TRACK

AND

HOLD

LVDS

OUTPUTS

3.3 V supply operation

Output data format option

CLK+

CLK–

Clock duty cycle stabilizer

Pin compatible to LVDS mode AD9430

CLOCK

MANAGEMENT

LVDS TIMING

DCO+

DCO–

S1

S5

APPLICATIONS

Wireless and wired broadband communications

Cable reverse path

Figure 1.

Communications test equipment

Radar and satellite subsystems

Power amplifier linearization

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD9411 is a 10-bit monolithic sampling analog-to-digital

converter optimized for high performance, low power, and ease

of use. The product operates up to a 200 MSPS conversion rate

and is optimized for outstanding dynamic performance in

wideband carrier and broadband systems. All necessary

functions, including track-and-hold (T/H) and reference, are

included on the chip to provide a complete conversion solution.

1. High performance.

Maintains 60 dB SNR @ 200 MSPS with a 70 MHz input.

2. Low power.

Consumes only 1.25 W @ 200 MSPS.

3. Ease of use.

LVDS output data and output clock signal allow interface

to current FPGA technology. The on-chip reference and

sample-and-hold function provide flexibility in system

design. Use of a single 3.3 V supply simplifies system

power supply design.

The ADC requires a 3.3 V power supply and a differential

sample clock for full performance operation. The digital outputs

are LVDS compatible and support both twos complement and

offset binary format. A data clock output is available to ease

data capture.

4. Out-of-range (OR).

The OR output bit indicates when the input signal is

beyond the selected input range.

Fabricated on an advanced BiCMOS process, the AD9411 is

available in a 100-lead surface-mount plastic package (e-PAD

TQFP-100) specified over the industrial temperature range

(–40°C to +85°C).

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights ofthird parties that may result fromits use. Specifications subject to change without notice. No

licenseis granted byimplication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9411

Data Sheet

TABLE OF CONTENTS

DC Specifications ............................................................................. 3

Clock Outputs (DCO+, DCO–)............................................... 19

Voltage Reference ....................................................................... 19

Noise Power Ratio Testing (NPR)............................................ 19

Evaluation Board ............................................................................ 21

Power Connector........................................................................ 21

Analog Inputs ............................................................................. 21

Gain.............................................................................................. 21

Clock ............................................................................................ 21

Voltage Reference ....................................................................... 21

Data Format Select..................................................................... 21

Data Outputs............................................................................... 21

CLOCK XTAL ............................................................................ 21

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

AC Specifications.............................................................................. 4

Digital Specifications........................................................................ 5

Switching Specifications .................................................................. 6

Explanation of Test Levels........................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Terminology .................................................................................... 10

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics ........................................... 13

Application Notes ........................................................................... 18

Clock Input.................................................................................. 18

Analog Input ............................................................................... 18

LVDS Outputs............................................................................. 19

REVISION HISTORY

1/12—Data Sheet Changed from Rev. A to Rev. B

Added Exposed Pad Notation to Figure 3..................................... 8

Added Pin 55 to Table 6................................................................... 9

Changes to Ordering Guide .......................................................... 27

7/04—Data Sheet Changed from Rev. 0 to Rev. A

Added 200 MSPS Grade ....................................................Universal

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide .......................................................... 27

1/04—Revision 0: Initial Version

Rev. B | Page 2 of 28

Data Sheet

AD9411

DC SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T_MIN= –40°C, T_MAX= +85°C, f_IN= –0.5 dBFS, internal reference, full scale = 1.536 V, unless

otherwise noted.

Table 1.

AD9411-170

AD9411-200

Test

Parameter

RESOLUTION

ACCURACY

Temp Level Min

Typ

Max

Min

Typ

Max

Unit

12

Bits

No Missing Codes

Offset Error

Gain Error

Differential Nonlinearity (DNL)

Full

VI

I

VI

I

Guaranteed

–3

–5

Guaranteed

–3

–5

25°C

Full

25°C

Full

+3

+5

+0.5

+0.6

+0.8

+1

+3

mV

+5

% FS

LSB

–0.5

–0.6

–0.8

–1

0.15

0.25

0.5

–0.5

–0.6

–0.8

–1

0.15

0.25

0.5

+0.5

+0.6

+0.8

+1

Integral Nonlinearity (INL)

VI

0.5

TEMPERATURE DRIFT

Offset Error

Full

V

58

0.02

+0.12/

–0.24

58

0.02

+0.12/

–0.24

μV/°C

%/°C

mV/°C

Gain Error

Reference Out (VREF)

REFERENCE

Reference Out (VREF)

Output Current¹

25°C

I

IV

I

1.15

1.235

1.3

3.0

20

1.15

1.235

1.3

3.0

20

V

mA

I_VREFInput Current²

I_SENSEInput Current²

ANALOG INPUTS (VIN+, VIN–)³

Differential Input Voltage Range

(S5 = GND)

I

1.6

5.0

1.6

5.0

Full

V

1.536

0.766

1.536

0.766

V

Differential Input Voltage Range

(S5 = AVDD)

Input Common-Mode Voltage

Input Resistance

Input Capacitance

POWER SUPPLY (LVDS Mode)

AVDD

Full

25°C

VI

V

2.65

2.2

2.8

3

5

2.9

3.8

2.65

2.2

2.8

3

5

2.9

3.8

V

kΩ

pF

Full

IV

3.1

3.0

3.3

3.6

3.2

3.0

3.3

3.6

V

DRVDD

Supply Currents

I_ANALOG(AVDD = 3.3 V)⁴

I_DIGITAL(DRVDD = 3.3 V)⁴

Power Dissipation⁴

Power Supply Rejection

Full

25°C

VI

V

335

49

1.27

–7.5

372

57

1.42

385

49

1.43

–7.5

425

57

1.59

mA

W

mV/V

¹Internal reference mode; SENSE = floats.

²External reference mode; SENSE = DRVDD; VREF driven by external 1.23 V reference.

³S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc, ac tests, unless otherwise specified

⁴I_AVDDand I_DRVDDare measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated clock rate, and in LVDS output mode. See the Typical Performance

Characteristics and Application Notes sections for I_DRVDD. Power consumption is measured with a dc input at rated clock rate in LVDS output mode.

Rev. B | Page 3 of 28

AD9411

Data Sheet

AC SPECIFICATIONS¹

AVDD = 3.3 V, DRVDD = 3.3 V, T_MIN= –40°C, T_MAX= +85°C, f_IN= –0.5 dBFS, internal reference, full scale = 1.536 V, unless

otherwise noted.

Table 2.

AD9411-170

Typ

AD9411-200

Test

Level

Parameter

Temp

Min

Max Min

Typ

Max

Unit

SNR

Analog Input @ –0.5 dBFS

10 MHz

70 MHz

100 MHz

240 MHz

25°C

I

V

59

60.2

60.1

60

59

60.2

60.1

60

dB

59.1

SINAD

Analog Input @ –0.5 dBFS

10 MHz

70 MHz

100 MHz

240 MHz

25°C

I

V

58.5

60

59.5

57.5

58.5

60

59.5

57.5

dB

EFFECTIVE NUMBER OF BITS (ENOB)

10 MHz

70 MHz

100 MHz

240 MHz

25°C

I

V

9.5

9.8

9.7

9.3

9.5

9.8

9.7

9.3

Bits

WORST HARMONIC (Second or Third)

Analog Input @ –0.5 dBFS 10 MHz

10 MHz

70 MHz

100 MHz

240 MHz

25°C

I

V

–80

−74

−69

–73

–80

−74

−69

–70

dBc

WORST HARMONIC (Fourth or Higher)

Analog Input @ –0.5 dBFS 10 MHz

10 MHz

70 MHz

100 MHz

240 MHz

25°C

I

V

–82

−76

−70

–75

–82

−76

−70

–75

dBc

TWO-TONE IMD²

F1, F2 @ –7 dBFS

ANALOG INPUT BANDWIDTH

25°C

V

70

dBc

700

MHz

¹All ac specifications tested by driving CLK+ and CLK– differentially.

²F1 = 30.5 MHz, F2 = 31 MHz.

Rev. B | Page 4 of 28

Data Sheet

AD9411

DIGITAL SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T_MIN= –40°C, T_MAX= +85°C, unless otherwise noted.

Table 3.

AD9411-170

AD9411-200

Typ

Parameter

Temp Test Level Min

Typ

Max

Min

Max

Unit

CLOCK INPUTS

(CLK+, CLK–)¹

Differential Input Voltage²

Common-Mode Voltage³

Input Resistance

Full

25°C

IV

VI

V

0.2

1.375

3.2

0.2

1.375 1.5

3.2

V

kΩ

pF

1.5

5.5

4

1.575

6.5

1.575

6.5

5.5

4

Input Capacitance

LOGIC INPUTS (S1, S2, S4, S5)

Logic 1 Voltage

Full

25°C

IV

VI

V

2.0

V

μA

kΩ

pF

Logic 0 Voltage

0.8

190

10

0.8

190

10

Logic 1 Input Current

Logic 0 Input Current

Input Resistance

30

4

30

4

Input Capacitance

LVDS LOGIC OUTPUTS⁴

V_ODDifferential Output Voltage

V_OSOutput Offset Voltage

Output Coding

V

Full

VI

247

1.125

454

1.375

247

1.125

454

1.375

mV

V

Twos Complement or Binary Twos Complement or Binary

¹See the Equivalent Circuits section.

²All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.

³Clock inputs’ common mode can be externally set, such that 0.9 V < CLK< 2.6 V.

⁴LVDS R_TERM= 100 Ω, LVDS output current set resistor (R_SET) = 3.74 kΩ(1% tolerance).

Rev. B | Page 5 of 28

AD9411

Data Sheet

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, T_MIN= –40°C, T_MAX= +85°C, unless otherwise noted.

Table 4.

AD9411-170

AD9411-200

Parameter (Conditions)

Temp Test

Level

Min

Typ

Max Min

Typ

Max Unit

Maximum Conversion Rate¹

Minimum Conversion Rate¹

Full

VI

V

170

200

40

MSPS

40

MSPS

ns

1

CLK+ Pulse Width High (t_EH

)

IV

2

12.5

2

12.5

CLK+ Pulse Width Low (t_EL)¹

OUTPUT (LVDS Mode)

Valid Time (t_V)

ns

Full

25°C

Full

25°C

VI

V

2.0

ns

Cycles

ns

ps

Propagation Delay (t_PD

)

3.2

0.5

2.7

0.5

14

4.3

3.2

0.5

2.7

0.5

14

4.3

Rise Time (t_R) (20% to 80%)

Fall Time (t_F) (20% to 80%)

DCO Propagation Delay (t_CPD

Data to DCO Skew (t_PD–t_CPD

Latency

V

)

VI

IV

V

1.8

0.2

3.8

0.8

1.8

0.2

3.8

0.8

)

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_J)

1.2

0.25

1.2

0.25

V

rms

Out-of-Range Recovery Time

25°C

V

1

Cycles

¹All ac specifications tested by driving CLK+ and CLK– differentially.

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and sample tested at specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%

production tested at temperature extremes for military devices.

N–1

N

N+1

A

IN

t_EL

t_EH

1/f

S

CLK+

CLK–

t_PD

N–14

N–13

N

N+1

DATA OUT

14 CYCLES

DCO+

DCO–

t_CPD

Figure 2. LVDS Timing Diagram

Rev. B | Page 6 of 28

Data Sheet

AD9411

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Rating

Stresses above those listed under Absolute Maximum Ratings

AVDD, DRVDD

Analog Inputs

Digital Inputs

REFIN Inputs

4 V

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions outside of those indicated in the operation

section of this specification is not implied. Exposure to absolute

maximum ratings conditions for extended periods may affect

device reliability.

–0.5 V to AVDD +0.5 V

–0.5 V to DRVDD +0.5 V

–0.5 V to AVDD +0.5 V

20 mA

–55ºC to +125°C

–65ºC to +150°C

150°C

Digital Output Current

Operating Temperature

Storage Temperature

Maximum Junction Temperature

Maximum Case Temperature

150°C

25°C/W, 32°C/W

1

θ_JA

¹Typical θ_JA= 32°C/W (heat slug not soldered); typical θ_JA= 25°C/W (heat slug

soldered) for multilayer board in still air with solid ground plane.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. B | Page 7 of 28

AD9411

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

S5

DNC

1

2

75 DRVDD

74

73

72

DRGND

D6+

AGND

3

D6–

4

AVDD

S1

5

71 D5+

6

70

69

68

67

66

65

64

63

62

61

D5–

7

LVDSBIAS

AVDD

D4+

8

D4–

9

AGND

SENSE

VREF

DRGND

D3+

10

11

12

13

14

15

D3–

AGND

AVDD

DCO+

DCO–

DRVDD

DRGND

AD9411

TOP VIEW

(Not to Scale)

AVDD

AGND 16

AGND 17

60 D2+

59 D2–

18

58

AVDD

D1+

AVDD 19

AGND 20

57 D1–

56 D0+

VIN+ 21

VIN– 22

55 D0–

54 DRVDD

AGND

AVDD

AGND

DRGND

DNC

23

24

25

53

52

51

DNC

NOTES

1. THE AD9411 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF

THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL

TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE

SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

Figure 3. TQFP_EP Pinout

Rev. B | Page 8 of 28

Data Sheet

AD9411

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Function

1

S5

Full-Scale Adjust Pin. AVDD sets FS = 0.768 V p-p differential;

GND sets FS = 1.536 V p-p differential.

Do Not Connect.

2, 42–46,49–52

DNC

3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31,

32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100

AGND

Analog Ground. AGND and DRGND should be tied together to a common

ground plane.

5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34,

39, 40, 88, 89, 90, 94, 95, 98, 99

AVDD

3.3 V Analog Supply.

6

7

S1

Data Format Select. GND = binary; AVDD = twos complement.

Set Pin for LVDS Output Current. Place a 3.74 kΩ resistor terminated to

ground.

LVDSBIAS

10

11

21

SENSE

VREF

VIN+

Reference Mode Select Pin. Float for internal reference operation.

1.235 V Reference Input/Output. Function depends on SENSE.

Analog Input. True.

22

VIN–

Analog Input. Complement.

36

37

CLK+

CLK–

DRVDD

DRGND

Clock Input. True (LVPECL levels).

Clock Input. Complement (LVPECL levels).

3.3 V Digital Output Supply (3.0 V to 3.6 V).

Digital Output Ground. AGND and DRGND should be tied together to a

common ground plane.

47, 54, 62, 75, 83

48, 53, 61, 67, 74, 82

55

56

57

58

59

60

63

64

65

66

68

69

70

71

72

73

76

77

78

79

80

81

84

85

D0–

D0+

D1–

D1+

D2–

D2+

DCO–

DCO+

D3–

D3+

D4–

D4+

D5–

D5+

D6–

D6+

D7–

D7+

D8–

D8+

D9–

D9+

OR–

OR+

D0 Complement Output Bit.

D0 True Output Bit.

D1 Complement Output Bit.

D1 True Output Bit.

D2 Complement Output Bit.

D2 True Output Bit.

Data Clock Output. Complement.

Data Clock Output. True.

D3 Complement Output Bit.

D3 True Output Bit.

D4 Complement Output Bit.

D4 True Output Bit.

D5 Complement Output Bit.

D5 True Output Bit.

D6 Complement Output Bit.

D6 True Output Bit.

D7 Complement Output Bit.

D7 True Output Bit.

D8 Complement Output Bit.

D8 True Output Bit.

D9 Complement Output Bit.

D9 True Output Bit.

Overrange Complement Output Bit.

Overrange True Output Bit.

Rev. B | Page 9 of 28

AD9411

Data Sheet

TERMINOLOGY

Analog Bandwidth

Clock Pulse Width/Duty Cycle

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Pulse width high is the minimum amount of time the clock

pulse should be left in the Logic 1 state to achieve rated

performance; pulse width low is the minimum time the clock

pulse should be left in the low state. Refer to the timing

implications of changing t_ENCHin the Application Notes, Clock

Input section. At a given clock rate, these specifications define

an acceptable CLOCK duty cycle.

Aperture Delay

The delay between the 50% point of the rising edge of the clock

command and the instant at which the analog input is sampled.

Full-Scale Input Power

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Crosstalk

Expressed in dBm. Computed using the following equation:









V ²

FULLSCALE

RMS

Coupling onto one channel being driven by a low level (–40 dBFS)

signal when the adjacent interfering channel is driven by a full-

scale signal.





Power_FULLSCALE 10log

Z_INPUT









0.001

Differential Analog Input Resistance, Differential Analog

Input Capacitance, and Differential Analog Input Impedance

Gain Error

The difference between the measured and ideal full-scale input

voltage range of the ADC.

The real and complex impedances measured at each analog

input port. The resistance is measured statically and the

capacitance and differential input impedances are measured

with a network analyzer.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the

second harmonic component, reported in dBc.

Differential Analog Input Voltage Range

Harmonic Distortion, Third

The peak-to-peak differential voltage that must be applied to

the converter to generate a full-scale response. Peak differential

voltage is computed by observing the voltage on a single pin

and subtracting the voltage from the other pin, which is 180°

out of phase. Peak-to-peak differential is computed by rotating

the input’s phase 180° and again taking the peak measurement.

The difference is then computed between both peak

measurements.

The ratio of the rms signal amplitude to the rms value of the

third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line

measured in fractions of 1 LSB using a “best straight line”

determined by a least square curve fit.

Differential Nonlinearity

Minimum Conversion Rate

The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits (ENOB)

The CLOCK rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed

limit.

Calculated from the measured SNR based on the equation

Maximum Conversion Rate

SNR_MEASURED1.76 dB

ENOB 

The CLOCK rate at which parametric testing is performed.

Output Propagation Delay

6.02

The delay between a differential crossing of CLK+ and CLK–

and the time when all output data bits are within valid logic

levels.

Rev. B | Page 10 of 28

Data Sheet

AD9411

Noise (for Any Range within the ADC)

Two-Tone Intermodulation Distortion Rejection

Calculated as follows:

The ratio of the rms value of either input tone to the rms value of

the worst third-order intermodulation product, reported in dBc.

FS

 SNR_dBc Signal_dBFS









dBM

V_NOISE

 Z  0.00110

Two-Tone SFDR

10





The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product. May be reported in dBc

(i.e., degrades as signal level is lowered) or in dBFS (always

related back to converter full scale).

where Z is the input impedance, FS is the full scale of the device

for the frequency in question, SNR is the value of the particular

input level, and Signal is the signal level within the ADC reported

in dB below full scale. This value includes both thermal and

quantization noise.

Worst Other Spur

Power Supply Rejection Ratio (PSRR)

The ratio of the rms signal amplitude to the rms value of the

worst spurious component (excluding the second and third

harmonics) reported in dBc.

The ratio of a change in input offset voltage to a change in

power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

Transient Response Time

The ratio of the rms signal amplitude (set 1 dB below full scale)

to the rms value of the sum of all other spectral components,

including harmonics but excluding dc.

The time it takes for the ADC to reacquire the analog input

after a transient from 10% above negative full scale to 10%

below positive full scale.

Signal-to-Noise Ratio (without Harmonics)

Out-of-Range Recovery Time

The ratio of the rms signal amplitude (set at 1 dB below full

scale) to the rms value of the sum of all other spectral compo-

nents, excluding the first five harmonics and dc.

The time it takes for the ADC to reacquire the analog input

after a transient from 10% above positive full scale to 10% above

negative full scale, or from 10% below negative full scale to 10%

below positive full scale.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the

peak spurious spectral component. The peak spurious compo-

nent may or may not be a harmonic. May be reported in dBc

(i.e., degrades as signal level is lowered) or dBFS (always related

back to converter full scale).

Rev. B | Page 11 of 28

AD9411

Data Sheet

EQUIVALENT CIRCUITS

AVDD

FULL

SCALE

K

12k

150

10k

12k

0.1F

VREF

CLK+

CLK–

150

A1

1V

10k

200

SENSE

1k

DISABLE

A1

VDD

Figure 4. Clock Inputs

AVDD

Figure 7. VREF, SENSE I/O

3.5k

20k

DRVDD

VIN+

VIN–

20k

V+

V–

DX–

V–

DX+

V+

Figure 5. Analog Inputs

VDD

Figure 8. Data Outputs

S1,S5

30k

Figure 6. S1 to S5 Inputs

Rev. B | Page 12 of 28

Data Sheet

AD9411

TYPICAL PERFORMANCE CHARACTERISTICS

0

–10

0

SNR = 59.7dB

SINAD = 59.5dB

H2 = –83.6dBc

H3 = –72.6dBc

SFDR = 72.5dBc

–10

SNR = 60.1dB

SINAD = 59.9dB

H2 = –91.3dBc

–20

–30

–40

H3 = –75.2dBc

SFDR = 75.3dBc

–40

–50

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

0

10

20

30

40

50

60

70

80

90

100

0

10

20

30

40

MHz

50

60

70

80

MHz

Figure 12. FFT: fS = 200 MSPS, AIN = 10.3 MHz @ −0.5 dBFS

Figure 9. FFT: fS = 170 MSPS, AIN = 10.3 MHz @ −0.5 dBFS

0

–10

SNR = 59.5dB

SINAD = 59.4dB

H2 = –82.5dBc

H3 = –72.8dBc

SFDR = 72.7dBc

–10

–20

SNR = 59.8dB

SINAD = 59.8dB

H2 = –91.9dBc

H3 = –80.6dBc

SFDR = 73.2dBc

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

0

10

20

30

40

50

60

70

80

90

100

10

20

30

40

MHz

50

60

70

80

MHz

Figure 13. FFT: fS = 200 MSPS, AIN = 65 MHz @ −0.5 dBFS

Figure 10. FFT: fS = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS

0

–10

0

–10

SNR = 50.6dB

SINAD = 43.8dB

H2 = –44.8dBc

H3 = –67.4dBc

SFDR = 43.6dBc

SNR = 59.2dB

SINAD = 59.1dB

H2 = –70.1dBc

H3 = –87.0dBc

SFDR = 69.8dBc

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

0

10

20

30

40

50

60

70

80

90

100

10

20

30

40

MHz

50

60

70

80

MHz

Figure 14. FFT: fS = 200 MSPS, AIN = 70 MHz @ −0.5 dBFS,

Single-Ended Drive, 1.5 V Input Range

Figure 11. FFT: fS = 170 MSPS, AIN = 10.3, MHz @ –0.5 dBFS,

Single-Ended Input, 0.76 V Input Range

Rev. B | Page 13 of 28

AD9411

Data Sheet

100

0

–10

SFDR = 71.5dBc

90

–20

–30

80

–40

THIRD

–50

SFDR

SECOND

70

60

50

40

–60

–70

–80

–90

–100

–110

–120

0

50

100

150

200

250

300

350

400

0

10

20

30

40

MHz

50

60

70

80

A

(MHz)

IN

Figure 15. Harmonic Distortion (Second and Third) and SFDR vs. AIN

Frequency @ 170 MSPS

Figure 18. Two-Tone Intermodulation Distortion

(30.5 MHz and 31.0 MHz; fS = 170 MSPS)

100

0

90

–20

–40

SECOND

80

70

–60

THIRD

SFDR = 78.8dBc

SFDR

60

–80

50

40

–100

–120

0

50

100

150

200

250

300

350

400

0

10

20

30

40

50

60

70

80

90

100

(MHz)

Figure 16. Harmonic Distortion (Second and Third) and SFDR vs. AIN

Frequency @ 200 MSPS

Figure 19. Two-Tone Intermodulation Distortion

(69.3 MHz and 70.3 MHz; fS = 200 MSPS)

61

80

75

70

65

60

55

50

45

40

SNR_170

SFDR_170

59

57

SNR_200

SFDR_200

SINAD_170

55

SINAD_170

53

SINAD_200

51

SINAD_200

49

47

45

0

50

100

150

200

250

300

350

400

450

0

50

100

150

200

250

(MHz)

(MSPS)

Figure 20. SINAD and SFDR vs. Clock Rate

(AIN = 10.3 MHz @ –0.5 dBFS) 170/200 grade

Figure 17. SNR and SINAD vs. AIN Frequency; fS = 170/200 MSPS,

AIN @ –0.5 dBFS Full Scale = 1.536 V

Rev. B | Page 14 of 28

Data Sheet

AD9411

450

400

350

300

250

200

150

100

50

90

80

70

60

50

40

30

20

10

0

80

75

70

65

60

55

50

ANALOG SUPPLY

CURRENT

SFDR

OUTPUT SUPPLY

CURRENT

SNR

SINAD

0

100

20

30

40

50

60

70

80

120

140

160

180

200

220

240

SAMPLE CLOCK POSITIVE DUTY CYCLE

ENCODE (MSPS)

Figure 24. SINAD and SFDR vs. Clock Pulse Width High

(AIN = 10.3 MHz @ –0.5 dBFS, 200 MSPS)

Figure 21. IAVDD and IDRVDD vs. Clock Rate, 170 MSPS Grade, CLOAD = 5 pF

(AIN = 10.3 MHz @ –0.5 dBFS)

1.4

450

400

350

300

250

200

150

100

50

90

80

70

60

50

40

30

20

10

0

1.2

1.0

0.8

0.6

0.4

0.2

0

R

= 13 TYP

O

ANALOG SUPPLY CURRENT

OUTPUT SUPPLY CURRENT

0

100

120

140

160

180

200

220

240

0

1

2

3

4

5

6

7

8

SAMPLE RATE (MSPS)

I

(mA)

LOAD

Figure 22. IAVDD and IDRVDD vs. Clock Rate, 200 MSPS Grade, CLOAD = 5 pF

(AIN = 10.3 MHz @ –0.5 dBFS)

Figure 25. VREFOUT vs. ILOAD (Both Speed Grades)

75

80

73

SFDR

75

70

65

60

55

50

71

69

67

65

63

SNR

61

SINAD

59

SINAD

57

55

20

30

40

50

60

70

80

90

0.5

0.7

0.9

1.1

1.3

1.5

V

(V)

REF

ENCODE POSITIVE DUTY CYCLE (%)

Figure 23. SINAD and SFDR vs. Clock Pulse Width High

(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)

Figure 26. Sinad, SFDR vs. VREF in External Reference Mode

(AIN = 70 MHz @ –0.5 dBFS, 200 MSPS)

Rev. B | Page 15 of 28

AD9411

Data Sheet

2.0

90

85

80

75

70

65

60

55

50

1.5

1.0

0.5

% GAIN ERROR

USING EXT REF

SFDR

0

–0.5

–1.0

–1.5

SNR

SINAD

–2.0

–50

–30

–10

10

30

50

70

90

–50

–30

–10

10

30

50

70

90

TEMPERATURE (°C)

Figure 27. Full-Scale Gain Error vs. Temperature

(AIN = 10.3 MHz @ –0.5 dBFS, 170/200 MSPS)

Figure 30. SNR, SINAD, and SFDR vs. Temperature

(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)

60

59

58

57

56

1.00

0.75

0.50

0.25

0

AVDD = 3.6V

AVDD = 3.3V

AVDD = 3.15V

–0.25

–0.50

–0.75

–1.00

AVDD = 3.0V

55

–40

–20

0

20

40

60

80

0

100 200 300 400 500 600 700 800 900 1000

CODE

TEMPERATURE (°C)

Figure 28. SINAD vs. Temperature and AVDD

(AIN = 10.3 MHz @ –0.5 dBFS, 200 MSPS)

Figure 31. Typical INL Plot

(AIN = 10.3 MHz @ –0.5 dBFS, 170/200 MSPS)

1.0

0.8

1.250

1.245

1.240

1.235

1.230

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

1.225

2.5

0

100 200 300 400 500 600 700 800 900 1000

CODE

2.7

2.9

3.1

3.3

3.5

3.7

3.9

AVDD (V)

Figure 29. VREF Output Voltage vs. AVDD (Both Speed Grades)

Figure 32. Typical DNL Plot (AIN = 10.3 MHz @ –0.5 dBFS) 170/200 MSPS

Rev. B | Page 16 of 28

Data Sheet

AD9411

110

100

90

0

–20

NPR = 51 dB

CLK = 200MSPS

NOTCH AT 18.5MHz

SFDR –dBFS

80

–40

70

60

–60

50

40

80dB

–80

REFERENCE LINE

30

20

10

0

SFDR –dBc

–100

–120

0

5

10

15

20

25

30

35

40

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

MHz

ANALOG INPUT LEVEL (dBFS)

Figure 33. SFDR vs. AIN Input Level 10.3 MHz, AIN @ 170 MSPS

Figure 36. Noise Power Ratio Plot (200 MSPS Grade)

90

80

70

4.5

4.0

3.5

3.0

2.5

60

SFDR –dBc

SFDR –dBFS

50

40

30

T

PD

70dB REFERENCE LINE

20

CPD

10

0

–70

–60

–50

–40

–30

–20

–10

0

–40

–20

0

20

40

60

80

100

ANALOG INPUT LEVEL (dBFS)

TEMPERATURE (°C)

Figure 37. Propagation Delay vs. Temperature (Both Speed Grades)

Figure 34. SFDR vs. AIN Input Level 70 MHz, AIN @ 200 MSPS

0

900

800

700

600

500

400

300

200

100

0

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

NPR = 51.2dB

ENCODE = 170MSPS

NOTCH @ 18.15MHz

–20

V

OS

–40

–60

–80

V

OD

–100

–120

–140

0

10

20

MHz

30

40

0

2

4

6

8

10

12

14

RSET (k

Figure 35. Noise Power Ratio Plot (170 MSPS Grade)

Figure 38. LVDS Output Swing, Common-Mode Voltage vs. RSET,

Placed at LVDSBIAS (Both Speed Grades)

Rev. B | Page 17 of 28

AD9411

Data Sheet

APPLICATION NOTES

The AD9411 architecture is optimized for high speed and ease

of use. The analog inputs drive an integrated high bandwidth

track-and-hold circuit that samples the signal prior to quantiza-

tion by the 10-bit core. For ease of use, the part includes an on-

board reference and input logic that accepts TTL, CMOS, or

LVPECL levels. The digital output’s logic levels are LVDS

(ANSI-644) compatible.

Table 7. Output Select Coding¹

S5 (Full-Scale

S1 (Data Format

Select)

Select)²

Mode

1

0

X

1

0

Twos Complement

Offset Binary

Full Scale = 0.768 V

Full Scale = 1.536 V

CLOCK INPUT

X

¹X = Don’t Care.

Any high speed A/D converter is extremely sensitive to the

quality of the sampling clock provided by the user. A track-and-

hold circuit is essentially a mixer, and any noise, distortion, or

timing jitter on the clock is combined with the desired signal at

the A/D output. For this reason, considerable care has been

taken in the design of the clock inputs of the AD9411, and the

user is advised to give careful thought to the clock source.

²S5 full-scale adjust (refer to the Analog Input section).

ANALOG INPUT

The analog input to the AD9411 is a differential buffer. For best

dynamic performance, impedances at VIN+ and VIN– should

match. The analog input is optimized to provide superior wide-

band performance and requires that the analog inputs be driven

differentially. SNR and SINAD performance degrades signifi-

cantly if the analog input is driven with a single-ended signal.

The AD9411 has an internal clock duty cycle stabilization

circuit that locks to the rising edge of CLK+ and optimizes

timing internally. This allows a wide range of input duty cycles

at the input without degrading performance. Jitter in the rising

edge of the input is still of paramount concern and is not

reduced by the internal stabilization circuit. The duty cycle

control loop does not function for clock rates less than 30 MHz

nominally. The time constant associated with the loop should

be considered in applications where the clock rate changes

dynamically, requiring a wait time of 1.5 μs to 5 μs after a

dynamic clock frequency increase before valid data is available.

This circuit is always on and cannot be disabled by the user.

A wideband transformer, such as Mini-Circuits’ ADT1-1WT,

can provide the differential analog inputs for applications that

require a single-ended-to-differential conversion. Both analog

inputs are self-biased by an on-chip resistor divider to a

nominal 2.8 V (refer to the Equivalent Circuits section). Note

that the input common-mode can be overdriven by

approximately +/−150 mV around the self-bias point, as shown

in Figure 42.

Special care was taken in the design of the analog input section

of the AD9411 to prevent damage and corruption of data when

the input is overdriven. The nominal differential input range is

approximately 1.5 V p-p ~ (768 mV × 2). Note that the best

performance is achieved with S5 = 0 (full-scale = 1.5). See

Figure 40 and Figure 41.

The clock inputs are internally biased to 1.5 V (nominal) and

support either differential or single-ended signals. For best

dynamic performance, a differential signal is recommended. An

MC100LVEL16 performs well in the circuit to drive the clock

inputs, as illustrated in Figure 39. Note that for this low voltage

PECL device, the ac coupling is optional.

0.1F

AD9411

CLK+

S5 = GND

VIN+

PECL

GATE

CLK–

0.1F

510

768mV 2.8V

2.8V

Figure 39. Driving Clock Inputs with LVEL16

VIN–

DIGITALOUT = ALL 1s

DIGITALOUT = ALL 0s

Figure 40. Differential Analog Input Range

Rev. B | Page 18 of 28

Data Sheet

AD9411

providing a low skew clocking solution (see Figure 2). The on-

chip clock buffers should not drive more than 5 pF of capacitance

to limit switching transient effects on performance. The output

clocks are LVDS signals requiring 100 Ω differential termination

at receiver.

S5 = AVDD

VIN+

768mV 2.8V

2.8V

VOLTAGE REFERENCE

VIN– = 2.8V

A stable and accurate 1.23 V voltage reference is built into the

AD9411 (VREF). The analog input full-scale range is linearly

proportional to the voltage at VREF. Note that an external

reference can be used by connecting the SENSE pin to VDD

(disabling internal reference) and driving VREF with the

external reference source. No appreciable degradation in

performance occurs when VREF is adjusted 5%. A 0.1 μF

capacitor to ground is recommended at the VREF pin in

internal and external reference applications. Float the SENSE

pin for internal reference operation.

Figure 41. Single-Ended Analog Input Range

61

60

59

58

57

SINAD

FULL

SCALE

K

S5 = 0

S5 = 1

K = 1.24

K = 0.62

0.1F

VREF

A1

1V

EXTERNAL 1.23V

REFERENCE

200

56

2.0

2.2

2.4

2.6

2.8

3.0

3.2

SENSE

ANALOG INPUT COMMON MODE (V)

1k

3.3V

Figure 42. SINAD Sensitivity to Analog Input Common-Mode Voltage,

(Ain = −.5 dBfs Differential Drive, S5 = 0)

DISABLE

A1

VDD

LVDS OUTPUTS

Figure 43. Using an External Reference

The off-chip drivers provide LVDS compatible output levels. A

3.74 kΩ RSET resistor placed at Pin 7 (LVDSBIAS) to ground

sets the LVDS output current. The RSET resistor current is

ratioed on-chip, setting the output current at each output equal

to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential termi-

nation resistor placed at the LVDS receiver inputs results in a

nominal 350 mV swing at the receiver. LVDS mode facilitates

interfacing with LVDS receivers in custom ASICs and FPGAs

that have LVDS capability for superior switching performance

in noisy environments. Single point-to-point network topologies

are recommended with a 100 Ω termination resistor as close to

the receiver as possible. It is recommended to keep the trace

lengths < 4 inches and to keep differential output trace lengths

as equal as possible.

NOISE POWER RATIO TESTING (NPR)

NPR is a test that is commonly used to characterize the return

path of cable systems where the signals are typically QAM sig-

nals with a “noise-like” frequency spectrum. NPR performance

of the AD9411 was characterized in the lab yielding an effective

NPR = 51.2 dB at an analog input of 18 MHz. This agrees with a

theoretical maximum NPR of 51.6 dB for a 10-bit ADC at 13 dB

backoff. The rms noise power of the signal inside the notch is

compared with the rms noise level outside the notch using an

FFT. This test requires sufficiently long record lengths to

guarantee a large number of samples inside the notch. A high-

order band-stop filter that provides the required notch depth

for testing is also needed.

CLOCK OUTPUTS (DCO+, DCO–)

The input clock is buffered on-chip and available off-chip at

DCO+ and DCO–. These clocks can facilitate latching off-chip,

Rev. B | Page 19 of 28

AD9411

Data Sheet

3.3V

+

AVDD GND DRVDD GND

VDL GND

SIGNAL

GENERATOR

BAND-PASS

FILTER

ANALOG

J4

REFIN

DATA

CAPTURE

AND

AD9411 EVALUATION BOARD

PROCESSING

10MHz

CLOCK

J5

REFOUT

SIGNAL

GENERATOR

Figure 44. Evaluation Board Connections

Rev. B | Page 20 of 28

Data Sheet

AD9411

EVALUATION BOARD

The AD9411 evaluation board offers an easy way to test the

AD9411 in LVDS mode. It requires a clock source, an analog

input signal, and a 3.3 V power supply. The clock source is

buffered on the board to provide the clocks for the ADC,

latches, and a data-ready signal. The digital outputs and output

clocks are available at a 40-pin connector, P23. The board has

several different modes of operation and is shipped in the

following configurations:

GAIN

Full scale is set at E17–E19, E17–E18 sets S5 low, full scale =

1.5 V differential; E17–E19 sets S5 high, full scale = 0.75 V

differential. Best performance is obtained at 1.5 V full scale.

CLOCK

The clock input is terminated to ground through 50 Ω resistor

at SMB connector J5. The input is ac-coupled to a high speed

differential receiver (LVEL16) that provides the required low

jitter, fast edge rates needed for optimum performance. J5 input

should be > 0.5 V p-p. Power to the LVEL16 is set at Jumper

E47. E47–E45 powers the buffer from AVDD; E47–E46 powers

the buffer from VCLK/V_XTAL.



Offset binary

Internal voltage reference

Full-scale adjust = low

POWER CONNECTOR

VOLTAGE REFERENCE

Power is supplied to the board via a detachable 12-lead power

strip (three 4-pin blocks).

The AD9411 has an internal 1.23 V voltage reference. The ADC

uses the internal reference as the default when Jumpers E24–E27

and E25–E26 are left open. The full scale can be increased by

placing an optional resistor (R3). The required value varies with

the process and needs to be tuned for the specific application.

Full scale can similarly be reduced by placing R4; tuning is

required here as well. An external reference can be used by

shorting the SENSE pin to 3.3 V (place Jumper E26–E25).

Jumper E27–E24 connects the ADC VREF pin to the

EXT_VREF pin at the power connector.

Table 8. Power Connector, LVDS Mode

AVDD¹3.3 V

DRVDD¹3.3 V

VDL¹3.3 V

Analog Supply for ADC (350 mA)

Output Supply for ADC (50 mA)

Supply for Support Logic

VCLK/V_XTAL

EXT_VREF²

Supply for Clock Buffer/Optional XTAL

Optional External Reference Input

¹AVDD, DRVDD, and VDL are the minimum required power connections.

²LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper.

DATA FORMAT SELECT

ANALOG INPUTS

Data format select (DFS) sets the output data format of the

ADC. Setting DFS (E1–E2) low sets the output format to be

offset binary; setting DFS high (E1–E3) sets the output to twos

complement.

The evaluation board accepts a 1.3 V p-p analog input signal

centered at ground at SMB connector J4. This signal is

terminated to ground through 50 Ω by R16. The input can be

alternatively terminated at the T1 transformer secondary by

R13 and R14. T1 is a wideband RF transformer that provides a

single-ended-to-differential conversion, allowing the ADC to be

driven differentially, which minimizes even-order harmonics.

An optional second transformer, T2, can be placed following T1

if desired. This provides some performance advantage (~1 dB to

2 dB) for high analog input frequencies (>100 MHz). If T2 is

placed, cut the two shorting traces at the pads. The analog

signal can be low-pass filtered by R41, C12 and R42, C13 at the

ADC input. The footprint for transformer T2 can be modified

to accept a wideband differential amplifier (AD8351) for low

frequency applications where gain is required. See the PCB

schematic for more information.

DATA OUTPUTS

The ADC LVDS digital outputs are routed directly to the

connector at the card edge. Resistor pads placed at the output

connector allow for termination if the connector receiving logic

lack the differential termination for the data bits and DCO.

Each output trace pair should be terminated differentially at

the far end of the line with a single 100 ohm resistor.

CLOCK XTAL

An optional XTAL oscillator can be placed on the board to

serve as a clock source for the PCB. Power to the XTAL is

through the VCLK/VXTAL pin at the power connector. If an

oscillator is used, ensure proper termination for best results.

The board was tested with a Valpey Fisher VF561 and a Vectron

JN00158-163.84.

Rev. B | Page 21 of 28

AD9411

Data Sheet

Table 9. Evaluation Board Bill of Material—AD9411 PCB

No. Quantity

Reference Designator

Device

Package

Value

1

33

4

C1, C3*, C4–C11, C15–C17, C18*,

C19–C32, C35, C36, C39*, C40*, C58-C62

Capacitor

0603

0.1 μF

2

3

4

5

Capacitor

0402

0.1 μF

C33*, C34*, C37*, C38*

C63–C66

4

1

Capacitor

TAJD CAPL

0603

10 μF

10 pF

20 pF

C2*

2

C12*, C13*

0603

6

7

2

J4, J5

P21, P22

Jacks

SMB

25.602.5453.0

Wieland

Power Connectors—Top

8

9

2

1

P21, P22

P23

Power Connectors—Posts

Z5.531.3425.0

Wieland

Digi-Key

40-Pin Right Angle Connector

S2131-20-ND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

16

1

3

2

6

5

2

1

2

1

R1, R6–R12*, R15*, R31–R37*

Resistor

RF Transformer

0402

0603

0402

100

3.7 kΩ

50

R2

R5, R16, R27

R17, R18

510

150

1 kΩ

25

R19, R20

R29, R30

R41, R42

R3, R4

3.8 kΩ

25

R13, R14

R22*, R23*, R24*, R25*, R26*, R28*

100

25

R38*, R39*, R40*, R45*, R47*

R43*, R44*

10 kΩ

1.2 kΩ

0

R46*

R48*, R49*

R50*, R51*

1 kΩ

T1, T2*

Mini Circuits

ADT1-1WT

26

27

28

29

1

U2

U9

U1

U3

RF Amp

AD8351

Optional XTAL

AD9411

JN00158 or VF561

TQFP-100

MC100LVEL16

SO8NB

* C2, C3, C12, C13, C18, C33, C34, C37, C38, C39, C40, R1, R6–R12, R15, R22–R26, R28, R31–R40, R43–R51 and T2 not placed.

Rev. B | Page 22 of 28

Data Sheet

AD9411

7 6 – D 7

7 7 + D 7

5 0

D N C

4 9

D N C

7 8

4 8

D R G N D

–

D 8

G N D

7 9 + D 8

8 0 – D 9

8 1 + D 9

8 2

4 7

D D D R V

4 6

D N C

4 5

D N C

D R G N D

4 4

D N C

G N D

D D D R V

8 3

R D D V

D N C 4 3

4 2

8 4 – O R

D N C

A G N 4 1 D

4 0

8 5

8 6

8 7

O R +

G N D

A G N D

D D A V

D D A V 3 9

3 8

G N D

C V C

C

V C

C

V C

8 8 D D A V

8 9 D D A V

9 0 D D A V

A G N D

G N D

3 7

3 6

V C

– K C L

K + C L

N C ~ E

V C

G N D

V C

9 1

9 2

9 3

A G N D

3 5

A G N D

G N D

V C

A G N D

3 4

3 3

D D A V

C

D D A V

9 4

A G N 3 2 D

A G N 3 1 D

9 5 D D A V

V C

G N D

V C

G N D

V C

9 6

9 7

A G N D

3 0

A G N D

D D A V 2 9

C

9 8 D D A V

9 9 D D A V

2 8

D D A V

D D A V 2 7

2 6

V C

G N D

1 0 0

A G N D

G N D

P T M 1 C R O 4

P 2 1

P T M 1 C R O 4

P 2 2

Figure 45. Evaluation Board Schematic

Rev. B | Page 23 of 28

AD9411

Data Sheet

VCC

+

C64

10F

C23

0.1F

C22

0.1F

C25

0.1F

C24

0.1F

C27

0.1F

C26

0.1F

C29

0.1F

C28

0.1F

C31

0.1F

C16

0.1F

C17

0.1F

C32

0.1F

C35

0.1F

C19

0.1F

C21

0.1F

C20

0.1F

GND

VDL

DRVDD

VREF

+

C66

10F

+

C65

10F

C61

0.1F

C62

0.1F

C18

0.1F

C60

0.1F

C59

0.1F

C58

0.1F

C63

10F

GND

TO USE VF561 CRYSTAL

GND

VDL

R28

100

JN00158

R23

100

1

2

3

E/D

VCC

6

5

4

VDL

NC

OUTPUTB

OUTPUT

P4

R22

100

GND

R25

100

U9

GND

VDL

R24

100

P5

R26

100

GND

Figure 46. Evaluation Board Schematic (continued)

R51

1k

R50

1k

VDL

GND

VDL

POWER DOWN

USE R43 OR R44

C38

0.1F

C37

0.1F

VDL

GND

R43

10k

R44

10k

U2

AD8351

GND

R47

25k

R38

1

2

3

4

5

PWUP

VOCM 10

25k

C33

C39

R49

R39

RGP1

INHI

VPOS

OPHI

9

8

7

6

0.1F

0

25k

AMPINB

AMPIN

OPLO

INLO

C34

0.1F

R40

25k

C40

0.1F

R48

0

AMP IN

AMP

GND

RPG2

COMM

R45

25k

R46

1.2k

Figure 47. Evaluation Board Schematic (continued)

Rev. B | Page 24 of 28

Data Sheet

AD9411

Figure 50. PCB Ground Layer

Figure 48. PCB Top Side Silkscreen

Figure 51. PCB Split Power Plane

Figure 49. PCB Top Side Copper Routing

Rev. B | Page 25 of 28

AD9411

Data Sheet

Figure 52. PCB Bottom Side Copper Routing

Figure 53. PCB Bottom Side Silkscreen

Rev. B | Page 26 of 28

Data Sheet

AD9411

OUTLINE DIMENSIONS

16.00 BSC SQ

1.20

MAX

0.75

0.60

0.45

14.00 BSC SQ

100

1

76

75

76

100

75

1

SEATING

PLANE

PIN 1

BOTTOM VIEW

(PINS UP)

TOP VIEW

(PINS DOWN)

CONDUCTIVE

HEAT SINK

51

25

26

50

26

0.20

0.09

1.05

1.00

0.95

6.50

NOM

7°

3.5°

0°

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.15

0.05

COPLANARITY

0.08

0.27

0.22

0.17

0.50 BSC

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD

Figure 54. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-100)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

SV-100

AD9411BSVZ-170

AD9411BSVZ-200

–40°C to +85°C

100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

¹Z = RoHS Compliant Part.

Rev. B | Page 27 of 28

AD9411

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D04530-0-1/12(B)

Rev. B | Page 28 of 28

型号:	AD9430BST-170
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	QFP
包装说明：	HEAT SINK, PLASTIC, TQFP-100
针数：	100
Reach Compliance Code：	compliant
ECCN代码：	3A991.C.2
HTS代码：	8542.39.00.01
风险等级：	5.8
转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0
长度：	14 mm
最大线性误差 (EL)：	0.0122%
模拟输入通道数量：	1
位数：	12
功能数量：	1
端子数量：	100
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出位码：	OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：	PARALLEL, WORD
封装主体材料：	PLASTIC/EPOXY
封装代码：	HTFQFP
封装形状：	RECTANGULAR
封装形式：	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
采样速率：	170 MHz
采样并保持/跟踪并保持：	TRACK
座面最大高度：	1.2 mm
标称供电电压：	3.3 V
表面贴装：	YES
技术：	BICMOS
温度等级：	INDUSTRIAL
端子面层：	TIN LEAD
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm
Base Number Matches：	1

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