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  • AD9500BQ图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
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  • 深圳市芯脉实业有限公司

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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
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  • 深圳市得捷芯城科技有限公司

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  • 数量135 
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  • 北京顺科电子科技有限公司

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  • 集好芯城

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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
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  • 数量2500 
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  • 绿盛电子(香港)有限公司

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  • 数量2015 
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  • 深圳市恒益昌科技有限公司

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  • 深圳市晶美隆科技有限公司

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  • 深圳市赛尔通科技有限公司

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  • 深圳市卓越微芯电子有限公司

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  • 数量6500 
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  • 深圳市宏世佳电子科技有限公司

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  • 数量4675 
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  • 上海振基实业有限公司

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  • 数量73 
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  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
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  • 数量5800 
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  • 北京罗彻斯特电子科技有限公司

     该会员已使用本站18年以上
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  • 数量320 
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  • 深圳市一线半导体有限公司

     该会员已使用本站11年以上
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  • 数量15000 
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  • 深圳市隆鑫创展电子有限公司

     该会员已使用本站15年以上
  • AD9500BQ
  • 数量30000 
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  • 深圳市创思克科技有限公司

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  • AD9500BQ
  • 数量120 
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  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
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  • 数量20000 
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  • 深圳市晨豪科技有限公司

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  • 数量89630 
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  • 深圳市创芯联科技有限公司

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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • AD9500BQ
  • 数量69055 
  • 厂家AD 
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  • 批号2023+ 
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • AD9500BQ
  • 数量12300 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
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  • 数量15862 
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  • 批号23+ 
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  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • AD9500BQ
  • 数量12245 
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  • 深圳市晶美隆科技有限公司

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  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
  • AD9500BQ
  • 数量8000 
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  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • AD9500BQ
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  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
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  • 深圳市芯柏然科技有限公司

     该会员已使用本站7年以上
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  • 深圳市一线半导体有限公司

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产品型号AD9500BQ的概述

AD9500BQ芯片概述 AD9500BQ是一款高性能的时钟生成器,专为需要超高频率的应用而设计。该芯片具有出色的相位噪声特性和极低的抖动,使其在高速数字信号处理、无线通信、射频(RF)和视频应用等领域广泛使用。AD9500BQ的可编程功能允许用户通过简单的方式定制输出频率,兼容多种输入频率,满足当前市场对高精度时钟信号产生的需求。 该芯片采用先进的CMOS工艺,具有高集成度及多功能性,能够有效地优化PCB设计空间。此外,AD9500BQ的工作电压范围和广泛的温度稳定性使它适用于各种工业环境。其设计理念在于尽可能地降低系统复杂度,并提供灵活的调节机制。 AD9500BQ芯片的详细参数 AD9500BQ具备以下主要参数: - 工作电源电压(VDD): 2.5V至3.3V - 功耗(Quiescent Current): ≤ 200mA - 输出频率范围: 10MHz至1GHz - 输出负...

产品型号AD9500BQ的Datasheet PDF文件预览

Digitally Programmable  
Delay Generator  
a
AD9500  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
10 ps Delay Resolution  
C
EXT  
2.5 ns to 10 s Full-Scale Range  
Fully Differential Inputs  
ECL COMMON  
C
+V  
S
S
Separate Trigger and Reset Inputs  
Low Power Dissipation—310 mW  
MIL-STD-883 Compliant Versions Available  
AD9500  
TRIGGER  
DIFFERENTIAL  
ANALOG  
INPUT  
TIMING  
CONTROL  
CIRCUIT  
TRIGGER  
RESET  
Q
STAGE  
RESET  
APPLICATIONS  
ATE  
ECL  
VOLTAGE  
REFERENCE  
Q
Q
Pulse Deskewing  
ECL  
REF  
Arbitrary Waveform Generators  
High Stability Timing Source  
Multiple Phase Clock Generators  
INTERNAL DAC  
TTL LATCHES  
R
R
S
REFERENCE  
CURRENT  
R
SET  
GROUND  
LATCH OFFSET  
ENABLE ADJUST  
–V  
D
D
D
D
D
D
D D  
S
0
1
2
3
4
5 6 7  
(LSB)  
(MSB)  
–V  
S
GENERAL DESCRIPTION  
The AD9500 is a digitally programmable delay generator, which  
provides programmed delays, selected through an 8-bit digital  
code, in resolutions as small as 10 ps. The AD9500 is con-  
structed in a high performance bipolar process, designed to  
provide high speed operation for both digital and analog circuits.  
PIN CONFIGURATIONS  
D
D
D
D
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
3
2
4
5
D
6
D
D
1
0
The AD9500 employs differential TRIGGER and RESET  
inputs which are designed primarily for ECL signal levels but  
function with analog and TTL input levels. An onboard ECL  
reference midpoint allows both of the inputs to be driven by  
either single ended or differential ECL circuits. The AD9500  
output is a complementary ECL stage, which also provides a QR  
parallel output circuit to facilitate reset timing implementations.  
D
(MSB)  
(LSB)  
7
AD9500  
TOP VIEW  
ECL  
LATCH ENABLE  
GROUND  
REF  
OFFSET ADJUST  
(Not to Scale)  
R
S
C
S
–V  
S
+V  
S
ECL COMMON  
TRIGGER  
TRIGGER  
RESET  
Q
R
The digital control data is passed to the AD9500 through a  
transparent latch controlled by the LATCH ENABLE signal. In  
the transparent mode, the internal DAC of the AD9500 will  
attempt to follow changes at the inputs. The LATCH ENABLE  
is otherwise used to strobe the digital data into the AD9500  
latches.  
10  
11  
12  
Q
Q
RESET  
The AD9500 is available as an industrial temperature range  
device, –25°C to +85°C, and as an extended temperature range  
device, –55°C to +125°C. Both grades are packaged in a 24-lead  
cerdip (0.3" package width), as well as 28-leaded and leadless  
surface mount packages. The AD9500 is available in versions  
compliant with MIL-STD-883. Refer to the Analog Devices  
Military Products Databook or current AD9500/883B data  
sheet for detailed specifications.  
4
3
2
1
28 27 26  
5
25  
D
(MSB)  
D
(LSB)  
7
0
ECL  
6
7
24  
LATCH ENABLE  
REF  
23 GROUND  
AD9500  
OFFSET ADJUST  
NC  
8
22  
21  
NC  
TOP VIEW  
(Not to Scale)  
C
S
9
R
S
+V  
S
10  
–V  
20  
19  
S
TRIGGER  
11  
ECL COMMON  
12 13  
16 17 18  
14 15  
NC = NO CONNECT  
REV. D  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1999  
AD9500–SPECIFICATIONS  
ABSOLUTE MAXIMUM RATINGS1  
Digital Output Current (QR ) . . . . . . . . . . . . . . . . . . . . 2 mA  
Offset Adjust Current (Sinking) . . . . . . . . . . . . . . . . . . . 4 mA  
Operating Temperature Range  
AD9500BP/BQ . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C  
AD9500TE/TQ . . . . . . . . . . . . . . . . . . . . –55°C to +125°C  
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C  
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+175°C  
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C  
Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . . +7 V  
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . –7 V  
ECL COMMON to Ground Differential . . . . –2.0 V to +5.0 V  
Digital Input Voltage Range . . . . . . . . . . . . . –3.5 V to +5.0 V  
Trigger/Reset Input Voltage Range . . . . . . . . . . . . . . . ±5.0 V  
Trigger/Reset Differential Voltage . . . . . . . . . . . . . . . . . .5.0 V  
Minimum RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Ω  
Digital Output Current (Q and Q) . . . . . . . . . . . . . . . 30 mA  
ELECTRICAL CHARACTERISTICS2 (Supply Voltages +VS = +5.0 V, VS = –5.2 V; CEXT = 0 pF; RSET = 500 unless otherwise noted)  
–25؇C to +85؇C  
AD9500BP/BQ  
–55؇C to +125؇C  
AD9500TE/TQ  
Test  
Parameter  
Level Temp  
Min  
Typ  
Max  
Min  
Typ  
Max  
Units  
RESOLUTION  
8
8
Bits  
ACCURACY3  
Differential Linearity  
Integral Linearity  
Monotonicity  
I
I
I
+25°C  
+25°C  
+25°C  
0.5  
1.0  
0.5  
1.0  
LSB  
LSB  
Guaranteed  
Guaranteed  
DIGITAL INPUT  
Logic “1” Voltage  
Logic “0” Voltage  
Logic “1” Current  
Logic “0” Current  
Digital Input Capacitance  
Data Setup Time4  
Data Hold Time5  
VI  
VI  
VI  
VI  
VI  
V
Full  
Full  
Full  
Full  
+25°C  
+25°C  
+25°C  
+25°C  
2.0  
3.0  
2.0  
3.0  
V
V
0.8  
5
5
5.5  
0.75  
0.75  
0.8  
5
5
5.5  
0.75  
0.75  
µA  
µA  
pF  
ns  
ns  
ns  
0.4  
0.4  
0.4  
0.4  
V
V
Latch Pulsewidth (tLPW  
)
RESET/TRIGGER INPUTS6  
TRIGGER Input Voltage Range  
RESET Input Voltage Range  
Differential Switching Voltage  
Input Bias Current  
IV  
IV  
IV  
I
VI  
IV  
IV  
Full  
Full  
Full  
+25°C  
Full  
+25°C  
+25°C  
–2.5; 4.5  
–2.5; 2.0  
40  
–2.5; 4.5  
–2.5; 2.0  
40  
V
V
mV  
µA  
µA  
kΩ  
pF  
300  
50  
75  
300  
50  
75  
40  
40  
Input Resistance  
Input Capacitance  
Minimum Input Pulsewidth  
tTPW, tRPW  
4
6.5  
4
6.5  
7.25  
7.25  
V
+25°C  
2.0  
2.0  
ns  
DYNAMIC PERFORMANCE7  
Maximum Trigger Rate  
Minimum Propagation Delay (tPD  
Minimum Propagation Delay TC  
Full-Scale Range TC9  
IV  
I
V
V
V
I
IV  
IV  
V
I
+25°C  
+25°C  
Full  
60  
60  
MHz  
ns  
ps/°C  
ps/°C  
ps  
ns  
ns  
ns  
ns  
ns  
ns  
8
)
5.4  
6.4  
7.5  
0.5  
10  
6.4  
0
7.4  
7.4  
5.4  
6.4  
7.5  
0.5  
10  
6.4  
0
7.4  
7.4  
Full  
Delay Uncertainty (Jitter)  
Reset Propagation Delay (tRD  
+25°C  
+25°C  
+25°C  
+25°C  
+25°C  
+25°C  
+25°C  
+25°C  
+25°C  
10  
)
5.4  
0.2  
2.0  
5.4  
0.2  
2.0  
11  
Reset-to-Trigger Holdoff (tTHO  
Trigger-to-Reset Holdoff (tRHO  
Minimum Output Pulsewidth  
Output Rise Time7  
)
12  
)
1.5  
3.3  
1.5  
3.3  
2.0  
2.0  
2.0  
2.0  
Output Fall Time7  
I
V
V
13  
Delay Coefficient Settling Time (tDAC  
Linear Ramp Settling Time (tLRS  
)
29  
22  
29  
22  
ns  
ns  
)
–2–  
REV. D  
AD9500  
–25؇C to +85؇C  
–55؇C to +125؇C  
Test  
Level Temp  
AD9500BP/BQ  
AD9500TE/TQ  
Parameter  
Min  
Typ  
Max  
Min  
Typ  
Max  
Units  
SUPPORT FUNCTIONS  
ECLREF  
IV  
V
V
+25°C  
Full  
Full  
–1.4  
–1.1  
–1.3  
1.1  
–2  
–1.2  
–1.4  
–1.3  
1.1  
–2  
–1.2  
V
ECLREF Voltage Drift14  
Offset Adjust Range  
mV/°C  
mA  
DIGITAL OUTPUTS7  
Logic “1” Voltage  
Logic “0” Voltage  
VI  
VI  
Full  
Full  
–1.1  
V
V
–1.5  
–1.5  
POWER SUPPLY15  
Positive Supply Current (+5.0 V)  
I
VI  
I
VI  
V
+25°C  
Full  
+25°C  
Full  
24  
28  
30  
42  
44  
24  
28  
30  
42  
44  
mA  
mA  
mA  
mA  
mW  
Negative Supply Current (–5.2 V)  
37  
37  
Nominal Power Dissipation  
Power Supply Rejection Ratio16  
Full-Scale Range Sensitivity  
Minimum Propagation Delay  
Sensitivity  
+25°C  
312  
70  
312  
70  
I
I
+25°C  
+25°C  
300  
500  
300  
500  
ps/V  
ps/V  
150  
150  
NOTES  
1Absolute maximum ratings are limiting values, to be applied individually, and beyond which serviceability of the circuit may be impaired. Functional operability under  
any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.  
2Typical thermal impedance  
24-Lead Cerdip  
θJA = 56°C/W; θJC = 16°C/W  
θJA = 60°C/W; θJC = 22°C/W  
θJA = 69°C/W; θJC = 25°C/W  
28-Leadless PLCC (Plastic)  
28-Leaded Ceramic LCC  
3RSET = 10 k(Full-scale delay = 100 ns).  
4The digital data inputs must remain stable for the specified time prior to the LATCH ENABLE signal.  
5The digital data inputs must remain stable for the specified time after the LATCH ENABLE signal.  
6The TRIGGER and RESET inputs are differential and must be driven relative to one another. Both of these inputs are ECL compatible, but can also be used with  
TTL logic families in a limited fashion.  
7Outputs terminated through 50 resistors to –2.0 V.  
8Program Delay = 0.0 ps (Digital Data = 00H). In Operation, any programmed delays are in addition to the Minimum Propagation Delay.  
9Change in total delay through AD9500, exclusive of changes in minimum propagation delay tPD  
.
10Measured from the 50% transition point of the reset signal input, to the 50% transition point of the resetting output.  
11Minimum time from falling edge of RESET to triggering input, to ensure a valid output event.  
12Minimum time from triggering event to rising edge of RESET, to ensure a valid output event.  
13Measured from the LATCH ENABLE input to the point when the AD9500 becomes 8-bit accurate again, after a full-scale change in the programmed delay.  
14Standard 10K and 10KH ECL families operate with a 1.1 mV/°C drift by design.  
15Supply voltages should remain stable within ±5% for normal operation.  
16Measured at ± 5% of –VS and +VS.  
Specifications subject to change without notice.  
EXPLANATION OF TEST LEVELS  
ORDERING GUIDE  
Test Level  
Temperature  
Ranges  
Package  
Descriptions  
Package  
Options  
I
– 100% production tested.  
Model  
II – 100% production tested at +25°C, and sample tested at  
AD9500BP –25°C to +85°C 28-Leadless PLCC (Plastic),  
Industrial Temperature  
specified temperatures.  
P-28A  
Q-24  
AD9500BQ –25°C to +85°C 24-Lead Cerdip,  
Industrial Temperature  
AD9500TE –55°C to +125°C 28-Leaded LCC,  
Extended Temperature  
III – Periodically sample tested.  
IV – Parameter is guaranteed by design and characterization  
testing.  
E-28A  
Q-24  
AD9500TQ –55°C to +125°C 24-Lead Cerdip,  
V
– Parameter is a typical value only.  
Extended Temperature  
VI – All devices are 100% production tested at +25°C. 100%  
production tested at temperature extremes for extended  
temperature devices; sample tested at temperature ex-  
tremes for commercial/industrial devices.  
REV. D  
–3–  
AD9500  
PIN FUNCTION DESCRIPTIONS  
Pin Name  
D4–D6  
Description  
One of eight digital inputs used to set the programmed delay.  
D7 (MSB)  
One of eight digital inputs used to set the programmed delay. D7 (MSB) is the most significant bit of the  
digital input word.  
ECLREF  
ECL midpoint reference, nominally –1.3 V. Use of the ECLREF allows either of the TRIGGER or RESET  
inputs to be configured for single-ended ECL inputs.  
OFFSET ADJUST  
CS  
The OFFSET ADJUST is used to adjust the minimum propagation delay (tPD), by pulling or pushing a  
small current out of or into the pin.  
CS allows the full-scale range to be extended by using an external timing capacitor. The value of CEXT  
connected between CS and +VS, may range from no external capacitance to 0.1 µF+.  
See RS (CINTERNAL = 10 pF).  
,
+VS  
Positive supply terminal, nominally +5.0 V.  
TRIGGER  
Noninverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by  
the programmed delay, after the triggering event. The programmed delay is set by the digital input word.  
The TRIGGER input must be driven in conjunction with the TRIGGER input.  
TRIGGER  
RESET  
Inverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by the  
programmed delay, after the triggering event. The programmed delay is set by the digital input word. The  
TRIGGER input must be driven in conjunction with the TRIGGER input.  
Inverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a signal  
is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will be  
equal to the “reset propagation delay,” tRD. The RESET input must be driven in conjunction with the  
RESET input.  
RESET  
Noninverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a  
signal is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will  
be equal to the “reset propagation delay,” tRD. The RESET input must be driven in conjunction with the  
RESET input.  
Q
One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic HIGH on  
the Q output. A “resetting” event at the inputs will produce a logic LOW on the Q output.  
Q
One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic LOW on  
the Q output. A “resetting” event at the inputs will produce a logic HIGH on the Q output.  
output is parallel to the Q output. The output is typically used to drive delaying circuits for extend-  
QR  
QR  
QR  
ing output pulsewidths. A “triggering” event at the inputs will produce a logic LOW on the  
output. A  
QR  
“resetting” event at the inputs will produce a logic HIGH on the  
output.  
QR  
ECL COMMON  
The collector common for the ECL output stage. The collector common may be tied to +5.0 V, but nor-  
mally it is tied to the circuit ground for standard ECL outputs.  
–VS  
RS  
Negative supply terminal, nominally –5.2 V.  
RS is the reference current setting terminal. An external setting resistor, RSET, connected between RS and  
–VS determines the internal reference current. See CS (250 Ω ≤ RSET 50 k).  
GROUND  
The ground return for the TTL and analog inputs.  
LATCH ENABLE  
Transparent TTL latch control line. A logic HIGH on the LATCH ENABLE freezes the digital code at the  
logic inputs. A logic LOW on the LATCH ENABLE allows the internal current levels to be continuously  
updated through the logic inputs D0 thru D7.  
D0 (LSB)  
D3–D1  
One of eight digital inputs used to set the programmed delay. D0 (LSB) is the least significant bit of the  
digital input word.  
One of eight digital inputs used to set the programmed delay.  
REV. D  
–4–  
AD9500  
Figure 1. System Timing Diagram  
MECHANICAL INFORMATION  
DIE LAYOUT  
Die Dimensions . . . . . . . . . . . . . . . 104 ϫ 103 ϫ 18 (max) mils  
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . 4 ϫ 4 (min) mils  
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum  
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None  
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS  
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride  
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold Eutectic  
Bond Wire . . . . . . . . 1.25 mil, Aluminum; Ultrasonic Bonding  
or 1 mil, Gold; Gold Ball Bonding  
REV. D  
–5–  
AD9500  
Figure 2. Input/Output Circuits  
REV. D  
–6–  
AD9500  
INSIDE THE AD9500  
The heart of the AD9500 is the linear ramp generator. A trig-  
gering event at the input of the AD9500 initiates the ramp cycle.  
As the ramp voltage falls, it will eventually go below the thresh-  
old set up by the internal DAC (digital-to-analog converter). A  
comparator monitors both the linear ramp voltage and the DAC  
threshold level. The output of the comparator serves as the  
output for the AD9500, and the interval from the trigger until  
the output switches is the total delay time of the AD9500.  
The total delay through the AD9500 is made up of two compo-  
nents. The first is the full-scale programmed delay, tD (max)  
,
determined by RSET and CEXT. The second component of the  
total delay is the minimum propagation delay through the  
AD9500 (tPD). The full-scale delay is variable from 2.5 ns to  
greater than 1 ms. The internal DAC is capable of generating  
256 separate programmed delays within the full-scale range (this  
gives 10 ps increments for a 2.5 ns full-scale setting).  
The actual programmed delay is directly related to both the  
digital control data (digital data to the internal DAC) and the  
RC time constant established by RSET and CEXT. The specific  
relationship is as follows:  
Figure 4. Internal Timing Diagram  
Total Delay = Minimum Propagation Delay +  
Programmed Delay  
On resetting, the ramp voltage held in the timing capacitor  
(CEXT + 10 pF) is discharged. The AD9500 discharges the bulk  
of the ramp voltage very quickly, but to maintain absolute accu-  
racy, subsequent triggering events should be held off until after  
the linear ramp settling time (tLRS). Applications which employ  
high frequency triggering at a constant rate will not be affected  
by the slight settling errors since they will be constant for fixed  
reset-to-trigger cycles.  
= tPD + (digital value/256) RSET (CEXT + 10 pF)  
The RESET and TRIGGER inputs of the AD9500 are differen-  
tial and must be driven relative to one another. Accordingly, the  
TRIGGER and RESET inputs are ideally suited for analog or  
complementary input signals. Single-ended ECL input signals  
can be accommodated by using the ECL midpoint reference  
(ECLREF) to drive one side of the differential inputs.  
The output of the AD9500 consists of both Q and Q driver  
stages, as well as the QR output which is used primarily for  
extending the output pulsewidth. In the most direct reset con-  
figuration, either the Q or the Q output is tied to the respective  
RESET input. This generates a delayed output pulse with a  
duration equal to the reset delay time (tRD) of approximately  
6 ns. Note that the reset delay time (tRD) becomes extended for  
very small programmed delay settings. The duration of the  
output pulse can be extended by driving the reset inputs with the  
QR output through an RC network (see “Extended Output  
Pulsewidth” application). Using the QR output to drive the  
reset circuit avoids loading the Q or Q outputs.  
Figure 3. Typical Programmed Delay Ranges  
The internal DAC determines the programmed delay by way of  
the threshold level at its output. The LATCH ENABLE control  
for the onboard latch is active (latches) logic “HIGH.” In the  
logic “LOW” state, the latch is transparent, and the internal  
DAC will attempt to follow changes at the digital data inputs.  
Both the LATCH ENABLE control and the data inputs are  
TTL compatible. The internal DAC may be updated at any  
time, but full timing accuracy may not be attained unless trig-  
gering events are held off until after the DAC settling time  
(tDAC).  
Values in the specification table are based on 5 ns FSR test  
conditions. Nearly all dynamic specifications degrade for longer  
full scales. For details of performance change, request the appli-  
cation note “Using Digitally Programmable Delay Generators.”  
REV. D  
–7–  
AD9500  
APPLICATIONS  
the Q and the Q outputs are completely free for other uses. Q  
has limited current drive; the minimum resistance for RD should  
be 4 k.  
The AD9500 is a very versatile device that is not difficult to use.  
Essentially there are only a few basic configurations which can  
be extended into a number of applications. The TRIGGER and  
RESET inputs of the AD9500 can be treated as single ended, or  
as differential, which allows the AD9500 to operate with a wide  
range of signal sources. The output pulse from the AD9500 can  
be reset in one of two ways, either immediately by driving the  
RESET inputs with the output itself, or in a delayed mode.  
MINIMUM CONFIGURATION  
The minimum configuration uses only one of the TRIGGER  
inputs. The other is connected to the ECL reference midpoint,  
ECLREF. This allows the AD9500 to be triggered with standard  
10K or 10KH ECL signals. Once a triggering event occurs, the  
Q output will go into the logic HIGH state, and the Q output  
will go into the logic LOW state after the programmed delay.  
The Q output is then used to drive the RESET input, causing  
the AD9500 to reset itself. The result is a delayed output pulse  
which is only as wide as the reset propagation delay (tRD).  
Figure 6. Extended Output Pulsewidth Configuration  
MULTICHANNEL DESKEWING  
Perhaps the most appropriate use of the AD9500 is in multiple  
delay matching applications. Slight differences in impedance  
and cable length can create large timing skews within a high-  
speed system. Much of this skew can be eliminated by running  
each signal through an AD9500. With one line used as a stan-  
dard, the programmed delays of the other AD9500s are adjusted  
to eliminate the timing skews. With the very fine timing adjust-  
ments possible from the AD9500 (as small as 10 ps), nearly any  
high-speed system should be able to automatically adjust itself  
to extremely tight tolerances.  
Figure 5. Single Input–Minimum Timing Configuration  
EXTENDED OUTPUT PULSEWIDTHS  
The extended pulse configuration is similar to the minimum  
configuration. The difference here is that the output pulsewidth  
has been extended. Operation is identical in terms of triggering  
the AD9500; the functional difference is in the resetting circuit.  
In this case the  
output is used to drive the RESET input  
QR  
Figure 7. Multiple Delay Matching  
through a resistor/capacitor charging network. The charging  
network will cause the signal at the RESET input to fall more  
slowly, which will extend the output pulsewidth. An added  
benefit of the extended pulsewidth configurations is that both  
REV. D  
–8–  
AD9500  
MEASURING UNKNOWN DELAYS  
equals the DAC threshold. By varying the DAC threshold level  
and adjusting the second AD9500 programmed delay, a point  
by point reconstruction of the ac waveform can be created.  
Two AD9500s can be combined to measure delays with a high  
degree of precision. One AD9500 is set with little or no pro-  
grammed delay, and its output is used to drive the unknown  
delay circuit, which in turn drives the input of a “D” type flip-  
flop. The second AD9500 is triggered along with the first, and  
its output provides a clocking signal for the flip-flop. The pro-  
grammed delay of the second AD9500 is then varied to detect  
the output edge from the unknown delay circuit.  
Detecting the output edge is relatively straightforward. If the  
programmed delay through the second AD9500 is too long, the  
flip-flop output will be at logic HIGH. If, on the other hand, the  
programmed delay through the second AD9500 is too short, the  
flip-flop output will be at logic LOW. When the programmed  
delay is properly adjusted, the flip-flop will likely bounce be-  
tween logic HIGH and logic LOW. The digital code value used  
to create the second programmed delay is a direct indication of  
the delay through the unknown circuit. The most accurate re-  
sults can only be attained by calibrating the system without the  
unknown delay circuit in place.  
Figure 9. Measuring AC Waveforms  
PROGRAMMABLE OSCILLATOR  
Another interesting use of the AD9500 is in a digitally program-  
mable oscillator. The highly accurate delays generated by the  
AD9500 can be exploited to create a ring oscillator with variable  
duty cycle. The delayed output of the first AD9500 is used to  
drive the TRIGGER input of the second AD9500. The output  
of the second AD9500, in turn, is used to drive the TRIGGER  
input of the first AD9500. Together the two devices will alter-  
nately trigger each other creating two pulse chains on the outputs.  
The total delay through both AD9500s combined, determines  
the period of the oscillation frequency. The duty cycle can be  
controlled by using the outputs to drive the SET and RESET  
inputs of a flip-flop. The total delay through the first AD9500  
will control the flip-flop logic LOW output pulsewidth, and the  
second AD9500 will control the flip-flop logic HIGH output  
pulsewidth.  
Figure 8. Measuring Unknown Delays  
MEASURING HIGH SPEED AC WAVEFORMS  
The same circuitry used to measure unknown delays can be  
extended to measure the time response of high speed ac wave-  
forms. With the addition of a digital-to-analog converter and an  
analog comparator, the circuit functions very much like the  
previous application. The DAC sets a threshold level which  
drives one of the differential comparator inputs. The other com-  
parator input is driven by the device under test (DUT). The  
output of the first AD9500 causes the DUT to produce an  
output. The second AD9500, which is also triggered along with  
the first AD9500, strobes the comparator latch enable.  
Figure 10. Ring Oscillator  
If the DUT output is greater than the DAC threshold when the  
comparator is latched, the comparator output will be at logic  
HIGH. If the output is below the DAC threshold, the compara-  
tor will be at logic LOW. The programmed delay setting of the  
second AD9500 is adjusted to the point where the DUT output  
REV. D  
–9–  
AD9500  
LAYOUT CONSIDERATIONS  
GENERAL PERFORMANCE ENHANCEMENTS  
The AD9500 is a precision timing device, and as such high  
frequency design techniques must be employed to achieve the  
best performance. The use of a low impedance ground plane is  
particularly important. Ideally the ground plane should be on  
the component side of the layout and extend under the  
AD9500, to shield it from system timing signals. Sockets pose a  
special problem for a circuit like the AD9500 because of the  
additional inter-lead capacitance they create. If sockets must be  
used, pin sockets are generally preferred. Power supply decou-  
pling is also critical to a high-speed design; a 0.1 µF ceramic  
capacitor and a 0.01 µF mica capacitor for both power supplies  
should be very effective. DAC threshold stability can be improved  
by decoupling the OFFSET ADJUST pin to +5.0 V (note that this  
High speed operation is generally more consistent if CEXT is  
kept small (i.e., no external capacitor) to maintain small dis-  
charge time constants. Integral linearity, however, benefits from  
larger values of CEXT by buffering small system spikes and  
surges. Another means of improving integral linearity is to draw  
a small current (200 µA) out of the OFFSET ADJUST pin  
with a 47 kpull-down resistor. This has the effect of moving  
the internal DAC reference levels into a relatively more linear  
region of the ramp. This technique is generally only useful for  
small full-scale delay configurations. Its use with larger full-scale  
delays will extend the minimum propagation delay (tPD). A pull-  
up resistor to +5.0 V creates the opposite effect by reducing the  
minimum propagation delay (tPD) at the expense of increased  
reset propagation delay (tRD) and degraded linearity (see OFF-  
SET matching circuit).  
will lengthen the DAC settling time, tDAC  
)
DELAY OFFSET ADJUSTMENTS  
Caution should be used when applying high slew rate data at the  
inputs of the AD9500. For data inputs with slew rates in excess  
of 1 V/ns, a 100 series resistor should be utilized in the data  
path.  
As the full-scale delay is increased, a component of the mini-  
mum propagation delay also increases. This is caused by the  
additional time required by the ramp (now with a much “flatter”  
slope) to fall below the DAC threshold corresponding to the  
minimum propagation delay (tPD). One means of decreasing the  
minimum propagation delay (when the full-scale delay, set by  
RSET and CEXT is large) is to offset the internal DAC threshold  
toward the initial ramp levels, thus reducing the time for the  
internal ramp to cross the threshold once the AD9500 is triggered.  
An external DAC can be used with the AD9500 for increased  
resolution and higher update rates. For the most part, a stan-  
dard ECL DAC, operating between +5.0 V and ground, should  
work with the AD9500. The output of the external DAC must  
be connected to the OFFSET ADJUST pin of the AD9500 with  
the internal DAC turned off (D0 thru D7 at logic LOW). For  
normal operation, the external DAC output should range from  
0 mA to –2 mA (sinking).  
Figure 12. Operation with External DAC  
Figure 11. The Offset Adjust Pin Can Be Used to Match  
Several AD9500s  
The DAC levels are offset toward the initial ramp level by in-  
jecting a small current into the offset adjust pin. Note, however,  
that the ramp start-up region is less linear than the later portions  
of the ramp, which is the primary reason for the built-in offset.  
If the minimum propagation delay is kept above 5 ns (the linear  
portion of the ramp), no significant degradation in linearity  
should result. This concept can be extended to match the actual  
propagation delays of several AD9500s, by injecting or sinking  
a small current (<2 mA) into or out of each of the OFFSET  
ADJUST pins.  
REV. D  
–10–  
AD9500  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
24-Lead Cerdip  
(Q-24)  
0.005 (0.13) MIN  
0.098 (2.49) MAX  
13  
24  
0.310 (7.87)  
0.220 (5.59)  
1
12  
0.320 (8.13)  
0.290 (7.37)  
PIN 1  
0.060 (1.52)  
0.015 (0.38)  
1.280 (32.51) MAX  
0.200 (5.08)  
MAX  
0.150  
(3.81)  
MIN  
0.200 (5.08)  
0.125 (3.18)  
0.015 (0.38)  
0.008 (0.20)  
SEATING  
PLANE  
0.023 (0.58)  
0.014 (0.36)  
0.070 (1.78)  
0.030 (0.76)  
0.100 (2.54)  
BSC  
15°  
0°  
28-Leaded LCC  
(E-28A)  
0.300 (7.62)  
BSC  
0.150  
0.075  
(1.91)  
REF  
0.100 (2.54)  
0.064 (1.63)  
(3.51)  
BSC  
0.015 (0.38)  
MIN  
0.095 (2.41)  
0.075 (1.90)  
4
26  
28  
25  
5
0.028 (0.71)  
0.022 (0.56)  
0.458 (11.63)  
1
0.442 (11.23)  
SQ  
0.458  
0.011 (0.28)  
0.007 (0.18)  
R TYP  
BOTTOM  
VIEW  
(11.63)  
MAX  
SQ  
0.050  
(1.27)  
BSC  
12  
0.075  
(1.91)  
REF  
19  
18  
11  
45° TYP  
0.200  
(5.08)  
BSC  
0.055 (1.40)  
0.045 (1.14)  
0.088 (2.24)  
0.054 (1.37)  
28-Leadless PLCC  
(P-28A)  
0.180 (4.57)  
0.165 (4.19)  
0.048 (1.21)  
0.042 (1.07)  
0.056 (1.42)  
0.042 (1.07)  
0.025 (0.63)  
0.015 (0.38)  
0.048 (1.21)  
4
26  
25  
0.042 (1.07)  
5
PIN 1  
IDENTIFIER  
0.021 (0.53)  
0.013 (0.33)  
0.430 (10.92)  
0.390 (9.91)  
0.050  
(1.27)  
BSC  
TOP VIEW  
(PINS DOWN)  
0.032 (0.81)  
0.026 (0.66)  
11  
19  
12  
18  
SQ  
SQ  
0.020  
(0.50)  
R
0.040 (1.01)  
0.025 (0.64)  
0.456 (11.58)  
0.450 (11.43)  
0.495 (12.57)  
0.485 (12.32)  
0.110 (2.79)  
0.085 (2.16)  
REV. D  
–11–  
配单直通车
AD9500BQ产品参数
型号:AD9500BQ
是否Rohs认证: 不符合
生命周期:Obsolete
零件包装代码:DIP
包装说明:0.300 INCH, CERDIP-24
针数:24
Reach Compliance Code:not_compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.84
模拟集成电路 - 其他类型:ANALOG CIRCUIT
JESD-30 代码:R-GDIP-T24
JESD-609代码:e0
标称负供电电压 (Vsup):-5.2 V
功能数量:1
端子数量:24
最高工作温度:85 °C
最低工作温度:-25 °C
封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP
封装等效代码:DIP24,.3
封装形状:RECTANGULAR
封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED
电源:5,-5.2 V
认证状态:Not Qualified
座面最大高度:5.08 mm
子类别:Other Analog ICs
最大供电电流 (Isup):74 mA
最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V
表面贴装:NO
技术:BIPOLAR
温度等级:OTHER
端子面层:TIN LEAD
端子形式:THROUGH-HOLE
端子节距:2.54 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mm
Base Number Matches:1
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