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  • 深圳市华斯顿电子科技有限公司

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  • 深圳市晶美隆科技有限公司

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  • 深圳市集创讯科技有限公司

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  • 深圳市华斯顿电子科技有限公司

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  • 数量1200 
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  • 深圳市和诚半导体有限公司

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  • 数量5600 
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  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
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  • 数量7536 
  • 厂家Analog Devices Inc. 
  • 封装32-LFCSP-VQ(5x5) 
  • 批号23+ 
  • 数模转换器DAC原装现货
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  • 深圳市捷立辉科技有限公司

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  • 厂家ADI/亚德诺 
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
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  • 厂家ADI/亚德诺 
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  • 深圳市原力达电子有限公司

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  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
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  • 数量7500 
  • 厂家ADI 
  • 封装LFCSP32 
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  • 深圳市科庆电子有限公司

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  • 深圳市双微电子科技有限公司

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  • 北京元坤伟业科技有限公司

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  • 数量5000 
  • 厂家ANALOGDE 
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
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  • 数量
  • 厂家ADI 
  • 封装32-Lead LFCSP (5mm x 5mm w/ EP) 
  • 批号新批次 
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
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  • 数量8348 
  • 厂家ADI(亚德诺) 
  • 封装LFCSP 
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • AD9707BCPZ
  • 数量3817 
  • 厂家ADI 
  • 封装32-LFCSP 
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • AD9707-EBZ
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  • 数量44990 
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     该会员已使用本站7年以上
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  • 数量8800 
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     该会员已使用本站14年以上
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     该会员已使用本站17年以上
  • AD9707BCPZ
  • 数量21147 
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  • 封装32-Lead LFCSP 
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  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • AD9707BCPZ
  • 数量3300 
  • 厂家ADI/亚德诺 
  • 封装 
  • 批号2020+ 
  • 绝对全新原装,一片也是批量价.
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产品型号AD9707的Datasheet PDF文件预览

8-/10-/12-/14-Bit, 175 MSPS TxDAC  
Digital-to-Analog Converters  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
The AD9704/AD9705/AD9706/AD9707 has an optional serial  
peripheral interface (SPI®) that provides a higher level of program-  
mability to enhance performance of the DAC. An adjustable  
output, common-mode feature allows for easy interfacing to other  
components that require common modes from 0 V t o 1. 2 V.  
FEATURES  
175 MSPS update rate  
Low power member of pin-compatible  
TxDAC product family  
Low power dissipation  
Edge-triggered input latches and a 1.0 V temperature-compensated  
band gap reference have been integrated to provide a complete,  
monolithic DAC solution. The digital inputs support 1.8 V and  
3.3 V CMOS logic families.  
12 mW at 80 MSPS, 1.8 V  
50 mW at 175 MSPS, 3.3 V  
Wide supply voltage: 1.7 V to 3.6 V  
SFDR to Nyquist  
AD9707: 84 dBc at 5 MHz output  
AD9707: 83 dBc at 10 MHz output  
AD9707: 75 dBc at 20 MHz output  
Adjustable full-scale current outputs: 1 mA to 5 mA  
On-chip 1.0 V reference  
PRODUCT HIGHLIGHTS  
1. Pin Compatible. The AD9704/AD9705/AD9706/AD9707  
line of TxDAC® converters is pin-compatible with the  
AD9748/AD9740/AD9742/AD9744 TxDAC line (LFCSP  
package).  
CMOS-compatible digital interface  
Common-mode output: adjustable 0 V to 1.2 V  
Power-down mode <2 mW at 3.3 V (SPI controllable)  
Self-calibration  
2. Low Power. Complete CMOS DAC operates on a single  
supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V)  
and 12 mW (1.8 V). The DAC full-scale current can be  
reduced for lower power operation. Sleep and power-down  
modes are provided for low power idle periods.  
3. Self-Calibration. Self-calibration enables true 14-bit INL  
and DNL performance in the AD9707.  
Compact 32-lead LFCSP, RoHS compliant package  
GENERAL DESCRIPTION  
The AD9704/AD9705/AD9706/AD9707 are the fourth-generation  
family in the TxDAC series of high performance, CMOS digital-to-  
analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit  
resolution family is optimized for low power operation, while  
maintaining excellent dynamic performance. The AD9704/  
AD9705/AD9706/AD9707 family is pin-compatible with the  
AD9748/AD9740/AD9742/AD9744 family of TxDAC converters  
and is specifically optimized for the transmit signal path of  
communication systems. All of the devices share the same  
interface, LFCSP package, and pinout, providing an upward or  
downward component selection path based on performance,  
resolution, and cost. The AD9704/AD9705/AD9706/AD9707  
offers exceptional ac and dc performance, while supporting  
update rates up to 175 MSPS.  
4. Twos Complement/Binary Data Coding Support. Data  
input supports twos complement or straight binary data  
coding.  
5. Flexible Clock Input. A selectable high speed, single-ended,  
and differential CMOS clock input supports 175 MSPS  
conversion rate.  
6. Device Configuration. Device can be configured through  
pin strapping, and SPI control offers a higher level of  
programmability.  
7. Easy Interfacing to Other Components. Adjustable  
common-mode output allows for easy interfacing to other  
signal chain components that accept common-mode levels  
from 0 V to 1.2 V.  
8. On-Chip Voltage Reference. The AD9704/AD9705/AD9706/  
AD9707 include a 1.0 V temperature-compensated band  
gap voltage reference.  
The flexible power supply operating range of 1.7 V to 3.6 V and low  
power dissipation of the AD9704/AD9705/AD9706/AD9707 parts  
make them well suited for portable and low power applications.  
9. Industry-Standard 32-Lead LFCSP Package.  
Power dissipation of the AD9704/AD9705/AD9706/AD9707 can  
be reduced to 15 mW, with a small trade-off in performance, by  
lowering the full-scale current output. In addition, a power-down  
mode reduces the standby power dissipation to approximately  
2.2 mW.  
Rev. D  
Document Feedback  
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
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Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2006–2017 Analog Devices, Inc. All rights reserved.  
Technical Support  
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AD9704/AD9705/AD9706/AD9707  
Data Sheet  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Terminology.................................................................................... 29  
Theory of Operation ...................................................................... 30  
Serial Peripheral Interface......................................................... 30  
SPI Register Map ........................................................................ 32  
SPI Register Descriptions.......................................................... 33  
Reference Operation.................................................................. 34  
Reference Control Amplifier .................................................... 34  
DAC Transfer Function............................................................. 35  
Analog Outputs .......................................................................... 35  
Adjustable Output Common Mode......................................... 36  
Digital Inputs .............................................................................. 36  
Clock Input.................................................................................. 36  
DAC Timing................................................................................ 36  
Power Dissipation....................................................................... 37  
Self-Calibration........................................................................... 38  
Applications Information.............................................................. 40  
Output Configurations.............................................................. 40  
Differential Coupling Using a Transformer ............................... 40  
Single-Ended Buffered Output Using an Op Amp................ 40  
Differential Buffered Output Using an Op Amp ................... 41  
Evaluation Board........................................................................ 41  
Outline Dimensions....................................................................... 42  
Ordering Guide .......................................................................... 42  
General Description......................................................................... 1  
Product Highlights ........................................................................... 1  
Revision History ............................................................................... 2  
Functional Block Diagram .............................................................. 4  
Specifications..................................................................................... 5  
DC Specifications (3.3 V)............................................................ 5  
Dynamic Specifications (3.3 V).................................................. 6  
Digital Specifications (3.3 V)...................................................... 7  
DC Specifications (1.8 V)............................................................ 8  
Dynamic Specifications (1.8 V).................................................. 9  
Digital Specifications (1.8 V).................................................... 10  
Timing Diagram ......................................................................... 10  
Absolute Maximum Ratings.......................................................... 11  
Thermal Characteristics ............................................................ 11  
ESD Caution................................................................................ 11  
Pin Configurations and Function Descriptions ......................... 12  
AD9707........................................................................................ 12  
AD9706........................................................................................ 13  
AD9705........................................................................................ 14  
AD9704........................................................................................ 15  
Typical Performance Characteristics ........................................... 16  
AD9707......................................................................................... 16  
AD9704, AD9705 and AD9706.................................................. 23  
REVISION HISTORY  
11/2017—Rev. C to Rev. D  
Changes to Table 2.............................................................................6  
Changes to Table 4.............................................................................8  
Changes to Table 5.............................................................................9  
Changes to Figure 3 and Table 9................................................... 12  
Changes to Figure 4 and Table 10................................................. 13  
Changes to Figure 5 and Table 11................................................. 14  
Changes to Figure 6 and Table 12................................................. 15  
Changes to Figure 15 and Figure 16............................................. 17  
Moved Figure 41 to Figure 24 Position........................................ 18  
Moved Figure 42 to Figure 25 Position and Moved Figure 43 to  
Figure 26 Position........................................................................... 19  
Changes to Figure 27...................................................................... 20  
Changes to Figure 33 to Figure 35................................................ 21  
Moved Figure 24 to Figure 41 Position........................................ 22  
Moved Figure 25 to Figure 43 Position and Moved Figure 26 to  
Figure 44 Position........................................................................... 23  
Changes to Figure 44...................................................................... 23  
Changes to Figure 57...................................................................... 26  
Changed CP-32-7 to CP-32-2 ...................................... Throughout  
Updated Outline Dimensions....................................................... 42  
Changes to Ordering Guide .......................................................... 42  
9/2017—Rev. B to Rev. C  
Changed CP-32-2 to CP-32-7 ...................................... Throughout  
Changes to Table 9.......................................................................... 12  
Changes to Table 10........................................................................ 13  
Changes to Table 11........................................................................ 14  
Changes to Table 12........................................................................ 15  
Changes to Reference Operation Section.................................... 34  
Updated Outline Dimensions....................................................... 42  
Changes to Ordering Guide .......................................................... 42  
10/2011—Rev. A to Rev. B  
Changes to Features Section............................................................ 1  
Changes to Table 1............................................................................ 5  
Rev. D | Page 2 of 42  
 
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
Changes to Figure 44 ......................................................................23  
Changes to Figure 57 ......................................................................26  
Changes to Figure 70 ......................................................................29  
Changes to Serial Peripheral Interface Section ...........................30  
Changes to Table 15 ........................................................................32  
Deleted Table 23; Renumbered Sequentially...............................33  
Changes to Reference Operation Section and Reference Control  
Amplifier Section ............................................................................34  
Changes to Adjustable Output Common Mode Section and  
DAC Timing Section.......................................................................36  
Added the Deskew Mode Section.................................................36  
Deleted Figure 80; Renumbered Sequentially .............................36  
Changed Sleep and Power-Down Operation (Pin Mode) Section  
to Sleep Operation (Pin Mode) Section .......................................38  
Changes to Sleep Operation (Pin Mode) Section .......................38  
Changes to Self-Calibration Section.............................................39  
Changes to Evaluation Board Section ..........................................41  
Added Exposed Pad Notation to Outline Dimensions ..............42  
Changes to Ordering Guide...........................................................42  
Deleted Evaluation Board Schematics Section............................43  
Deleted Figure 92 to Figure 102 ....................................................43  
4/2007—Rev. 0 to Rev. A  
Changes to Features List...................................................................1  
Changes to Product Highlights .......................................................1  
Changes to General Description.....................................................3  
Changes to Table 3 ............................................................................6  
Changes to Table 4 ............................................................................7  
Changes to Table 6 ............................................................................9  
Changes to Figure 17 and Figure 18.............................................16  
Deleted Figure 29, Renumbered Sequentially.............................19  
Changes to Figure 44 ......................................................................22  
Changes to Figure 57 Caption .......................................................25  
Changes to Figure 73, Figure 75, and Figure 77..........................31  
Changes to Table 16 ........................................................................32  
Replaced Single-Ended Buffered Output Using an Op  
Amp Section ....................................................................................40  
Changes to Figure 91 ......................................................................41  
Changes to Figure 93 ......................................................................44  
Changes to Figure 96 ......................................................................47  
7/2006—Revision 0: Initial Version  
Rev. D | Page 3 of 42  
AD9704/AD9705/AD9706/AD9707  
FUNCTIONAL BLOCK DIAGRAM  
Data Sheet  
1.7V TO 3.6V  
AVDD  
ACOM  
1.0V REF  
0.1µF  
AD9707  
REFIO  
CURRENT  
SOURCE  
ARRAY  
OTCM  
FS ADJ  
1.7V  
CLKVDD  
IOUTA  
IOUTB  
R
SET  
TO  
SEGMENTED  
SWITCHES  
LSB  
SWITCHES  
3.6V  
CLKCOM  
CLK+  
CLK–  
PIN/SPI/RESET  
MODE/SDIO  
LATCHES  
SPI  
1.7V TO  
3.6V  
CMODE/SCLK  
DVDD  
DCOM  
SLEEP/CSB  
DIGITAL INPUTS (DB13 TO DB0)  
Figure 1.  
Rev. D | Page 4 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
SPECIFICATIONS  
DC SPECIFICATIONS (3.3 V)  
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.  
Table 1.  
AD9707  
Typ  
AD9706  
Typ  
AD9705  
Typ  
AD9704  
Typ  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
RESOLUTION  
DC ACCURACY1  
14  
12  
10  
8
Bits  
Integral Nonlinearity (INL)  
Precalibration  
1.4  
0.9  
1.2  
0.4  
6.0  
0.41  
0.30  
0.35  
0.13  
1.48  
0.10  
0.10  
0.09  
0.03  
0.36  
0.03  
0.02  
0.09 LSB  
LSB  
Integral Nonlinearity (INL)  
Postcalibration  
Differential Nonlinearity  
(DNL) Precalibration  
4.4  
1.17  
0.31  
0.08 LSB  
LSB  
Differential Nonlinearity  
(DNL) Postcalibration  
ANALOG OUTPUT  
Offset Error  
−0.03  
−2.7  
0
+0.03 −0.03  
0
+0.03 −0.03  
0
+0.03 −0.03  
0
+0.03 % of FSR  
Gain Error (With External  
Reference  
−0.1  
+2.7  
−2.7  
−0.1  
+2.7  
−2.7  
−0.1  
+2.7  
−2.7  
−0.1  
+2.7  
% of FSR  
Gain Error (With Internal  
Reference)  
Full-Scale Output Current2  
−2.7  
−0.1  
2
+2.7  
−2.7  
−0.1  
2
+2.7  
−2.7  
−0.1  
2
+2.7  
−2.7  
−0.1  
2
+2.7  
% of FSR  
1
5
1
5
1
5
1
5
mA  
V
Output Compliance Range  
(From OTCM to  
IOUTA/IOUTB)  
−0.8  
+0.8  
−0.8  
+0.8  
−0.8  
+0.8  
−0.8  
+0.8  
Output Resistance  
Output Capacitance  
REFERENCE OUTPUT  
Reference Voltage  
200  
5
200  
5
200  
5
200  
5
MΩ  
pF  
0.98  
0.1  
1.025 1.08  
100  
0.98  
0.1  
1.025 1.08  
100  
0.98  
0.1  
1.025 1.08  
100  
0.98  
0.1  
1.025 1.08  
100  
V
Reference Output Current3  
nA  
REFERENCE INPUT  
Input Compliance Range  
1.25  
10  
1.25  
10  
1.25  
10  
1.25  
10  
V
Reference Input Resistance  
(Reference Powered Up)  
kΩ  
Reference Input Resistance  
(Reference Powered Down)  
1
1
1
1
MΩ  
TEMPERATURE COEFFICIENTS  
Offset Drift  
0
0
0
0
ppm of  
FSR/°C  
Gain Drift (Without Internal  
Reference)  
29  
40  
25  
29  
40  
25  
29  
40  
25  
29  
40  
25  
ppm of  
FSR/°C  
Gain Drift (With Internal  
Reference)  
ppm of  
FSR/°C  
Reference Voltage Drift  
POWER SUPPLY  
Supply Voltage  
AVDD  
ppm/°C  
3.3  
3.6  
3.6  
3.6  
6.7  
6.6  
4.7  
57  
3.3  
3.6  
3.6  
3.6  
6.7  
6.6  
4.7  
57  
3.3  
3.6  
3.6  
3.6  
6.7  
6.6  
4.7  
57  
3.3  
3.6  
3.6  
3.6  
6.7  
6.6  
4.7  
57  
V
DVDD  
3.3  
3.3  
3.3  
3.3  
V
CLKVDD  
3.3  
3.3  
3.3  
3.3  
V
Analog Supply Current (IAVDD  
)
5.2  
5.2  
5.1  
5.1  
mA  
mA  
mA  
mW  
mA  
4
Digital Supply Current (IDVDD  
)
5.9  
5.4  
5.0  
4.6  
4
4.1  
4.1  
4.1  
4.1  
Clock Supply Current (ICLKVDD  
Power Dissipation4  
Supply Current Sleep Mode  
(IAVDD  
)
50.2  
0.37  
48.5  
0.37  
46.9  
0.37  
45.5  
0.37  
0.4  
0.4  
0.4  
0.4  
)
Rev. D | Page 5 of 42  
 
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
AD9707  
AD9706  
Typ  
AD9705  
Typ  
AD9704  
Typ  
Parameter  
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Supply Current Power-Down  
0.7  
7.5  
0.7  
7.5  
0.7  
7.5  
0.7  
7.5  
µA  
Mode (IAVDD  
)
Supply Current Clock Power-  
0.6  
1
0.6  
1
0.6  
1
0.6  
1
mA  
µA  
5
Down Mode (IDVDD  
)
Supply Current Clock Power-  
42.5  
64  
42.5  
64  
42.5  
64  
42.5  
64  
5
Down Mode (ICLKVDD  
)
Power Supply Rejection Ratio −0.2  
(AVDD)6  
+0.03 +0.2  
+85  
−0.2  
−40  
+0.03 +0.2  
+85  
−0.2  
−40  
+0.03 +0.2  
+85  
−0.2  
−40  
+0.03 +0.2  
+85  
% of  
FSR/V  
OPERATING RANGE  
−40  
°C  
1 Measured at IOUTA, driving a virtual ground.  
2 Normal full scale current, IOUTFS is 32 × the IREF current.  
3 Use an external buffer amplifier with an input bias current <100 nA to drive any external load.  
4 Measured at fCLOCK = 175 MSPS and fOUT = 1.0 MHz, using a differential clock.  
5 Measured at fCLOCK = 100 MSPS and fOUT = 1.0 MHz, using a differential clock.  
6
5% power supply variation.  
DYNAMIC SPECIFICATIONS (3.3 V)  
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, differential transformer coupled output, 453 Ω differentially  
terminated unless otherwise noted.  
Table 2.  
AD9707  
Min Typ  
AD9706  
Max Min Typ  
AD9705  
Max Min Typ  
AD9704  
Max Min Typ  
Parameter  
Max Unit  
DYNAMIC PERFORMANCE  
Maximum Output Update Rate, fCLOCK  
Output Settling Time, tST (to 0.1%)1  
Output Propagation Delay, tPD  
Glitch Impulse  
Output Rise Time (10% to 90%)1  
Output Fall Time (10% to 90%)1  
AC LINEARITY  
175  
175  
175  
175  
MSPS  
ns  
11  
4
11  
4
11  
4
11  
4
ns  
5
5
5
5
pV-s  
ns  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
ns  
Spurious-Free Dynamic Range to  
Nyquist  
fCLOCK = 10 MSPS, fOUT = 2.1 MHz  
fCLOCK = 25 MSPS, fOUT = 2.1 MHz  
fCLOCK = 65 MSPS, fOUT = 5.1 MHz  
fCLOCK = 65 MSPS, fOUT = 10.1 MHz  
fCLOCK = 80 MSPS, fOUT = 1.0 MHz  
fCLOCK = 125 MSPS, fOUT = 15.1 MHz  
fCLOCK = 125 MSPS, fOUT = 25.1 MHz  
fCLOCK = 175 MSPS, fOUT = 20.1 MHz  
fCLOCK = 175 MSPS, fOUT = 40.1 MHz  
Noise Spectral Density  
84  
84  
84  
83  
83  
78  
77  
75  
72  
84  
83  
84  
83  
82  
78  
77  
75  
71  
84  
84  
84  
83  
82  
78  
76  
75  
71  
70  
68  
70  
71  
70  
68  
69  
69  
67  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
74  
72  
72  
66  
fCLOCK = 175 MSPS, fOUT = 6.0 MHz,  
OUTFS = 2 mA  
−152  
−161  
−146  
−152  
−144  
−136  
dBc/Hz  
dBc/Hz  
dBc/Hz  
I
fCLOCK = 175 MSPS, fOUT = 6.0 MHz,  
IOUTFS = 5 mA  
fCLOCK = 175 MSPS, fOUT = 6.0 MHz,  
OUTFS = 1 mA  
I
1 Measured single-ended into 500 Ω load.  
Rev. D | Page 6 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
DIGITAL SPECIFICATIONS (3.3 V)  
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.  
Table 3.  
AD9707  
AD9706  
AD9705  
AD9704  
Parameter  
DIGITAL INPUTS1  
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit  
Logic 1 Voltage  
2.1  
3
0
2.1  
3
0
2.1  
3
0
2.1  
3
0
V
Logic 0 Voltage  
0.9  
+10  
10  
0.9  
+10  
10  
0.9  
+10  
10  
0.9  
+10  
10  
V
Logic 1 Current  
−10  
−10  
−10  
−10  
µA  
µA  
pF  
ns  
ns  
ns  
ns  
ns  
Logic 0 Current  
Input Capacitance  
5
5
5
5
Input Setup Time, tS, +25°C  
Input Hold Time, tH, +25°C  
Input Setup Time, tS, −40°C to +85°C  
Input Hold Time, tH, −40°C to +85°C  
Latch Pulse Width, tLPW  
CLK INPUTS2  
1.4  
0.3  
1.6  
0.6  
2.8  
1.4  
0.3  
1.6  
0.6  
2.8  
1.4  
0.3  
1.6  
0.6  
2.8  
1.4  
0.3  
1.6  
0.6  
2.8  
Input Voltage Range  
Common-Mode Voltage  
Differential Voltage  
0
3
0
3
0
3
0
3
V
V
V
0.75 1.5  
0.5 1.5  
2.25  
0.75 1.5  
0.5 1.5  
2.25  
0.75 1.5  
0.5 1.5  
2.25  
0.75 1.5  
0.5 1.5  
2.25  
1 Includes CLK+ pin in single-ended clock input mode.  
2 Applicable to CLK+ input and CLK− input when configured for differential clock input mode.  
Rev. D | Page 7 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
DC SPECIFICATIONS (1.8 V)  
TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 2 mA, unless otherwise noted.  
Table 4.  
AD9707  
Typ  
AD9706  
Typ  
AD9705  
Typ  
AD9704  
Typ  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
RESOLUTION  
DC ACCURACY1  
14  
12  
10  
8
Bits  
Integral Nonlinearity (INL)  
Precalibration  
1.4  
1.2  
6.03  
4.34  
0.42  
0.36  
1.50  
1.17  
0.10  
0.09  
0.36  
0.30  
0.03  
0.02  
0.09 LSB  
0.07 LSB  
Differential Nonlinearity  
(DNL) Precalibration  
ANALOG OUTPUT  
Offset Error  
−0.03  
−2.7  
0
+0.03 −0.03  
0
+0.03 −0.03  
0
+0.03 −0.03  
0
+0.03 % of FSR  
Gain Error (With Internal  
Reference)  
−0.2  
+2.7  
−2.7  
−0.2  
+2.7  
−2.7  
−0.2  
+2.7  
−2.7  
−0.2  
+2.7  
% of FSR  
Full-Scale Output Current2  
1
2
2.5  
1
2
2.5  
1
2
2.5  
1
2
2.5  
mA  
V
Output Compliance Range  
(With OTCM = AGND)  
−0.8  
+0.8  
−0.8  
+0.8  
−0.8  
+0.8  
−0.8  
+0.8  
Output Resistance  
Output Capacitance  
REFERENCE OUTPUT  
Reference Voltage  
200  
5
200  
5
200  
5
200  
5
MΩ  
pF  
0.98  
0.1  
1.025 1.08  
100  
0.98  
0.1  
1.025 1.08  
100  
0.98  
0.1  
1.025 1.08  
100  
0.98  
0.1  
1.025 1.08  
100  
V
Reference Output Current3  
nA  
REFERENCE INPUT  
Input Compliance Range  
1.25  
10  
1.25  
10  
1.25  
10  
1.25  
10  
V
Reference Input Resistance  
(Reference Powered Up)  
kΩ  
Reference Input Resistance  
(External Reference)  
1
1
1
1
MΩ  
TEMPERATURE COEFFICIENTS  
Offset Drift  
0
0
0
0
ppm of  
FSR/°C  
Gain Drift (Without Internal  
Reference)  
30  
60  
25  
30  
60  
25  
30  
60  
25  
30  
60  
25  
ppm of  
FSR/°C  
Gain Drift (With Internal  
Reference)  
ppm of  
FSR/°C  
Reference Voltage Drift  
POWER SUPPLY  
Supply Voltage  
AVDD  
ppm/°C  
1.7  
1.7  
1.7  
1.8  
1.8  
1.8  
1.7  
1.7  
1.7  
1.8  
1.8  
1.8  
1.7  
1.7  
1.7  
1.8  
1.8  
1.8  
1.7  
1.7  
1.7  
1.8  
1.8  
1.8  
V
DVDD  
V
CLKVDD  
V
Analog Supply Current  
3.8  
1.3  
1.3  
4.8  
1.5  
1.5  
3.8  
1.2  
1.3  
4.8  
1.5  
1.5  
3.8  
1.1  
1.3  
4.8  
1.5  
1.5  
3.8  
1.0  
1.3  
4.8  
1.5  
1.5  
mA  
4
(IAVDD  
)
Digital Supply Current  
mA  
mA  
4
5
,
(IDVDD  
)
Clock Supply Current  
4 5  
,
(ICLKVDD  
)
Power Dissipation4 5  
,
11.5  
0.3  
13.2  
0.4  
11.3  
0.3  
13.2  
0.4  
11.1  
0.3  
13.2  
0.4  
11.0  
0.3  
13.2  
0.4  
mW  
mA  
Supply Current Sleep Mode  
(IAVDD  
Supply Current Power-Down  
Mode (IAVDD  
Supply Current Clock Power-  
)
5
6
5
6
5
6
5
6
µA  
mA  
µA  
)
0.22  
9.5  
0.28  
16  
0.22  
9.5  
0.28  
16  
0.22  
9.5  
0.28  
16  
0.22  
9.5  
0.28  
16  
5
Down Mode (IDVDD  
)
Supply Current Clock Power-  
5
Down Mode (ICLKVDD  
)
Rev. D | Page 8 of 42  
 
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
AD9707  
Typ  
AD9706  
Typ  
AD9705  
Typ  
AD9704  
Typ  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Power Supply Rejection  
Ratio (AVDD)6  
−2  
−0.1  
+2  
−2  
−0.1  
+2  
−2  
−0.1  
+2  
−2  
−0.1  
+2  
% of  
FSR/V  
OPERATING RANGE  
−40  
+85  
−40  
+85  
−40  
+85  
−40  
+85  
°C  
1 Measured at IOUTA, driving a virtual ground.  
2 Nominal full-scale current, IOUTFS, is 32 × the IREF current.  
3 Use an external buffer amplifier with an input bias current <100 nA to drive any external load.  
4 Measured at IOUTFS = 1 mA.  
5 Measured at fCLOCK = 80 MSPS and fOUT = 1 MHz, using a differential clock.  
6
5% power supply variation.  
DYNAMIC SPECIFICATIONS (1.8 V)  
TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 1 mA, differential transformer coupled output, 453 Ω differentially  
terminated unless otherwise noted.  
Table 5.  
AD9707  
Min Typ  
AD9706  
Max Min Typ  
AD9705  
Max Min Typ  
AD9704  
Max Min Typ  
Parameter  
Max Unit  
DYNAMIC PERFORMANCE  
Maximum Output Update Rate, fCLOCK  
Output Settling Time, tST, (to 0.1%)1  
Output Propagation Delay (tPD)  
Glitch Impulse  
Output Rise Time (10% to 90%)1  
Output Fall Time (10% to 90%)1  
AC LINEARITY  
125  
125  
125  
125  
MSPS  
ns  
11  
5.6  
5
11  
5.6  
5
11  
5.6  
5
11  
5.6  
5
ns  
pV-s  
ns  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
ns  
Spurious-Free Dynamic Range to  
Nyquist  
fCLOCK = 10 MSPS; fOUT = 2.1 MHz  
fCLOCK = 25 MSPS; fOUT = 2.1 MHz  
fCLOCK = 25 MSPS; fOUT = 5.1 MHz  
fCLOCK = 65 MSPS; fOUT = 10.1 MHz  
fCLOCK = 65 MSPS; fOUT = 15.1 MHz  
fCLOCK = 80 MSPS; fOUT = 1.0 MHz  
fCLOCK = 80 MSPS; fOUT = 15.1 MHz  
fCLOCK = 80 MSPS; fOUT = 30.1 MHz  
Noise Spectral Density  
86  
87  
82  
82  
77  
82  
77  
60  
86  
86  
82  
79  
76  
82  
77  
59  
85  
84  
82  
78  
74  
82  
77  
59  
70  
68  
68  
70  
69  
70  
68  
60  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
74  
72  
72  
66  
fCLOCK = 80 MSPS; fOUT = 10 MHz;  
−145  
−151  
−144  
−140  
−128  
dBc/Hz  
dBc/Hz  
I
OUTFS = 1 mA  
fCLOCK = 80 MSPS; fOUT = 10 MHz;  
OUTFS = 2 mA  
I
1 Measured single-ended into 500 Ω load.  
Rev. D | Page 9 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
DIGITAL SPECIFICATIONS (1.8 V)  
TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 1 mA, unless otherwise noted.  
Table 6.  
AD9707  
AD9706  
AD9705  
AD9704  
Parameter  
DIGITAL INPUTS1  
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit  
Logic 1 Voltage  
1.2  
1.8  
0
1.2  
1.8  
0
1.2  
1.8  
0
1.2  
1.8  
0
V
Logic 0 Voltage  
0.5  
0.5  
0.5  
0.5  
V
Logic 1 Current  
−10  
+10  
+10  
−10  
+10  
+10  
−10  
+10  
+10  
−10  
+10  
+10  
µA  
µA  
pF  
ns  
ns  
ns  
ns  
ns  
Logic 0 Current  
Input Capacitance  
5
5
5
5
Input Setup Time, tS, 25°C  
Input Hold Time, tH, 25°C  
Input Setup Time, tS, −40°C to +85°C  
Input Hold Time, tH, −40°C to +85°C  
Latch Pulse Width, tLPW  
CLK INPUTS2  
2.3  
0
2.3  
0
2.3  
0
2.3  
0
2.4  
0.1  
6.2  
2.4  
0.1  
6.2  
2.4  
0.1  
6.2  
2.4  
0.1  
6.2  
Input Voltage Range  
Common-Mode Voltage  
Differential Voltage  
0
1.8  
1.3  
0
1.8  
1.3  
0
1.8  
1.3  
0
1.8  
1.3  
V
V
V
0.4  
0.5  
0.9  
1.5  
0.4  
0.5  
0.9  
1.5  
0.4  
0.5  
0.9  
1.5  
0.4  
0.5  
0.9  
1.5  
1 Includes CLK+ pin in single-ended clock input mode.  
2 Applicable to CLK+ input and CLK– input when configured for differential clock input mode.  
TIMING DIAGRAM  
DB0 TO DB13  
tS  
tH  
CLOCK  
tLPW  
tST  
tPD  
IOUTA  
OR  
IOUTB  
0.1%  
0.1%  
Figure 2. Timing Diagram  
Rev. D | Page 10 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
ABSOLUTE MAXIMUM RATINGS  
Table 7.  
Stresses at or above those listed under Absolute Maximum  
Ratings may cause permanent damage to the product. This is a  
stress rating only; functional operation of the product at these  
or any other conditions above those indicated in the operational  
section of this specification is not implied. Operation beyond  
the maximum operating conditions for extended periods may  
affect product reliability.  
Parameter  
Rating  
AVDD to ACOM  
−0.3 V to +3.9 V  
−0.3 V to +3.9 V  
−0.3 V to +3.9 V  
−0.3 V to +0.3 V  
−0.3 V to +0.3 V  
−0.3 V to +0.3 V  
−3.9 V to +3.9 V  
−3.9 V to +3.9 V  
−3.9 V to +3.9 V  
−0.3 V to DVDD + 0.3 V  
−0.3 V to DVDD + 0.3 V  
−1.0 V to AVDD + 0.3 V  
−0.3 V to AVDD + 0.3 V  
−0.3 V to CLKVDD + 0.3 V  
150°C  
DVDD to DCOM  
CLKVDD to CLKCOM  
ACOM to DCOM  
ACOM to CLKCOM  
THERMAL CHARACTERISTICS  
DCOM to CLKCOM  
AVDD to DVDD  
Thermal impedance measurements were taken on a 4-layer board  
in still air, in accordance with EIA/JESD51-7.  
AVDD to CLKVDD  
DVDD to CLKVDD  
Table 8. Thermal Resistance  
SLEEP to DCOM  
Package Type  
θJA  
Unit  
Digital Inputs, MODE to DCOM  
IOUTA, IOUTB to ACOM  
REFIO, FS ADJ, OTCM to ACOM  
CLK+, CLK–, CMODE to CLKCOM  
Junction Temperature  
Storage Temperature Range  
Lead Temperature (10 sec)  
32-Lead LFCSP  
32.5  
°C/W  
ESD CAUTION  
−65°C to +150°C  
300°C  
Rev. D | Page 11 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
AD9707  
PIN 1  
INDICATOR  
DB7  
DB6  
DVDD  
DB5  
DB4  
DB3  
1
2
3
4
5
6
7
8
24 FS ADJ  
23 REFIO  
22 ACOM  
21 IOUTA  
20 IOUTB  
19 OTCM  
AD9707  
TOP VIEW  
(Not to Scale)  
DB2  
DB1  
18 AVDD  
17 PIN/SPI/RESET  
NOTES  
1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE  
THERMALLY CONNECTED TO A COPPER GROUND  
PLANE FOR ENHANCED ELECTRICAL AND THERMAL  
PERFORMANCE.  
Figure 3. AD9707 Pin Configuration  
Table 9. AD9707 Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
Data Bit 12 to Data Bit 1.  
28 to 32, 1,  
2, 4 to 8  
DB12 to DB1  
3
DVDD  
Digital Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
9
DB0 (LSB)  
DCOM  
CLKVDD  
CLK+  
Least Significant Data Bit (LSB).  
10, 26  
11  
12  
13  
14  
15  
Digital Common.  
Clock Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
Positive Differential Clock Input.  
Negative Differential Clock Input.  
Clock Common.  
CLK−  
CLKCOM  
CMODE/SCLK In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver  
(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver. In SPI mode, this pin is the serial  
data clock input.  
16  
17  
MODE/SDIO  
In pin mode, this pin selects the input data format. Connect to DCOM for straight binary, and DVDD for twos  
complement. In SPI mode, this pin acts as SPI data input/output.  
PIN/SPI/RESET Selects SPI Mode or Pin Mode Operation. Active high for pin mode operation and active low for SPI mode  
operation. Pulse high to reset SPI registers to default values.  
18  
19  
20  
21  
22  
23  
AVDD  
OTCM  
IOUTB  
IOUTA  
ACOM  
REFIO  
Analog Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.  
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.  
DAC Current Output. Full-scale current is sourced when all data bits are 1s.  
Analog Common.  
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V  
reference output when internal reference is activated. Requires a 0.1 µF capacitor to ACOM when internal  
reference is activated.  
24  
25  
27  
FS ADJ  
Full-Scale Current Output Adjust.  
SLEEP/CSB  
DB13 (MSB)  
EPAD  
In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low).  
Most Significant Data Bit (MSB).  
It is recommended that the exposed pad be thermally connected to a copper ground plane for enhanced  
electrical and thermal performance.  
Rev. D | Page 12 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
AD9706  
PIN 1  
INDICATOR  
DB5  
DB4  
DVDD  
DB3  
DB2  
DB1  
1
24 FS ADJ  
23 REFIO  
22 ACOM  
21 IOUTA  
20 IOUTB  
19 OTCM  
18 AVDD  
2
3
4
5
6
7
8
AD9706  
TOP VIEW  
(Not to Scale)  
DB0 (LSB)  
NC  
17 PIN/SPI/RESET  
NOTES  
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.  
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE  
THERMALLY CONNECTED TO A COPPER GROUND  
PLANE FOR ENHANCED ELECTRICAL AND THERMAL  
PERFORMANCE.  
Figure 4. AD9706 Pin Configuration  
Table 10. AD9706 Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
28 to 32, 1,  
2, 4 to 6  
DB10 to DB1  
Data Bit 10 to Data Bit 1.  
3
DVDD  
DB0 (LSB)  
NC  
Digital Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
7
Least Significant Data Bit (LSB).  
8, 9  
10, 26  
11  
12  
13  
14  
15  
No Connect.  
DCOM  
CLKVDD  
CLK+  
Digital Common.  
Clock Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
Positive Differential Clock Input.  
Negative Differential Clock Input.  
Clock Common.  
CLK−  
CLKCOM  
CMODE/SCLK In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver (drive  
CLK+ and float CLK–). Connect to CLKVDD for differential receiver. In SPI mode, this pin is the serial data  
clock input.  
16  
17  
MODE/SDIO  
In pin mode, this pin selects the input data format. Connect to DCOM for straight binary, and DVDD for twos  
complement. In SPI mode, this pin acts as SPI data input/output.  
PIN/SPI/RESET Selects SPI Mode or Pin Mode Operation. Active high for pin mode operation, and active low for SPI mode  
operation. Pulse high to reset SPI registers to default values.  
18  
19  
20  
21  
22  
23  
AVDD  
OTCM  
IOUTB  
IOUTA  
ACOM  
REFIO  
Analog Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.  
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.  
DAC Current Output. Full-scale current is sourced when all data bits are 1s.  
Analog Common.  
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V  
reference output when internal reference is activated. Requires a 0.1 µF capacitor to ACOM when internal  
reference is activated.  
24  
25  
27  
FS ADJ  
Full-Scale Current Output Adjust.  
SLEEP/CSB  
DB11 (MSB)  
EPAD  
In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low).  
Most Significant Data Bit (MSB).  
It is recommended that the exposed pad be thermally connected to a copper ground plane for enhanced  
electrical and thermal performance.  
Rev. D | Page 13 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
AD9705  
PIN 1  
INDICATOR  
DB3  
DB2  
DVDD  
DB1  
1
2
3
4
5
6
7
8
24 FS ADJ  
23 REFIO  
22 ACOM  
21 IOUTA  
20 IOUTB  
19 OTCM  
AD9705  
TOP VIEW  
DB0 (LSB)  
NC  
(Not to Scale)  
NC  
NC  
18 AVDD  
17 PIN/SPI/RESET  
NOTES  
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.  
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE  
THERMALLY CONNECTED TO A COPPER GROUND  
PLANE FOR ENHANCED ELECTRICAL AND THERMAL  
PERFORMANCE.  
Figure 5. AD9705 Pin Configuration  
Table 11. AD9705 Pin Function Descriptions  
Pin No. Mnemonic Description  
Data Bit 8 to Data Bit 1.  
28 to 32, DB8 to DB1  
1, 2, 4  
3
DVDD  
DB0 (LSB)  
NC  
Digital Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
5
Least Significant Data Bit (LSB).  
6 to 9  
10, 26  
11  
No Connect.  
DCOM  
CLKVDD  
CLK+  
Digital Common.  
Clock Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
12  
Positive Differential Clock Input.  
Negative Differential Clock Input.  
Clock Common.  
13  
CLK−  
14  
CLKCOM  
15  
CMODE/SCLK In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver (drive  
CLK+ and float CLK–). Connect to CLKVDD for differential receiver. In SPI mode, this pin is the serial data clock input.  
16  
17  
MODE/SDIO  
In pin mode, this pin selects the input data format. Connect to DCOM for straight binary, and DVDD for twos  
complement. In SPI mode, this pin acts as SPI data input/output.  
PIN/SPI/RESET Selects SPI Mode or Pin Mode Operation. Active high for pin mode operation and active low for SPI mode  
operation. Pulse high to reset SPI registers to default values.  
18  
19  
20  
21  
22  
23  
AVDD  
OTCM  
IOUTB  
IOUTA  
ACOM  
REFIO  
Analog Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.  
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.  
DAC Current Output. Full-scale current is sourced when all data bits are 1s.  
Analog Common.  
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference  
output when internal reference is activated. Requires a 0.1 µF capacitor to ACOM when internal reference is activated.  
24  
25  
27  
FS ADJ  
Full-Scale Current Output Adjust.  
SLEEP/CSB  
DB9 (MSB)  
EPAD  
In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low).  
Most Significant Data Bit (MSB).  
It is recommended that the exposed pad be thermally connected to a copper ground plane for enhanced  
electrical and thermal performance.  
Rev. D | Page 14 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
AD9704  
PIN 1  
INDICATOR  
1
24  
23  
22  
DB1  
DB0 (LSB)  
DVDD  
NC  
FS ADJ  
REFIO  
ACOM  
2
3
4
5
6
7
8
AD9704  
21 IOUTA  
20  
19 OTCM  
18 AVDD  
TOP VIEW  
NC  
NC  
NC  
NC  
IOUTB  
(Not to Scale)  
17 PIN/SPI/RESET  
NOTES  
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.  
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE  
THERMALLY CONNECTED TO A COPPER GROUND  
PLANE FOR ENHANCED ELECTRICAL AND THERMAL  
PERFORMANCE.  
Figure 6. AD9704 Pin Configuration  
Table 12. AD9704 Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
28 to 32, 1 DB6 to DB1  
Data Bit 6 to Data Bit 1.  
2
DB0 (LSB)  
DVDD  
NC  
Least Significant Data Bit (LSB).  
3
Digital Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
4 to 9  
10, 26  
11  
No Connect.  
DCOM  
CLKVDD  
CLK+  
Digital Common.  
Clock Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
12  
Positive Differential Clock Input.  
Negative Differential Clock Input.  
Clock Common.  
13  
CLK−  
14  
CLKCOM  
15  
CMODE/SCLK In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver (drive CLK+  
and float CLK−). Connect to CLKVDD for differential receiver. In SPI mode, this pin is the serial data clock input.  
16  
17  
MODE/SDIO  
In pin mode, this pin selects the input data format. Connect to DCOM for straight binary, and DVDD for twos  
complement. In SPI mode, this pin acts as SPI data input/output.  
PIN/SPI/RESET Selects SPI Mode or Pin Mode Operation. Active high for pin mode operation and active low for SPI mode  
operation. Pulse high to reset SPI registers to default values.  
18  
19  
20  
21  
22  
23  
AVDD  
OTCM  
IOUTB  
IOUTA  
ACOM  
REFIO  
Analog Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.  
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.  
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.  
DAC Current Output. Full-scale current is sourced when all data bits are 1s.  
Analog Common.  
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference output  
when internal reference is activated. Requires a 0.1 µF capacitor to ACOM when internal reference is activated.  
24  
25  
27  
FS ADJ  
Full-Scale Current Output Adjust.  
SLEEP/CSB  
DB7 (MSB)  
EPAD  
In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low).  
Most Significant Data Bit (MSB).  
It is recommended that the exposed pad be thermally connected to a copper ground plane for enhanced  
electrical and thermal performance.  
Rev. D | Page 15 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
TYPICAL PERFORMANCE CHARACTERISTICS  
AD9707  
VDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.  
95  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
fCLOCK = 10MSPS  
90  
fCLOCK = 65MSPS  
85  
80  
75  
fCLOCK = 175MSPS  
70  
65  
fCLOCK = 125MSPS  
60  
55  
50  
45  
0
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65  
1
0
0
10  
100  
fOUT (MHz)  
fOUT (MHz)  
Figure 10. SFDR vs. fOUT @ 125 MSPS  
Figure 7. SFDR vs. fOUT  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
1
2
3
4
5
10  
20  
30  
40  
50  
60  
70  
80  
fOUT (MHz)  
fOUT (MHz)  
Figure 11. SFDR vs. fOUT @ 175 MSPS  
Figure 8. SFDR vs. fOUT @ 10 MSPS  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
I
= 5mA  
OUTFS  
I
= 2mA  
OUTFS  
I
= 1mA  
OUTFS  
5
10  
15  
20  
25  
30  
35  
10  
20  
30  
40  
50  
60  
70  
80  
fOUT (MHz)  
fOUT (MHz)  
Figure 12. SFDR vs. fOUT and IOUTFS @ 175 MSPS  
Figure 9. SFDR vs. fOUT @ 65 MSPS  
Rev. D | Page 16 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
–120  
–125  
–130  
–135  
–140  
–145  
–150  
–155  
–160  
–165  
OTCM = 0V  
1mA  
2mA  
OTCM = 0.3V  
OTCM = 1.2V  
5mA  
0
10  
20  
30  
40  
50  
60  
70  
80  
0
10  
20  
30  
40  
50  
60  
70  
80  
FREQUENCY (MHz)  
fOUT (MHz)  
Figure 13. SFDR vs. fOUT and OTCM @ 175 MSPS  
Figure 16. NSD vs. fOUT and IOUTFS @ 175 MSPS  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
fCLOCK = 65MSPS  
fCLOCK = 75MSPS  
fCLOCK = 175MSPS  
fCLOCK = 125MSPS  
fCLOCK = 125MSPS  
fCLOCK = 175MSPS  
0
10  
20  
30  
40  
50  
60  
70  
80  
–10  
–8  
–6  
A
–4  
(dBFS)  
–2  
0
LOWER fOUT (MHz)  
OUT  
Figure 17. Dual-Tone IMD vs. Lower fOUT and fCLOCK @ 0 dBFS  
Figure 14. SFDR vs. AOUT and fCLOCK at fOUT = fCLOCK/5  
95  
90  
–125  
–130  
–135  
–140  
–145  
–150  
–155  
–160  
+25°C  
85  
80  
+85°C  
75  
70  
65  
125MSPS  
65MSPS  
175MSPS  
60  
55  
50  
45  
–40°C  
0
10  
20  
30  
40  
50  
60  
70  
80  
0
10  
20  
30  
40  
50  
60  
70  
80  
LOWER fOUT (MHz)  
FREQUENCY (MHz)  
Figure 18. Dual-Tone IMD vs. Lower fOUT and Temperature at 0 dBFS,  
175 MSPS  
Figure 15. NSD vs. fOUT and fCLOCK @ 0 dBFS  
Rev. D | Page 17 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
1.0  
0.5  
0
–0.5  
–1.0  
–1.5  
–0.1  
–0.2  
0
5000  
10000  
15000  
0
5000  
10000  
15000  
CODE  
CODE  
Figure 19. Typical Uncalibrated INL  
Figure 22. Typical Calibrated DNL  
95  
0.6  
0.4  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
–40°C  
0.2  
0
+25°C  
+85°C  
–0.2  
–0.4  
–0.6  
–0.8  
0
10  
20  
30  
40  
50  
60  
70  
80  
0
5000  
10000  
15000  
fOUT (MHz)  
CODE  
Figure 23. SFDR vs. fOUT and Temperature @ 175 MSPS  
Figure 20. Typical Uncalibrated DNL  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
0.6  
0.4  
fCLOCK = 78MSPS  
fOUT = 15.0MHz  
SFDR = 80dBc  
AMPLITUDE = 0dBFS  
0.2  
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
1
6
11  
16  
21  
26  
31  
36  
0
5000  
10000  
15000  
FREQUENCY (MHz)  
CODE  
Figure 24. Single-Tone SFDR  
Figure 21. Typical Calibrated INL  
Rev. D | Page 18 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
fCLOCK = 78MSPS  
fOUT1 = 15.0MHz  
fOUT2 = 15.4MHz  
fOUT3 = 15.8MHz  
fOUT4 = 16.2MHz  
SFDR = 77dBc  
fCLOCK = 78MSPS  
fOUT1 = 15.0MHz  
fOUT2 = 15.4MHz  
SFDR = 77dBc  
AMPLITUDE = 0dBFS  
AMPLITUDE = 0dBFS  
1
6
11  
16  
21  
26  
31  
36  
1
6
11  
16  
21  
26  
31  
36  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
Figure 25. Dual-Tone SFDR  
Figure 26. Four-Tone SFDR  
Rev. D | Page 19 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
VDD = 1.8 V, IOUTFS = 1 mA, unless otherwise noted.  
95  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
10MSPS  
90  
65MSPS  
85  
80  
I
= 1mA  
OUTFS  
75  
80MSPS  
70  
I
= 2mA  
OUTFS  
65  
60  
55  
50  
125MSPS  
45  
1
0
0
10  
100  
0
5
10  
15  
20  
25  
30  
35  
FREQUENCY (MHz)  
fOUT (MHz)  
Figure 27. SFDR vs. fOUT  
Figure 30. SFDR vs. fOUT and IOUTFS at 65 MSPS  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
I
= 1mA  
OUTFS  
I
= 2mA  
OUTFS  
0
5
10  
15  
20  
fOUT (MHz)  
25  
30  
35  
40  
1
2
3
4
5
fOUT (MHz)  
Figure 28. SFDR vs. fOUT at 10 MSPS  
Figure 31. SFDR vs. fOUT and IOUTFS at 80 MSPS  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
fCLOCK = 80MSPS  
fCLOCK = 65MSPS  
5
10  
15  
20  
25  
30  
35  
40  
–10  
–8  
–6  
A
–4  
(dBFS)  
–2  
0
fOUT (MHz)  
OUT  
Figure 29. SFDR vs. fOUT at 80 MSPS  
Figure 32. SFDR vs. AOUT at fOUT = fCLOCK/5  
Rev. D | Page 20 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
–115  
–120  
–125  
–130  
–135  
125MSPS, 1mA  
125MSPS, 2mA  
–40°C  
+85°C  
65MSPS, 1mA  
80MSPS, 1mA  
–140  
–145  
–150  
–155  
–160  
+25°C  
80MSPS, 2mA  
65MSPS, 2mA  
0
5
10  
15  
20  
25  
30  
35  
40  
0
10  
20  
30  
40  
50  
60  
70  
LOWER fOUT (MHz)  
FREQUENCY (MHz)  
Figure 36. Dual-Tone IMD vs. Lower fOUT and Temperature at 80 MSPS,  
OUTFS = 1 mA and 0 dBFS  
Figure 33. NSD vs. fOUT, fCLOCK, and IOUTFS at 0 dBFS  
I
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
+25°C  
–40°C  
65MSPS  
80MSPS  
25MSPS  
+80°C  
35  
125MSPS  
0
5
10  
15  
20  
25  
30  
40  
0
10  
20  
30  
40  
50  
60  
FREQUENCY (MHz)  
LOWER fOUT (MHz)  
Figure 34. Dual-Tone IMD vs. Lower fOUT at IOUTFS = 1 mA and 0 dBFS  
Figure 37. Dual-Tone IMD vs. Lower fOUT and Temperature at 80 MSPS,  
OUTFS = 2 mA and 0 dBFS  
I
95  
90  
85  
80  
1.0  
0.5  
65MSPS  
75  
0.0  
70  
25MSPS  
80MSPS  
65  
–0.5  
–1.0  
–1.5  
60  
55  
50  
125MSPS  
45  
0
10  
20  
30  
40  
50  
60  
0
5000  
10000  
15000  
FREQUENCY (MHz)  
CODE  
Figure 35. Dual-Tone IMD vs. Lower fOUT at IOUTFS = 2 mA and 0 dBFS  
Figure 38. Typical Uncalibrated INL  
Rev. D | Page 21 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
0.6  
0.4  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
fCLOCK = 78MSPS  
fOUT1 = 15.0MHz  
fOUT2 = 15.4MHz  
SFDR = 74dBc  
AMPLITUDE = 0dBFS  
0.2  
0
–0.2  
–0.4  
–0.6  
–0.8  
1
6
11  
16  
21  
26  
31  
36  
0
5000  
10000  
15000  
FREQUENCY (MHz)  
CODE  
Figure 39. Typical Uncalibrated DNL  
Figure 42. Dual-Tone SFDR  
95  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
fCLOCK = 78MSPS  
fOUT1 = 15.0MHz  
fOUT2 = 15.4MHz  
fOUT3 = 15.8MHz  
fOUT4 = 16.2MHz  
SFDR = 69dBc  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
–40°C  
AMPLITUDE = 0dBFS  
+85°C  
+25°C  
0
5
10  
15  
20  
25  
30  
35  
40  
1
6
11  
16  
21  
26  
31  
36  
fOUT (MHz)  
FREQUENCY (MHz)  
Figure 40. SFDR vs. Temperature at 80 MSPS  
Figure 43. Four-Tone SFDR  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
fCLOCK = 78MSPS  
fOUT = 15.0MHz  
SFDR = 79dBc  
AMPLITUDE = 0dBFS  
1
6
11  
16  
21  
26  
31  
36  
FREQUENCY (MHz)  
Figure 41. Single-Tone SFDR  
Rev. D | Page 22 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
AD9704, AD9705 AND AD9706  
VDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.  
0.01  
–115  
–120  
–125  
8-BIT  
–130  
10-BIT  
–135  
0
–140  
12-BIT  
14-BIT  
–145  
–150  
–155  
–160  
–0.01  
0
20  
40  
60  
80  
0
200  
400  
600  
800  
1000  
fOUT (MHz)  
CODE  
Figure 44. AD9704/AD9705/AD9706/AD9707 NSD vs. fOUT at 0 dBFS,  
175 MSPS  
Figure 47. AD9705 Typical Uncalibrated INL  
0.01  
0.03  
0.02  
0.01  
0
0
–0.01  
–0.02  
–0.01  
0
50  
100  
150  
200  
250  
0
200  
400  
600  
800  
1000  
CODE  
CODE  
Figure 45. AD9704 Typical Uncalibrated INL  
Figure 48. AD9705 Typical Uncalibrated DNL  
0.01  
0
0.3  
0.2  
0.1  
0
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
–0.01  
–0.02  
–0.03  
0
1000  
2000  
3000  
4000  
0
50  
100  
150  
200  
250  
CODE  
CODE  
Figure 49. AD9706 Typical Uncalibrated INL  
Figure 46. AD9704 Typical Uncalibrated DNL  
Rev. D | Page 23 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
0.01  
fCLOCK = 78MSPS  
fOUT = 15.0MHz  
SFDR = 75dBc  
AMPLITUDE = 0dBFS  
0
–0.01  
–0.02  
–0.03  
–0.04  
0
1000  
2000  
3000  
4000  
1
6
11  
16  
21  
26  
31  
36  
CODE  
FREQUENCY (MHz)  
Figure 50. AD9706 Typical Uncalibrated DNL  
Figure 53. AD9705 Single-Tone SFDR  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
fCLOCK = 78MSPS  
fOUT = 15.0MHz  
fCLOCK = 78MSPS  
fOUT1 = 15.0MHz  
fOUT2 = 15.4MHz  
SFDR = 73dBc  
SFDR = 67dBc  
AMPLITUDE = 0dBFS  
AMPLITUDE = 0dBFS  
1
6
11  
16  
21  
26  
31  
36  
1
6
11  
16  
21  
26  
31  
36  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
Figure 51. AD9704Single-Tone SFDR  
Figure 54. AD9705 Dual-Tone SFDR  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
fCLOCK = 78MSPS  
fOUT1 = 15.0MHz  
fOUT2 = 15.4MHz  
SFDR = 67dBc  
fCLOCK = 78MSPS  
fOUT1 = 15.0MHz  
SFDR = 77dBc  
AMPLITUDE = 0dBFS  
AMPLITUDE = 0dBFS  
1
6
11  
16  
21  
26  
31  
36  
1
6
11  
16  
21  
26  
31  
36  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
Figure 52. AD9704 Dual-Tone SFDR  
Figure 55. AD9706 Single-Tone SFDR  
Rev. D | Page 24 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
fCLOCK = 78MSPS  
fOUT1 = 15.0MHz  
fOUT2 = 15.4MHz  
SFDR = 77dBc  
AMPLITUDE = 0dBFS  
1
6
11  
16  
21  
26  
31  
36  
FREQUENCY (MHz)  
Figure 56. AD9706Dual-Tone SFDR  
Rev. D | Page 25 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
VDD = 1.8 V, IOUTFS = 1 mA, unless otherwise noted.  
–115  
0.08  
0.06  
0.04  
0.02  
0
–120  
–125  
8-BIT  
–130  
–135  
10-BIT  
–140  
12-BIT  
–145  
–0.02  
–0.04  
–0.06  
–0.08  
14-BIT  
–150  
–155  
–160  
0
5
10  
15  
20  
25  
30  
35  
0
0
0
200  
400  
600  
800  
1000  
1000  
4000  
fOUT (MHz)  
CODE  
Figure 57. AD9704/AD9705/AD9706/AD9707 NSD vs. fOUT at 0 dBFS, 80 MSPS  
Figure 60. AD9705 Typical Uncalibrated INL  
0.02  
0
0.04  
0.03  
0.02  
0.01  
0
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
–0.12  
–0.01  
–0.02  
200  
400  
600  
800  
0
50  
100  
150  
200  
250  
CODE  
CODE  
Figure 58. AD9704 Typical Uncalibrated INL  
Figure 61. AD9705Typical Uncalibrated DNL  
0.3  
0.2  
0.01  
0.1  
0
–0.01  
–0.02  
–0.03  
0
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
1000  
2000  
3000  
0
50  
100  
150  
200  
250  
CODE  
CODE  
Figure 59. AD9704 Typical Uncalibrated DNL  
Figure 62. AD9706 Typical Uncalibrated INL  
Rev. D | Page 26 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
0.1  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
fCLOCK = 78MSPS  
fOUT = 15.0MHz  
SFDR = 73dBc  
0
AMPLITUDE = 0dBFS  
–0.1  
–0.2  
–0.3  
–0.4  
0
1000  
2000  
3000  
4000  
1
6
11  
16  
21  
26  
31  
36  
CODE  
FREQUENCY (MHz)  
Figure 63. AD9706 Typical Uncalibrated DNL  
Figure 66. AD9705 Single-Tone SFDR  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
fCLOCK = 78MSPS  
fOUT = 15.0MHz  
fCLOCK = 78MSPS  
fOUT1 = 15.0MHz  
fOUT2 = 15.4MHz  
SFDR = 71dBc  
SFDR = 67dBc  
AMPLITUDE = 0dBFS  
AMPLITUDE = 0dBFS  
1
6
11  
16  
21  
26  
31  
36  
1
6
11  
16  
21  
26  
31  
36  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
Figure 64. AD9704Single-Tone SFDR  
Figure 67. AD9705 Dual-Tone SFDR  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
–10  
fCLOCK = 78MSPS  
fOUT1 = 15.0MHz  
fOUT2 = 15.4MHz  
SFDR = 67dBc  
fCLOCK = 78MSPS  
fOUT = 15.0MHz  
SFDR = 73dBc  
–20  
–30  
AMPLITUDE = 0dBFS  
AMPLITUDE = 0dBFS  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
1
6
11  
16  
21  
26  
31  
36  
1
6
11  
16  
21  
26  
31  
36  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
Figure 65. AD9704 Dual-Tone SFDR  
Figure 68. AD9706 Single-Tone SFDR  
Rev. D | Page 27 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
–10  
fCLOCK = 78MSPS  
–20  
fOUT1 = 15.0MHz  
fOUT2 = 15.4MHz  
SFDR = 73dBc  
–30  
AMPLITUDE = 0dBFS  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
1
6
11  
16  
21  
26  
31  
36  
FREQUENCY (MHz)  
Figure 69. AD9706 Dual-Tone SFDR  
Rev. D | Page 28 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
TERMINOLOGY  
Linearity Error (Integral Nonlinearity or INL)  
INL is defined as the maximum deviation of the actual analog  
output from the ideal output, determined by a straight line  
drawn from zero to full scale.  
Power Supply Rejection  
Power supply rejection is the maximum change in the full-scale  
output as the supplies are varied from nominal to minimum  
and maximum specified voltages.  
Differential Nonlinearity (DNL)  
Settling Time  
DNL is the measure of the variation in analog value, normalized  
to full scale, associated with a 1 LSB change in digital input code.  
Settling time is the time required for the output to reach and  
remain within a specified error band about its final value,  
measured from the start of the output transition.  
Monotonicity  
A digital-to-analog converter is monotonic if the output either  
increases or remains constant as the digital input increases.  
Glitch Impulse  
Asymmetrical switching times in a DAC give rise to undesired  
output transients that are quantified by a glitch impulse. It is  
specified as the net area of the glitch in picovolt-seconds (pV-s).  
Offset Error  
Offset error is the deviation of the output current from the ideal of  
zero. For IOUTA, 0 mA output is expected when the inputs are all  
0s. For IOUTB, 0 mA output is expected when all inputs are set to 1.  
Spurious-Free Dynamic Range (SFDR)  
SFDR is the difference, in decibels (dB), between the rms  
amplitude of the output signal and the peak spurious signal  
over the specified bandwidth.  
Gain Error  
Gain error is the difference between the actual and ideal output  
span. The actual span is determined by the output when all inputs  
are set to 1, minus the output when all inputs are set to 0. The  
ideal gain is calculated using the measured VREF. Therefore,  
the gain error does not include effects of the reference.  
Total Harmonic Distortion (THD)  
THD is the ratio of the rms sum of the first six harmonic  
components to the rms value of the measured input signal.  
It is expressed as a percentage or in decibels (dB).  
Output Compliance Range  
Multitone Power Ratio  
Output compliance range is the range of allowable voltage at the  
output of a current output DAC. Operation beyond the maximum  
compliance limits can cause either output stage saturation or  
breakdown, resulting in nonlinear performance.  
Multitone power ratio is the spurious-free dynamic range  
containing multiple carrier tones of equal amplitude. It is  
measured as the difference between the rms amplitude of  
a carrier tone to the peak spurious signal in the region of  
a removed tone.  
Temperature Drift  
Temperature drift is specified as the maximum change from the  
ambient (25°C) value to the value at either TMIN or TMAX. For  
offset and gain drift, the drift is reported in ppm of full-scale  
range (FSR) per °C. For reference drift, the drift is reported in  
ppm per °C.  
Noise Spectral Density (NSD)  
Noise spectral density is the average noise power normalized to  
a 1 Hz bandwidth, with the DAC converting and producing an  
output tone.  
1.7V TO 3.6V  
AVDD  
ACOM  
1.0V REF  
0.1µF  
AD9707  
REFIO  
CURRENT  
SOURCE  
ARRAY  
FS ADJ  
ADT4-6T+  
OTCM  
R
16k  
SET  
CLKVDD  
CLKCOM  
1.7V TO 3.6V  
AD9512  
IOUTA  
IOUTB  
SEGMENTED  
SWITCHES  
LSB  
SWITCHES  
JTX-4-10T+  
CLK+  
1kΩ  
CLK1  
50Ω  
LATCHES  
CLK–  
DVDD  
DCOM  
CLKB  
SPI  
1.7V TO 3.6V  
SLEEP/CSB  
DIGITAL  
DATA  
CLOCK  
OUTPUT  
LOW JITTER  
RF SOURCE  
DIGITAL DATA  
SOURCE DPG  
Figure 70. Basic AC Characterization Test Setup  
Rev. D | Page 29 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
THEORY OF OPERATION  
Figure 71 shows a simplified block diagram of the AD9707. The  
AD9704/AD9705/AD9706/AD9707 consist of a DAC, digital  
control logic, and full-scale output current control. The DAC  
contains a PMOS current source array capable of providing a  
nominal full-scale current (IOUTFS) of 2 mA and a maximum of  
5 mA. The array is divided into 31 equal currents that make up the  
five most significant bits (MSBs). The next four bits, or middle  
bits, consist of 15 equal current sources whose value is 1/16 of an  
MSB current source. The remaining LSBs are binary weighted frac-  
tions of the current sources of the middle bits. Implementing the  
middle and lower bits with current sources, instead of an R-2R  
ladder, enhances the AD9704/AD9705/AD9706/AD9707 dynamic  
performance for multitone or low amplitude signals and helps  
maintain the high output impedance of the DAC (that is,  
>200 MΩ).  
The external resistor, in combination with both the reference  
control amplifier and voltage reference, VREFIO, sets the reference  
current, IREF, which is replicated to the segmented current sources  
with the proper scaling factor. The full-scale current, IOUTFS, is  
32 × IREF  
.
The AD9704/AD9705/AD9706/AD9707 provide the option of  
setting the output common mode to a value other than ACOM  
via the output common mode (OTCM) pin. This facilitates  
interfacing the output of the AD9704/AD9705/AD9706/AD9707  
directly to components that require common-mode levels greater  
than 0 V.  
SERIAL PERIPHERAL INTERFACE  
The AD9704/AD9705/AD9706/AD9707 serial port is a flexible,  
synchronous serial communications port allowing easy interfacing  
to many industry-standard microcontrollers and microprocessors.  
The serial I/O is compatible with most synchronous transfer  
formats, including the Motorola SPI and Intel® SSR protocols.  
The interface allows read/write access to all registers that configure  
the AD9704/AD9705/AD9706/AD9707. Single or multiple byte  
transfers are supported, as well as MSB first or LSB first transfer  
formats. The serial interface port of the AD9704/AD9705/AD9706/  
AD9707 is configured as a single pin I/O. SPI terminal voltages  
are referenced to ACOM.  
All of these current sources are switched to one of the two  
output nodes (IOUTA or IOUTB) via PMOS differential current  
switches. The switches are based on the architecture pioneered  
in the AD9764 family, with further refinements made to reduce  
distortion contributed by the switching transient. This switch  
architecture also reduces various timing errors and provides  
matching complementary drive signals to the inputs of the  
differential current switches.  
The analog and digital sections of the AD9704/AD9705/AD9706/  
AD9707 have separate power supply inputs (AVDD and DVDD)  
that can operate independently over a 1.7 V to 3.6 V range. The  
digital section, capable of operating at a rate of up to 175 MSPS,  
consists of edge-triggered latches and segment decoding logic  
circuitry. The analog section includes the PMOS current  
sources, the associated differential switches, a 1.0 V band gap  
voltage reference, and a reference control amplifier.  
General Operation of the Serial Interface  
There are two phases to a communication cycle with the AD9704/  
AD9705/AD9706/AD9707. Phase 1 is the instruction cycle, which  
is the writing of an instruction byte into the AD9704/AD9705/  
AD9706/AD9707, coincident with the first eight SCLK rising  
edges. The instruction byte provides the AD9704/AD9705/  
AD9706/AD9707 serial port controller with information regarding  
the data transfer cycle, which is Phase 2 of the communication  
cycle. The Phase 1 instruction byte defines whether the upcoming  
data transfer is read or write, the number of bytes in the data  
transfer, and the starting register address for the first byte of the  
data transfer.  
The DAC full-scale output current is regulated by the reference  
control amplifier and can be set from 1 mA to 5 mA via an external  
resistor, RSET, connected to the full-scale adjust (FS ADJ) pin.  
1.7V TO 3.6V  
AVDD  
ACOM  
1.0V REF  
0.1µF  
AD9707  
REFIO  
CURRENT  
SOURCE  
ARRAY  
OTCM  
FS ADJ  
1.7V  
CLKVDD  
IOUTA  
R
SET  
TO  
SEGMENTED  
SWITCHES  
LSB  
SWITCHES  
3.6V  
CLKCOM  
IOUTB  
CLK+  
CLK–  
PIN/SPI/RESET  
MODE/SDIO  
LATCHES  
SPI  
1.7V TO  
3.6V  
CMODE/SCLK  
DVDD  
DCOM  
SLEEP/CSB  
DIGITAL INPUTS (DB13 TO DB0)  
Figure 71. Simplified Block Diagram  
Rev. D | Page 30 of 42  
 
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
A logic high on Pin 17 (PIN/SPI/RESET), followed by a logic  
low, resets the SPI port timing to the initial state of the instruction  
cycle. This is true regardless of the present state of the internal  
registers or the other signal levels present at the inputs to the SPI  
port. If the SPI port is in the midst of an instruction cycle or a  
data transfer cycle, none of the present data is written.  
CSB—Chip Select. Active low input starts and gates a communica-  
tion cycle. It allows more than one device to be used on the same  
serial communications lines. The SDIO pin goes to a high imped-  
ance state when this input is high. Chip select must stay low  
during the entire communication cycle.  
SDIO—Serial Data I/O. This pin is used as a bidirectional data  
line to transmit and receive data.  
The remaining SCLK edges are for Phase 2 of the communication  
cycle. Phase 2 is the actual data transfer between the AD9704/  
AD9705/AD9706/AD9707 and the system controller. Phase 2 of  
the communication cycle is a transfer of one, two, three, or four  
data bytes, as determined by the instruction byte. Using one  
multibyte transfer is the preferred method. Single byte data  
transfers are useful to reduce CPU overhead when register access  
requires one byte only. Registers change immediately upon  
writing to the last bit of each transfer byte.  
MSB/LSB Transfers  
The AD9704/AD9705/AD9706/AD9707 serial port can support  
both most significant bit (MSB) first or least significant bit  
(LSB) first data formats. This functionality is controlled by the  
DATADIR bit (Register 0x00, Bit 6). The default is MSB first  
(DATADIR = 0).  
When DATADIR = 0 (MSB first), the instruction and data bytes  
must be written from most significant bit to least significant bit.  
Multibyte data transfers in MSB first format start with an  
instruction byte that includes the register address of the most  
significant data byte. Subsequent data bytes should follow in  
order from high address to low address. In MSB first mode, the  
serial port internal byte address generator decrements for each  
data byte of the multibyte communication cycle.  
Instruction Byte  
The instruction byte contains the information shown in the bit  
map in Table 13.  
Table 13.  
MSB  
7
LSB  
0
6
5
4
3
2
1
When DATADIR = 1 (LSB first), the instruction and data bytes  
must be written from least significant bit to most significant bit.  
Multibyte data transfers in LSB first format start with an instruction  
byte that includes the register address of the least significant data  
byte followed by multiple data bytes. The serial port internal byte  
address generator increments for each byte of the multibyte  
communication cycle.  
R/W  
N1  
N0  
A4  
A3  
A2  
A1  
A0  
W
R/ , Bit 7 of the instruction byte, determines whether a read or  
a write data transfer occurs after the instruction byte write. Logic 1  
indicates a read operation. Logic 0 indicates a write operation.  
N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine the  
number of bytes to be transferred during the data transfer cycle.  
The bit decodes are shown in Table 14.  
The AD9704/AD9705/AD9706/AD9707 serial port controller  
data address decrements from the data address written toward  
0x00 for multibyte I/O operations if the MSB first mode is  
active. The serial port controller address increments from the  
data address written toward 0x1F for multibyte I/O operations  
if the LSB first mode is active.  
A4, A3, A2, A1, and A0, which are Bit 4, Bit 3, Bit 2, Bit 1, and  
Bit 0 of the instruction byte, respectively, determine which register  
is accessed during the data transfer portion of the communication  
cycle. For multibyte transfers, this address is the starting byte  
address. The remaining register addresses are generated by the  
AD9704/AD9705/AD9706/AD9707, based on the DATADIR bit  
(Register 0x00, Bit 6).  
Notes on Serial Port Operation  
The AD9704/AD9705/AD9706/AD9707 serial port configura-  
tion is controlled by Register 0x00, Bit 7. It is important to note  
that the configuration changes immediately upon writing to the  
last bit of the register. For multibyte transfers, writing to this  
register can occur during the middle of the communication cycle.  
Care must be taken to compensate for this new configuration  
for the remaining bytes of the current communication cycle.  
Table 14. Byte Transfer Count  
N1  
0
N0  
0
Description  
Transfer 1 byte  
Transfer 2 bytes  
Transfer 3 bytes  
Transfer 4 bytes  
0
1
1
0
1
1
The same considerations apply to setting the software reset,  
SWRST (Register 0x00, Bit 5). All registers are set to their default  
values except Register 0x00, which remains unchanged.  
Serial Interface Port Pin Descriptions  
SCLK—Serial Clock. The serial clock pin is used to synchronize  
data to and from the AD9704/AD9705/AD9706/AD9707and to  
run the internal state machines. The SCLK maximum frequency  
is 20 MHz. All data input to the AD9704/AD9705/AD9706/  
AD9707 is registered on the rising edge of SCLK. All data is  
driven out of the AD9704/AD9705/AD9706/AD9707 on the  
falling edge of SCLK.  
Use of single byte transfers is recommended when changing  
serial port configurations or initiating a software reset to  
prevent unexpected device behavior.  
Rev. D | Page 31 of 42  
 
 
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
INSTRUCTION CYCLE  
DATA TRANSFER CYCLE  
INSTRUCTION CYCLE  
DATA TRANSFER CYCLE  
CSB  
CSB  
SCLK  
SDIO  
SCLK  
A0 A1 A2 A3 A4 N0 N1 R/W  
D0  
D10 D20  
D4N D5N D6N D7N  
SDIO  
SDO  
R/W N1 N0 A4 A3 A2 A1 A0 D7N D6N D5N  
D30 D20 D10 D00  
Figure 75. Serial Register Interface Timing, LSB First Read  
Figure 72. Serial Register Interface Timing, MSB First Write  
tDS  
INSTRUCTION CYCLE  
DATA TRANSFER CYCLE  
tSCLK  
CSB  
CSB  
tPWH  
tPWL  
SCLK  
SCLK  
R/W N1 N0 A4 A3 A2 A1 A0  
D7  
D6N D5N  
D30 D20 D10 D00  
tDS  
SDIO  
SDO  
tDH  
INSTRUCTION BIT 7  
INSTRUCTION BIT 6  
SDIO  
Figure 76. Timing Diagram for SPI Register Write  
Figure 73. Serial Register Interface Timing, MSB First Read  
CSB  
INSTRUCTION CYCLE  
DATA TRANSFER CYCLE  
CSB  
SCLK  
SDIO  
SCLK  
t
SU  
t
HLD  
A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20  
D4N D5N D6N D7N  
I1  
I0  
D7  
D6  
D5  
SDIO  
Figure 74. Serial Register Interface Timing, LSB First Write  
Figure 77. Timing Diagram for SPI Register Read  
SPI REGISTER MAP  
Table 15.  
Mnemonic Addr Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SPI CTL  
Data  
0x00 SDIODIR  
0x02 DATAFMT  
0x0D  
DATADIR SWRST  
LNGINS  
DCLKPOL  
PDN  
Sleep  
CLKOFF  
EXREF  
DESKEW  
VER[3]  
CLKDIFF  
VER[2]  
CALCLK  
VER[0]  
Version  
CALMEM  
VER[1]  
0x0E  
CALMEM[1]  
CALMEM[0]  
DIVSEL[2]  
SMEMRD  
DIVSEL[1]  
DIVSEL[0]  
UNCAL  
MEMRDWR 0x0F CALSTAT  
MEMADDR 0x10  
CALEN  
SMEMWR  
MEMADDR[5] MEMADDR[4] MEMADDR[3] MEMADDR[2] MEMADDR[1] MEMADDR[0]  
MEMDATA[5] MEMDATA[4] MEMDATA[3] MEMDATA[2] MEMDATA[1] MEMDATA[0]  
MEMDATA  
0x11  
Rev. D | Page 32 of 42  
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
SPI REGISTER DESCRIPTIONS  
Table 16. SPI CTL—Register 0x00  
Mnemonic Bit No.  
Direction (I/O)  
Default Description  
SDIODIR  
7
I
1
0 = SDIO pin configured for input only during data transfer (4-wire interface).  
1 = SDIO pin configured for input or output during data transfer (3-wire interface).  
0 = Serial data uses MSB first format.  
DATADIR  
6
I
0
1 = Serial data uses LSB first format.  
SWRST  
5
4
I
I
0
0
1 = initiates a software reset; this bit is set to 0 upon reset completion.  
0 = uses 1 byte preamble (5 address bits).  
LNGINS  
1 = uses 2 byte preamble (13 address bits).  
PDN  
3
2
1
0
I
I
I
I
0
0
0
0
1 = shuts down DAC output current internal band gap reference.  
1 = DAC output current off.  
Sleep  
CLKOFF  
EXREF  
1 = disables internal master clock.  
0 = internal band gap reference.  
1 = external reference.  
Table 17. Data—Register 0x02  
Mnemonic Bit No. Direction (I/O)  
Default  
Description  
DATAFMT  
DCLKPOL  
DESKEW  
7
4
3
I
I
I
0
0
0
0 = unsigned binary input data format  
1 = twos complement input data format  
0 = data latched on DATACLK rising edge always  
1 = data latched on DATACLK falling edge (only active in DESKEW mode)  
0 = DESKEW mode disabled.  
1 = DESKEW mode enabled (adds a register in digital data path to remove  
skew in received data; one clock cycle of latency is introduced)  
CLKDIFF  
CALCLK  
2
0
I
I
0
0
0 = single-ended clock input  
1 = differential clock input  
0 = calibration clock disabled  
1 = calibration clock enabled  
Table 18. Version—Register 0x0D  
Mnemonic  
Bit No.  
Direction (I/O)  
Default  
Description  
VER[3:0]  
[3:0]  
O
0000  
Hardware version identifier  
Table 19. CALMEM—Register 0x0E  
Mnemonic  
Bit No.  
Direction (I/O)  
Default  
Description  
CALMEM[1:0] [5:4]  
O
00  
Calibration memory  
00 = uncalibrated  
01 = self-calibration  
10 = not used  
11 = user input  
DIVSEL[2:0]  
[2:0]  
I
000  
Calibration clock divide ratio from DAC clock rate  
000 = divide by 256  
001 = divide by 128  
110 = divide by 4  
111 = divide by 2  
Rev. D | Page 33 of 42  
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
Table 20. MEMRDWR—Register 0x0F  
Mnemonic  
CALSTAT  
CALEN  
Bit No.  
Direction (I/O)  
Default  
Description  
7
6
3
2
0
O
I
0
0
0
0
0
1 = calibration cycle complete  
1 = initiates device self-calibration  
1 = writes to static memory (calibration coefficients)  
1 = reads from static memory (calibration coefficients)  
SMEMWR  
SMEMRD  
UNCAL  
I
I
I
1 = resets calibration coefficients to default (uncalibrated)  
Table 21. MEMADDR—Register 0x10  
Mnemonic  
Bit No.  
Direction (I/O)  
Default  
Description  
MEMADDR[5:0]  
[5:0]  
I/O  
000000  
Address of static memory to be accessed  
Table 22. MEMDATA—Register 0x11  
Mnemonic  
Bit No.  
Direction (I/O)  
Default  
Description  
MEMDATA[5:0]  
[5:0]  
I/O  
111111  
Data for static memory access  
REFERENCE OPERATION  
Table 23. Reference Operation  
The AD9704/AD9705/AD9706/AD9707 contain an internal 1.0 V  
band gap reference. The internal reference can be disabled by  
writing a Logic 1 to Register 0x00, Bit 0 (EXREF) in the SPI.  
Reference  
Mode  
REFIO Pin  
Register Setting  
Internal  
Connect 0.1 µF capacitor  
Register 0x00, Bit 0 = 0  
(default)  
The internal 1.0 V band gap reference may on occasion power  
up in a state that leaves the DAC output nonfunctional. To clear  
this state, power up again, and check that the voltage on the  
REFIO pin is within the reference output specifications shown  
in Table 1 or Table 4. After the internal reference is powered up  
correctly, it does not fail as long as power is applied.  
External  
Apply external reference  
Register 0x00, Bit 0 = 1  
(for power saving)  
An external reference can be used in applications requiring  
tighter gain tolerances or lower temperature drift. Also, a variable  
external voltage reference can be used to implement a method  
for gain control of the DAC output. The external reference is  
applied to the REFIO pin. Note that the 0.1 μF compensation  
capacitor is not required. The internal reference can be directly  
overdriven by the external reference, or the internal reference  
can be powered down. The input impedance of REFIO is 10 kΩ  
when powered up and 1 MΩ when powered down.  
To use the internal reference, decouple the REFIO pin to ACOM  
with a 0.1 μF capacitor, enable the internal reference by writing  
a Logic 0 to Register 0x00, Bit 0 in the SPI. (Note that this is the  
default configuration.) The internal reference voltage is present  
at REFIO. If the voltage at REFIO is to be used anywhere else in  
the circuit, an external buffer amplifier with an input bias current of  
less than 100 nA must be used to avoid loading the reference. An  
example of the use of the internal reference is shown in Figure 78.  
REFERENCE CONTROL AMPLIFIER  
The AD9704/AD9705/AD9706/AD9707 contain a control  
amplifier that regulates the full-scale output current, IOUTFS. The  
control amplifier is configured as a V-I converter, as shown in  
Figure 78. The output current, IREF, is determined by the ratio of  
the VREFIO and an external resistor, RSET, as stated in Equation 4.  
IREF is mirrored to the segmented current sources with the  
proper scale factor to set IOUTFS, as stated in Equation 3.  
AD9704/AD9705/  
AD9706/AD9707  
DAC  
V
BG  
1.0V  
REFIO  
+
FS ADJ  
CURRENT  
SCALING  
x32  
0.1µF  
IOUTFS  
R
SET  
The control amplifier allows a 5:1 adjustment span of IOUTFS from  
1 mA to 5 mA by setting IREF between 31.25 μA and 156.25 μA  
(RSET between 6.4 kΩ and 32 kΩ). The wide adjustment span of  
IOUTFS provides several benefits. The first relates directly to the  
power dissipation of the AD9704/AD9705/AD9706/AD9707,  
which is proportional to IOUTFS (see the Power Dissipation section).  
The second benefit relates to the ability to adjust the output over a  
14 dB range, which is useful for controlling the transmitted power.  
I
REF  
AVSS  
Figure 78. Internal Reference Configuration  
REFIO serves as either an input or an output, depending on  
whether the internal or an external reference is used. Table 23  
summarizes the reference operation.  
Rev. D | Page 34 of 42  
 
 
Data Sheet  
AD9704/AD9705/AD9706/AD9707  
DAC TRANSFER FUNCTION  
ANALOG OUTPUTS  
The AD9704/AD9705/AD9706/AD9707 provide complementary  
current outputs, IOUTA and IOUTB. IOUTA provides a near  
full-scale current output, IOUTFS, when all bits are high (that is,  
DAC CODE = 2N − 1, where N = 8, 10, 12, or 14 for the AD9704,  
AD9705, AD9706, and AD9707, respectively), while IOUTB, the  
complementary output, provides no current. The current output  
appearing at IOUTA and IOUTB is a function of both the input  
code and IOUTFS and can be expressed as  
The complementary current outputs in each DAC, IOUTA, and  
IOUTB can be configured for single-ended or differential oper-  
ation. IOUTA and IOUTB can be converted into complementary  
single-ended voltage outputs, VIOUTA and VIOUTB, via a load resistor,  
RLOAD, as described in the DAC Transfer Function section by  
Equation 5 through Equation 8. The differential voltage, VDIFF  
,
existing between VIOUTA and VIOUTB, can also be converted to a  
single-ended voltage via a transformer or a differential amplifier  
configuration. The ac performance of the AD9704/AD9705/  
AD9706/AD9707 is optimum and is specified using a differential  
transformer-coupled output in which the voltage swing at  
IOUTA and IOUTB is limited to 0.5 V.  
N
IOUTA = (DAC CODE/2 ) × IOUTFS  
(1)  
(2)  
N N  
IOUTB = ((2 − 1) − DAC CODE)/2 × IOUTFS  
N
where DAC CODE = 0 to 2 − 1 (that is, decimal representation).  
I
OUTFS is a function of the reference current, IREF, which is  
The distortion and noise performance of the AD9704/AD9705/  
AD9706/AD9707 can be enhanced when it is configured for  
differential operation. The common-mode error sources of both  
IOUTA and IOUTB can be significantly reduced by the common-  
mode rejection of a transformer or differential amplifier. These  
common-mode error sources include even-order distortion  
products and noise. The enhancement in distortion performance  
becomes more significant as the frequency content of the  
reconstructed waveform increases and/or its amplitude increases.  
This is due to the first-order cancellation of various dynamic  
common-mode distortion mechanisms, digital feedthrough,  
and noise.  
nominally set by a reference voltage, VREFIO, and an external  
resistor, RSET. It can be expressed as  
IOUTFS = 32 × IREF  
where  
(3)  
(4)  
IREF = VREFIO/RSET  
The two current outputs typically drive a resistive load directly  
or via a transformer. If dc coupling is required, IOUTA and  
IOUTB should be connected to matching resistive loads (RLOAD  
that are tied to analog common (ACOM). The single-ended  
)
voltage output appearing at the IOUTA and IOUTB nodes is  
Performing a differential-to-single-ended conversion via a  
transformer also provides the ability to deliver twice the  
reconstructed signal power to the load (assuming no source  
termination). Because the output currents of IOUTA and  
IOUTB are complementary, they become additive when  
processed differentially.  
V
IOUTA = IOUTA × RLOAD  
(5)  
(6)  
VIOUTB = IOUTB × RLOAD  
To achieve the maximum output compliance of 1 V at the  
nominal 2 mA output current, RLOAD must be set to 500 Ω.  
Also, the full-scale value of VIOUTA and VIOUTB must not exceed  
the specified output compliance range to maintain specified  
distortion and linearity performance.  
When the AD9704/AD9705/AD9706/AD9707 is being used at its  
nominal operating point of 2 mA output current and 0.5 V output  
swing is desired, RLOAD must be set to 250 Ω. A properly selected  
transformer allows the AD9704/AD9705/AD9706/AD9707 to  
provide the required power and voltage levels to different loads.  
VDIFF = (IOUTA IOUTB) × RLOAD  
(7)  
Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be  
expressed as  
The output impedance of IOUTA and IOUTB is determined by  
the equivalent parallel combination of the PMOS switches  
associated with the current sources and is typically 200 MΩ in  
parallel with 5 pF. It is also slightly dependent on the output  
voltage (that is, VIOUTA and VIOUTB) due to the nature of a PMOS  
device. As a result, maintaining IOUTA and/or IOUTB at a  
virtual ground via an I-V op amp configuration results in the  
optimum dc linearity. Note that the INL/DNL specifications for  
the AD9704/AD9705/AD9706/AD9707 are measured with IOUTA  
maintained at a virtual ground via an op amp.  
N N  
VDIFF = {(2 × DAC CODE – (2 − 1))/2 } ×  
(32 × VREFIO/RSET) × RLOAD  
(8)  
Equation 7 and Equation 8 highlight some of the advantages of  
operating the AD9704/AD9705/AD9706/AD9707 differentially.  
First, the differential operation helps cancel common-mode error  
sources associated with IOUTA and IOUTB, such as noise,  
distortion, and dc offsets. Second, the differential code dependent  
current and subsequent voltage, VDIFF, is twice the value of the  
single-ended voltage output (that is, VIOUTA or VIOUTB), thus  
providing twice the signal power to the load.  
IOUTA and IOUTB also have a negative and positive voltage  
compliance range that must be adhered to in order to achieve  
optimum performance. The absolute maximum negative output  
compliance range of −1 V is set by the breakdown limits of the  
CMOS process. Operation beyond this maximum limit can result  
in a breakdown of the output stage and affect the reliability of  
the AD9704/AD9705/AD9706/AD9707.  
The gain drift temperature performance for a single-ended  
output (VIOUTA and VIOUTB) or the differential output (VDIFF) of  
the AD9704/AD9705/AD9706/AD9707 can be enhanced by  
selecting temperature tracking resistors for RLOAD and RSET  
,
because of their ratiometric relationship, as shown in Equation 8.  
Rev. D | Page 35 of 42  
 
AD9704/AD9705/AD9706/AD9707  
Data Sheet  
The positive output compliance range is slightly dependent on  
the full-scale output current, IOUTFS. It degrades slightly from its  
nominal 1.0 V for an IOUTFS = 2 mA to 0.8 V for an IOUTFS = 1 mA.  
The optimum distortion performance for a single-ended or  
differential output is achieved when the maximum full-scale  
signal at IOUTA and IOUTB does not exceed 0.5 V.  
The digital interface is implemented using an edge-triggered  
master/slave latch. The DAC output updates on the rising edge  
of the clock and is designed to support a clock rate as high as  
175 MSPS. The clock can be operated at any duty cycle that meets  
the specified latch pulse width. The setup and hold times can  
also be varied within the clock cycle, as long as the specified  
minimum times are met, although the location of these transition  
edges may affect digital feedthrough and distortion performance.  
Best performance is typically achieved when the input data  
transitions on the falling edge of a 50% duty cycle clock.