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产品型号AD9768SD的Datasheet PDF文件预览

Ultrahigh Speed IC  
D/A Converter  
a
AD9768  
FEATURES  
FUNCTIO NAL BLO CK D IAGRAM  
5 ns Settling Tim e  
100 MSPS Update Rate  
20 m A Output Current  
ECL-Com patible  
40 MHz Multiplying Mode  
APPLICATIONS  
Raster Scan & Vector Graphic Displays  
High Speed Waveform Generation  
Digital VCOs  
Ultrafast Digital Attenuators  
GENERAL D ESCRIP TIO N  
T he Analog Devices AD9768SD D/A converter is a monolithic  
current-output converter which can accept 8 bits of ECL-level  
digital input voltages and convert them into analog signals at  
update rates as high as 100 MSPS. In addition to its use as a  
standard D/A converter, it can also be utilized as a two-quadrant  
multiplying D/A at multiplying bandwidths as high as 40 MHz.  
T he reference voltage source is a modified bandgap type  
and is nominally –1.26 volts. This reference supply requires  
no external regulation. T o reduce the possibility of noise  
generation and/or instability, Pin 15 (REFERENCE OUT )  
can be decoupled using a high-quality ceramic chip  
capacitor. Stabilization of the internal loop amplifier is by a  
single capacitor connected from Pin 17 (COMPENSATION)  
to ground. The minimum value for this capacitor is 3900 pF,  
although a 0.01 µF ceramic chip capacitor is recommended.  
An inherently low glitch design is used, and the complementary  
current outputs are suitable for driving transmission lines  
directly. Nominal full-scale output is 20 mA, which corresponds  
to a 1 volt drop across a 50 load, or ±1 volt across 100 Ω  
returned to +1 volt. T he actual output current is determined by  
the on-chip reference voltage (VREF Ϸ –1.26 V) and an external  
current setting resistor, RSET  
.
Full-scale output current IOUT with digital “1” at all inputs is  
calculated with the equation:  
T he incredible speed characteristics of the AD9768SD D/A  
converter make it attractive for a wide range of high speed  
applications. T he ability of the unit to operate as a two-  
quadrant multiplying D/A converter adds another dimen-  
sion to its usefulness and makes the AD9768SD a truly  
versatile device.  
VRET VREF  
IOUT = 4 ×  
RSET  
T he setting resistor RSET and the output load resistor should  
both have low temperature coefficients. A complementary  
AD 9768SE P IN CO NNECTIO NS  
is also provided.  
IOUT  
AD 9768JD /SD P IN CO NNECTIO NS  
REV. A  
Inform ation furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assum ed by Analog Devices for its  
use, nor for any infringem ents of patents or other rights of third parties  
which m ay result from its use. No license is granted by im plication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.  
Tel: 617/ 329-4700  
Fax: 617/ 326-8703  
(typical @ +25؇C under following conditions unless otherwise noted; nominal digital  
input levels; nominal power supplies; R = 50 ; RSET = 220 ; V = 0 V)  
AD9768–SPECIFICATIONS  
L
RET  
P aram eter  
Unit  
Bits  
µA  
AD 9768SJD /SD /SE  
P aram eter  
Unit  
AD 9768SJD /SD /SE  
RESOLUT ION(FS = FULL SCALE)  
8
CURRENT -MULT IPLYING MODE  
(See Figure 4)  
LSB WEIGHT (CURRENT )  
78  
IM Range (at Pins 17 & 18)  
Resistance (at Pin 18)  
mA  
0 to 5  
160  
ACCURACY1  
Differential Nonlinearity  
Integral Nonlinearity  
Monotonicity  
± % FS  
± % FS  
0.2  
0.2  
T ransfer Function –  
Measured at Pin 13; Digital “0” Applied  
to Bits 1-8:  
Guaranteed  
60  
1 mA IM Input = 0 mA IOUT  
5 mA IM Input = 0 mA IOUT  
Measured at Pin 13; Digital “1” Applied  
to Bits 1-8:  
Zero Offset (lnitial)  
µA  
T EMPERAT URE COEFFICIENT S  
Zero Offset  
Reference Voltage (–1.26 V)  
ppm/°C  
ppm/°C  
1.5  
70  
1 mA IM Input = 4 mA IOUT  
5 mA IM Input = 20 mA IOUT  
40  
DIGIT AL DAT A INPUT S  
Logic Compatibility  
Logic Voltage Levels “l” =  
“0” =  
Large Signal Bandwidth (–3dB Point) MHz  
POWER REQUIREMENT S  
–5.2 V ±0.25  
ECL  
–0.9  
–1.7  
V
V
mA (max)  
mA (max)  
66(70)  
+5.0 V ±0.25  
14(15)  
410(430)  
0.07  
Coding  
Binary (BIN) = Unipolar Out  
Offset Binary (OBN) = Bipolar Out  
Power Dissipation  
mW (max)  
%/%  
Power Supply Sensitivity5  
OUT PUT  
Current (Unipolar) FS  
IOUT (@ Pin 13)  
All Digital “1” Input  
All Digital “0” Input  
IOUT (@ Pin 14)  
mA (max)  
2 to 20 (30)  
T EMPERAT URE RANGES6  
Operating  
mA  
mA  
20  
0
AD9768JD  
AD9768SD/SE  
Storage  
°C  
°C  
°C  
0 to +70  
–55 to +125  
–55 to +150  
All Digital “l” Input  
All Digital “0” Input  
Compliance  
mA  
mA  
V (Pin 13)  
V (Pin 14)  
(±15%)  
0
20  
T HERMAL RESlST ANCE 7  
Junction to Air, θJA (Free Air)  
Junction to Case, θJA  
PACKAGE OPT ION8  
Ceramic (D-18)  
°C/W  
°C/W  
90  
20  
–0.7 to +3.0  
–1.1 to +3.0  
750  
Impedance  
AD9768JD  
AD9768SD  
AD9768SE  
SPEED PERFORMANCE  
Settling T ime (to 0.2% FS)2  
Slew Rate  
Update Rate  
Rise T ime  
ns  
5
LCC (E-20A)  
V/µs  
MSPS  
ns  
400  
100  
1.8  
200  
NOT ES  
1Relative to FS, including linearity (within voltage compliance limits).  
Glitch Energy  
pV-sec  
2Worst case settling time; includes FS and Most Significant Bit (MSB) transitions.  
3Applies when operating AD9768 as standard D/A.  
4Based on RL = 50 ohms; RSET = 220 ohms; VRET = 0 V.  
51% change in either power supply voltage causes 0.07% change in analog output.  
6Case temperature.  
REFERENCE  
Internal, Monolithic3  
External, Variable4  
V
–1.26  
Voltage-Multiplying Mode  
Current-Multiplying Mode  
VOLT AGE-MULT IPLYING MODE4 (See Figure 2)  
VM Range (at Pin 16)  
VM Center  
Resistance (at Pin 16)  
V (max)  
mA (max)  
0 to –1.1 (–2)  
0 to –5 (–7.5 )  
7Maximum junction temperature 125°C.  
8D = Ceramic DIP, E = Leadless Ceramic Chip Carrier.  
Specifications subject to change without notice.  
V
V
kΩ  
±0.5  
–0.6  
800  
T ransfer Function –  
Measured at Pin 13; Digital “0” Applied  
to Bits 1-8:  
–0.1 VM Input = 0 mA IOUT  
–1.1 VM Input = 0 mA IOUT  
Measured at Pin 13; Digital “1” Applied  
to Bits 1-8:  
–0.1 VM Input = 1 mA IOUT  
–1.1 VM Input = 20 mA IOUT  
Large Signal Bandwidth (–3 dB Point)  
kHz  
250  
AD9768SD D/A Schem atic  
–2–  
REV. A  
AD9768  
speed, high performance device: optimum use requires careful  
attention to all design details, including the layout of the circuit  
in which the converter is used.  
TH EO RY O F O P ERATIO N  
Refer to the AD9768SD schematic.  
T he transistors pictured on the bottom of the diagram, con-  
nected to paired transistors in the middle of the schematic, are  
current sources which are always “on”. T he paired transistors  
are differential current switches, designed to steer current from  
CO NVENTIO NAL AD 9768SD  
Refer to Figure 1, Conventional AD9768SD.  
T he output current of the AD9768 appears at Pin 13 (IO) and  
develops a voltage across the load resistor RL which is based on:  
the current sources to either Pin 13 (IO) or Pin 14 (  
).  
IO  
Digital inputs applied to Pins 1-8 determine which transistors  
will be operating in each pair and establish what current will  
flow at Pins 13 and 14.  
A. IM (the current flowing through the single-transistor  
source discussed above)  
B. Value of RL  
T he transistor on the extreme left of the schematic is a base  
reference for the paired current switches and is used to assure  
the switches will be centered around an ECL voltage swing. T he  
diodes connected to the base of this transistor are temperature  
compensation devices for the base reference circuit.  
T here are three different current sources in the AD9768 D/A.  
T he eight transistors shown on the bottom of the schematic are  
structured as two identical groups of four current sources, each  
of which is binarily weighted. T he MSB group, comprised of the  
four on the right, is connected to the LSB group through a 15:1  
current divider made up of two 50 and two 750 resistor  
networks. T he geometry of the AD9768 guarantees the binary  
weighing ratios among the 100, 200, 400 and 800 resistors in  
each emitter circuit are correct.  
Figure 1. Conventional AD9768SD  
IM is a function of the return voltage (VRET ), the reference  
voltage (VREF), and the value of RSET ; all of these are selected by  
the user for his application. T he necessary equations for  
calculating precise values for each are part of Figure 1. As  
indicated, the voltage drop across RL is added to the return  
voltage; the resulting voltage is the total VOUT of the converter.  
T he resistor values which are shown indicate the ratios among  
the resistors, and not their nominal values.  
T he third current source is a single transistor, pictured in the  
lower left portion of the schematic with its collector connected  
to Pin 18 RSET . Its function is to help establish the base voltage  
on the eight current sources; it works in conjunction with the  
external RSET resistor selected by the user of the AD9768, and  
the reference amplifier. Current flowing through this transistor  
is referred to as IM in the figures and text.  
VO LTAGE MULTIP LYING MO D E  
In addition to its use as an ultra-high speed current output D/A  
converter, the AD9768 can also be used as a two-quadrant  
multiplying D/A in either a voltage mode or a current mode.  
When the AD9768 is operating as a conventional current-output  
D/A converter, IM develops a voltage across RSET which is one of  
the inputs to the on-board reference amplifier shown in the  
schematic. T he other input to this amplifier is the on-chip  
reference voltage of –1.26 volts.  
Refer to Figure 2, Multiplying AD9768 (Voltage Mode).  
When operating in this mode, the analog output of the AD9768  
is influenced by the digital inputs and an external multiplying  
voltage (VM) applied to Pin 16 REFERENCE IN, which takes  
the place of the internal reference used when the D/A is  
operating in a conventional manner.  
T he output of the reference amplifier adjusts the current-source  
base reference voltage at Pin 17; this, in turn, adjusts the value  
of IM in the single-transistor current source and causes it to  
develop a voltage across RSET which maintains Pin 18 at the  
–1.26 volts of the on-chip reference supply.  
T o maintain good stability in the internal loop reference  
amplifier, a ceramic chip capacitor with a nominal value of  
0.01 µF should be connected to Pin 17 COMPENSAT ION;  
minimum recommended value for this capacitor is 3900 pF.  
T he temperature coefficient of the load resistor (RL) can affect  
the performance of the AD9768 D/A converter, as it can with  
any current-output converter. T he design and use of the  
AD9768 and its dependence on an external RSET resistor, how-  
ever, make it sensitive also to the tempco of RSET . T he user is  
cautioned to select RL and RSET resistors which have low tem-  
perature coefficients.  
Figure 2. Multiplying AD9768 (Voltage Mode)  
T he value of IM flowing through RSET is set by the voltage of  
VRET minus the multiplying voltage (VM), divided by RSET ; the  
amount of this current is part of the equation which establishes  
the analog output (VOUT ) of the AD9768 and is chosen by the  
user for his application. As it is when operating the D/A in a  
conventional fashion, VRET can be any value between 0 volts and  
+3 volts. VM (for purposes of discussion here) is some negative  
voltage and can be varied over a range which is approximately 1  
volt peak-to-peak.  
DIGIT AL GROUND (Pin 11) and ANALOG RET URN (Pin  
12) are normally connected together; this connection should be  
made as close as possible to the device case to minimize possible  
noise problems. T he AD9768 D/A is similar to any other high-  
REV. A  
–3–  
AD9768  
VIN is some voltage chosen by the user for his particular applica-  
tion; the value of this voltage is based in part on the size of the  
load resistor and the 0 mA to 5 mA range of IM. VIN can have  
frequency components as high as 40 MHz. VADJ and RADJ pro-  
vide an offset adjustment to compensate for the dc component  
of VIN to assure IM is always a unipolar current between 0 mA  
and 5 mA. T he values of the required voltages and resistors can  
be calculated using the equations which are part of Figure 4.  
If the load resistor (RL) has a value of 50 ohms, if RSET has a  
value of 220 ohms, and if VRET is 0 V, the center of the VM  
voltage will be –0.6 V; and it can vary from –0.1 V to –1.1 V.  
T ypically, the frequency of these variations has an upper limit of  
250 kHz when operating in the voltage multiplying mode; that  
frequency is the 3 dB point of the bandwidth of the internal  
reference amplifier.  
T he combined effects of variations in VM and changes in digital  
input values are shown in Figure 3, IOUT vs. Multiplying Volt-  
age. In this illustration, the ordinate of the graph is expressed in  
terms of milliamps of IOUT current at Pin 13. VOUT , of course,  
will be a function of the value of RL chosen by the user.  
Refer to Figure 5, IOUT vs. Multiplying Current.  
Figure 5. IOUT vs. Multiplying Current  
As shown, IM can vary over the range of 0 mA to 5 mA; a value  
of approximately 0.3 mA may be the practical lower limit because  
of nonlinearities at extremely small current levels. T hese changes  
in IM are combined with variations in digital inputs, producing  
Figure 3. IOUT vs. Multiplying Voltage  
T he negative value of VM on the horizontal axis is shown start-  
ing at approximately –0.1 V, rather than 0 V, because the  
AD9768 must have some small value of voltage applied to per-  
form a multiplying function. For the conditions shown in the  
figure, output current starts to become nonlinear at approxi-  
mately 20 mA because of the maximum 30 mA output drive  
capabilities of the device. Different values for RSET and RL  
would alter the point where limiting first appears.  
complex changes in the output current (at pin 13) and in VOUT  
.
T he “rounding” of the current curve in the graph is the result of  
IOUT approaching the 30 mA maximum drive capabilities of the  
AD9768 and needs to be taken into account to assure optimum  
performance in the selected application.  
O UTLINE D IMENSIO NS  
D imensions shown in inches and (mm).  
CURRENT MULTIP LYING MO D E  
Cer am ic (D -18)  
T he AD9768 D/A converter can be operated at markedly higher  
multiplying rates when operated in a current-multiplying mode,  
as contrasted with the voltage multiplying mode. Refer to Figure  
4, Multiplying AD9768SD (Current Mode).  
LCC (E-20A)  
Figure 4. Multiplying AD9768SD (Current Mode)  
In this mode, the internal reference amplifier and its inherent  
frequency limitations are replaced by a current source comprised  
of U1 and associated circuits. T hese circuits supply a unipolar  
current IM which is one-fourth the full-scale output current  
(with digital “1” applied to all inputs) and set current flow  
through the load resistor.  
–4–  
REV. A  
配单直通车
AD9768SD产品参数
型号:AD9768SD
是否Rohs认证: 不符合
生命周期:Obsolete
零件包装代码:DIP
包装说明:HERMETIC SEALED, CERAMIC, DIP-18
针数:18
Reach Compliance Code:not_compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.76
转换器类型:D/A CONVERTER
输入位码:BINARY, OFFSET BINARY
输入格式:PARALLEL, 8 BITS
JESD-30 代码:R-CDIP-T18
JESD-609代码:e0
标称负供电电压:-5.2 V
位数:8
功能数量:1
端子数量:18
最高工作温度:125 °C
最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP
封装等效代码:DIP18,.3
封装形状:RECTANGULAR
封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED
电源:5,-5.2 V
认证状态:Not Qualified
座面最大高度:5.08 mm
标称安定时间 (tstl):0.005 µs
子类别:Other Converters
最大压摆率:70 mA
标称供电电压:5 V
表面贴装:NO
技术:BIPOLAR
温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE
端子节距:2.54 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mm
Base Number Matches:1
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