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  • AD9852ASVZ图
  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
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  • 数量8800 
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
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     该会员已使用本站15年以上
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
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  • 深圳市晶美隆科技有限公司

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  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
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  • 数量15000 
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  • 集好芯城

     该会员已使用本站13年以上
  • AD9852ASVZ
  • 数量14791 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • AD9852ASVZ
  • 数量15862 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • AD9852ASVZ
  • 数量15862 
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • AD9852ASVZ
  • 数量7548 
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  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • AD9852ASVZ
  • 数量26700 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • AD9852ASVZ
  • 数量12500 
  • 厂家ADI/亚德诺 
  • 封装NA 
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  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • AD9852ASVZ
  • 数量8800 
  • 厂家ADI/亚德诺 
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  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • AD9852ASVZ
  • 数量12500 
  • 厂家ADI/亚德诺 
  • 封装NA 
  • 批号24+ 
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • AD9852ASVZ
  • 数量12300 
  • 厂家ADI/亚德诺 
  • 封装TQFP 
  • 批号24+ 
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • AD9852ASVZ
  • 数量3817 
  • 厂家ADI 
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  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • AD9852ASVZ
  • 数量5369 
  • 厂家AD 
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  • 批号24+ 
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • AD9852ASVZ
  • 数量98500 
  • 厂家AD 
  • 封装TQFP 
  • 批号23+ 
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  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • AD9852ASVZ
  • 数量865000 
  • 厂家ADI/亚德诺 
  • 封装QFP 
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  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • AD9852ASVZ
  • 数量5000 
  • 厂家
  • 封装ADI 
  • 批号16+ 
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  • 深圳市恒意法科技有限公司

     该会员已使用本站17年以上
  • AD9852ASVZ
  • 数量9000 
  • 厂家Analog Devices Inc. 
  • 封装80-TQFP 裸露焊盘 
  • 批号21+ 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • AD9852ASVZ
  • 数量20465 
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • AD9852ASVZ
  • 数量6500 
  • 厂家ADI 
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  • 批号24+ 
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  • 深圳市一呈科技有限公司

     该会员已使用本站9年以上
  • AD9852ASVZ
  • 数量3210 
  • 厂家ADI(亚德诺) 
  • 封装TQFP-80 
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  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • AD9852ASVZ
  • 数量9220 
  • 厂家AD 
  • 封装TQFP 
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • AD9852ASVZ
  • 数量1424 
  • 厂家AD 
  • 封装TQFP 
  • 批号24+ 
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  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • AD9852ASVZ
  • 数量55350 
  • 厂家AD 
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  • 批号17+ 
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  • 上海熠富电子科技有限公司

     该会员已使用本站15年以上
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  • 数量8000 
  • 厂家ADI 
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     该会员已使用本站2年以上
  • AD9852ASVZ
  • 数量45200 
  • 厂家ADI(亚德诺) 
  • 封装TQFP-80 
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产品型号AD9852ASVZ的概述

AD9852ASVZ概述 AD9852ASVZ是一款高性能的数字频率合成器,属于Analog Devices公司生产的系列产品。该芯片利用直接数字合成(DDS)技术,能够生成宽频率范围内的稳定正弦波信号。借助其集成的数字电路,AD9852ASVZ能够实现高精度、低相位噪声的频率合成,广泛应用于通信、信号处理、测量仪器等领域。 AD9852ASVZ的工作频率范围通常在0 Hz到150 MHz之间,主要依赖于系统提供的时钟频率,以及内部的设计架构。相较于传统的模拟频率合成器,AD9852ASVZ具备更高的频率解析度和更好的相位噪声特性,这使得其在现代通信系统中占据了重要的位置。 详细参数 AD9852ASVZ的主要技术参数包括: - 频率范围:0 Hz 至 150 MHz - 分辨率:32 位频率调制 - 输出类型:正弦波 - 相位噪声(在100 kHz偏移):-130 dBc/Hz - ...

产品型号AD9852ASVZ的Datasheet PDF文件预览

CMOS 300 MSPS Complete DDS  
AD9852  
Frequency ramped FSK  
FEATURES  
<25 ps rms total jitter in clock generator mode  
Automatic bidirectional frequency sweeping  
Sin(x)/x correction  
300 MHz internal clock rate  
FSK, BPSK, PSK, chirp, AM operation  
Dual integrated 12-bit D/A converters  
Ultrahigh speed comparator, 3 ps rms jitter  
Excellent dynamic performance  
80 dB SFDR at 100 MHz ( 1 MHz) AOUT  
4× to 20× programmable reference clock multiplier  
Dual 48-bit programmable frequency registers  
Dual 14-bit programmable phase offset registers  
12-bit programmable amplitude modulation and on/off  
output shaped keying function  
Simplified control interface  
10 MHz serial 2-wire or 3-wire SPI-compatible  
100 MHz parallel 8-bit programming  
3.3 V single supply  
Multiple power-down functions  
Single-ended or differential input reference clock  
Small, 80-lead LQFP or TQFP with exposed pad  
APPLICATIONS  
Single-pin FSK and BPSK data interfaces  
PSK capability via I/O interface  
Linear or nonlinear FM chirp functions with single pin  
frequency hold function  
Agile LO frequency synthesis  
Programmable clock generator  
FM chirp source for radar and scanning systems  
Test and measurement equipment  
Commercial and amateur RF exciter  
FUNCTIONAL BLOCK DIAGRAM  
DIGITAL MULTIPLIERS  
SYSTEM CLOCK  
INV  
SINC  
FILTER  
DDS CORE  
12  
12  
4× TO 20×  
12-BIT  
COSINE  
DAC  
ANALOG  
OUT  
REFERENCE  
CLOCK IN  
I
REFCLK  
BUFFER  
REFCLK  
MULTIPLIER  
48  
48  
17  
17  
SYSTEM  
CLOCK  
DAC R  
SET  
DIFF/SINGLE  
SELECT  
MUX  
12-BIT  
CONTROL  
DAC  
ANALOG  
OUT  
SYSTEM  
CLOCK  
14  
48  
Q
12  
3
FSK/BPSK/HOLD  
DATA IN  
MUX  
48  
MUX  
MUX  
ANALOG  
IN  
DELTA  
FREQUENCY  
RATE TIMER  
PROGRAMMABLE  
AMPLITUDE AND  
RATE CONTROL  
SYSTEM  
CLOCK  
2
48  
48  
14  
COMPARATOR  
12  
SYSTEM  
CLOCK  
14  
CLOCK  
OUT  
DELTA  
FREQUENCY  
WORD  
FREQUENCY FREQUENCY  
FIRST 14-BIT  
PHASE/OFFSET  
WORD  
SECOND 14-BIT  
PHASE/OFFSET MODULATION CONTROL  
WORD  
AM  
12-BIT DC  
TUNING  
WORD 1  
TUNING  
WORD 2  
PROGRAMMING REGISTERS  
SYSTEM  
MODE SELECT  
OSK  
GND  
SYSTEM  
CLOCK  
CLK  
AD9852  
÷2  
BUS  
CLOCK  
Q
D
BIDIRECTIONAL  
INTERNAL/EXTERNAL  
I/O UPDATE CLOCK  
INT  
EXT  
INTERNAL  
PROGRAMMABLE  
UPDATE CLOCK  
I/O PORT BUFFERS  
+V  
S
READ  
WRITE SERIAL/  
6-BIT ADDRESS  
OR SERIAL  
PROGRAMMING  
LINES  
8-BIT  
PARALLEL  
LOAD  
MASTER  
RESET  
PARALLEL  
SELECT  
Figure 1.  
Rev. E  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved.  
 
AD9852  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Inverse Sinc Function ................................................................ 29  
REFCLK Multiplier.................................................................... 29  
High Speed Comparator............................................................ 30  
Power-Down ............................................................................... 30  
Programming the AD9852............................................................ 31  
MASTER RESET ........................................................................ 31  
Parallel I/O Operation ............................................................... 31  
Serial Port I/O Operation.......................................................... 31  
General Operation of the Serial Interface................................... 34  
Instruction Byte.......................................................................... 34  
Serial Interface Port Pin Descriptions ..................................... 35  
MSB/LSB Transfers .................................................................... 35  
Control Register Descriptions .................................................. 36  
Power Dissipation and Thermal Considerations ....................... 38  
Thermal Impedance................................................................... 38  
Junction Temperature Considerations .................................... 38  
Evaluation of Operating Conditions............................................ 40  
Thermally Enhanced Package Mounting Guidelines............ 40  
Evaluation Board ............................................................................ 41  
Evaluation Board Instructions.................................................. 41  
General Operating Instructions ............................................... 41  
Using the Provided Software .................................................... 43  
Support ........................................................................................ 43  
Outline Dimensions....................................................................... 51  
Ordering Guide .......................................................................... 52  
Applications....................................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 3  
General Description......................................................................... 4  
Overview........................................................................................ 4  
Specifications..................................................................................... 5  
Absolute Maximum Ratings............................................................ 8  
Thermal Resistance ...................................................................... 8  
Explanation of Test Levels........................................................... 8  
ESD Caution.................................................................................. 8  
Pin Configuration and Function Descriptions............................. 9  
Typical Performance Characteristics ........................................... 12  
Typical Applications ....................................................................... 16  
Modes of Operation ....................................................................... 18  
Single Tone (Mode 000)............................................................. 18  
Unramped FSK (Mode 001)...................................................... 19  
Ramped FSK (Mode 010).......................................................... 19  
Chirp (Mode 011)....................................................................... 22  
BPSK (Mode 100)....................................................................... 26  
Using the AD9852 .......................................................................... 27  
Internal and External Update Clock........................................ 27  
On/Off Output Shaped Keying (OSK) .................................... 27  
Cosine DAC ................................................................................ 29  
Control DAC............................................................................... 29  
Rev. E | Page 2 of 52  
AD9852  
REVISION HISTORY  
5/07—Rev. D to Rev. E  
3/02—Rev. A to Rev. B  
Changed AD9852ASQ to AD9852ASVZ ....................... Universal  
Changed AD9852AST to AD9852ASTZ......................... Universal  
Change to Features............................................................................1  
Changes to Endnote 10 of Table 1...................................................7  
Changes to Absolute Maximum Ratings........................................8  
Added Thermal Resistance Section ................................................8  
Change to Ramped FSK (Mode 010) Section..............................19  
Change to Internal and External Update Clock Section............27  
Change to Thermal Impedance Section.......................................38  
Changes to Junction Temperature Considerations Section.......38  
Changes to Thermally Enhanced Package Mounting  
Guidelines Section......................................................................40  
Deleted Figure 61 to Figure 64 ......................................................41  
Changes to Table 14 ........................................................................44  
Updated Outline Dimensions........................................................51  
Changes to Ordering Guide...........................................................52  
Changes to General Description.....................................................1  
Changes to Functional Block Diagram ..........................................1  
Changes to Specifications ................................................................3  
Changes to Absolute Maximum Ratings........................................5  
Changes to Pin Function Descriptions ..........................................6  
Changes to Figure 3 ..........................................................................8  
Deleted Two TPCs ..........................................................................11  
Changes to Figure 18 and Figure 19 .............................................11  
Changes to BPDK Mode Section ..................................................21  
Changes to Differential Refclk Enable Section ...........................24  
Changes to Master Reset Section..................................................24  
Changes to Parallel I/O Operation Section .................................24  
Changes to General Operation of the Serial  
Interface Section..............................................................................27  
Changes to Figure 50 ......................................................................27  
Changes to Figure 65 ......................................................................36  
12/05—Rev. C to Rev. D  
Updated Format.................................................................. Universal  
Changes to General Description .....................................................4  
Changes to Explanation of Test Levels Section .............................9  
Change to Pin Configuration ........................................................10  
Changes to Figure 65 ......................................................................47  
Changes to Outline Dimensions ...................................................52  
Changes to Ordering Guide...........................................................52  
4/04—Rev. B to Rev. C  
Updated Format.................................................................. Universal  
Changes to Figure 1...........................................................................1  
Changes to General Description .....................................................3  
Changes to Table 1 ............................................................................4  
Changes to Footnote 2......................................................................6  
Changes to Figure 2...........................................................................8  
Changes to Table 5 ..........................................................................17  
Changes to Equation in Ramped FSK (Mode 010).....................19  
Changes to Evaluation Board Instructions..................................39  
Changes to General Operating Instructions Section..................39  
Changes to Using the Provided Software Section.......................42  
Changes to Figure 65 ......................................................................43  
Changes to Figure 66 ......................................................................44  
Changes to Figure 72 and Figure 73 .............................................48  
Changes to Ordering Guide...........................................................48  
Rev. E | Page 3 of 52  
 
AD9852  
GENERAL DESCRIPTION  
The AD9852 programmable 4× to 20× REFCLK multiplier cir-  
cuit internally generates the 300 MHz system clock from a lower  
frequency external reference clock. This saves the user the expense  
and difficulty of implementing a 300 MHz system clock source.  
The AD9852 digital synthesizer is a highly integrated device  
that uses advanced DDS technology, coupled with an internal  
high speed, high performance D/A converter to form a digitally  
programmable, agile synthesizer function. When referenced to  
an accurate clock source, the AD9852 generates a highly stable  
frequency-, phase-, and amplitude-programmable cosine output  
that can be used as an agile LO in communications, radar, and  
many other applications. The innovative high speed DDS core  
of the AD9852 provides 48-bit frequency resolution (1 μHz  
tuning resolution with 300 MHz SYSCLK). Maintaining 17 bits  
ensures excellent SFDR.  
Direct 300 MHz clocking is also accommodated with either single-  
ended or differential inputs. Single-pin, conventional FSK and the  
enhanced spectral qualities of ramped FSK are supported. The  
AD9852 uses advanced 0.35 ꢀ CMOS technology to provide this  
high level of functionality on a single 3.3 V supply.  
The AD9852 is pin-for-pin compatible with the AD9854 single-  
tone synthesizer. The AD9852 is specified to operate over the  
extended industrial temperature range of −40°C to +85°C.  
The circuit architecture of the AD9852 allows the generation of  
output signals at frequencies up to 150 MHz, which can be  
digitally tuned at a rate of up to 100 million new frequencies  
per second. The (externally filtered) cosine wave output can be  
converted to a square wave by the internal comparator for agile  
clock generator applications. The device provides two 14-bit  
phase registers and a single pin for BPSK operation.  
OVERVIEW  
The AD9852 digital synthesizer is a highly flexible device that  
addresses a wide range of applications. The device consists of  
an NCO with a 48-bit phase accumulator, a programmable  
reference clock multiplier, an inverse sinc filter, a digital  
multiplier, two 12-bit/300 MHz DACs, a high speed analog  
comparator, and an interface logic. This highly integrated  
device can be configured to serve as a synthesized LO agile  
clock generator and FSK/BPSK modulator. The theory of  
operation for the functional blocks of the device and a technical  
description of the signal flow through a DDS device is provided  
by Analog Devices, Inc., in the tutorial A Technical Tutorial on  
Digital Signal Synthesis. The tutorial also provides basic  
applications information for a variety of digital synthesis  
implementations.  
For higher-order PSK operation, the I/O interface can be used  
for phase changes. The 12-bit cosine DAC, coupled with the  
innovative DDS architecture, provides excellent wideband and  
narrow-band output SFDR. When configured with the  
comparator, the 12-bit control DAC facilitates static duty cycle  
control in the high speed clock generator applications.  
The 12-bit digital multiplier permits programmable amplitude  
modulation, on/off output shaped keying, and precise amplitude  
control of the cosine DAC output. Chirp functionality is also  
included for wide bandwidth frequency sweeping applications.  
Rev. E | Page 4 of 52  
 
AD9852  
SPECIFICATIONS  
VS = 3.3 V 5%, RSET = 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9852ASVZ,  
external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9852ASTZ, unless otherwise noted.  
Table 1.  
Test  
AD9852ASVZ  
AD9852ASTZ  
Parameter  
Temp  
Level Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
REFERENCE CLOCK INPUT CHARACTERISTICS1  
Internal System Clock Frequency Range  
REFCLK Multiplier Enabled  
REFCLK Multiplier Disabled  
External Reference Clock Frequency Range  
REFCLK Multiplier Enabled  
REFCLK Multiplier Disabled  
Duty Cycle  
Full  
Full  
VI  
VI  
20  
DC  
300  
300  
20  
DC  
200  
200  
MHz  
MHz  
Full  
Full  
25°C  
25°C  
25°C  
VI  
VI  
IV  
IV  
IV  
5
DC  
45  
75  
300  
55  
5
DC  
45  
50  
200  
55  
MHz  
MHz  
%
pF  
kΩ  
50  
3
100  
50  
3
100  
Input Capacitance  
Input Impedance  
Differential Common-Mode Voltage Range  
Minimum Signal Amplitude2  
Common-Mode Range  
VIH (Single-Ended Mode)  
VIL (Single-Ended Mode)  
25°C  
25°C  
25°C  
25°C  
IV  
IV  
IV  
IV  
400  
1.6  
2.3  
400  
1.6  
2.3  
mV p-p  
1.75  
1.9  
1
1.75  
1.9  
1
V
V
V
DAC STATIC OUTPUT CHARACTERISTICS  
Output Update Speed  
Resolution  
Cosine and Control DAC Full-Scale Output Current  
Gain Error  
Full  
I
300  
20  
+2.2  
5
200  
20  
+2.2  
5
MSPS  
Bits  
mA  
25°C  
25°C  
25°C  
IV  
IV  
I
12  
10  
12  
10  
5
−6  
5
−6  
% FS  
Output Offset  
Differential Nonlinearity  
Integral Nonlinearity  
25°C  
25°C  
25°C  
25°C  
25°C  
I
I
I
IV  
I
2
1.25  
1.66  
2
1.25  
1.66  
μA  
LSB  
LSB  
kΩ  
V
0.3  
0.6  
100  
0.3  
0.6  
100  
Output Impedance  
Voltage Compliance Range  
DAC DYNAMIC OUTPUT CHARACTERISTICS  
DAC Wideband SFDR  
−0.5  
+1.0  
−0.5  
+1.0  
1 MHz to 20 MHz AOUT  
20 MHz to 40 MHz AOUT  
40 MHz to 60 MHz AOUT  
60 MHz to 80 MHz AOUT  
80 MHz to 100 MHz AOUT  
100 MHz to 120 MHz AOUT  
DAC Narrow-Band SFDR  
10 MHz AOUT ( 1 MHz)  
10 MHz AOUT ( 250 kHz)  
10 MHz AOUT ( 50 kHz)  
41 MHz AOUT ( 1 MHz)  
41 MHz AOUT ( 250 kHz)  
41 MHz AOUT ( 50 kHz)  
119 MHz AOUT ( 1 MHz)  
119 MHz AOUT ( 250 kHz)  
119 MHz AOUT ( 50 kHz)  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
V
V
V
V
V
V
58  
56  
52  
48  
48  
48  
58  
56  
52  
48  
48  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
V
V
V
V
V
V
V
V
V
83  
83  
91  
82  
84  
89  
71  
77  
83  
83  
83  
91  
82  
84  
89  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
Rev. E | Page 5 of 52  
 
 
AD9852  
Test  
AD9852ASVZ  
AD9852ASTZ  
Parameter  
Temp  
Level Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
Residual Phase Noise  
(AOUT = 5 MHz, External Clock = 30 MHz,  
REFCLK Multiplier Engaged at 10×)  
1 kHz Offset  
10 kHz Offset  
100 kHz Offset  
25°C  
25°C  
25°C  
V
V
V
140  
138  
142  
140  
138  
142  
dBc/Hz  
dBc/Hz  
dBc/Hz  
(AOUT = 5 MHz, External Clock = 300 MHz,  
REFCLK Multiplier Bypassed)  
1 kHz Offset  
0 kHz Offset  
100 kHz Offset  
25°C  
25°C  
25°C  
V
V
V
142  
148  
152  
142  
148  
152  
dBc/Hz  
dBc/Hz  
dBc/Hz  
PIPELINE DELAYS3, 4, 5  
DDS Core (Phase Accumulator and  
Phase-to-Amp Converter)  
25°C  
IV  
33  
33  
SYSCLK cycles  
Frequency Accumulator  
Inverse Sinc Filter  
Digital Multiplier  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
IV  
IV  
IV  
IV  
IV  
IV  
26  
16  
9
1
2
26  
16  
9
1
2
SYSCLK cycles  
SYSCLK cycles  
SYSCLK cycles  
SYSCLK cycles  
SYSCLK cycles  
SYSCLK cycles  
SYSCLK cycles  
DAC  
I/O Update Clock (Internal Mode)  
I/O Update Clock (External Mode)  
MASTER RESET DURATION  
COMPARATOR INPUT CHARACTERISTICS  
Input Capacitance  
Input Resistance  
Input Current  
Hysteresis  
3
3
IV  
10  
10  
25°C  
25°C  
25°C  
25°C  
V
IV  
I
3
500  
1
3
500  
1
pF  
kΩ  
μA  
mV p-p  
5
20  
5
20  
IV  
10  
10  
COMPARATOR OUTPUT CHARACTERISTICS  
Logic 1 Voltage, High-Z Load  
Logic 0 Voltage, High-Z Load  
Output Power, 50 Ω Load, 120 MHzToggle Rate  
Propagation Delay  
Output Duty Cycle Error6  
Rise/Fall Time, 5 pF Load  
Toggle Rate, High-Z Load  
Toggle Rate, 50 Ω Load  
Output Cycle-to-Cycle Jitter7  
COMPARATOR NARROW-BAND SFDR8  
10 MHz ( 1 MHz)  
10 MHz ( 250 MHz)  
10 MHz ( 50 kHz)  
41 MHz ( 1 MHz)  
41 MHz ( 250 kHz)  
41 MHz ( 50 kHz)  
119 MHz ( 1 MHz)  
119 MHz ( 250 kHz)  
119 MHz ( 50 kHz)  
Full  
Full  
VI  
VI  
I
IV  
I
3.1  
9
3.1  
9
V
V
dBm  
ns  
%
0.16  
+10  
0.16  
+10  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
11  
3
1
2
350  
400  
11  
3
1
2
350  
400  
−10  
−10  
V
ns  
IV  
IV  
IV  
300  
375  
300  
375  
MHz  
MHz  
ps rms  
4.0  
4.0  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
V
V
V
V
V
V
V
V
V
84  
84  
92  
76  
82  
89  
73  
73  
83  
84  
84  
92  
76  
82  
89  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
CLOCK GENERATOR OUTPUT JITTER8  
5 MHz AOUT  
40 MHz AOUT  
100 MHz AOUT  
25°C  
25°C  
25°C  
V
V
V
23  
12  
7
23  
12  
7
ps rms  
ps rms  
ps rms  
Rev. E | Page 6 of 52  
AD9852  
Test  
AD9852ASVZ  
AD9852ASTZ  
Parameter  
Temp  
Level Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
PARALLEL I/O TIMING CHARACTERISTICS  
tASU (Address Setup Time to WR Signal Active)  
tADHW (Address Hold Time to WR Signal Inactive)  
tDSU (Data Setup Time to WR Signal Inactive)  
tDHD (Data Hold Time to WR Signal Inactive)  
tWRLOW (WR Signal Minimum Low Time)  
tWRHIGH (WR Signal Minimum High Time)  
tWR (Minimum WR Time)  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
IV  
IV  
IV  
IV  
IV  
IV  
IV  
V
8.0  
0
7.5  
8.0  
0
7.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
3.0  
0
1.6  
1.8  
3.0  
0
1.6  
1.8  
2.5  
7
2.5  
7
10.5  
15  
5
10.5  
15  
5
tADV (Address to Data Valid Time)  
tADHR (Address Hold Time to RD Signal Inactive)  
tRDLOV (RD Low to Output Valid)  
15  
15  
IV  
IV  
IV  
15  
10  
15  
10  
tRDHOZ (RD High to Data Three-State)  
SERIAL I/O TIMING CHARACTERISTICS  
tPRE (CS Setup Time)  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
IV  
IV  
IV  
IV  
IV  
IV  
V
30  
100  
30  
40  
40  
0
30  
100  
30  
40  
40  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCLK (Period of Serial Data Clock)  
tDSU (Serial Data Setup Time)  
tSCLKPWH (Serial Data Clock Pulse Width High)  
tSCLKPWL (Serial Data Clock Pulse Width Low)  
tDHLD (Serial Data Hold Time)  
tDV (Data Valid Time)  
30  
30  
9
CMOS LOGIC INPUTS  
Logic 1 Voltage  
Logic 0 Voltage  
Logic 1 Current  
Logic 0 Current  
Input Capacitance  
POWER SUPPLY10  
VS Current11  
25°C  
25°C  
25°C  
25°C  
25°C  
I
I
IV  
IV  
V
2.2  
2.2  
V
V
μA  
μA  
pF  
0.8  
5
5
0.8  
12  
12  
3
3
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
25°C  
I
I
I
I
I
I
I
815  
640  
585  
2.70  
2.12  
1.93  
1
922  
725  
660  
3.20  
2.52  
2.29  
50  
585  
465  
425  
1.93  
1.53  
1.40  
1
660  
mA  
mA  
mA  
W
W
W
VS Current12  
520  
475  
2.39  
1.81  
1.65  
50  
VS Current13  
11  
PDISS  
PDISS  
PDISS  
12  
13  
PDISS Power-Down Mode  
mW  
1 The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine waves centered at one-half the applied VDD or a 3 V TTL-level pulse input.  
2 An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins.  
3 Pipeline delays of each individual block are fixed; however, if the first eight MSBs of a tuning word are all 0s, the delay appears longer. This is due to insufficient phase  
accumulation per a system clock period to produce enough LSB amplitude to the D/A converter.  
4 If a feature such as inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount.  
5 The I/O UD CLK transfers data from the I/O port buffers to the programming registers. This transfer is measured in system clocks.  
6 A change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.  
7 Represents the comparator’s inherent cycle-to-cycle jitter contribution. The input signal is a 1 V, 40 MHz square wave, and the measurement device is a Wavecrest DTS-2075.  
8 Comparator input originates from analog output section via external 7-pole elliptic low-pass filter. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 Ω.  
9
Avoid overdriving digital inputs. (Refer to equivalent circuits in Figure 3.)  
10 If all device functions are enabled, it is not recommended to simultaneously operate the device at the maximum ambient temperature of 85°C and at the maximum  
internal clock frequency. This configuration may result in violating the maximum die junction temperature of 150°C. Refer to the Power Dissipation and Thermal  
Considerations section for derating and thermal management information.  
11 All functions engaged.  
12 All functions except inverse sinc engaged.  
13 All functions except inverse sinc and digital multipliers engaged.  
Rev. E | Page 7 of 52  
AD9852  
ABSOLUTE MAXIMUM RATINGS  
Table 2.  
To determine the junction temperature on the application PCB  
use the following equation:  
Parameter  
Rating  
TJ = Tcase + (ΨJT × PD)  
Maximum Junction Temperature  
VS  
Digital Inputs  
Digital Output Current  
Storage Temperature  
Operating Temperature  
Lead Temperature (Soldering, 10 sec)  
Maximum Clock Frequency (ASVZ)  
Maximum Clock Frequency (ASTZ)  
150°C  
4 V  
where:  
−0.7 V to +VS  
5 mA  
−65°C to +150°C  
−40°C to +85°C  
300°C  
TJ is the junction temperature expressed in degrees Celsius.  
case is the case temperature expressed in degrees Celsius, as  
measured by the user at the top center of the package.  
ΨJT = 0.3°C/W.  
PD is the power dissipation (PD); see the Power Dissipation and  
Thermal Considerations section for the method to calculate PD.  
T
300 MHz  
200 MHz  
EXPLANATION OF TEST LEVELS  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Table 4.  
Test Level  
Description  
I
III  
IV  
100% production tested.  
Sample tested only.  
Parameter is guaranteed by design and  
characterization testing.  
V
Parameter is a typical value only.  
VI  
Devices are 100% production tested at 25°C and  
guaranteed by design and characterization testing  
for industrial operating temperature range.  
THERMAL RESISTANCE  
The heat sink of the AD9852ASVZ 80-lead TQFP package must  
be soldered to the PCB.  
ESD CAUTION  
Table 3.  
Thermal Characteristic  
θJA (0 m/sec airflow)1, 2, 3  
θJMA (1.0 m/sec airflow)2, 3, 4, 5  
θJMA (2.5 m/sec airflow)2, 3, 4, 5  
TQFP  
LQFP  
16.2°C/W  
13.7°C/W  
12.8°C/W  
0.3°C/W  
2.0°C/W  
38°C/W  
1, 2  
ΨJT  
6, 7  
θJC  
1 Per JEDEC JESD51-2 (heat sink soldered to PCB).  
2 2S2P JEDEC test board.  
3 Values of θJA are provided for package comparison and PCB design  
considerations.  
4 Per JEDEC JESD51-6 (heat sink soldered to PCB).  
5 Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the  
more metal that is directly in contact with the package leads from metal  
traces through holes, ground, and power planes, the more θJA is reduced.  
6 Per MIL-Std 883, Method 1012.1.  
7 Values of θJC are provided for package comparison and PCB design  
considerations when an external heat sink is required.  
Rev. E | Page 8 of 52  
 
AD9852  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61  
1
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
D7  
AVDD  
AGND  
NC  
PIN 1  
2
D6  
D5  
3
4
D4  
NC  
5
D3  
DAC R  
SET  
6
D2  
DACBP  
AVDD  
AGND  
IOUT2  
IOUT2  
AVDD  
IOUT1  
IOUT1  
AGND  
AGND  
AGND  
AVDD  
VINN  
7
D1  
AD9852  
TOP VIEW  
(Not to Scale)  
8
D0  
9
DVDD  
DVDD  
DGND  
DGND  
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
A5  
A4  
A3  
A2/IO RESET  
A1/SDO  
A0/SDIO  
I/O UD CLK  
VINP  
AGND  
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
NC = NO CONNECT  
Figure 2. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin Number  
Mnemonic  
D7 to D0  
DVDD  
Description  
1 to 8  
9, 10, 23, 24, 25,  
73, 74, 79, 80  
8-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.  
Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND  
and DGND.  
11, 12, 26, 27, 28,  
72, 75 to 78  
DGND  
Connections for Digital Circuitry Ground Return. Same potential as AGND.  
13, 35, 57, 58, 63  
14 to 16  
NC  
A5 to A3  
No Internal Connection.  
Parallel Address Inputs for Program Registers (Part of 6-Bit Parallel Address Inputs for Program  
Register, A5:A0). Used only in parallel programming mode.  
17  
A2/IO RESET  
A1/SDO  
Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program  
Register, A5:A0)/IO Reset. A2 is used only in parallel programming mode. IO RESET is used when  
the serial programming mode is selected, allowing an IO RESET of the serial communication bus  
that is unresponsive due to improper programming protocol. Resetting the serial bus in this  
manner does not affect previous programming, nor does it invoke the default programming  
values seen in Table 9. Active high.  
Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program  
Register, A5:A0)/Unidirectional Serial Data Output. A1 is used only in parallel programming  
mode. SDO is used in 3-wire serial communication mode when the serial programming mode is  
selected.  
18  
Rev. E | Page 9 of 52  
 
AD9852  
Pin Number  
Mnemonic  
Description  
19  
A0/SDIO  
Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program  
Register, A5:A0)/Bidirectional Serial Data Input/Output. A0 is used only in parallel programming  
mode. SDIO is used in 2-wire serial communication mode.  
20  
I/O UD CLK  
Bidirectional I/O Update Clock. Direction is selected in control register. If selected as an input, a  
rising edge transfers the contents of the I/O port buffers to the programming registers. If I/O UD  
CLK is selected as an output (default), an output pulse (low to high) with a duration of eight  
system clock cycles indicates that an internal frequency update has occurred.  
21  
22  
29  
WR/SCLK  
Write Parallel Data to I/O Port Buffers. Shared function with SCLK. Serial clock signal associated  
with the serial programming bus. Data is registered on the rising edge. This pin is shared with  
WR when the parallel mode is selected. The mode is dependent on Pin 70 (S/P SELECT).  
RD/CS  
Read Parallel Data from Programming Registers. Shared function with CS. Chip select signal  
associated with the serial programming bus. Active low. This pin is shared with RD when the  
parallel mode is selected.  
Multifunction Pin. Functions according to the mode of operation selected in the programming  
control register. If in the FSK mode, logic low selects F1 and logic high selects F2. If in the BPSK  
mode, logic low selects Phase 1 and logic high selects Phase 2. In chirp mode, logic high  
engages the hold function, causing the frequency accumulator to halt at its current location. To  
resume or commence chirp, logic low is asserted.  
FSK/BPSK/HOLD  
30  
OSK  
Output Shaped Keying. Must first be selected in the programming control register to function.  
A logic high causes the cosine DAC outputs to ramp up from zero-scale to full-scale amplitude  
at a preprogrammed rate. Logic low causes the full-scale output to ramp down to zero scale at  
the preprogrammed rate.  
31, 32, 37, 38, 44, 50, 54, AVDD  
60, 65  
Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND  
and DGND.  
33, 34, 39, 40, 41, 45, 46, AGND  
47, 53, 59, 62, 66, 67  
Connections for Analog Circuitry Ground Return. Same potential as DGND.  
36  
VOUT  
Noninverted Output of the Internal High Speed Comparator. Designed to drive 10 dBm to 50 Ω  
loads as well as standard CMOS logic levels.  
42  
43  
48  
49  
51  
52  
55  
VINP  
VINN  
Voltage Input Positive. The noninverting input of the internal high speed comparator.  
Voltage Input Negative. The inverting input of the internal high speed comparator.  
Unipolar Current Output of the Cosine DAC (refer to Figure 3).  
Complementary Unipolar Current Output of the Cosine DAC.  
Complementary Unipolar Current Output of the Control DAC.  
Unipolar Current Output of the Control DAC.  
Common Bypass Capacitor Connection for Both DACs. A 0.01 μF chip capacitor from this pin to  
AVDD improves harmonic distortion and SFDR slightly. No connect is permissible, but results in  
a slight degradation in SFDR.  
IOUT1  
IOUT1  
IOUT2  
IOUT2  
DACBP  
56  
61  
DAC RSET  
Common Connection for Both DACs. Used to set the full-scale output current. RSET = 39.9/ IOUT  
Normal RSET range is from 8 kΩ (5 mA) to 2 kΩ (20 mA).  
.
PLL FILTER  
Connection for the External Zero-Compensation Network of the REFCLK Multiplier’s PLL Loop  
Filter. The zero-compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF  
capacitor. The other side of the network should be connected to AVDD as close as possible to  
Pin 60. For optimum phase noise performance, the REFCLK multiplier can be bypassed by  
setting the bypass PLL bit in Control Register 1E hex.  
64  
68  
69  
DIFF CLK ENABLE Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK  
and REFCLK (Pin 69 and Pin 68, respectively).  
REFCLK  
Complementary (180° Out of Phase) Differential Clock Signal. User should tie this pin high or  
low when single-ended clock mode is selected. Same signal levels as REFCLK.  
REFCLK  
Single-Ended (CMOS Logic Levels Required) Reference Clock Input or One of Two Differential  
Clock Signals. In differential reference clock mode, both inputs can be CMOS logic levels or have  
greater than 400 mV p-p square or sine waves centered about 1.6 V dc.  
70  
71  
S/P SELECT  
Selects between serial programming mode (logic low) and parallel programming mode  
(logic high).  
Initializes the serial/parallel programming bus to prepare for user programming, and sets  
programming registers to a do-nothing state defined by the default values listed in Table 9.  
Active on logic high. Asserting this pin is essential for proper operation upon power-up.  
MASTER RESET  
Rev. E | Page 10 of 52  
AD9852  
DVDD  
AVDD  
DIGITAL  
IN  
AVDD  
AVDD  
I
I
VINP/  
VINN  
OUT OUTB  
AVOID OVERDRIVING  
COMPARATOR  
OUT  
MUST TERMINATE OUTPUTS  
FOR CURRENT FLOW. DO  
NOT EXCEED THE OUTPUT  
VOLTAGE COMPLIANCE RATING.  
DIGITAL INPUTS. FORWARD  
BIASING ESD DIODES MAY  
COUPLE DIGITAL NOISE  
ONTO POWER PINS.  
A. DAC Outputs  
B. Comparator Output  
C. Comparator Input  
D. Digital Inputs  
Figure 3. Equivalent Input and Output Circuits  
Rev. E | Page 11 of 52  
 
AD9852  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9852 from 19.1 MHz to 119.1 MHz fundamental  
output, reference clock = 30 MHz, REFCLK multiplier = 10×. Each graph is plotted from 0 MHz to 150 MHz (Nyquist).  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
START 0Hz  
15MHz/  
STOP 150MHz  
START 0Hz  
15MHz/  
STOP 150MHz  
Figure 4. Wideband SFDR, 19.1 MHz  
Figure 7. Wideband SFDR, 79.1 MHz  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
START 0Hz  
15MHz/  
STOP 150MHz  
START 0Hz  
15MHz/  
STOP 150MHz  
Figure 5. Wideband SFDR, 39.1 MHz  
Figure 8. Wideband SFDR, 99.1 MHz  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
START 0Hz  
15MHz/  
STOP 150MHz  
START 0Hz  
15MHz/  
STOP 150MHz  
Figure 6. Wideband SFDR, 59.1 MHz  
Figure 9. Wideband SFDR, 119.1 MHz  
Rev. E | Page 12 of 52  
 
 
 
AD9852  
Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the  
internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. Compare the noise floor of  
Figure 11 and Figure 12 with that of Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 12 is a direct result of sampling  
the fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a wider bandwidth, which  
effectively lowers the noise floor.  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
CENTER 39.1MHz  
100kHz/  
SPAN 1MHz  
CENTER 39.1MHz  
100kHz/  
SPAN 1MHz  
Figure 10. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,  
300 MHz REFCLK with REFCLK Multiplier Bypassed  
Figure 13. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,  
30 MHz REFCLK with REFCLK Multiplier = 10×  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
CENTER 39.1MHz  
5kHz/  
SPAN 50kHz  
CENTER 39.1MHz  
5kHz/  
SPAN 50kHz  
Figure 11. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,  
300 MHz REFCLK with REFCLK Multiplier Bypassed  
Figure 14. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,  
30 MHz REFCLK with REFCLK Multiplier = 10×  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
CENTER 39.1MHz  
5kHz/  
SPAN 50kHz  
CENTER 39.1MHz  
5kHz/  
SPAN 50kHz  
Figure 12. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,  
100 MHz REFCLK with REFCLK Multiplier Bypassed  
Figure 15. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,  
10 MHz REFCLK with REFCLK Multiplier = 10×  
Rev. E | Page 13 of 52  
 
 
 
 
 
AD9852  
Figure 18 and Figure 19 show the residual phase noise performance of the AD9852 when operating with a 300 MHz reference clock with  
the REFCLK multiplier bypassed vs. a 30 MHz reference clock with the REFCLK multiplier enabled at 10×.  
–90  
0
–10  
–100  
–20  
–110  
–120  
–130  
–140  
–150  
–160  
A
= 80MHz  
OUT  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
A
= 5MHz  
100  
OUT  
10  
1k  
10k  
100k  
1M  
CENTER 112.469MHz  
50kHz/  
SPAN 500kHz  
FREQUENCY (Hz)  
Figure 16. A Slight Change in Tuning Word Yields Dramatically Better Results;  
112.469 MHz with All Spurs Shifted Out-of-Band, 300 MHz REFCLK  
Figure 19. Residual Phase Noise,  
30 MHz REFCLK with REFCLK Multiplier = 10×  
55  
54  
53  
52  
51  
50  
49  
48  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
0
5
10  
15  
20  
25  
CENTER 39.1MHz  
5kHz/  
SPAN 50kHz  
DAC CURRENT (mA)  
Figure 17. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,  
200 MHz REFCLK with REFCLK Multiplier Bypassed  
Figure 20. SFDR vs. DAC Current, 59.1 AOUT  
300 MHz REFCLK with REFCLK Multiplier Bypassed  
,
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
620  
615  
610  
605  
600  
595  
590  
A
= 80MHz  
OUT  
A
= 5MHz  
OUT  
0
20  
40  
60  
80  
100  
120  
140  
10  
100  
1k  
10k  
100k  
1M  
FREQUENCY (MHz)  
FREQUENCY (Hz)  
Figure 21. Supply Current vs. Output Frequency (Variation Is Minimal,  
Expressed as a Percentage, and Heavily Dependent on Tuning Word)  
Figure 18. Residual Phase Noise,  
300 MHz REFCLK with REFCLK Multiplier Bypassed  
Rev. E | Page 14 of 52  
 
 
AD9852  
1200  
1000  
800  
600  
400  
200  
0
RISE TIME  
1.04ns  
JITTER  
[10.6ps RMS]  
MINIMUM COMPARATOR  
INPUT DRIVE  
V
= 0.5V  
CM  
–33ps  
0ps  
+33ps  
0
100  
200  
300  
400  
500  
500ps/DIV  
232mV/DIV  
50Ω INPUT  
FREQUENCY (MHz)  
Figure 22. Typical Comparator Output Jitter, 40 MHz AOUT  
,
Figure 24. Comparator Toggle Voltage Requirement  
300 MHz REFCLK with REFCLK Multiplier Bypassed  
REF1 RISE  
1.174ns  
C1 FALL  
1.286ns  
CH1  
500mVΩ  
M
500ps CH1  
980mV  
Figure 23. Comparator Rise/Fall Times  
Rev. E | Page 15 of 52  
AD9852  
TYPICAL APPLICATIONS  
RF/IF  
INPUT  
BASEBAND  
LOW-PASS  
FILTER  
COS  
REFCLK  
AD9852  
Figure 25. Synthesized LO Application for the AD9852  
8
8
I
I/Q MIXER  
AND  
LOW-PASS  
FILTER  
DUAL  
8-/10-BIT  
ADC  
Rx BASEBAND  
DIGITAL  
DATA OUT  
Rx  
RF IN  
DIGITAL  
DEMODULATOR  
Q
VCA  
AGC  
ADC CLOCK FREQUENCY  
LOCKED TO Tx CHIP/  
SYMBOL/PN RATE  
ADC ENCODE  
AD9852  
48  
CLOCK  
GENERATOR  
CHIP/SYMBOL/PN  
RATE DATA  
REFERENCE  
CLOCK  
Figure 26. Chip Rate Generator in Spread Spectrum Application  
BAND-PASS  
AMPLIFIER  
FILTER  
I
OUT  
AD9852  
50Ω  
50Ω  
AD9852  
SPECTRUM  
FINAL OUTPUT  
SPECTRUM  
FUNDAMENTAL  
F
– F  
F
+ F  
F + F  
C O  
IMAGE  
C
O
C
O
IMAGE  
IMAGE  
F
CLK  
BAND-PASS  
FILTER  
Figure 27. Using an Aliased Image to Generate a High Frequency  
REFERENCE  
CLOCK  
RF FREQUENCY  
OUT  
PHASE  
COMPARATOR  
LOOP  
FILTER  
VCO  
FILTER  
REFCLK IN  
AD9852  
DAC OUT  
DDS  
PROGRAMMABLE  
TUNING  
WORD  
DIVIDE-BY-N FUNCTION  
(WHERE N = 2 /TUNING WORD)  
48  
Figure 28. Programmable Fractional Divide-by-N Synthesizer  
Rev. E | Page 16 of 52  
 
AD9852  
REFERENCE  
CLOCK  
RF FREQUENCY  
OUT  
AD9852  
FILTER  
PHASE  
COMPARATOR  
LOOP  
FILTER  
DDS  
VCO  
TUNING  
WORD  
DIVIDE-BY-N  
Figure 29. Agile High Frequency Synthesizer  
DIFFERENTIAL  
TRANSFORMER-COUPLED  
OUTPUT  
I
REFERENCE  
CLOCK  
OUT  
FILTER  
50Ω  
AD9852  
DDS  
I
OUT  
50Ω  
1:1 TRANSFORMER  
®
THAT IS, Mini-Circuits T1-1T  
Figure 30. Differential Output Connection for Reduction of Common-Mode Signals  
AD9852  
LOW-PASS  
FILTER  
COSINE  
DAC  
8-BIT PARALLEL OR  
SERIAL PROGRAMMING  
DATA AND CONTROL  
SIGNALS  
NOTES  
1. I = APPROXIMATELY 20mA MAX WHEN R  
2. SWITCH POSITION 1 PROVIDES COMPLEMENTARY  
SINUSOIDAL SIGNALS TO THE COMPARATOR TO  
PRODUCE A FIXED 50% DUTY CYCLE FROM THE  
COMPARATOR.  
μPROCESSOR/  
CONTROLLER  
FPGA, ETC.  
1
2
= 2kΩ.  
SET  
OUT  
LOW-PASS  
FILTER  
CONTROL  
DAC  
300MHz MAX DIRECT  
3. SWITCH POSITION 2 PROVIDES A USER-PROGRAMMABLE  
DC THRESHOLD VOLTAGE TO ALLOW SETTING OF THE  
COMPARATOR DUTY CYCLE.  
MODE OR 15MHz TO 75MHz  
MAX IN THE 4× TO 20× CLOCK  
MULTIPLIER MODE  
REFERENCE  
CLOCK  
2kΩ  
R
SET  
CMOS LOGIC CLOCK OUT  
Figure 31. Frequency Agile Clock Generator Applications for the AD9852  
Rev. E | Page 17 of 52  
AD9852  
MODES OF OPERATION  
There are five programmable modes of operation of the AD9852.  
Selecting a mode requires that three bits in the control register  
(Parallel Address 1F hex) be programmed as shown in Table 6.  
As with all Analog Devices DDS devices, the value of the frequency  
tuning word is determined using the following equation:  
FTW = (Desired Output Frequency × 2N)/SYSCLK  
Table 6. Mode Selection Table  
where:  
N is the phase accumulator resolution (48 bits in this instance).  
Desired Output Frequency is expressed in hertz.  
FTW (frequency tuning word) is a decimal number.  
Mode 2  
Mode 1  
Mode 0  
Result  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Single tone  
FSK  
Ramped FSK  
Chirp  
After a decimal number has been calculated, it must be rounded  
to an integer and then converted to binary format—a series of  
48 binary-weighted 1s and 0s. The fundamental sine wave DAC  
output frequency range is from dc to one-half SYSCLK.  
BPSK  
In each mode, engaging certain functions may be prohibited.  
Table 7 lists some important functions and their availability for  
each mode.  
Changes in frequency are phase continuous; therefore, the first  
sampled phase value of the new frequency is referenced from the  
time of the last sampled phase value of the previous frequency.  
SINGLE TONE (MODE 000)  
The 14-bit phase register adjusts the cosine DACs output phase.  
When the MASTER RESET pin is asserted, single-tone mode  
becomes the default. The user can also access this mode by  
programming it into the control register. The phase accumulator,  
responsible for generating an output frequency, is presented with  
a 48-bit value from the Frequency Tuning Word 1 registers with  
default values of 0. Default values from the remaining applicable  
registers further define the single-tone output signal qualities.  
The single-tone mode allows the user to control the following  
signal qualities:  
Output frequency to 48-bit accuracy  
Output amplitude to 12-bit accuracy  
Fixed, user-defined amplitude control  
Variable, programmable amplitude control  
Automatic, programmable, single-pin-controlled  
on/off output shaped keying  
The default values after a master reset configures the device  
with an output signal of 0 Hz and zero phase. Upon power-up  
and reset, the output from both DACs is a dc value equal to the  
midscale output current. This is the default mode amplitude setting  
of 0. Refer to the On/Off Output Shaped Keying (OSK) section  
for further explanation of the output amplitude control. It is  
necessary to program all or some of the 28 program registers to  
produce a user-defined output signal. Figure 32 shows the  
transition from the default condition (0 Hz) to a user-defined  
output frequency (F1).  
Output phase to 14-bit accuracy  
Furthermore, all of these qualities can be changed or modulated  
via the 8-bit parallel programming port at a 100 MHz parallel  
byte rate or at a 10 MHz serial rate. Incorporating this attribute  
permits FM, AM, PM, FSK, PSK, and ASK operation in the  
single-tone mode.  
FREQUENCY  
F1  
0
MODE 000 (DEFAULT)  
000 (SINGLE TONE)  
F1  
TW1  
0
MASTER RESET  
I/O UD CLK  
Figure 32. Default State to User-Defined Output Transition  
Rev. E | Page 18 of 52  
 
 
 
AD9852  
Table 7. Function Availability vs. Mode of Operation  
Function  
Single-Tone Mode  
FSK Mode  
Ramped FSK Mode  
Chirp Mode  
BPSK Mode  
Phase Adjust 1  
Phase Adjust 2  
Single-Pin FSK/BPSK or HOLD  
Single-Pin Output Shaped Keying  
Phase Offset or Modulation  
Amplitude Control or Modulation  
Inverse Sinc Filter  
Frequency Tuning Word 1  
Frequency Tuning Word 2  
Automatic Frequency Sweep  
UNRAMPED FSK (MODE 001)  
RAMPED FSK (MODE 010)  
When this mode is selected, the output frequency of the DDS is  
a function of the values loaded into Frequency Tuning Word  
Register 1 and Frequency Tuning Word Register 2 and the logic  
level of Pin 29 (FSK/BPSK/HOLD). A logic low on Pin 29  
chooses F1 (Frequency Tuning Word 1, Parallel Address 4 hex  
to Parallel Address 9 hex), and a logic high chooses F2  
(Frequency Tuning Word 2, Parallel Register Address A hex to  
Parallel Register Address F hex). Changes in frequency are  
phase continuous and are internally coincident with the FSK  
data pin (Pin 29); however, there is deterministic pipeline delay  
between the FSK data signal and the DAC output (see Table 1).  
In this method of FSK, changes from F1 to F2 are not  
instantaneous, but are accomplished in a frequency sweep or  
ramped fashion. The ramped notation implies the sweep is  
linear. Although linear sweeping, or frequency ramping, is  
easily and automatically accomplished, it is only one of many  
possibilities. Other frequency transition schemes can be  
implemented by changing the ramp rate and ramp step size at  
any time during operation.  
Frequency ramping, whether linear or nonlinear, necessitates  
that many intermediate frequencies between F1 and F2 are  
output in addition to the primary F1 and F2 frequencies.  
Figure 34 and Figure 35 graphically depict the frequency vs.  
time characteristics of a linear ramped FSK signal.  
The unramped FSK mode (see Figure 33) is representative  
of traditional FSK, radio teletype (RTTY), or teletype (TTY)  
transmission of digital data. FSK is a very reliable means of  
digital communication; however, it makes inefficient use of  
the bandwidth in the RF spectrum. Ramped FSK, shown in  
Figure 34, is a method of conserving the bandwidth.  
In ramped FSK mode, the delta frequency word (DFW) is  
required to be programmed as a positive twos complement  
value. Another requirement is that the lowest frequency (F1) be  
programmed in the Frequency Tuning Word 1 registers.  
F2  
FREQUENCY  
F1  
0
000 (DEFAULT)  
001 (FSK NO RAMP)  
MODE  
TW1  
0
0
F1  
F2  
TW2  
I/O UD CLK  
FSK DATA (PIN 29)  
Figure 33. Unramped (Traditional) FSK Mode  
Rev. E | Page 19 of 52  
 
 
 
AD9852  
F2  
FREQUENCY  
F1  
0
MODE  
000 (DEFAULT)  
010 (RAMPED FSK)  
TW1  
TW2  
DFW  
0
0
F1  
F2  
REQUIRES A POSITIVE TWOS COMPLEMENT VALUE  
RAMP RATE  
I/O UD CLK  
FSK DATA (PIN 29)  
Figure 34. Ramped FSK Mode (Start at F1)  
F2  
FREQUENCY  
F1  
0
000 (DEFAULT)  
010 (RAMPED FSK)  
MODE  
TW1  
0
0
F1  
F2  
TW2  
I/O UD CLK  
FSK DATA (PIN 29)  
Figure 35. Ramped FSK Mode (Start at F2)  
The purpose of ramped FSK is to provide better bandwidth  
containment than can be achieved using traditional FSK. In  
ramped FSK, the instantaneous frequency changes of traditional  
FSK are replaced with more gradual, user-defined frequency  
changes. The dwell time at F1 and F2 can be equal to or much  
greater than the time spent at each intermediate frequency. The  
user controls the dwell time at F1 and F2, the number of  
intermediate frequencies, and the time spent at each frequency.  
Unlike unramped FSK, ramped FSK requires the lowest  
frequency to be loaded into the F1 registers and the highest  
frequency to be loaded into the F2 registers.  
For piecewise, nonlinear frequency transitions, it is necessary  
to reprogram the registers while the frequency transition is in  
progress to affect the desired response.  
Parallel Register Address 1A hex to Parallel Register Address 1C  
hex comprise the 20-bit ramp rate clock registers. This is a  
countdown counter that outputs a single pulse whenever the  
count reaches 0. The counter is activated any time a logic level  
change occurs on the FSK input (Pin 29). This counter is run at  
the system clock rate, 300 MHz maximum. The time period  
between each output pulse is  
(N + 1) × System Clock Period  
Several registers must be programmed to instruct the DDS  
regarding the resolution of intermediate frequency steps (48 bits)  
and the time spent at each step (20 bits). Furthermore, the CLR  
ACC1 bit in the control register should be toggled (low-high-low)  
prior to operation to ensure that the frequency accumulator is  
starting from an all 0s output condition.  
where N is the 20-bit ramp rate clock value programmed by  
the user.  
The allowable range of N is from 1 to (220 − 1). The output of  
this counter clocks the 48-bit frequency accumulator shown in  
Rev. E | Page 20 of 52  
 
 
AD9852  
Figure 36. The ramp rate clock determines the amount of time  
spent at each intermediate frequency between F1 and F2.  
PHASE  
ACCUMULATOR  
The counter stops automatically when the destination  
frequency is achieved. The dwell time spent at F1 and F2 is  
determined by the duration that the FSK input (Pin 29) is held  
high or low after the destination frequency has been reached.  
ADDER  
FREQUENCY  
ACCUMULATOR  
INSTANTANEOUS  
PHASE OUT  
48-BIT DELTA  
FREQUENCY  
WORD (TWOS  
COMPLEMENT)  
FSK (PIN 29)  
Parallel Register Address 10 hex to Parallel Register Address 15 hex  
comprise the 48-bit, twos complement delta frequency word  
registers. This 48-bit word is accumulated (added to the  
accumulators output) every time it receives a clock pulse from  
the ramp rate counter. The output of this accumulator is added  
to or subtracted from the F1 or F2 frequency word, which is  
then fed into the input of the 48-bit phase accumulator that  
forms the numerical phase steps for the sine and cosine wave  
outputs. In this fashion, the output frequency is ramped up and  
down in frequency according to the logic state of Pin 29. This  
ramping rate is a function of the 20-bit ramp rate clock. When  
the destination frequency is achieved, the ramp rate clock is  
stopped, halting the frequency accumulation process.  
FREQUENCY  
TUNING  
WORD 1  
FREQUENCY  
TUNING  
WORD 2  
20-BIT  
RAMP RATE  
CLOCK  
SYSTEM  
CLOCK  
Figure 36. Block Diagram of Ramped FSK Function  
F2  
FREQUENCY  
F1  
0
Generally speaking, the delta frequency word is a much smaller  
value compared with the value of the F1 or F2 tuning word. For  
example, if F1 and F2 are 1 kHz apart at 13 MHz, the delta  
frequency word might be only 25 Hz.  
MODE  
010 (RAMPED FSK)  
TW1  
TW2  
F1  
F2  
Figure 39 shows that premature toggling causes the ramp to  
immediately reverse itself and proceed at the same rate and  
resolution until the original frequency is reached.  
FSK DATA  
TRIANGLE BIT  
The control register contains a triangle bit at Parallel Register  
Address 1F hex. Setting this bit high in Mode 010 causes an  
automatic ramp-up and ramp-down between F1 and F2 to  
occur without toggling Pin 29 (shown in Figure 37). In fact, the  
logic state of Pin 29 has no effect once the triangle bit is set  
high. This function uses the ramp rate clock time period and  
the step size of the delta frequency word to form a continuously  
sweeping linear ramp from F1 to F2 and back to F1 with equal  
dwell times at every frequency. Use this function to automatically  
sweep between any two frequencies from dc to Nyquist.  
I/O UD CLK  
Figure 37. Effect of Triangle Bit in Ramped FSK Mode  
F2  
FREQUENCY  
F1  
0
In the ramped FSK mode with the triangle bit set high, an  
automatic frequency sweep begins at either F1 or F2, according  
to the logic level on Pin 29 (FSK input pin) when the triangle  
bit’s rising edge occurs, as shown in Figure 38. If the FSK data  
bit is high instead of low, F2, rather than F1, is chosen as the  
start frequency.  
MODE 000 (DEFAULT)  
010 (RAMPED FSK)  
TW1  
TW2  
0
0
F1  
F2  
FSK DATA  
TRIANGLE BIT  
Figure 38. Automatic Linear Ramping Using the Triangle Bit  
Rev. E | Page 21 of 52  
 
 
 
AD9852  
even when a static F1 or F2 destination frequency has been  
achieved.  
Additional flexibility in the ramped FSK mode is provided by  
the AD9852s ability to respond to changes in the 48-bit delta  
frequency word and/or the 20-bit ramp rate counter at any time  
during the ramping from F1 to F2 or vice versa. To create these  
nonlinear frequency changes, it is necessary to combine several  
linear ramps with different slopes in a piecewise fashion. This is  
done by programming and executing a linear ramp at a rate or  
slope and then altering the slope (by changing the ramp rate  
clock or delta frequency word, or both). Changes in slope can  
be made as often as needed before the destination frequency has  
been reached to form the desired nonlinear frequency sweep  
response. These piecewise changes can be precisely timed using  
the 32-bit internal update clock (see the Internal and External  
Update Clock section).  
Alternatively, the CLR ACC2 control bit (Register Address 1F hex)  
can be used to clear both the frequency accumulator (ACC1)  
and the phase accumulator (ACC2). When this bit is set high,  
the output of the phase accumulator results in 0 Hz output from  
the DDS. As long as this bit is set high, the frequency and phase  
accumulators are cleared, resulting in 0 Hz output. To return to  
previous DDS operation, CLR ACC2 must be set to logic low.  
CHIRP (MODE 011)  
Chirp mode is also known as pulsed FM. Most chirp systems  
use a linear FM sweep pattern, but the AD9852 can also support  
nonlinear patterns. In radar applications, use of chirp or pulsed  
FM allows operators to significantly reduce the output power  
needed to achieve the same result a single frequency radar  
system produces. Figure 41 represents a very low resolution  
nonlinear chirp that demonstrates the different slopes created  
by varying the time steps (ramp rate) and frequency steps (delta  
frequency word).  
Nonlinear ramped FSK has the appearance of the chirp function  
shown in Figure 41. The major difference between a ramped  
FSK function and a chirp function is that FSK is limited to  
operation between F1 and F2, whereas chirp operation has no  
F2 limit frequency.  
Two additional control bits (CLR ACC1 and CLR ACC2) are  
available in the ramped FSK mode that allow more options. Setting  
CLR ACC1 (Register Address 1F hex) high clears the 48-bit  
frequency accumulator (ACC1) output with a retriggerable  
one-shot pulse of one system clock duration. If the CLR ACC1  
bit is left high, a one-shot pulse is delivered on the rising edge of  
every update clock. The effect is to interrupt the current ramp,  
reset the frequency to the start point (F1 or F2), and then  
continue to ramp up (or down) at the previous rate. This occurs  
The AD9852 permits precise, internally generated linear,  
or externally programmed nonlinear, pulsed or continuous  
FM over the complete frequency range, duration, frequency  
resolution, and sweep direction(s). All of these options are user  
programmable. A block diagram of the FM chirp components  
is shown in Figure 40.  
F2  
FREQUENCY  
F1  
0
000 (DEFAULT)  
010 (RAMPED FSK)  
MODE  
TW1  
0
0
F1  
F2  
TW2  
I/O UD CLK  
FSK DATA  
Figure 39. Effect of Premature Ramped FSK Data  
Rev. E | Page 22 of 52  
 
 
AD9852  
OUT  
PHASE  
ACCUMULATOR  
ADDER  
FREQUENCY  
ACCUMULATOR  
CLR ACC2  
48-BIT DELTA  
FREQUENCY  
WORD (TWOS  
COMPLEMENT)  
CLR ACC1  
FREQUENCY  
TUNING  
WORD 1  
20-BIT  
RAMP RATE  
CLOCK  
SYSTEM  
CLOCK  
HOLD  
Figure 40. FM Chirp Components  
FREQUENCY  
F1  
0
MODE 000 (DEFAULT)  
010 (RAMPED FSK)  
F1  
TW1  
DFW  
0
RAMP RATE  
I/O UD CLK  
Figure 41. Example of a Nonlinear Chirp  
Basic FM Chirp Programming Steps  
It is important to note that FTW1 is only a starting point for  
FM chirp. There is no built-in restraint requiring a return to  
FTW1. Once the FM chirp begins, it is free to move (under  
program control) within the Nyquist bandwidth (dc to one-half  
the system clock). However, instant return to FTW1 can be  
easily achieved.  
1. Program a start frequency into Frequency Tuning Word 1  
(Parallel Register Address 4 hex to Parallel Register  
Address 9 hex), hereafter called FTW1.  
2. Program the frequency step resolution into the 48-bit, twos  
complement delta frequency word (Parallel Register  
Address 10 hex to Parallel Register Address 15 hex).  
Two control bits (CLR ACC1 and CLR ACC2) are available in the  
FM chirp mode that allow the device to return to the beginning  
frequency, FTW1, or to 0 Hz. When the CLR ACC1 bit (Register  
Address 1F hex) is set high, the 48-bit frequency accumulator  
(ACC1) output is cleared with a retriggerable one-shot pulse of  
one system clock duration. The 48-bit delta frequency word input  
to the accumulator is unaffected by the CLR ACC1 bit. If the  
CLR ACC1 bit is held high, a one-shot pulse is delivered to the  
frequency accumulator (ACC1) on every rising edge of the I/O  
update clock. The effect is to interrupt the current chirp, reset the  
frequency to that programmed into FTW1, and continue the chirp  
at the previously programmed rate and direction. Figure 42 shows  
clearing of the frequency accumulator output in chirp mode.  
Shown in the diagram is the I/O update clock, which is either user  
3. Program the rate of change (time at each frequency) into  
the 20-bit ramp rate clock (Parallel Register Address 1A hex  
to Parallel Register Address 1C hex).  
When programming is complete, an I/O update pulse at Pin 20  
engages the program commands.  
The necessity for a twos complement delta frequency word is to  
define the direction in which the FM chirp moves. If the 48-bit  
delta frequency word is negative (MSB is high), the incremental  
frequency changes are in a negative direction from FTW1. If the  
48-bit word is positive (MSB is low), the incremental frequency  
changes are in a positive direction from FTW1.  
Rev. E | Page 23 of 52  
 
 
AD9852  
supplied or internally generated. See the Internal and External  
Update Clock section for a discussion of the I/O update.  
Another function only available in the chirp mode is the  
HOLD pin (Pin 29). This function stops the clock signal to the  
ramp rate counter, thereby halting any further clocking pulses  
to the frequency accumulator, ACC1.  
Alternatively, the CLR ACC2 control bit (Register Address 1F hex)  
is available to clear both the frequency accumulator (ACC1)  
and the phase accumulator (ACC2). When this bit is set high,  
the output of the phase accumulator results in 0 Hz output from  
the DDS. As long as this bit is set high, the frequency and phase  
accumulators are cleared, resulting in 0 Hz output. To return to  
the previous DDS operation, CLR ACC2 must be set to logic  
low. This bit is useful for generating pulsed FM.  
The effect is to halt the chirp at the frequency existing just  
before the HOLD pin is pulled high. When the HOLD pin is  
returned low, the clock resumes and chirp continues. During a  
hold condition, the user can change the programming registers;  
however, the ramp rate counter must resume operation at its  
previous rate until a count of 0 is obtained before a new ramp  
rate count can be loaded. Figure 44 illustrates the effect of the  
hold function on the DDS output frequency.  
Figure 43 graphically illustrates the effect of the CLR ACC2 bit on  
the DDS output frequency. Reprogramming the registers while  
the CLR ACC2 bit is high allows a new FTW1 frequency and  
slope to be loaded.  
FREQUENCY  
F1  
0
000 (DEFAULT)  
0
011 (CHIRP)  
F1  
MODE  
FTW1  
DELTA FREQUENCY WORD  
DFW  
RAMP RATE  
RAMP RATE  
I/O UD CLK  
CLR ACC1  
Figure 42. Effect of CLR ACC1 in FM Chirp Mode  
Rev. E | Page 24 of 52  
 
AD9852  
FREQUENCY  
F1  
0
000 (DEFAULT)  
011 (CHIRP)  
MODE  
TW1  
DPW  
0
RAMP RATE  
CLR ACC2  
I/O UD CLK  
Figure 43. Effect of CLR ACC2 in FM Chirp Mode  
FREQUENCY  
F1  
0
000 (DEFAULT)  
0
011 (CHIRP)  
F1  
MODE  
TW1  
DELTA FREQUENCY WORD  
RAMP RATE  
DFW  
RAMP RATE  
HOLD  
I/O UD CLK  
Figure 44. Example of Hold Function  
The 32-bit automatic I/O update counter can be used to  
construct complex chirp or ramped FSK sequences. Because  
this internal counter is synchronized with the AD9852 system  
clock, it allows precisely timed program changes to be invoked.  
For such changes, the user need only reprogram the desired  
registers before the automatic I/O update clock is generated.  
When the chirp destination frequency is reached, the user can  
choose any of the following actions:  
Stop at the destination frequency either by using the  
HOLD pin or by loading all 0s into the delta frequency  
word registers of the frequency accumulator (ACC1).  
Use the HOLD pin function to stop the chirp, and then ramp  
down the output amplitude either by using the digital multi-  
plier stages and the output shaped keying pin (Pin 30) or by  
using the program register control (Address 21 hex to  
Address 24 hex).  
In chirp mode, the destination frequency is not directly speci-  
fied. If the user fails to control the chirp, the DDS automatically  
confines itself to the frequency range between dc and Nyquist.  
Unless terminated by the user, the chirp continues until power  
is removed.  
Abruptly end the transmission with the CLR ACC2 bit.  
Rev. E | Page 25 of 52  
 
 
AD9852  
Continue chirp by reversing the direction and returning to  
the previous or another destination frequency in a linear or  
user-directed manner. If this involves reducing the  
BPSK (MODE 100)  
Binary, biphase, or bipolar phase shift keying is a means to  
rapidly select between two preprogrammed 14-bit output phase  
offsets. The logic state of BPSK (Pin 29) controls the selection of  
Phase Adjust Register 1 or Phase Adjust Register 2. When low,  
BPSK selects Phase Adjust Register 1; when high, it selects  
Phase Adjust Register 2. Figure 45 illustrates phase changes  
made to four cycles of an output carrier.  
frequency, a negative 48-bit delta frequency word (the  
MSB is set to 1) must be loaded into Register 10 hex to  
Register 15 hex. Any decreasing frequency step of the delta  
frequency word requires the MSB to be set to logic high.  
Continue chirp by immediately returning to the beginning  
frequency (F1) in a sawtooth fashion, and then repeating the  
previous chirp process. In this case, an automatic repeating  
chirp can be set up by using the 32-bit update clock to issue  
the CLR ACC1 command at precise time intervals. Adjusting  
the timing intervals or changing the delta frequency word  
changes the chirp range. It is incumbent upon the user to  
balance the chirp duration and frequency resolution to  
achieve the proper frequency range.  
Basic BPSK Programming Steps  
1. Program a carrier frequency into Frequency Tuning Word 1.  
2. Program the appropriate 14-bit phase words into Phase Adjust  
Register 1 and Phase Adjust Register 2.  
3. Attach the BPSK data source to Pin 29.  
4. Activate the I/O update clock when ready.  
If higher-order PSK modulation is desired, the user can select  
single-tone mode and program Phase Adjust Register 1 using  
the serial or high speed parallel programming bus.  
360  
PHASE  
0
000 (DEFAULT)  
0
100 (BPSK)  
MODE  
FTW1  
F1  
PHASE ADJUST 1  
PHASE ADJUST 2  
BPSK DATA  
270°  
90°  
I/O UD CLK  
Figure 45. BPSK Mode  
Rev. E | Page 26 of 52  
 
 
AD9852  
USING THE AD9852  
INTERNAL AND EXTERNAL UPDATE CLOCK  
ON/OFF OUTPUT SHAPED KEYING (OSK)  
The update clock function is composed of a bidirectional  
I/O pin (Pin 20) and a programmable 32-bit down-counter. In  
order for programming changes to be transferred from the I/O  
buffer registers to the active core of the DDS, a clock signal  
(low-to-high edge) must be externally supplied to Pin 20 or  
internally generated by the 32-bit update clock.  
The on/off OSK feature allows the user to control the amplitude  
vs. time slope of the cosine DAC output signal. This function is  
used in burst transmissions of digital data to reduce the adverse  
spectral impact of short, abrupt bursts of data. Users must first  
enable the digital multiplier by setting the OSK EN bit (Control  
Register Address 20 hex) to logic high in the control register.  
Otherwise, if the OSK EN bit is set low, the digital multiplier  
responsible for amplitude control is bypassed, and the cosine  
DAC output is set to full-scale amplitude.  
When the user provides an external update clock, it is internally  
synchronized with the system clock to prevent partial transfer  
of program register information due to violation of data setup  
or hold times. This mode provides the user with complete control  
of when updated program information becomes effective. The  
default mode for the update clock is internal (internal/external  
update clock control register bit is logic high). To switch to  
external update clock mode, the internal/external update clock  
control register bit must be set to logic low. The internal update  
mode generates automatic, periodic update pulses at intervals  
set by the user.  
In addition to setting the OSK EN bit, a second control bit, OSK  
INT (also at Address 20 hex), must be set to logic high. Logic high  
selects the linear internal control of the output ramp-up or ramp-  
down function. A logic low in the OSK INT bit switches control  
of the digital multiplier to a user-programmable 12-bit register,  
allowing users to dynamically shape the amplitude transition in  
practically any fashion. The 12-bit register, labeled output shape  
key, is located at Address 21 hex to Address 22 hex, as indicated  
in Table 9. The maximum output amplitude is a function of the  
An internally generated update clock can be established by  
programming the 32-bit update clock registers (Address 16 hex  
to Address 19 hex) and setting the internal/external update clock  
control register bit (Address 1F hex) to logic high. The update  
clock countdown counter function operates at half the rate of  
the system clock (150 MHz maximum) and counts down from a  
32-bit binary value (programmed by the user). When the count  
reaches 0, an automatic I/O update of the DDS output or the DDS  
functions is generated. The update clock is internally and externally  
routed to Pin 20 to allow users to synchronize the programming of  
update information with the update clock rate. The time between  
update pulses is given as  
R
SET resistor and is not programmable when OSK INT is enabled.  
ABRUPT ON/OFF KEYING  
ZERO  
SCALE  
FULL  
SCALE  
ZERO  
SCALE  
FULL  
SCALE  
SHAPED ON/OFF KEYING  
Figure 46. On/Off Output Shaped Keying  
(N + 1)(System Clock Period × 2)  
The transition time from zero scale to full scale must also be  
programmed. The transition time is a function of two fixed  
elements and one variable. The variable element is the pro-  
grammable 8-bit ramp rate counter. This is a countdown counter  
that is clocked at the system clock rate (300 MHz maximum)  
and generates one pulse whenever the counter reaches 0. This  
pulse is routed to a 12-bit counter that increments with each  
pulse received. The outputs of the 12-bit counter are connected  
to the 12-bit digital multiplier. When the digital multiplier has  
a value of all 0s at its inputs, the input signal is multiplied by 0,  
producing zero scale. When the multiplier has a value of all 1s,  
the input signal is multiplied by a value of 4095 or 4096, producing  
nearly full scale. There are 4094 remaining fractional multiplier  
values that produce output amplitudes scaled according to their  
binary values.  
where N is the 32-bit value programmed by the user, and the  
allowable range of N is from 1 to (232 − 1).  
The internally generated update pulse output on Pin 20 has a  
fixed high time of eight system clock cycles.  
Programming the update clock register for values less than 5 causes  
the I/O UD CLK pin to remain high. Although the update clock  
can still function in this state, it cannot be used to indicate when  
data is transferring. This is an effect of the minimum high pulse  
time when I/O UD CLK functions as an output.  
Rev. E | Page 27 of 52  
 
 
AD9852  
A total of 4096 output pulses is required to advance the 12-bit  
up-counter from zero scale to full scale. Therefore, the minimum  
output shaped keying ramp time for a 100 MHz system clock is  
The two fixed elements of the transition time are the period of  
the system clock (which drives the ramp rate counter) and the  
number of amplitude steps (4096). For example, if the system  
clock of the AD9852 is 100 MHz (10 ns period) and the ramp  
rate counter is programmed for a minimum count of 3, two system  
clock periods are required: one rising edge loads the countdown  
value, and the next edge decrements the counter from 3 to 2. If the  
countdown value is less than 3, the ramp rate counter stalls and  
therefore produces a constant scaling value to the digital multiplier.  
This stall condition may have an application for the user.  
4096 × 4 × 10 ns ≈ 164 μs  
The maximum ramp time is  
4096 × 256 × 10 ns ≈ 10.5 ms  
Finally, by changing the logic state of Pin 30, output shaped  
keying automatically performs the programmed output envelope  
functions when OSK INT is high. A logic high on Pin 30 causes  
the outputs to linearly ramp up to full-scale amplitude and hold  
until the logic level is changed to low, causing the outputs to  
ramp down to zero scale.  
The relationship of the 8-bit countdown value to the time between  
output pulses is given as  
(N + 1) × System Clock Period  
where N is the 8-bit countdown value.  
(BYPASS MULTIPLIER)  
DIGITAL  
SIGNAL IN  
OSK EN = 0  
OSK EN = 1  
OSK EN = 0  
DDS DIGITAL  
OUTPUT  
12  
12  
COSINE  
DAC  
12-BIT DIGITAL  
MULTIPLIER  
OSK EN = 1  
12  
USER-PROGRAMMABLE  
12-BIT MULTIPLIER  
OUTPUT SHAPED  
KEYING MULTIPLIER  
REGISTER  
OSK INT = 1  
12  
OSK INT = 0  
12  
12-BIT  
UP/DOWN  
COUNTER  
8-BIT RAMP  
RATE  
COUNTER  
1
SYSTEM  
CLOCK  
ON/OFF OUTPUT SHAPED  
KEYING PIN  
Figure 47. Block Diagram of the Digital Multiplier Section Responsible for the Output Shaped Keying Function  
Rev. E | Page 28 of 52  
AD9852  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
COSINE DAC  
The cosine output of the DDS drives the cosine DAC (300 MSPS  
maximum). Its maximum output amplitude is set by the DAC RSET  
resistor at Pin 56. This is a current-output DAC with a full-scale  
maximum output of 20 mA; however, a nominal 10 mA output  
current provides best spurious-free dynamic range (SFDR) perfor-  
mance. The value of RSET is 39.93/IOUT, where IOUT is expressed in  
amps. DAC output compliance specifications limit the maximum  
voltage developed at the outputs to −0.5 V to +1 V. Voltages  
developed beyond this limitation cause excessive DAC distortion  
and possibly permanent damage. The user must choose a proper  
load impedance to limit the output voltage swing to the compliance  
limits. Both DAC outputs should be terminated equally for best  
SFDR, especially at higher output frequencies, where harmonic  
distortion errors are more prominent.  
ISF  
SYSTEM  
0
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
–3.0  
–3.5  
–4.0  
SINC  
0
0.1  
0.2  
0.3  
0.4  
0.5  
FREQUENCY NORMALIZED TO SAMPLE RATE  
Figure 48. Inverse Sinc Filter Response  
INVERSE SINC FUNCTION  
The cosine DAC is preceded by an inverse sin(x)/x filter  
(also called an inverse sinc filter) that precompensates for  
DAC output amplitude variations over frequency to achieve  
flat amplitude response from dc to Nyquist. This DAC can be  
powered down when not needed by setting the DAC PD bit  
high (Address 1D hex of the control register). Cosine DAC  
This filter precompensates input data to the cosine DAC for  
the sin(x)/x roll-off characteristic inherent in the DACs  
output spectrum. This allows wide bandwidth signals, such  
as QPSK, to be output from the DAC without appreciable  
amplitude variations as a function of frequency. The inverse  
sinc function can be bypassed to significantly reduce power  
consumption, especially at higher clock speeds.  
IOUT1  
outputs are designated as IOUT1 (Pin 48) and  
(Pin 49).  
CONTROL DAC  
Inverse sinc is engaged by default and is bypassed by bringing  
the bypass inverse sinc bit high in Control Register 20 hex, as  
noted in Table 9.  
The control DAC output can provide dc control levels to  
external circuitry, generate ac signals, or enable duty cycle  
control of the on-board comparator. The input to the control  
DAC is configured to accept twos complement data supplied by  
the user. Data is channeled through the serial or parallel inter-  
face to the 12-bit control DAC register (Address 26 hex and  
Address 27 hex) at a maximum data rate of 100 MHz. This DAC  
is clocked at the system clock, 300 MSPS (maximum), and has  
the same maximum output current capability as that of the  
cosine DAC. The single RSET resistor on the AD9852 sets the  
full-scale output current for both DACs. When not needed, the  
control DAC can be powered down separately to conserve power  
by setting the control DAC power-down bit high (Address 1D hex).  
Control DAC outputs are designated as IOUT2 (Pin 52) and  
REFCLK MULTIPLIER  
The REFCLK multiplier is a programmable PLL-based  
reference clock multiplier that allows the user to select an  
integer clock multiplying value over the range of 4× to 20×. Use  
of this function allows users to input as little as 15 MHz at the  
REFCLK input to produce a 300 MHz internal system clock.  
Five bits in Control Register 1E hex set the multiplier value, as  
described in Table 8.  
The REFCLK multiplier function can be bypassed to allow  
direct clocking of the AD9852 from an external clock source.  
The system clock for the AD9852 is either the output of the  
REFCLK multiplier (if it is engaged) or the REFCLK inputs.  
REFCLK can be either a single-ended or differential input by  
setting Pin 64 (DIFF CLK ENABLE) low or high, respectively.  
IOUT2  
(Pin 51).  
PLL Range Bit  
The PLL range bit selects the frequency range of the REFCLK  
multiplier PLL. For operation from 200 MHz to 300 MHz  
(internal system clock rate), the PLL range bit should be set to  
Logic 1. For operation below 200 MHz, set the PLL range bit to  
Logic 0. The PLL range bit adjusts the PLL loop parameters for  
optimized phase noise performance within each range.  
Rev. E | Page 29 of 52  
 
AD9852  
50 Ω or CMOS logic levels into high impedance loads. The com-  
parator can be powered down separately to conserve power. This  
comparator is used in clock-generator applications to square up  
the filtered sine wave generated by the DDS.  
PLL Filter  
The PLL FILTER pin (Pin 61) provides the connection for the  
external zero-compensation network of the PLL loop filter. The  
zero-compensation network consists of a 1.3 kΩ resistor in  
series with a 0.01 μF capacitor. The other side of the network  
should be connected as close as possible to Pin 60 (AVDD). For  
optimum phase noise performance, the clock multiplier can be  
bypassed by setting the bypass PLL bit in Control Register  
Address 1E hex.  
POWER-DOWN  
The programming registers allow several individual stages to be  
powered down to reduce power consumption while maintaining  
the functionality of the desired stages. These stages are identified in  
the Register Layout table (Table 9) in the Address 1D hex section.  
Power-down is achieved by setting the specified bits to logic high.  
A logic low indicates that the stages are powered up.  
Differential REFCLK Enable  
A high level on the DIFF CLK ENABLE pin enables the differential  
REFCLK  
clock inputs, REFCLK (Pin 69) and  
(Pin 68). The min-  
Furthermore, and perhaps most importantly, the inverse sinc  
filters and the digital multiplier stages can be bypassed to achieve  
significant power reduction by programming the control regis-  
ters in Address 20 hex. Again, logic high causes the stage to be  
bypassed. Of particular importance is the inverse sinc filter  
because this stage consumes a significant amount of power.  
imum differential signal amplitude required is 400 mV p-p at  
the REFCLK input pins. The center point or common-mode  
range of the differential signal can range from 1.6 V to 1.9 V.  
When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK (Pin 69)  
is the only active clock input. This is referred to as single-ended  
REFCLK  
mode. In this mode, Pin 68 ( ) should be tied low or high.  
A full power-down occurs when all four PD bits in Control  
Register 1D hex are set to logic high. This reduces power  
consumption to approximately 10 mW (3 mA).  
HIGH SPEED COMPARATOR  
The comparator is optimized for high speed and has a toggle  
rate greater than 300 MHz, low jitter, sensitive input, and built-  
in hysteresis. It also has an output level of 1 V p-p minimum into  
Rev. E | Page 30 of 52  
 
AD9852  
PROGRAMMING THE AD9852  
The AD9852 Register Layout table (Table 9) contains information  
for programming a chip for a desired functionality. Although  
many applications require very little programming to configure  
the AD9852, some use all 12 accessible register banks. The  
AD9852 supports an 8-bit parallel I/O operation or an SPI-  
compatible serial I/O operation. All accessible registers can be  
written and read back in either I/O operating mode.  
Table 8. REFCLK Multiplier Control Register Values  
Reference Multiplier  
Multiplier Value  
Bit 4  
0
Bit 3  
0
Bit 2  
1
Bit 1  
0
Bit 0  
0
1
0
1
4
5
0
0
1
0
6
0
0
1
1
7
0
0
1
1
8
9
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
S/P SELECT (Pin 70) is used to configure the I/O mode.  
Systems that use a parallel I/O mode must connect the S/P  
SELECT pin to VDD. Systems that operate in the serial I/O mode  
must tie the S/P SELECT pin to GND.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Regardless of the mode, the I/O port data is written to a buffer  
memory that only affects operation of the part after the contents  
of the buffer memory are transferred to the register banks. This  
transfer of information occurs synchronous to the system clock  
in one of two ways:  
The transfer is internally controlled at a rate programmed  
by the user.  
The transfer is externally controlled by the user. I/O opera-  
tions can occur in the absence of REFCLK, but data cannot be  
moved from the buffer memory to the register bank without  
REFCLK. (See the Internal and External Update Clock  
section for details.)  
1
0
1
0
0
SERIAL PORT I/O OPERATION  
With the S/P SELECT pin tied low, the serial I/O mode is  
active. The AD9852 serial port is a flexible, synchronous, serial  
communication port, allowing easy interface to many industry-  
standard microcontrollers and microprocessors. The serial I/O  
is compatible with most synchronous transfer formats, including  
both the Motorola 6905/11 SPI and Intel 8051 SSR protocols.  
The interface allows read/write access to all 12 registers that  
configure the AD9852 and can be configured as a single-pin  
I/O (SDIO) or two unidirectional pins for input and output  
(SDIO/SDO). Data transfers are supported in MSB- or LSB-  
first format at up to 10 MHz.  
MASTER RESET  
The MASTER RESET pin must be held at logic high active for  
a minimum of 10 system clock cycles. This initializes the com-  
munication bus and loads the default values listed in Table 9.  
PARALLEL I/O OPERATION  
With the S/P SELECT pin tied high, the parallel I/O mode is  
active. The I/O port is compatible with industry-standard DSPs  
and microcontrollers. Six address bits, eight bidirectional data  
bits, and separate write/read control inputs comprise the I/O  
port pins.  
When configured for serial I/O operation, most pins from the  
AD9852 parallel port are inactive; only some pins are used for  
serial I/O operation. Table 10 describes pin requirements for  
serial I/O operation.  
Parallel I/O operation allows write access to each byte of any  
register in a single I/O operation of up to one per 10.5 ns.  
Readback capability for each register is included to ease  
designing with the AD9852.  
When operating the device in the serial I/O mode, it is best to  
use the external I/O update clock mode to avoid an I/O update  
clock occurring during a serial communication cycle. Such an  
occurrence may cause incorrect programming due to a partial  
data transfer. Therefore, users should write to the device between  
I/O update clocks. To exit the default internal update mode,  
program the device for external update operation at power-up  
before starting the REFCLK signal but after a master reset.  
Starting the REFCLK causes this information to transfer to the  
register bank, forcing the device to switch to external update mode.  
Reads are not guaranteed at 100 MHz, because they are  
intended for software debugging only.  
Parallel I/O operation timing diagrams are shown in Figure 49  
and Figure 50.  
Rev. E | Page 31 of 52  
 
 
AD9852  
Table 9. Register Layout1  
Parallel  
Address  
(Hex)  
Serial  
Address  
(Hex)  
AD9852 Register Layout  
Bit 4 Bit 3  
Default  
Value  
(Hex)  
Bit 7  
Bit 6  
Bit 5  
Bit 2  
Bit 1  
Bit 0  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
0
1
2
Phase Adjust Register 1 <13:8> (Bits 15, 14 don’t care)  
Phase Adjust Register 1 <7:0>  
Phase Adjust Register 2 <13:8> (Bits 15, 14 don’t care)  
Phase Adjust Register 2 <7:0>  
Frequency Tuning Word 1 <47:40>  
Frequency Tuning Word 1 <39:32>  
Frequency Tuning Word 1 <31:24>  
Frequency Tuning Word 1 <23:16>  
Frequency Tuning Word 1 <15:8>  
Frequency Tuning Word 1 <7:0>  
Frequency Tuning Word 2 <47:40>  
Frequency Tuning Word 2 <39:32>  
Frequency Tuning Word 2 <31:24>  
Frequency Tuning Word 2 <23:16>  
Frequency Tuning Word 2 <15:8>  
Frequency Tuning Word 2 <7:0>  
Delta frequency word <47:40>  
Delta frequency word <39:32>  
Delta frequency word <31:24>  
Delta frequency word <23:16>  
Delta frequency word <15:8>  
Phase 1  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
10  
Phase 2  
Frequency 1  
3
Frequency 2  
Delta frequency word <7:0>  
5
Update clock <31:24>  
Update clock <23:16>  
Update clock <15:8>  
Update clock <7:0>  
6
7
Ramp rate clock <19:16> (Bits 23, 22, 21, 20, don’t care)  
Ramp rate clock <15:8>  
Ramp rate clock <7:0>  
Don’t care  
CR [31]  
Don’t care  
Don’t  
care  
Comp  
PD  
Reserved, Control  
always  
low  
DAC PD DIG PD  
DAC PD  
1E  
1F  
20  
Don’t care  
CLR ACC1  
Don’t care  
PLL range  
CLR ACC2  
Bypass  
PLL  
Ref  
Mult 4  
Ref  
Mult 3  
Ref Mult 2 Ref  
Mult 1  
Mode 0 Int/Ext  
update clock  
Ref Mult 0  
64  
01  
20  
Triangle Don’t  
care  
Mode 2  
Mode 1  
Bypass inv  
sinc  
OSK EN  
OSK INT Don’t care Don’t care LSB first SDO active  
CR [0]  
21  
22  
23  
24  
25  
26  
27  
8
9
Output shaped keying multiplier <11:8> (Bits 15, 14, 13, 12 don’t care)  
Output shaped keying multiplier <7:0>  
00  
00  
00  
00  
80  
00  
00  
Don’t care  
Don’t care  
A
B
Output shaped keying ramp rate <7:0>  
Control DAC <11:8> (Bits 15, 14, 13, 12 don’t care)  
Control DAC <7:0> (Data is required to be in twos complement format)  
1 The shaded sections comprise the control register.  
Rev. E | Page 32 of 52  
 
AD9852  
A<5:0>  
D<7:0>  
RD  
A1  
D1  
A2  
D2  
A3  
D3  
tRDHOZ  
tAHD  
SPECIFICATION VALUE  
tRDLOV  
tADV  
DESCRIPTION  
tADV  
15ns  
5ns  
15ns  
10ns  
ADDRESS TO DATA VALID TIME (MAXIMUM)  
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)  
RD LOW TO OUTPUT VALID (MAXIMUM)  
tAHD  
tRDLOV  
tRDHOZ  
RD HIGH TO DATA THREE-STATE (MAXIMUM)  
Figure 49. Parallel Port Read Timing Diagram  
tWR  
A<5:0>  
A1  
A2  
A3  
D<7:0>  
WR  
D1  
D2  
D3  
tASU  
tAHD  
tDSU  
tWRLOW  
tWRHIGH  
tDHD  
SPECIFICATION VALUE DESCRIPTION  
tASU  
8.0ns  
3.0ns  
0ns  
0ns  
2.5ns  
7ns  
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE  
DATA SETUP TIME TO WR SIGNAL ACTIVE  
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE  
DATA HOLD TIME TO WR SIGNAL INACTIVE  
WR SIGNAL MINIMUM LOW TIME  
tDSU  
tADH  
tDHD  
tWRLOW  
tWRHIGH  
tWR  
WR SIGNAL MINIMUM HIGH TIME  
10.5ns MINIMUM WRITE TIME  
Figure 50. Parallel Port Write Timing Diagram  
Table 10. Serial I/O Pin Requirements  
Pin Number  
Mnemonic  
Serial I/O Description  
1 to 8  
14 to 16  
17  
D [7:0]  
A [5:3]  
A2/IO RESET  
A1/SDO  
The parallel data pins are not active; tie these pins to VDD or GND.  
The A5, A4, and A3 parallel address pins are not active; tie these pins to VDD or GND.  
IO RESET.  
SDO.  
18  
19  
20  
21  
A0/SDIO  
I/O UD CLK  
WR/SCLK  
RD/CS  
SDIO.  
Update Clock. Same functionality for serial mode as parallel mode.  
SCLK.  
22  
CS—Chip Select.  
Rev. E | Page 33 of 52  
 
 
 
AD9852  
GENERAL OPERATION OF THE SERIAL INTERFACE  
There are two phases of a serial communication cycle with the  
AD9852. Phase 1 is the instruction cycle, which is the writing of  
an instruction byte into the AD9852 coincident with the first  
eight SCLK rising edges. The instruction byte provides the  
AD9852 serial port controller with information regarding the  
data transfer cycle, which is Phase 2 of the communication  
cycle. The Phase 1 instruction byte defines whether the next  
data transfer is a read or write and the register address to be  
acted upon.  
All data input to the AD9852 is registered on the rising edge of  
SCLK, and all data is driven out of the AD9852 on the falling  
edge of SCLK.  
Figure 51 and Figure 52 are useful in understanding the general  
operation of the AD9852 serial port.  
CS  
INSTRUCTION  
DATA BYTE 1 DATA BYTE 2 DATA BYTE 3  
DATA TRANSFER  
BYTE  
SDIO  
The first eight SCLK rising edges of each communication cycle  
are used to write the instruction byte into the AD9852. The  
remaining SCLK edges are for Phase 2 of the communication  
cycle. Phase 2 is the actual data transfer between the AD9852  
and the system controller. The number of data bytes transferred  
during Phase 2 of the communication cycle is a function of the  
register address. The AD9852 internal serial I/O controller  
expects every byte of the register being accessed to be  
transferred. Table 11 describes how many bytes must be  
transferred.  
INSTRUCTION  
CYCLE  
Figure 51. Using SDIO as a Read/Write Transfer  
CS  
INSTRUCTION  
BYTE  
SDIO  
INSTRUCTION  
CYCLE  
DATA TRANSFER  
DATA BYTE 1 DATA BYTE 2 DATA BYTE 3  
SDO  
Table 11. Register Address vs. Data Bytes Transferred  
DATA TRANSFER  
Serial  
Number  
Register  
Address Register Name  
of Bytes  
Transferred  
Figure 52. Using SDIO as an Input and SDO as an Output  
INSTRUCTION BYTE  
0
1
2
3
4
5
6
7
8
A
Phase Offset Tuning Word Register 1  
2
2
6
6
6
4
3
4
2
1
Phase Offset Tuning Word Register 2  
Frequency Tuning Word 1  
Frequency Tuning Word 2  
Delta frequency register  
Update clock rate register  
Ramp rate clock register  
Control register  
The instruction byte contains the following information:  
MSB  
LSB  
D0  
A0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
R/W  
X
X
X
A3  
A2  
A1  
W
R/ —Bit 7 of the instruction byte determines whether a read  
or write data transfer occurs following the instruction byte.  
Logic high indicates that a read operation will occur. Logic 0  
indicates that a write operation will occur.  
Digital multiplier register  
On/off output shaped keying ramp  
rate register  
B
Control DAC register  
2
Bit 6, Bit 5, and Bit 4 of the instruction byte are dummy bits  
(don’t care).  
At the completion of a communication cycle, the AD9852 serial  
port controller expects the subsequent eight rising SCLK edges  
to be the instruction byte of the next communication cycle. In  
addition, an active high input on the IO RESET pin immediately  
terminates the current communication cycle. After IO RESET  
returns low, the AD9852 serial port controller requires the sub-  
sequent eight rising SCLK edges to be the instruction byte of  
the next communication cycle.  
A3, A2, A1, A0—Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction  
byte determine which register is accessed during the data transfer  
portion of the communication cycle (see Table 9 for register  
address details).  
Rev. E | Page 34 of 52  
 
 
 
 
AD9852  
SERIAL INTERFACE PORT PIN DESCRIPTIONS  
Table 12.  
Pin  
Description  
SCLK  
Serial Clock (Pin 21). The serial clock pin is used to synchronize data to and from the AD9852 and to run the internal state  
machines. The SCLK maximum frequency is 10 MHz.  
CS  
Chip Select (Pin 22). Active low input that allows more than one device on the same serial communication line. The SDO and  
SDIO pins go to a high impedance state when this input is high. If this pin is driven high during a communication cycle, the  
cycle is suspended until CS is reactivated low. The chip select pin can be tied low in systems that maintain control of SCLK.  
SDIO  
SDO  
Serial Data I/O (Pin 19). Data is always written to the AD9852 on this pin. However, this pin can be used as a bidirectional data  
line. The configuration of this pin is controlled by Bit 0 of Register Address 20 hex. The default is Logic 0, which configures the  
SDIO pin as bidirectional.  
Serial Data Out (Pin 18). Data is read from this pin for protocols that use separate lines for transmitting and receiving data.  
In the case where the AD9852 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high  
impedance state.  
IO RESET  
Synchronize I/O Port (Pin 17). Synchronizes the I/O port state machines without affecting the contents of the addressable  
registers. An active high input on the IO RESET pin causes the current communication cycle to terminate. After the IO RESET pin  
returns low (Logic 0), another communication cycle can begin, starting with the instruction byte.  
Notes on Serial Port Operation  
MSB/LSB TRANSFERS  
The AD9852 serial port configuration bits reside in Bit 1 and Bit 0  
of Register Address 20 hex. The configuration changes immediately  
upon a valid I/O update. For multibyte transfers, writing to this  
register can occur during the middle of a communication cycle.  
Care must be taken to compensate for this new configuration  
during the remainder of the current communication cycle.  
The AD9852 serial port can support both MSB- and LSB-first  
data formats. This functionality is controlled by Bit 1 of Serial  
Bank 20 hex. When this bit is set active high, the AD9852 serial  
port is in LSB-first format. This bit defaults low, to the MSB-first  
format. The instruction byte must be written in the format  
indicated by Bit 1 of Serial Register Bank 20 hex. Therefore, if  
the AD9852 is in LSB-first mode, the instruction byte must be  
written from LSB to MSB.  
The system must maintain synchronization with the AD9852;  
otherwise, the internal control logic is not able to recognize further  
instructions. For example, if the system sends the instruction to  
write a 2-byte register and then pulses the SCLK pin for a 3-byte  
register (24 additional SCLK rising edges), communication  
synchronization is lost. In this case, the first 16 SCLK rising  
edges after the instruction cycle properly write the first two data  
bytes into the AD9852, but the subsequent eight rising SCLK  
edges are interpreted as the next instruction byte, not the final  
byte of the previous communication cycle.  
tPRE  
tSCLK  
tSCLKPWH  
CS  
tDSU  
tSCLKPWL  
SCLK  
SDIO  
tDHLD  
FIRST BIT  
SECOND BIT  
SYMBOL  
MIN  
DEFINITION  
tPRE  
30ns  
CS SETUP TIME  
In cases where synchronization is lost between the system and  
the AD9852, the IO RESET pin provides a means to re-establish  
synchronization without reinitializing the entire chip. Asserting  
the IO RESET pin (active high) resets the AD9852 serial port  
state machine, terminating the current I/O operation and forcing  
the device into a state in which the next eight SCLK rising edges  
are understood to be an instruction byte. The IO RESET pin  
must be deasserted (low) before the next instruction byte write  
can begin. Any information written to the AD9852 registers  
during a valid communication cycle prior to loss of synchro-  
nization remains intact.  
tSCLK  
100ns PERIOD OF SERIAL DATA CLOCK  
tDSU  
30ns  
40ns  
40ns  
0ns  
SERIAL DATA SETUP TIME  
tSCLKPWH  
tSCLKPWL  
tDHLD  
SERIAL DATA CLOCK PULSE WIDTH HIGH  
SERIAL DATA CLOCK PULSE WIDTH LOW  
SERIAL DATA HOLD TIME  
Figure 53. Timing Diagram for Data Write to AD9852  
CS  
SCLK  
SDIO  
SDO  
FIRST BIT  
SECOND BIT  
tDV  
SYMBOL MAX DEFINITION  
tDV  
30ns DATA VALID TIME  
Figure 54. Timing Diagram for Read from AD9852  
Rev. E | Page 35 of 52  
 
AD9852  
CONTROL REGISTER DESCRIPTIONS  
The control register is located at Address 1D hex to Address 20 hex (shown in the shaded portion of Table 9). It is composed of 32 bits.  
Bit 31 is located at the top left position, and Bit 0 is located in the lower right position of the shaded area of Table 9. The register has been  
subdivided into bits to make it easier to locate the information associated with specific control categories.  
Table 13. Control Register Bit Descriptions  
Bit  
Description  
CR [31:29]  
CR [28]  
Open.  
The comparator power-down bit. When this bit is set to Logic 1, it indicates to the comparator that a power-down mode is  
active. This bit is an output of the digital section and is an input to the analog section.  
CR [27]  
CR [26]  
CR [25]  
Must always be written to Logic 0. Writing this bit to Logic 1 causes the AD9852 to stop functioning until a master reset is applied.  
The control DAC power-down bit. When this bit is set to Logic 1, it indicates to the control DAC that power-down mode is active.  
The full DAC power-down bit. When this bit is set to Logic 1, it indicates to both the cosine and control DACs, as well as the  
reference, that a power-down mode is active.  
CR [24]  
The digital power-down bit. When this bit is set to Logic 1, it indicates to the digital section that a power-down mode is  
active. Within the digital section, the clocks are forced to dc, effectively powering down the digital section. The PLL still  
accepts the REFCLK signal and continues to output the higher frequency.  
CR [23]  
CR [22]  
Reserved. Write to 0.  
The PLL range bit. The PLL range bit controls the VCO gain. The power-up state of the PLL range bit is Logic 1; a higher gain is  
required for frequencies greater than 200 MHz.  
CR [21]  
The bypass PLL bit, active high. When this bit is active, the PLL is powered down and the REFCLK input is used to drive the  
system clock signal. The power-up state of the bypass PLL bit is Logic 1 with PLL bypassed.  
CR [20:16]  
CR [15]  
The PLL multiplier factor. These bits are the REFCLK multiplication factor unless the bypass PLL bit is set. The PLL multiplier  
valid range is from 4 to 20, inclusive.  
The Clear Accumulator 1 bit. This bit has a one-shot type of function. When this bit is written active (Logic 1), a Clear  
Accumulator 1 signal is sent to the DDS logic, resetting the accumulator value to 0. The bit is then automatically reset, but  
the buffer memory is not reset. This bit allows the user to easily create a sawtooth frequency sweep pattern with minimal  
user intervention. This bit is intended for chirp mode only, but its function is still retained in other modes.  
CR [14]  
CR [13]  
The clear accumulator bit. When this bit is active high, it holds both the Accumulator 1 and Accumulator 2 values at 0 for as  
long as the bit is active. This allows the DDS phase to be initialized via the I/O port.  
The triangle bit. When this bit is set, the AD9852 automatically performs a continuous frequency sweep from F1 to F2  
frequencies and back. The effect is a triangular frequency sweep. When this bit is set, the operating mode must be set to  
ramped FSK.  
CR [12]  
Don’t care.  
CR [11:9]  
The three bits that describe the five operating modes of the AD9852:  
0x0 = single-tone mode  
0x1 = FSK mode  
0x2 = ramped FSK mode  
0x3 = chirp mode  
0x4 = BPSK mode  
CR [8]  
The internal update active bit. When this bit is set to Logic 1, the I/O UD CLK pin is an output and the AD9852 generates the  
I/O UD CLK signal. When this bit is set to Logic 0, external I/O update function is performed, and the I/O UD CLK pin is  
configured as an input.  
CR [7]  
CR [6]  
Reserved. Write to 0.  
This is the inverse sinc filter bypass bit. When this bit is set, the data from the DDS block goes directly to the output shaped  
keying logic, and the clock for the inverse sinc filter is stopped. Default is clear with the filter enabled.  
CR [5]  
CR [4]  
The output shaped keying enable bit. When this bit is set, the output ramping function is enabled and is performed in  
accordance with the CR [4] bit requirements.  
The internal/external output shaped keying control bit. When this bit is set to Logic 1, the output shaped keying factor is  
internally generated and applied to the cosine DAC path. When this bit is cleared (default), the output shaped keying function is  
externally controlled by the user, and the output shaped keying factor is the value of the output shaped keying multiplier  
register. The two output shaped keying multiplier registers also default low so that the output is off at power-up until the device  
is programmed by the user.  
CR [3:2]  
CR [1]  
CR [0]  
Reserved. Write to 0.  
The serial port MSB-/LSB-first bit. Defaults low, MSB first.  
The serial port SDO active bit. Defaults low, inactive.  
Rev. E | Page 36 of 52  
 
AD9852  
INSTRUCTION CYCLE  
DATA TRANSFER CYCLE  
CS  
SCLK  
SDIO  
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 55. Serial Port Write Timing Clock Stall Low  
INSTRUCTION CYCLE  
DATA TRANSFER CYCLE  
CS  
SCLK  
SDIO  
SDO  
I
I
I
I
I
I
I
I
0
DON’T CARE  
7
6
5
4
3
2
1
D
D
D
D
D
D
D
D
O7  
O6  
O5  
O4  
O3  
O2  
O1  
O0  
Figure 56. 3-Wire Serial Port Read Timing Clock Stall Low  
INSTRUCTION CYCLE  
DATA TRANSFER CYCLE  
CS  
SCLK  
SDIO  
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Figure 57. Serial Port Write Timing Clock Stall High  
INSTRUCTION CYCLE  
DATA TRANSFER CYCLE  
CS  
SCLK  
SDIO  
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
7
6
5
4
3
2
1
0
O7  
O6  
O5  
O4  
O3  
O2  
O1  
O0  
Figure 58. 2-Wire Serial Port Read Timing Clock Stall High  
Rev. E | Page 37 of 52  
AD9852  
POWER DISSIPATION AND THERMAL CONSIDERATIONS  
The AD9852 is a multifunctional, high speed device that targets  
a wide variety of synthesizer and agile clock applications. The  
numerous innovative features contained in the device each  
consume incremental power. If enabled in combination, the safe  
thermal operating conditions of the device may be exceeded.  
Careful analysis and consideration of power dissipation and  
thermal management is a critical element in the successful  
application of the AD9852 device.  
JUNCTION TEMPERATURE CONSIDERATIONS  
The power dissipation (PDISS) of the AD9852 device in a given  
application is determined by many operating conditions. Some  
of the conditions have a direct relationship with PDISS, such as  
supply voltage and clock speed, but others are less deterministic.  
The total power dissipation within the device and its effect on  
the junction temperature must be considered when using the  
device. The junction temperature of the device is given by  
Junction Temperature = (Thermal Impedance ×  
Power Consumption) + Ambient Temperature  
The AD9852 device is specified to operate within the industrial  
temperature range of –40°C to +85°C. This specification is con-  
ditional, however, such that the absolute maximum junction  
temperature of 150°C is not exceeded. At high operating tem-  
peratures, extreme care must be taken when operating the device  
to avoid exceeding the junction temperature and potentially  
damaging the device.  
The maximum ambient temperature combined with the  
maximum junction temperature establish the following power  
consumption limits for each package: 4.06 W for ASVZ models  
and 1.71 W for ASTZ models.  
Supply Voltage  
Many variables contribute to the operating junction temperature  
within the device, including  
Because PDISS = V × I, the supply voltage affects power dissipation  
and junction temperature. Users should design for 3.3 V nominally;  
however, the device is guaranteed to meet specifications over the  
full temperature range and over the supply voltage range of  
3.135 V to 3.465 V.  
Package style  
Selected mode of operation  
Internal system clock speed  
Supply voltage  
Clock Speed  
Ambient temperature  
Clock speed directly and linearly influences the total power  
dissipation of the device and therefore the junction temperature.  
As a rule, the user should select the lowest internal clock speed  
possible to support a given application to minimize power  
dissipation. Typically, the usable frequency output bandwidth  
from a DDS is limited to 40% of the clock rate to ensure that the  
requirements on the output low-pass filter are reasonable. For a  
typical DDS application, the system clock frequency should be  
2.5 times the highest desired output frequency.  
The combination of these variables determines the junction  
temperature within the AD9852 device for a given set of  
operating conditions.  
The AD9852 device is available in two package styles: a  
thermally enhanced surface-mount package with an exposed  
heat sink and a standard (nonthermally enhanced) surface-  
mount package. The thermal impedance of these packages is  
16°C/W and 38°C/W, respectively, measured under still air  
conditions.  
Mode of Operation  
The selected mode of operation for the AD9852 significantly  
influences the total power consumption. The AD9852 offers  
many features and modes, each of which imposes an additional  
power requirement. The available features make the AD9852  
suitable for a variety of applications, but the device is designed  
to operate with only a few features enabled in a given application.  
Enabling multiple features at high clock speeds may result in  
exceeding the maximum junction temperature of the die and  
therefore severely limit the long-term reliability of the device.  
Figure 59 and Figure 60 show the power requirements associated  
with each feature of the AD9852. These charts should be used  
as a guide when determining how to optimize the AD9852 for  
reliable operation in a specific application.  
THERMAL IMPEDANCE  
The thermal impedance of a package can be thought of as a  
thermal resistor that exists between the semiconductor surface  
and the ambient air. The thermal impedance is determined by  
the package material and the physical dimensions of the package.  
The dissipation of the heat from the package is directly depen-  
dent on the ambient air conditions and the physical connection  
made between the IC package and the PCB.  
Adequate dissipation of power from the AD9852 relies on all  
power and ground pins of the device being soldered directly to a  
copper plane on a PCB. In addition, the thermally enhanced  
package of the AD9852ASVZ has an exposed paddle on the  
bottom that must be soldered to a large copper plane, which,  
for convenience, can be the ground plane. Sockets for either  
package style of the AD9852 device are not recommended.  
Figure 59 shows the supply current consumed by the AD9852  
over a range of frequencies for two possible configurations. All  
circuits enabled means that the output scaling multipliers, the  
Rev. E | Page 38 of 52  
 
 
AD9852  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
inverse sinc filter, both DACs, and the on-board comparator  
are enabled. Basic configuration means the output scaling  
multipliers, the inverse sinc filter, the control DAC, and the  
on-board comparator are disabled.  
INVERSE SINC FILTER  
Figure 60 shows the approximate current consumed by each of  
the four functions.  
OUTPUT SCALING  
MULTIPLIERS  
1400  
1200  
CONTROL DAC  
COMPARATOR  
1000  
ALL CIRCUITS ENABLED  
0
800  
600  
20  
60  
100  
140  
180  
220  
260  
300  
FREQUENCY (MHz)  
NOTES  
THIS GRAPH ASSUMES THAT THE AD9852 DEVICE IS SOLDERED  
TO A MULTILAYER PCB PER THE RECOMMENDED BEST  
MANUFACTURING PRACTICES AND PROCEDURES FOR THE  
GIVEN PACKAGE TYPE.  
400  
BASIC CONFIGURATION  
200  
Figure 60. Current Consumption by Function vs. Clock Frequency  
0
20  
60  
100  
140  
180  
220  
260  
300  
FREQUENCY (MHz)  
NOTES  
THIS GRAPH ASSUMES THAT THE AD9852 DEVICE IS SOLDERED  
TO A MULTILAYER PCB PER THE RECOMMENDED BEST  
MANUFACTURING PRACTICES AND PROCEDURES FOR THE  
GIVEN PACKAGE TYPE.  
Figure 59. Current Consumption vs. Clock Frequency  
Rev. E | Page 39 of 52  
 
 
AD9852  
EVALUATION OF OPERATING CONDITIONS  
power dissipation limit of 4.1 W and 1.7 W for the thermally and  
nonthermally enhanced packages, respectively. Therefore, for a  
3.3 V nominal power supply voltage, the current consumed by the  
device under full operating conditions must not exceed 515 mA  
for the standard plastic package or 1242 mA for the thermally  
enhanced package. The total set of enabled functions and  
operating conditions for a given application must support these  
current consumption limits.  
The first step in applying the AD9852 is to select the internal  
clock frequency. Clock frequency selections greater than 200 MHz  
require use of the thermally enhanced package (AD9852ASVZ);  
clock frequency selections equal to or less than 200 MHz may  
allow use of the standard (nonthermally enhanced) plastic  
surface-mount package, but more information is needed to  
make this determination.  
The second step is to determine the maximum required  
operating temperature for the AD9852 in a given application.  
Subtract this value from 150°C, which is the maximum junction  
temperature allowed for the AD9852. For the extended indust-  
rial temperature range, the maximum operating temperature is  
85°C, which results in a difference of 65°C. This is the maxi-  
mum temperature gradient the device can experience due to  
power dissipation.  
Figure 59 and Figure 60 can be used to determine the suitability  
of a given AD9852 application in terms of the power dissipation  
requirements. These graphs assume that the AD9852 device is  
soldered to a multilayer PCB according to the recommended best  
manufacturing practices and procedures for a given package type.  
This ensures that the specified thermal impedance specifications  
are achieved.  
THERMALLY ENHANCED PACKAGE  
MOUNTING GUIDELINES  
The third step is to divide this maximum temperature gradient  
by the thermal impedance to determine the maximum power  
dissipation allowed for the application. For this example, 65°C  
divided by the thermal impedance of the package yields a total  
Refer to the AN-772 Application Note for details on mounting  
devices with an exposed paddle.  
Rev. E | Page 40 of 52  
 
AD9852  
EVALUATION BOARD  
An evaluation board is available that supports the AD9852 DDS  
device. This evaluation board consists of a PCB, software, and  
documentation to facilitate bench analysis of the performance of  
the AD9852 device. It is recommended that users of the AD9852  
familiarize themselves with the operation and performance  
capabilities of the device by using the evaluation board. The  
evaluation board should also be used as a PCB reference design  
to ensure optimum dynamic performance from the device.  
GENERAL OPERATING INSTRUCTIONS  
Load the CD software onto the PCs hard disk. Connect a  
printer cable from the PC to the AD9852 evaluation board  
printer port connector labeled J11. The current software  
(Version 1.72) supports Windows® 95 or better operating  
systems.  
Hardware Preparation  
Using the schematic in conjunction with these instructions  
helps acquaint the user with the electrical functioning of the  
evaluation board.  
EVALUATION BOARD INSTRUCTIONS  
The AD9852/AD9854 Rev. E evaluation board includes either  
an AD9852ASVZ or AD9854ASVZ IC.  
Attach power wires to the connector labeled TB1 using the  
screw-down terminals. This is a plastic connector that press-fits  
over a 4-pin header soldered to the board. Table 14 lists the  
connections to each pin.  
The ASVZ package permits 300 MHz operation by virtue of its  
thermally enhanced design. This package has a bottom-side  
heat slug that must be soldered to the ground plane of the  
PCB directly beneath the IC. In this manner, the evaluation  
board PCB ground plane layer extracts heat from the AD9852  
or AD9854 IC package. If device operation is limited to 200 MHz  
or less, the ASTZ package can be used without a heat slug in  
customer installations over the full temperature range.  
Table 14. Power Requirements for DUT Pins1  
AVDD 3.3 V  
DVDD 3.3 V  
VCC 3.3 V  
Ground  
All DUT  
analog pins  
All DUT  
digital pins  
All other  
devices  
All devices  
1 DUT = device under test.  
Evaluation boards for both the AD9852 and AD9854 are  
identical except for the installed IC.  
Clock Input, J25  
To assist in proper placement of the pin header shorting  
jumpers, the instructions refer to direction (left, right, top,  
bottom) as well as header pins to be shorted. Pin 1 for each  
3-pin header is marked on the PCB corresponding with the  
schematic diagram. When following these instructions, position  
the PCB so that the PCB text can be read from left to right. The  
board is shipped with the pin headers configuring the board as  
follows:  
Attach REFCLK to the clock input, J25. This is a single-ended  
input that is routed to the MC100LVEL16D for conversion to  
differential PECL output. This is accomplished by attaching a 2  
V p-p clock or sine wave source to J25. This is a 50 Ω impedance  
point set by R13. The input signal is ac-coupled and then biased  
to the center-switching threshold of the MC100LVEL16D. To  
engage the differential clocking mode of the AD9852, Pin 2 and  
Pin 3 (the bottom two pins) of W3 must be connected with a  
shorting jumper.  
REFCLK for the AD9852 or AD9854 is configured as  
differential. The differential clock signals are provided by  
the MC100LVEL16D differential receiver.  
Input clock for the MC100LVEL16D is single ended via  
J25. This signal may be 3.3 V CMOS or a 2 V p-p sine wave  
capable of driving 50 Ω (R13).  
Both DAC outputs from the AD9852 or AD9854 are  
routed through the two 120 MHz elliptical LP filters, and  
their outputs are connected to J7 (Q, or control DAC) and  
J6 (I , or cosine DAC).  
The signal arriving at the AD9852 is called the reference clock.  
If the user chooses to engage the on-chip PLL clock multiplier,  
this signal is the reference clock for the PLL and the multiplied  
PLL output becomes the system clock. If the user chooses to bypass  
the PLL clock multiplier, the reference clock that has been supplied  
is directly operating the AD9852 and is therefore the system clock.  
Three-State Control  
Three of the following control or switch headers must be  
shorted to allow the provided software to control the evaluation  
board via Printer Port Connector J11: W9, W11, W12, W13,  
W14, and W15.  
The board is set up for software control via the printer port  
connector.  
The output currents of the DAC are configured for 10 mA.  
Rev. E | Page 41 of 52  
 
 
 
AD9852  
the I and Q signals to remove images, aliased harmonics, and  
other spurious signals that are greater than approximately  
120 MHz:  
Programming  
If a PC and Analog Devices software are not used to program  
the AD9852, the W9, W11, W12, W13, W14, and W15 headers  
should be opened (shorting jumpers removed). This effectively  
detaches the PC interface and allows J10 (the 40-pin header) and J1  
to assume control without bus contention. Input signals on J10  
and J1 going to the AD9852 should be 3.3 V CMOS logic levels.  
1. Install shorting jumpers at W7 and W10.  
2. Install a shorting jumper at W16.  
3. Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins)  
of the 3-pin W1 header.  
4. Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins)  
of the 3-pin W4 header.  
Low-Pass Filter Testing  
5. Install a shorting jumper on Pin 2 and Pin 3 (bottom two pins)  
of the 3-pin W2 and W8 headers.  
The purpose of the 2-pin W7 and W10 headers (associated with  
J4 and J5) is to allow the two 50 Ω, 120 MHz filters to be tested  
during PCB assembly without interference from other circuitry  
attached to the filter inputs. Normally, a shorting jumper is attached  
to each header to allow the DAC signals to be routed to the filters.  
If the user wishes to test the filters, the shorting jumpers at W7 and  
W10 should be removed and 50 Ω test signals should be applied at  
the J4 and J5 inputs to the 50 Ω elliptic filters. The user can refer to  
the provided schematic (Figure 61 and Figure 62) and the  
following sections to properly position the remaining shorting  
jumpers.  
The resulting signals appear as nearly pure sine waves and are  
90° out of phase with each other. These filters are designed with  
the assumption that the system clock speed is at or near its  
maximum speed (300 MHz). If the system clock speed is much  
less than 300 MHz, for example 200 MHz, it is possible, or  
inevitable, that unwanted DAC products other than the  
fundamental signal will be passed by the low-pass filters.  
If an AD9852 evaluation board is used, any reference to the Q  
signal should be interpreted to mean the control DAC.  
Observing the Unfiltered IOUT1 and the Unfiltered  
IOUT2 DAC Signals  
IOUT1  
Observing the Filtered IOUT1 and the Filtered  
The unfiltered DAC outputs can be observed at J5 (the I, or  
cosine DAC, signal) and J4 (the Q, or control DAC, signal). Use  
the following procedure to route the two 50 Ω terminated analog  
DAC outputs to the SMB connectors and to disconnect any other  
circuitry.  
The filtered I DAC outputs can be observed at J6 (the true signal)  
and J7 (the complementary signal). Use the following procedure to  
route the 120 MHz low-pass filters in the true and complementary  
output paths of the I DAC to remove images, aliased harmonics,  
and other spurious signals above approximately 120 MHz:  
1. Install shorting jumpers at W7 and W10.  
2. Remove the shorting jumper at W16.  
1. Install shorting jumpers at W7 and W10.  
2. Install a shorting jumper at W16.  
3. Remove the shorting jumper from the 3-pin W1 header.  
4. Install a shorting jumper on Pin 1 and Pin 2 (bottom two  
pins) of the 3-pin W4 header.  
3. Install a shorting jumper on Pin 2 and Pin 3 (top two pins)  
of the 3-pin W1 header.  
4. Install a shorting jumper on Pin 2 and Pin 3 (top two pins)  
of the 3-pin W4 header.  
5. Install a shorting jumper on Pin 2 and Pin 3 (bottom two pins)  
of the 3-pin W2 and W8 headers.  
The raw DAC outputs may appear as a series of quantized  
(stepped) output levels that do not resemble a sine wave until  
they are filtered. The default 10 mA output current develops a  
0.5 V p-p signal across the on-board 50 Ω termination. If the  
observation equipment uses 50 Ω inputs, the DAC develops  
only 0.25 V p-p due to the double termination.  
The resulting signals appear as nearly pure sine waves and are  
180° out of phase with each other. If the system clock speed is  
much less than 300 MHz, for example 200 MHz, it is possible,  
or inevitable, that unwanted DAC products other than the  
fundamental signal will be passed by the low-pass filters.  
If using the AD9852 evaluation board, the user can control  
IOUT2 (the control DAC output) by using the serial or parallel  
ports. The 12-bit, twos complement value(s) is/are written to  
the control DAC register that sets the IOUT2 output to a static  
dc level. Allowable hexadecimal values are 7FF (maximum) to  
800 (minimum), with all 0s being midscale. Rapidly changing  
the contents of the control DAC register (up to 100 MSPS)  
allows IOUT2 to assume any programmable waveform.  
Connecting the High Speed Comparator  
To connect the high speed comparator to the DAC output  
signals use either the quadrature filtered output configuration  
(AD9854 only) or the complementary filtered output configuration  
(both AD9854 and AD9852). Follow Step 1 through Step 4 of  
either the Observing th