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产品型号ADC0848MDC的Datasheet PDF文件预览

June 1999  
ADC0844/ADC0848  
8-Bit µP Compatible A/D Converters with Multiplexer  
Options  
General Description  
Features  
n Easy interface to all microprocessors  
n Operates ratiometrically or with 5 VDC  
voltage reference  
The ADC0844 and ADC0848 are CMOS 8-bit successive ap-  
proximation A/D converters with versatile analog input multi-  
plexers. The 4-channel or 8-channel multiplexers can be  
software configured for single-ended, differential or  
pseudo-differential modes of operation.  
n No zero or full-scale adjust required  
n 4-channel or 8-channel multiplexer with address logic  
n Internal clock  
n 0V to 5V input range with single 5V power supply  
n 0.3" standard width 20-pin or 24-pin DIP  
n 28 Pin Molded Chip Carrier Package  
The differential mode provides low frequency input common  
mode rejection and allows offsetting the analog range of the  
converter. In addition, the A/D’s reference can be adjusted  
enabling the conversion of reduced analog ranges with 8-bit  
resolution.  
The A/Ds are designed to operate from the control bus of a  
wide variety of microprocessors. TRI-STATE® output latches  
that directly drive the data bus permit the A/Ds to be config-  
ured as memory locations or I/O devices to the microproces-  
sor with no interface logic necessary.  
Key Specifications  
n Resolution  
8 Bits  
LSB and 1 LSB  
1
±
±
n Total Unadjusted Error  
n Single Supply  
n Low Power  
2
5 VDC  
15 mW  
40 µs  
n Conversion Time  
Block and Connection Diagrams  
DS005016-1  
*ADC0848 shown in DIP Package CH5-CH8 not included on the ADC0844  
TRI-STATE® is a registered trademark of National Semiconductor Corp.  
© 1999 National Semiconductor Corporation  
DS005016  
www.national.com  
Block and Connection Diagrams (Continued)  
Molded Chip Carrier Package  
Dual-In-Line Package  
Dual-In-Line Package  
DS005016-2  
Top View  
DS005016-29  
DS005016-30  
Top View  
See Ordering Information  
Top View  
Ordering Information  
Temperature  
Total Unadjusted Error  
MUX  
Package  
Outline  
N20A  
1
±
±
1 LSB  
Range  
2
LSB  
Channels  
ADC0844CCN  
4
0˚C to +70˚C  
Molded Dip  
N24C  
ADC0848BCN  
ADC0844BCJ  
ADC0848BCV  
8
4
8
ADC0848CCN  
ADC0844CCJ  
ADC0848CCV  
Molded Dip  
J20A  
Cerdip  
−40˚C to +85˚C  
V28A  
Molded Chip Carrier  
www.national.com  
2
Absolute Maximum Ratings (Notes 1, 2)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales Office/  
Distributors for availability and specifications.  
Lead Temperature  
(Soldering, 10 seconds)  
Dual-In-Line Package (Plastic)  
Dual-In-Line Package (Ceramic)  
Molded Chip Carrier Package  
Vapor Phase (60 seconds)  
Infrared (15 seconds)  
260˚C  
300˚C  
Supply Voltage (VCC  
)
6.5V  
215˚C  
220˚C  
Voltage  
Logic Control Inputs  
−0.3V to +15V  
−0.3V to VCC+0.3V  
5 mA  
At Other Inputs and Outputs  
Input Current at Any Pin (Note 3)  
Package Input Current (Note 3)  
Storage Temperature  
Operating Conditions (Notes 1, 2)  
20 mA  
Supply Voltage (VCC  
)
4.5 VDC to 6.0 VDC  
−65˚C to +150˚C  
875 mW  
Temperature Range  
T
MINTATMAX  
=
Package Dissipation at TA 25˚C  
ADC0844CCN, ADC0848BCN,  
ADC0848CCN  
0˚CTA70˚C  
ESD Susceptibility (Note 4)  
800V  
ADC0844BCJ, ADC0844CCJ,  
ADC0848BCV, ADC0848CCV  
−40˚CTA85˚C  
Electrical Characteristics  
=
The following specifications apply for VCC 5 VDC unless otherwise specified.Boldface limits apply from TMIN to TMAX; all  
=
=
other limits TA Tj 25˚C.  
ADC0844CCN  
ADC0848BCN, ADC0848CCN  
ADC0848BCV, ADC0848CCV  
ADC0844BCJ  
ADC0844CCJ  
Limit  
Units  
Parameter  
Conditions  
Typ  
Tested  
Limit  
Design  
Limit  
Typ  
Tested  
Limit  
Design  
(Note 5)  
(Note 5)  
Limit  
(Note 6)  
(Note 7)  
(Note 6)  
(Note 7)  
CONVERTER AND MULTIPLEXER CHARACTERISTICS  
=
Maximum Total  
VREF 5.00 VDC  
Unadjusted Error  
(Note 8)  
1
1
±
±
ADC0844BCN, ADC0848BCN, BCV  
ADC0844CCN, ADC0848CCN, CCV  
ADC0844CCJ  
2  
2
LSB  
LSB  
LSB  
k  
±
±
1
1
±
1
Minimum Reference  
Input Resistance  
2.4  
2.4  
1.1  
2.4  
2.4  
1.2  
5.4  
1.1  
5.9  
Maximum Reference  
Input Resistance  
5.9  
kΩ  
V
Maximum Common-Mode  
Input Voltage  
(Note 9)  
VCC+0.05  
VCC+0.05  
VCC+0.05  
Minimum Common-Mode  
Input Voltage  
(Note 9)  
GND−0.05  
GND−0.05  
GND−0.05  
V
1
1
1
±
±
±
±
±
±
±
±
±
±
DC Common-Mode Error  
Power Supply Sensitivity  
Off Channel Leakage  
Current  
Differential Mode  
1/16  
1/16  
4
8
1/16  
1/16  
4
8
4
8
LSB  
LSB  
1
1
1
=
±
VCC 5V 5%  
(Note 10)  
=
On Channel 5V,  
−1  
1
−0.1  
0.1  
−1  
1
µA  
µA  
=
Off Channel 0V  
=
On Channel 0V,  
=
Off Channel 5V  
DIGITAL AND DC CHARACTERISTICS  
VIN(1), Logical “1” Input  
Voltage (Min)  
=
VCC 5.25V  
2.0  
0.8  
1
2.0  
0.8  
2.0  
0.8  
1
V
V
=
VCC 4.75V  
VIN(0), Logical “0” Input  
Voltage (Max)  
=
IIN(1), Logical “1” Input  
Current (Max)  
VIN 5.0V  
0.005  
0.005  
µA  
µA  
=
IIN(0), Logical “0” Input  
Current (Max)  
VIN 0V  
−0.005  
−1  
−0.005  
−1  
=
VCC 4.75V  
VOUT(1), Logical “1”  
Output Voltage (Min)  
=
IOUT −360 µA  
2.4  
4.5  
2.8  
4.6  
2.4  
4.5  
V
V
=
IOUT −10 µA  
3
www.national.com  
Electrical Characteristics (Continued)  
=
The following specifications apply for VCC 5 VDC unless otherwise specified.Boldface limits apply from TMIN to TMAX; all  
=
=
other limits TA Tj 25˚C.  
ADC0844CCN  
ADC0848BCN, ADC0848CCN  
ADC0848BCV, ADC0848CCV  
ADC0844BCJ  
ADC0844CCJ  
Limit  
Units  
Parameter  
Conditions  
Typ  
Tested  
Limit  
Design  
Limit  
Typ  
Tested  
Limit  
Design  
(Note 5)  
(Note 5)  
Limit  
(Note 6)  
(Note 7)  
(Note 6)  
(Note 7)  
DIGITAL AND DC CHARACTERISTICS  
VOUT(0), Logical “0”  
=
VCC 4.75V  
0.4  
0.34  
0.4  
V
=
IOUT 1.6 mA  
Output Voltage (Max)  
IOUT, TRI-STATE Output  
Current (Max)  
=
VOUT 0V  
−0.01  
0.01  
−14  
−3  
3
−0.01  
0.01  
−14  
−0.3  
0.3  
−3  
3
µA  
µA  
=
VOUT 5V  
=
ISOURCE, Output Source  
Current (Min)  
VOUT 0V  
−6.5  
−7.5  
−6.5  
mA  
=
ISINK, Output Sink  
VOUT VCC  
16  
1
8.0  
2.5  
16  
1
9.0  
2.3  
8.0  
2.5  
mA  
mA  
Current (Min)  
=
ICC, Supply Current (Max)  
CS 1, VREF  
Open  
AC Electrical Characteristics  
=
=
=
The following specifications apply for VCC 5VDC, tr tf 10 ns unless otherwise specified. Boldface limits apply from TMIN  
=
=
to TMAX; all other limits TA Tj 25˚C.  
Tested  
Limit  
(Note 6)  
40  
Design  
Limit  
Parameter  
Conditions  
Typ  
(Note 5)  
30  
Units  
(Note 7)  
60  
tC, Maximum Conversion Time (See Graph)  
µs  
ns  
ns  
t
W(WR), Minimum WR Pulse Width  
(Note 11)  
50  
150  
=
t
ACC, Maximum Access Time (Delay from Falling Edge of  
CL 100 pF  
145  
225  
200  
RD to Output Data Valid)  
1H, t0H, TRI-STATE Control (Maximum Delay from Rising  
Edge of RD to Hi-Z State)  
WI, tRI, Maximum Delay from Falling Edge of WR or RD to  
(Note 11)  
=
=
t
CL 10 pF, RL 10k  
125  
200  
ns  
ns  
(Note 11)  
t
(Note 11)  
400  
Reset of INTR  
tDS, Minimum Data Set-Up Time  
(Note 11)  
(Note 11)  
50  
0
100  
50  
ns  
ns  
pF  
pF  
tDH, Minimum Data Hold Time  
C
C
IN, Capacitance of Logic Inputs  
5
OUT, Capacitance of Logic Outputs  
5
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating  
the device beyond its specified operating conditions.  
Note 2: All voltages are measured with respect to the ground pins.  
+
<
>
V ) the absolute value of the current at that pin should be limited  
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V  
IN IN  
V or V  
IN  
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.  
Note 4: Human body model, 100 pF discharged through a 1.5 kresistor.  
Note 5: Typicals are at 25˚C and represent most likely parametric norm.  
Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).  
Note 7: Design limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels.  
Note 8: Total unadjusted error includes offset, full-scale, linearity, and multiplexer error.  
Note 9: For V (−) V (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input  
IN IN  
voltages one diode drop below ground or one diode drop greater than V supply. Be careful during testing at low V levels (4.5V), as high level analog inputs (5V)  
CC CC  
can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias  
of either diode. This means that as long as the analog V does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an  
IN  
absolute 0 V to 5 V input voltage range will therefore require a minimum supply voltage of 4.950 V over temperature variations, initial tolerance and loading.  
D
C
D
C
D
C
Note 10: Off channel leakage current is measured after the channel selection.  
Note 11: The temperature coefficient is 0.3%/˚C.  
www.national.com  
4
Typical Performance Characteristics  
Logic Input Threshold  
Voltage vs Supply Voltage  
Output Current vs  
Temperature  
Power Supply Current vs  
Temperature  
DS005016-32  
DS005016-31  
DS005016-33  
Linearity Error vs VREF  
Conversion Time vs VSUPPLY  
DS005016-34  
DS005016-35  
Conversion Time vs  
Temperature  
Unadjusted Offset Error vs  
VREF Voltage  
DS005016-36  
DS005016-37  
5
www.national.com  
TRI-STATE Test Circuits and Waveforms  
=
t1H, CL 10 pF  
t1H  
DS005016-5  
DS005016-4  
=
t
20 ns  
r
=
t0H, CL 10 pF  
t0H  
DS005016-7  
=
r
t
20 ns  
DS005016-6  
Leakage Current Test Circuit  
DS005016-8  
www.national.com  
6
Timing Diagrams  
Programming New Channel Configuration and Starting a Conversion  
DS005016-9  
Note 12: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR .  
Note 13: MA stands for MUX address.  
Using the Previously Selected Channel Configuration and Starting a Conversion  
DS005016-10  
7
www.national.com  
ADC0848 Functional Block Diagram  
www.national.com  
8
The actual voltage converted is always the difference be-  
tween an assigned “+” input terminal and a “−” input terminal.  
The polarity of each input terminal of the pair being con-  
verted indicates which line the converter expects to be the  
most positive. If the assigned “+” input is less than the “−” in-  
put the converter responds with an all zeros output code.  
Functional Description  
The ADC0844 and ADC0848 contain  
a 4-channel and  
8-channel analog input multiplexer (MUX) respectively. Each  
MUX can be configured into one of three modes of operation  
differential, pseudo-differential, and single ended. These  
modes are discussed in the Applications Information Sec-  
tion. The specific mode is selected by loading the MUX ad-  
dress latch with the proper address (see Table 1 and Table  
2). Inputs to the MUX address latch (MA0-MA4) are common  
with data bus lines (DB0-DB4) and are enabled when the RD  
line is high. A conversion is initiated via the CS and WR lines.  
If the data from a previous conversion is not read, the INTR  
line will be low. The falling edge of WR will reset the INTR  
line high and ready the A/D for a conversion cycle. The rising  
edge of WR, with RD high, strobes the data on the MA0/  
DB0-MA4/DB4 inputs into the MUX address latch to select a  
new input configuration and start a conversion. If the RD line  
is held low during the entire low period of WR the previous  
MUX configuration is retained, and the data of the previous  
conversion is the output on lines DB0-DB7. After the conver-  
sion cycle (tC 40 µs), which is set by the internal clock fre-  
quency, the digital data is transferred to the output latch and  
the INTR is asserted low. Taking CS and RD low resets INTR  
output high and outputs the conversion result on the data  
lines (DB0-DB7).  
A unique input multiplexing scheme has been utilized to pro-  
vide multiple analog channels. The input channels can be  
software configured into three modes: differential, single  
ended, or pseudo-differential. Figure 1 shows the three  
modes using the 4-channel MUX ADC0844. The eight inputs  
of the ADC0848 can also be configured in any of the three  
modes. In the differential mode, the ADC0844 channel inputs  
are grouped in pairs, CH1 with CH2 and CH3 with CH4. The  
polarity assignment of each channel in the pair is inter-  
changeable. The single-ended mode has CH1–CH4 as-  
signed as the positive input with the negative input being the  
analog ground (AGND) of the device. Finally, in the  
pseudo-differential mode CH1–CH3 are positive inputs ref-  
erenced to CH4 which is now  
a pseudo-ground. This  
pseudo-ground input can be set to any potential within the in-  
put common-mode range of the converter. The analog signal  
conditioning required in transducer-based data acquisition  
systems is significantly simplified with this type of input flex-  
ibility. One converter package can now handle ground refer-  
enced inputs and true differential inputs as well as signals  
with some arbitrary reference voltage.  
Applications Information  
The analog input voltages for each channel can range from  
50 mV below ground to 50 mV above VCC (typically 5V) with-  
out degrading conversion accuracy.  
1.0 MULTIPLEXER CONFIGURATION  
The design of these converters utilizes a sampled-data com-  
parator structure which allows a differential analog input to  
be converted by a successive approximation routine.  
TABLE 1. ADC0844 MUX ADDRESSING  
MUX Address  
CS  
WR  
RD  
Channel#  
MUX  
MA3  
X
MA2  
L
MA1  
L
MA0  
L
CH1  
+
CH2  
CH3  
CH4  
AGND  
Mode  
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
X
L
L
H
L
+
Differential  
X
L
H
H
L
+
+
X
L
H
L
L
H
H
H
H
H
H
H
X
+
+
L
L
L
H
L
+
+
Single-Ended  
L
H
H
L
+
L
H
L
+
H
H
H
X
Pseudo-  
L
L
L
H
L
Differential  
H
X
+
X
Previous Channel Configuration  
=
X
don’t care  
9
www.national.com  
Applications Information (Continued)  
4 Single-Ended  
2 Differential  
DS005016-12  
DS005016-13  
3 Pseudo-Differential  
Combined  
DS005016-14  
DS005016-15  
FIGURE 1. Analog Input Multiplexer Options  
most typical). The time interval between sampling the “+” in-  
2.0 REFERENCE CONSIDERATIONS  
1
put and then the “−” inputs is  
change in the common-mode voltage during this short time  
interval can cause conversion errors. For  
common-mode signal this error is:  
2
of a clock period. The  
The voltage applied to the reference input of these convert-  
ers defines the voltage span of the analog input (the differ-  
ence between VIN(MAX) and VIN(MIN)) over which the 256  
possible output codes apply. The devices can be used in ei-  
ther ratiometric applications or in systems requiring absolute  
accuracy. The reference pin must be connected to a voltage  
source capable of driving the minimum reference input resis-  
tance of 1.1 k. This pin is the top of a resistor divider string  
used for the successive approximation conversion.  
a sinusoidal  
DS005016-38  
where fCM is the frequency of the common-mode signal,  
In a ratiometric system (Figure 2a), the analog input voltage  
is proportional to the voltage used for the A/D reference. This  
voltage is typically the system power supply, so the VREF pin  
can be tied to VCC. This technique relaxes the stability re-  
quirements of the system reference as the analog input and  
A/D reference move together maintaining the same output  
code for a given input condition.  
V
peak is its peak voltage value and tC is the conversion time.  
For a 60 Hz common-mode signal to generate a 1  
4
LSB error  
(5 mV) with the converter running at 40 µS, its peak value  
would have to be 5.43V. This large a common-mode signal is  
much greater than that generally found in a well designed  
data acquisition system.  
For absolute accuracy (Figure 2b), where the analog input  
varies between very specific voltage limits, the reference pin  
can be biased with a time and temperature stable voltage  
source. The LM385 and LM336 reference diodes are good  
low current devices to use with these converters.  
The maximum value of the reference is limited to the VCC  
supply voltage. The minimum value, however, can be quite  
small (see Typical Performance Characteristics) to allow di-  
rect conversions of transducer outputs providing less than a  
5V output span. Particular care must be taken with regard to  
noise pickup, circuit layout and system error voltage sources  
when operating with a reduced span due to the increased  
sensitivity of the converter (1 LSB equals VREF/256).  
3.0 THE ANALOG INPUTS  
3.1 Analog Differential Voltage Inputs and  
Common-Mode Rejection  
The differential input of these converters actually reduces  
the effects of common-mode input noise, a signal common  
to both selected “+” and “−” inputs for a conversion (60 Hz is  
www.national.com  
10  
Applications Information (Continued)  
TABLE 2. ADC0848 MUX Addressing  
MUX Address  
CS WR RD  
Channel  
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 AGND  
MUX  
MA4 MA3 MA2 MA1 MA0  
Mode  
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
+
+
L
L
H
H
L
+
+
L
L
L
H
L
Differential  
L
H
H
H
H
L
+
+
L
L
H
L
L
H
H
L
+
+
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
+
L
L
L
H
L
+
L
L
H
H
L
+
L
L
L
H
L
+
Single-Ended  
L
H
H
H
H
L
+
L
L
H
L
+
L
H
H
L
+
L
H
L
+
H
H
H
H
H
H
H
X
+
L
L
H
L
+
L
H
H
L
+
Pseudo-  
L
L
L
H
L
+
Differential  
H
H
H
X
+
L
H
L
+
H
X
+
Previous Channel Configuration  
X
3.2 Input Current  
put 0000 0000 digital code for this minimum input voltage by  
biasing any VIN (−) input at this VIN(MIN) value. This is useful  
for either differential or pseudo-differential modes of input  
channel configuration.  
Due to the sampling nature of the analog inputs, short dura-  
tion spikes of current enter the “+” input and exit the “−” input  
at the clock edges during the actual conversion. These cur-  
rents decay rapidly and do not cause errors as the internal  
comparator is strobed at the end of a clock period. Bypass  
capacitors at the inputs will average these currents and  
cause an effective DC current to flow through the output re-  
sistance of the analog signal source. Bypass capacitors  
should not be used if the source resistance is greater than  
1 k.  
The zero error of the A/D converter relates to the location of  
the first riser of the transfer function and can be measured by  
grounding the Vinput and applying a small magnitude posi-  
tive voltage to the V+ input. Zero error is the difference be-  
tween actual DC input voltage which is necessary to just  
cause an output digital code transition from 0000 0000 to  
1
0000 0001 and the ideal  
2  
LSB value (1⁄  
LSB 9.8 mV for  
=
2
=
VREF 5.000 VDC).  
3.3 Input Source Resistance  
4.2 Full-Scale  
The limitation of the input source resistance due to the DC  
leakage currents of the input multiplexer is important. A  
The full-scale adjustment can be made by applying a differ-  
ential input voltage which is 1 1  
LSB down from the desired  
±
worst-case leakage current of 1 µA over temperature will  
2
create a 1 mV input error with a 1 ksource resistance. An  
op amp RC active low pass filter can provide both imped-  
ance buffering and noise filtering should a high impedance  
signal source be required.  
analog full-scale voltage range and then adjusting the mag-  
nitude of the VREF input for a digital output code changing  
from 1111 1110 to 1111 1111.  
4.3 Adjusting for an Arbitrary Analog Input Voltage  
Range  
4.0 OPTIONAL ADJUSTMENTS  
4.1 Zero Error  
If the analog zero voltage of the A/D is shifted away from  
ground (for example, to accommodate an analog input signal  
which does not go to ground), this new zero reference  
The zero of the A/D does not require adjustment. If the mini-  
mum analog input voltage value, VIN(MIN), is not ground, a  
zero offset can be done. The converter can be made to out-  
should be properly adjusted first. A VIN (+) voltage which  
1
equals this desired zero reference plus  
2 LSB (where the  
11  
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reference voltage at the corresponding “−” input should then  
be adjusted to just obtain the 00HEX to 01HEX code transition.  
Applications Information (Continued)  
=
LSB is calculated for the desired analog span, 1 LSB ana-  
log span/256) is applied to selected “+” input and the zero  
DS005016-16  
DS005016-17  
a) Ratiometric  
b) Absolute with a Reduced Span  
FIGURE 2. Referencing Examples  
The full-scale adjustment should be made [with the proper  
VIN (−) voltage applied] by forcing a voltage to the VIN (+) in-  
put which is given by:  
The VREF (or VCC) voltage is then adjusted to provide a code  
change from FEHEX to FFHEX. This completes the adjust-  
ment procedure.  
For an example see the Zero-Shift and Span Adjust circuit  
below.  
=
where VMAX the high end of the analog input range and  
=
VMIN the low end (the offset zero) of the analog range. (Both  
are ground referenced.)  
Zero-Shift and Span Adjust (2VVIN5V)  
DS005016-18  
www.national.com  
12  
Applications Information (Continued)  
Differential Voltage Input 9-Bit A/D  
DS005016-19  
Span Adjust (0VVIN3V)  
DS005016-20  
Protecting the Input  
DS005016-21  
Diodes are 1N914  
13  
www.national.com  
Applications Information (Continued)  
High Accuracy Comparators  
DS005016-22  
=
>
<
DO all 1s if V (+)  
V
V
(−)  
(−)  
IN  
IN  
=
DO all 0s if V (+)  
IN  
IN  
Operating with Automotive Ratiometric Transducers  
DS005016-23  
=
*V (−) 0.15 V  
IN CC  
15% of V V  
85% of V  
CC  
CC XDR  
www.national.com  
14  
Applications Information (Continued)  
A Stand Alone Circuit  
DS005016-25  
Note: DUT pin numbers in parentheses are for ADC0844, others are for ADC0848.  
Start a Conversion without Updating the Channel Configuration  
DS005016-26  
CS WR will update the channel configuration and start a conversion.  
CS RD will read the conversion data and start a new conversion without updating the channel configuration.  
Waiting for the end of this conversion is not necessary. A CS WR can immediately follow the CSRD .  
15  
www.national.com  
Applications Information (Continued)  
ADC0844 — INS8039 Interface  
DS005016-27  
SAMPLE PROGRAM FOR ADC0844 — INS8039 INTERFACE  
CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS  
ORG  
JMP  
0H  
0000  
0010  
04 10  
B9 FF  
BEGIN  
10H  
;START PROGRAM AT ADDR 10  
ORG  
MOV  
;MAIN PROGRAM  
BEGIN:  
R1,#0FFH  
;LOAD R1 WITH A UNUSED ADDR  
;LOCATION  
0012  
0014  
0016  
B8 20  
89 FF  
23 00  
MOV  
ORL  
MOV  
R0,#20H  
P1,#0FFH  
A,00H  
;A/D DATA ADDRESS  
;SET PORT 1 OUTPUTS HIGH  
;LOAD THE ACC WITH A/D MUX DATA  
;CH1 AND CH2 DIFFERENTIAL  
;CALL THE CONVERSION SUBROUTINE  
;LOAD THE ACC WITH A/D MUX DATA  
;CH3 AND CH4 DIFFERENTIAL  
;INCREMENT THE A/D DATA ADDRESS  
;CALL THE CONVERSION SUBROUTINE  
0018  
001A  
14 50  
23 02  
CALL  
MOV  
CONV  
A,#02H  
001C  
001D  
18  
INC  
R0  
14 50  
CALL  
CONV  
;CONTINUE MAIN PROGRAM  
;CONVERSION SUBROUTINE  
;ENTRY:ACC — A/D MUX DATA  
;EXIT: ACC — CONVERTED DATA  
ORG  
ANL  
MOVX  
IN  
50H  
0050  
0052  
0053  
99 FE  
91  
CONV:  
LOOP:  
P1,#0FEH  
;CHIP SELECT THE A/D  
@
R1,A  
;LOAD A/D MUX & START CONVERSION  
;INPUT INTR STATE  
09  
A,P1  
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16  
Applications Information (Continued)  
SAMPLE PROGRAM FOR ADC0844 — INS8039 INTERFACE  
CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS (Continued)  
=
0054  
0056  
0057  
0059  
005A  
32 53  
81  
JB1  
LOOP  
;IF INTR 1 GOTO LOOP  
=
@
A, R1  
MOVX  
ORL  
MOV  
RET  
;IF INTR 0 INPUT A/D DATA  
89 01  
A0  
P1,&01H  
;CLEAR THE A/D CHIP SELECT  
;STORE THE A/D DATA  
@
R0,A  
83  
;RETURN TO MAIN PROGRAM  
I/O Interface to NSC800  
DS005016-28  
SAMPLE PROGRAM FOR ADC0848 — NSC800 INTERFACE  
0008  
000F  
001F  
3C00  
NCONV  
DEL  
EQU  
EQU  
EQU  
EQU  
16  
15  
;DELAY 50 µsec CONVERSION  
;THE BOARD ADDRESS  
;START OF RAM FOR A/D  
;DATA  
CS  
1FH  
003CH  
ADDTA  
0000'  
0004'  
0008'  
000A'  
000C'  
000F'  
0012'  
08 09 0A 0B  
0C 0D 0E 0F  
0E 1F  
MUXDTA:  
START:  
DB  
DB  
LD  
08H,09H,0AH,0BH  
0CH,0DH,0EH,0FH  
C,CS  
;MUX DATA  
06 16  
LD  
B,NCONV  
21 0000'  
11 003C  
ED A3  
LD  
HL,MUXDTA  
DE,ADDTA  
LD  
STCONV:  
WAIT:  
OUTI  
;LOAD A/D’S MUX DATA  
;AND START A CONVERSION  
=
0014'  
EB  
EX  
DE,HL  
;HL RAM ADDRESS FOR THE  
;A/D DATA  
0015'  
0017'  
0018'  
001B'  
3E 0F  
3D  
LD  
A,DEL  
A
DEC  
JP  
;WAIT 50 µsec FOR THE  
;CONVERSION TO FINISH  
;STORE THE A/D’S DATA  
;CONVERTED ALL INPUTS?  
C2 0013'  
ED A2  
NZ,WAIT  
INI  
001D'  
001E'  
EB  
EX  
JP  
DE,HL  
C2 000E'  
NZ,STCONV  
;IF NOT GOTO STCONV  
END  
Note 14: This routine sequentially programs the MUX data latch in the signal-ended mode. For CH1-CH8 a conversion is started, then a 50 µs wait for the A/D to  
complete a conversion and the data is stored at address ADDTA for CH1, ADDTA + 1 for CH2, etc.  
17  
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Physical Dimensions inches (millimeters) unless otherwise noted  
Ceramic Dual-In-Line Package (J)  
NS Package Number J20A  
Molded Dual-In-Line Package (N)  
NS Package Number N20A  
www.national.com  
18  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
Molded Dual-In-Line Package (N)  
NS Package Number N24C  
19  
www.national.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
Molded Chip Carrier Package (V)  
NS Package Number V28A  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL  
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant  
into the body, or (b) support or sustain life, and  
whose failure to perform when properly used in  
accordance with instructions for use provided in the  
labeling, can be reasonably expected to result in a  
significant injury to the user.  
2. A critical component is any component of a life  
support device or system whose failure to perform  
can be reasonably expected to cause the failure of  
the life support device or system, or to affect its  
safety or effectiveness.  
National Semiconductor  
Corporation  
Americas  
Tel: 1-800-272-9959  
Fax: 1-800-737-7018  
Email: support@nsc.com  
National Semiconductor  
Europe  
National Semiconductor  
Asia Pacific Customer  
Response Group  
Tel: 65-2544466  
Fax: 65-2504466  
National Semiconductor  
Japan Ltd.  
Tel: 81-3-5639-7560  
Fax: 81-3-5639-7507  
Fax: +49 (0) 1 80-530 85 86  
Email: europe.support@nsc.com  
Deutsch Tel: +49 (0) 1 80-530 85 85  
English Tel: +49 (0) 1 80-532 78 32  
Français Tel: +49 (0) 1 80-532 93 58  
Italiano Tel: +49 (0) 1 80-534 16 80  
Email: sea.support@nsc.com  
www.national.com  
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.  
配单直通车
ADC0848MDC产品参数
型号:ADC0848MDC
生命周期:Transferred
IHS 制造商:NATIONAL SEMICONDUCTOR CORP
包装说明:DIE, DIE OR CHIP
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.53
Is Samacsys:N
最大模拟输入电压:5.05 V
最小模拟输入电压:-0.05 V
最长转换时间:60 µs
转换器类型:ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码:X-XUUC-N
模拟输入通道数量:8
位数:8
功能数量:1
最高工作温度:70 °C
最低工作温度:
输出位码:BINARY
输出格式:PARALLEL, 8 BITS
封装主体材料:UNSPECIFIED
封装代码:DIE
封装等效代码:DIE OR CHIP
封装形状:UNSPECIFIED
封装形式:UNCASED CHIP
电源:5 V
认证状态:Not Qualified
子类别:Analog to Digital Converters
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子形式:NO LEAD
端子位置:UPPER
Base Number Matches:1
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