ADC1415S105HN-C1全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

当前位置：IC37首页_>A字母起始型号索引_>A字母起始型号索引第432页更新时间：2024-10-31 17:27:19

批量询价
供应商
型号
数量
厂商
封装
批号
交易说明
询价

柒号芯城电子商务（深圳）有限公司
ADC1415S105HN-C1
数量-
厂家-
封装-
批号-
-
QQ：2881677436 复制
QQ：2881620402 复制
18922803401

深圳市中利达电子科技有限公司
ADC1415S105HN-C1
数量-
厂家-
封装-
批号-
-
QQ：1902134819 复制
QQ：2881689472 复制
0755-83200645/13686833545

深圳市芯福林电子有限公司
ADC1415S105HN-C1
数量-
厂家-
封装-
批号-
-
QQ：2881495808 复制
QQ：308365177 复制
13418564337

北京元坤伟业科技有限公司
ADC1415S105HN-C1
数量-
厂家-
封装-
批号-
-
QQ：857273081 复制
QQ：1594462451 复制
010-62104931、62106431、62104891、62104791

首天国际（深圳）科技有限公司
ADC1415S105HN-C1
数量-
厂家-
封装-
批号-
-
QQ：528164397 复制
QQ：1318502189 复制
0755-82807802/82807803

集好芯城
ADC1415S105HN-C1

数量1068
厂家Renesas Electronics America Inc.
封装
批号最新批次
原厂原装公司现货
QQ：3008092965 复制
QQ：3008092965 复制
0755-83239307

深圳市中杰盛科技有限公司销售2部
ADC1415S105HN-C1

数量28620
厂家IDT
封装40-VFQFPN
批号24+
数据采集IC★★★绝对有货
QQ：1125805706 复制
0755-22968359

深圳市一线半导体有限公司
ADC1415S105HN-C18

数量9713
厂家IDT. Integrated Device Technology Inc
封装
批号
全新原装部分现货其他订货
QQ：2881493920 复制
QQ：2881493921 复制
0755-88608801多线

深圳市一线半导体有限公司
ADC1415S105HN-C1

数量3728
厂家IDT. Integrated Device Technology Inc
封装
批号
全新原装部分现货其他订货
QQ：2881493920 复制
QQ：2881493921 复制
0755-88608801多线

深圳市芯泽盛世科技有限公司
ADC1415S105HN-C1

数量3000
厂家RENESAS
封装
批号23+
全新原装正品价优
QQ：2881147141 复制
0755-89697675

深圳市科宏特电子有限公司
ADC1415S105HN-C1

数量36000000
厂家Renesas
封装
批号2001+
原装正品
QQ：2856990945 复制
0755-83046318

深圳市科雨电子有限公司
ADC1415S105HN-C18

数量1001
厂家IDT
封装QFN-40
批号21+
★体验愉快问购元件！！就找我吧!《停产物料》
QQ：97671956 复制
171-4729-1886（微信同号）

深圳市科雨电子有限公司
ADC1415S105HN-C1

数量1001
厂家IDT
封装QFN-40
批号21+
★体验愉快问购元件！！就找我吧!《停产物料》ADC1415S125/DB
QQ：97671959 复制
171-4729-9698（微信同号）

产品型号ADC1415S105HN-C1的Datasheet PDF文件预览

ADC1415S series

Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps

with input buffer; CMOS or LVDS DDR digital outputs

Rev. 05 — 2 July 2012

Product data sheet

1. General description

The ADC1415S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performance and low power consumption at sample rates up to 125 Msps.

Pipelined architecture and output error correction ensure the ADC1415S is accurate

enough to guarantee zero missing codes over the entire operating range. Supplied from a

single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,

thanks to a separate digital output supply.

The ADC1415S supports the Low Voltage Differential Signalling (LVDS) Double Data

Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the

user to easily configure the ADC.

The device also includes a SPI programmable full-scale to allow flexible input voltage

range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the

baseband to input frequencies of 170 MHz or more, the ADC1415S is ideal for use in

communications, imaging and medical applications - especially in high Intermediate

Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures

that the input impedance remains constant and low and the performance consistent over

a wide frequency range.

2. Features and benefits

 SNR, 72 dBFS; SFDR, 86 dBc

 Input bandwidth, 600 MHz

 Power dissipation, 635 mW at 80 Msps,

including analog input buffer

 Sample rate up to 125 Msps

 14-bit pipelined ADC core

 Clock input divided by 2 for less jitter

contribution

 Serial Peripheral Interface (SPI)

 Duty cycle stabilizer

 Integrated input buffer

 Fast OuT-of-Range (OTR) detection

 Flexible input voltage range: 1 V (p-p) to  Offset binary, two’s complement, gray

2 V (p-p)

code

 CMOS or LVDS DDR digital outputs

 Power-down mode and Sleep mode

 Pin compatible with ADC1215S series,  HVQFN40 package

ADC1015S series and the

ADC1115S125

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

3. Applications

 Wireless and wired broadband

communications

 Spectral analysis

 Portable instrumentation

 Imaging systems

 Ultrasound equipment

 Software defined radio

 Digital predistortion loop, power

amplifier linearization

4. Ordering information

Table 1.

Ordering information

Type number

f_s(Msps) Package

Name

Description

Version

ADC1415S125HN-C1 125

ADC1415S105HN-C1 105

ADC1415S080HN-C1 80

ADC1415S065HN-C1 65

HVQFN40 plastic thermal enhanced very thin quad flat package; no

SOT618-6

leads; 40 terminals; body 6  6  0.85 mm

HVQFN40 plastic thermal enhanced very thin quad flat package; no

SOT618-6

leads; 40 terminals; body 6  6  0.85 mm

HVQFN40 plastic thermal enhanced very thin quad flat package; no

leads; 40 terminals; body 6  6  0.85 mm

HVQFN40 plastic thermal enhanced very thin quad flat package; no

leads; 40 terminals; body 6  6  0.85 mm

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

2 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

5. Block diagram

SDIO/ODS

SCLK/DFS

ADC1415S

ERROR

CORRECTION AND

DIGITAL

SPI

PROCESSING

OTR

CMOS:

D13 to D0

INP

INM

S/H

INPUT

STAGE

ADC CORE

14-BIT

PIPELINED

LVDS DDR:

D12_D13_P

to D0_D1_P

D12_D13_M

to D0_D1_M

CMOS:

INPUT

BUFFER

OUTPUT

DRIVERS

DAV

LVDS DDR:

DAVP

OUTPUT

DRIVERS

DAVM

SYSTEM

REFERENCE AND

POWER

CLOCK INPUT

STAGE AND DUTY

CYCLE CONTROL

PWD

MANAGEMENT

VREF

REFB

CLKP CLKM

VCM SENSE REFT

005aaa101

Fig 1. Block diagram

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

3 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

6. Pinning information

6.1 Pinning

terminal 1

index area

terminal 1

index area

REFB

REFT

D0_D1_P

D0_D1_M

D2_D3_P

D2_D3_M

D4_D5_P

D4_D5_M

D6_D7_P

D6_D7_M

D8_D9_P

D8_D9_M

REFB

REFT

AGND

VCM

AGND

VCM

VDDA5V

AGND

INM

ADC1215S

HVQFN40

VDDA5V

AGND

INM

ADC1415S

HVQFN40

INP

AGND

VDDA3V

INP

AGND

VDDA3V

005aaa103

Transparent top view

005aaa102

Fig 2. Pin configuration with CMOS digital outputs

selected

Fig 3. Pin configuration with LVDS/DDR digital

outputs selected

6.2 Pin description

Table 2.

Symbol

REFB

REFT

AGND

VCM

Pin description (CMOS digital outputs)

Type ^[1]

Description

bottom reference

top reference

analog ground

common-mode output voltage

5 V analog power supply

analog ground

VDDA5V

AGND

INM

complementary analog input

analog input

INP

AGND

VDDA3V

CLKP

CLKM

DEC

analog ground

3 V analog power supply

clock input

complementary clock input

regulator decoupling node

output enable, active LOW

power down, active HIGH

PWD

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

4 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 2.

Symbol

D13

Pin description (CMOS digital outputs) …continued

Type ^[1]

Description

data output bit 13 (Most Significant Bit (MSB))

data output bit 12

D12

D11

data output bit 11

D10

data output bit10

data output bit 9

data output bit 8

data output bit 7

data output bit 6

data output bit 5

data output bit 4

data output bit 3

data output bit 2

data output bit 1

data output bit 0 (Least Significant Bit (LSB))

data valid output clock

not connected

DAV

n.c.

VDDO

OGND

OTR

SCLK/DFS

SDIO/ODS

output power supply

output ground

out of range

SPI clock / data format select

SPI data IO / output data standard

SPI chip select

I/O

SENSE

VREF

reference programming pin

voltage reference input/output

I/O

[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.

Table 3.

Symbol

Pin description (LVDS DDR) digital outputs)

Pin^[1]Type ^[2]Description

D12_D13_M 17

D12_D13_P 18

D10_D11_M 19

D10_D11_P 20

differential output data D12 and D13 multiplexed, complement

differential output data D12 and D13 multiplexed, true

differential output data D10 and D11 multiplexed, complement

differential output data D10 and D11 multiplexed, true

differential output data D8 and D9 multiplexed, complement

differential output data D8 and D9 multiplexed, true

differential output data D6 and D7 multiplexed, complement

differential output data D6 and D7 multiplexed, true

differential output data D4 and D5 multiplexed, complement

differential output data D4 and D5 multiplexed, true

differential output data D2 and D3 multiplexed, complement

differential output data D2 and D3 multiplexed, true

differential output data D0 and D1 multiplexed, complement

D8_D9_M

D8_D9_P

D6_D7_M

D6_D7_P

D4_D5_M

D4_D5_P

D2_D3_M

D2_D3_P

D0_D1_M

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

5 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 3.

Symbol

D0_D1_P

DAVM

Pin description …continued (LVDS DDR) digital outputs)

Pin^[1]

Type ^[2]Description

differential output data D0 and D1 multiplexed, true

data valid output clock, complement

data valid output clock, true

DAVP

[1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2)

[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

V_Ooutput voltage

Conditions

Min

Max

Unit

pins D13 to D0 or

0.4

+3.9

pins D12_D13_P to D0_D1_P

and D12_D13_M to D0_D1_M

V_DDA(3V)analog supply

voltage 3 V

on pin VDDA3V

0.4

0.5

+4.6

+6.0

V_DDA(5V)analog supply

voltage 5 V

on pin VDDA5V

V_DDO

T_stg

T_amb

T_j

output supply voltage

0.4

55

40

+4.6

+125

+85

storage temperature

ambient temperature

junction temperature

C

125

8. Thermal characteristics

Table 5.

Symbol

R_th(j-a)

Thermal characteristics

Parameter

Conditions

Typ

Unit

[1]

thermal resistance from junction to ambient

thermal resistance from junction to case

30.5

13.3

K/W

R_th(j-c)

[1] Value for six layers board in still air with a minimum of 25 thermal vias.

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

6 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

9. Static characteristics

Table 6.

Symbol

Supplies

V_DDA(5V)

V_DDA(3V)

V_DDO

Static characteristics^[1]

Parameter

Conditions

Min

Typ

Max

Unit

analog supply voltage 5 V

analog supply voltage 3 V

output supply voltage

4.75

2.85

1.65

2.85

5.0

3.0

1.8

3.0

5.25

3.4

3.6

CMOS mode

LVDS DDR mode

I_DDA(5V)

I_DDA(3V)

I_DDO

analog supply current 5 V

analog supply current 3 V

output supply current

f_clk= 125 Msps;

f_i= 70 MHz

f_clk= 125 Msps;

f_i= 70 MHz

205

CMOS mode;

f_clk= 125 Msps;

f_i= 70 MHz

LVDS DDR mode:

f_clk= 125 Msps;

f_i= 70 MHz

power dissipation

ADC1415S125;

analog supply only

840

770

635

580

ADC1415S105;

analog supply only

ADC1415S080;

analog supply only

ADC1415S065;

analog supply only

Power-down mode

Standby mode

Clock inputs: pins CLKP and CLKM

LVPECL

V_i(clk)dif

SINE wave

V_i(clk)dif

LVCMOS

V_IL

differential clock input voltage

peak-to-peak

peak

1.6

differential clock input voltage

3.0

LOW-level input voltage

HIGH-level input voltage

0.3V_DDA(3V)

V_IH

0.7V_DDA(3V)

Logic inputs: pins PWD and OE

V_IL

V_IH

I_IL

LOW-level input voltage

0.8

HIGH-level input voltage

LOW-level input current

HIGH-level input current

V_DDA(3V)

A

I_IH

Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS

V_IL

V_IH

LOW-level input voltage

HIGH-level input voltage

0.3V_DDA(3V)

V_DDA(3V)

0.7V_DDA(3V)

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

7 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 6.

Static characteristics^[1]…continued

Symbol

Parameter

Conditions

Min

10

50

Typ

Max

+10

+50

Unit

A

I_IL

I_IH

C_I

LOW-level input current

HIGH-level input current

input capacitance

A

Digital outputs, CMOS mode: pins D13 to D0, OTR, DAV

Output levels, V_DDO= 3 V

V_OL

V_OH

C_O

LOW-level output voltage

HIGH-level output voltage

output capacitance

OGND

0.8V_DDO

0.2V_DDO

V_DDO

high impedance;

OE = HIGH

Output levels, V_DDO= 1.8 V

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

OGND

0.2V_DDO

V_DDO

0.8V_DDO

Digital outputs, LVDS mode: pins D12_D13_P to D0_D1_P, D12_D13_M to D0_D1_M, DAVP and DAVM

Output levels, V_DDO= 3 V only, R_load= 100 

V_O(offset)

V_O(dif)

C_O

output offset voltage

differential output voltage

output capacitance

output buffer current

set to 3.5 mA

1.2

350

output buffer current

set to 3.5 mA

Analog inputs: pins INP and INM

I_I

input current

5

A



R_I

input resistance

550

1.3

1.5

600

C_I

input capacitance

common-mode input voltage

input bandwidth

V_I(cm)

B_i

V_INP= V_INM

0.9

MHz

V_I(dif)

differential input voltage

peak-to-peak

Common mode output voltage: pin VCM

V_O(cm)

I_O(cm)

common-mode output voltage

common-mode output current

0.5V_DDA(3V)

I/O reference voltage: pin VREF

V_VREF

voltage on pin VREF

output

input

0.5 to 1

0.5

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

8 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 6.

Symbol

Accuracy

INL

Static characteristics^[1]…continued

Parameter

Conditions

Min

Typ

Max

Unit

integral non-linearity

5

LSB

DNL

differential non-linearity

guaranteed no

missing codes

0.95

0.5

+0.95

E_offset

E_G

offset error

gain error

2

0.5

%FS

Supply

PSRR

power supply rejection ratio

200 mV (p-p) on

V_DDA(3V)

54

dBc

[1] Typical values measured at V_DDA(3V)= 3 V, V_DDO= 1.8 V, V_DDA(5V)= 5 V; T_amb= 25 C and C_L= 5 pF; minimum and maximum values

are across the full temperature range T_amb= 40 C to +85 C at V_DDA(3V)= 3 V, V_DDO= 1.8 V, V_DDA(5V)= 5 V, V_INP V_INM= 1 dBFS;

internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

9 of 40

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

10. Dynamic characteristics

10.1 Dynamic characteristics

Table 7.

Symbol

Dynamic characteristics^[1]

Parameter

Conditions

ADC1415S065

Min Typ Max

ADC1415S080

Min Typ Max

ADC1415S105

Min Typ Max

ADC1415S125

Min Typ Max

Unit

Analog signal processing

_2H

second

harmonic level

f_i= 3 MHz

dBc

bits

f_i= 30 MHz

f_i= 70 MHz

f_i= 170 MHz

f_i= 3 MHz

_3H

third harmonic

level

f_i= 30 MHz

f_i= 70 MHz

f_i= 170 MHz

f_i= 3 MHz

THD

ENOB

SNR

SFDR

total harmonic

distortion

f_i= 30 MHz

f_i= 70 MHz

f_i= 170 MHz

f_i= 3 MHz

effective

number of bits

11.7

11.6

11.5

11.4

72.1

71.3

70.7

70.2

11.7

11.5

11.4

72.0

71.2

70.7

70.1

11.6

11.5

11.4

11.3

71.8

71.2

70.6

70.0

11.6

11.5

11.4

11.3

71.4

71.1

70.5

69.9

f_i= 30 MHz

f_i= 70 MHz

f_i= 170 MHz

f_i= 3 MHz

bits

signal-to-

noise ratio

dBFS

dBc

f_i= 30 MHz

f_i= 70 MHz

f_i= 170 MHz

f_i= 3 MHz

spurious-

free dynamic

range

f_i= 30 MHz

f_i= 70 MHz

f_i= 170 MHz

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 7.

Symbol

Dynamic characteristics^[1]…continued

Parameter

Conditions

ADC1415S065

Min Typ Max

ADC1415S080

Min Typ Max

ADC1415S105

Min Typ Max

ADC1415S125

Min Typ Max

Unit

IMD

Intermodul-

f_i= 3 MHz

dBc

ation distortion

f_i= 30 MHz

f_i= 70 MHz

f_i= 170 MHz

[1] Typical values measured at V_DDA(3V)= 3 V, V_DDO= 1.8 V, V_DDA(5V)= 5 V; T_amb= 25 C and C_L= 5 pF; minimum and maximum values are across the full temperature range

_amb= 40 C to +85 C at V_DDA(3V)= 3 V, V_DDO= 1.8 V, V_DDA(5V)= 5 V, V_INP V_INM= 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise

specified.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

10.2 Clock and digital output timing

Table 8.

Symbol

Clock and digital output timing characteristics^[1]

Parameter

Conditions

ADC1410S065

Min Typ Max

ADC1410S080

Min Typ Max

ADC1410S105

Min Typ Max

ADC1410S125

Min Typ Max

Unit

Clock timing input: pins CLKP and CLKM

f_clk

clock frequency

105

100

125 MHz

t_lat(data)

data latency

time

13.5

clock

cycles

_clk

clock duty cycle DCS_EN = 1

DCS_EN = 0

0.8

t_d(s)

sampling delay

time

t_wake

wake-up time

s

CMOS Mode timing output: pins D13 to D0 and DAV

t_PD

propagation

delay

DATA

DAV

13.6

14.9

4.2

12.5

3.4

16.4

11.9

12.9

3.6

9.8

3.3

14.4

8.0

10.8

3.3

6.8

3.1

12.4

8.2

9.7

3.4

5.6

2.8

11.3 ns

t_su

t_h

t_r

set-up time

hold time

rise time

[2]

DATA

DAV

0.39

0.26

0.19

2.4

0.39

0.26

0.19

2.4

0.39

0.26

0.19

2.4

0.39

0.26

0.19

2.4

t_f

fall time

DATA

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 8.

Symbol

Clock and digital output timing characteristics^[1]…continued

Parameter

Conditions

ADC1410S065

Min Typ Max

LVDS DDR mode timing output: pins D12_D13_P to D0_D1_P, D12_D13_M to D0_D1_M, DAVP and DAVM

ADC1410S080

ADC1410S105

ADC1410S125

Min Typ Max

Unit

Min Typ Max

t_PD

propagation

delay

DATA

DAV

3.3

5.1

2.8

5.4

2.2

7.6

2.9

4.6

2.5

4.1

2.0

7.1

2.5

4.2

6.8

2.2

4.0

6.6

2.3

2.6

1.8

2.2

1.9

1.7

t_su

t_h

t_r

set-up time

hold time

rise time

[3]

DATA

DAV

0.5

0.18

0.15

0.5

0.18

0.15

0.5

0.18

0.15

0.5

0.18

0.15

2.4

1.6

2.4

1.6

2.4

1.6

2.4

1.6

t_f

fall time

DATA

[1] Typical values measured at V_DDA(3V)= 3 V, V_DDO= 1.8 V, V_DDA(5V)= 5 V; T_amb= 25 C and C_L= 5 pF; minimum and maximum values are across the full temperature range

_amb= 40 C to +85 C at V_DDA(3V)= 3 V, V_DDO= 1.8 V, V_DDA(5V)= 5 V, V_INP V_INM= 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise

specified.

[2] Measured between 20 % to 80 % of V_DDO

[3] Rise time measured from 50 mV to +50 mV; fall time measured from +50 mV to 50 mV.

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

N + 1

d(s)

N + 2

clk

CLKP

CLKM

(N − 14)

(N − 13)

(N − 12)

(N − 11)

DATA

DAV

clk

005aaa060

Fig 4. CMOS mode timing

N + 1

d(s)

N + 2

clk

CLKP

CLKM

(N − 14)

(N − 13)

(N − 12)

(N − 11)

D _D

x + 1

D _D

x + 1

su h

DAVP

DAVM

clk

005aaa061

Fig 5. LDVS DDR mode timing

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

14 of 40

ADC1415S series

Integrated Device Technology

10.3 SPI timings

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 9.

Symbol

t_w(SCLK)

t_w(SCLKH)

t_w(SCLKL)

t_su

SPI timings characteristics^[1]

Parameter

Conditions

Min Typ

Max

Unit

SCLK pulse width

SCLK HIGH pulse width

SCLK LOW pulse width

set-up time

data to SCLK HIGH

CS to SCLK HIGH

data to SCLK HIGH

CS to SCLK HIGH

t_h

hold time

f_clk(max)

maximum clock frequency

MHz

[1] Typical values measured at V_DDA(3V)= 3 V, V_DDO= 1.8 V, V_DDA(5V)= 5 V, T_amb= 25 C and C_L= 5 pF;

minimum and maximum values are across the full temperature range T_amb= 40 C to +85 C at

_DDA= 3 V, V_DDO= 1.8 V

w(SCLKL)

w(SCLKH)

w(SCLK)

SCLK

SDIO

A12

A11

R/W

005aaa065

Fig 6. SPI timing

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

15 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

10.4 Typical characteristics

001aam616

001aam615

100

SNR

SFDR

(dBc)

(1)

(dBFS)

(2)

δ (%)

T = 25 C; V_DD= 3 V; f_i= 170 MHz; f_s= 125 Msps

(1) DCS on

T = 25 C; V_DD= 3 V; f_i= 170 MHz; f_s= 125 Msps

(1) DCS on

(2) DCS off

Fig 7. Spurious-free dynamic range as a function of

Fig 8. Signal-to-noise ratio as a function of duty

duty cycle ()

cycle ()

001aam617

001aam618

SFDR

SNR

(dBc)

(dBFS)

(1)

(2)

(1)

(2)

(3)

δ (%)

(1) T_amb= 40 C, typical supply voltages

(2) T_amb= +25 C, typical supply voltages

(3) T_amb= +90 C, typical supply voltages

(1) T_amb= 40 C, typical supply voltages

(2) T_amb= +25 C, typical supply voltages

(3) T_amb= +90 C, typical supply voltages

Fig 9. Spurious-free dynamic range as a function of

Fig 10. Signal-to-noise ratio as a function of duty

duty cycle ()

cycle ()

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

16 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

001aam659

001aam660

SNR

SFDR

(dBc)

(dBFS)

0.5

1.0

1.5

2.0

2.5

3.0

I(cm)

3.5

0.5

1.0

1.5

2.0

2.5

3.0

I(cm)

3.5

(V)

Fig 11. Spurious-free dynamic range as a function of

Fig 12. Signal-to-noise ratio as a function of

common-mode input voltage (V_i(cm)

)

11. Application information

11.1 Device control

The ADC1415S can be controlled via the Serial Peripheral Interface (SPI control mode) or

directly via the I/O pins (Pin control mode).

11.1.1 SPI and Pin control modes

The device enters Pin control mode at power-up, and remains in this mode as long as pin

CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as

static control pins.

SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been

enabled, the device remains in this mode. The transition from Pin control mode to SPI

control mode is illustrated in Figure 13.

Pin control mode

SPI control mode

SCLK/DFS

SDIO/ODS

Data format

offset binary

Data format

two's complement

LVDS DDR

R/W

A12

CMOS

005aaa039

Fig 13. Control mode selection.

When the device enters SPI control mode, the output data standard and data format are

determined by the level on pin SDIO as soon as a transition is triggered by a falling edge

on CS.

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

17 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

11.1.2 Operating mode selection

The active ADC1415S operating mode (Power-up, Power-down or Sleep) can be selected

via the SPI interface (see Table 19) or using pins PWD and OE in Pin control mode, as

described in Table 10.

Table 10. Operating mode selection via pin PWD and OE

Pin PWD

Pin OE

Operating mode

Power-up

Output high-Z

Power-up

yes

Sleep

Power-down

11.1.3 Selecting the output data standard

The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface

(see Table 23) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is

HIGH, otherwise CMOS is selected.

11.1.4 Selecting the output data format

The output data format can be selected via the SPI interface (offset binary, two’s

complement or gray code; see Table 23) or using pin DFS in Pin control mode (offset

binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is

HIGH, two’s complement is selected.

11.2 Analog inputs

11.2.1 Input stage

The analog input of the ADC1415S supports a differential or a single-ended input drive.

Optimal performance is achieved using differential inputs. The ADC inputs are internally

biased and need to be decoupled.

The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)

via a programmable internal reference (see Section 11.3 and Table 21).

The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input

stage, including ElectroStatic Discharge (ESD) protection and circuit and package

parasitics, is shown in Figure 14.

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

18 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

package

ESD

parasitics

switch

= 15 Ω

4 pF

INP

sampling

capacitor

internal

clock

INPUT

BUFFER

switch

= 15 Ω

4 pF

INM

sampling

capacitor

internal

clock

005aaa107

Fig 14. Input sampling circuit and input buffer

The integrated input buffer offers the following advantages:

• The kickback effect is avoided - the charge injection and glitches generated by the

S/H input stage are isolated from the input circuitry. So there’s no need for additional

filtering.

• The input capacitance is very low and constant over a wide frequency range, which

makes the ADC1415S easy to drive.

The sample phase occurs when the internal clock (derived from the clock signal on pin

CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the

clock signal goes LOW, the stage enters the hold phase and the voltage information is

transmitted to the ADC core.

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

19 of 40

ADC1415S series

Integrated Device Technology

11.2.2 Transformer

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

The configuration of the transformer circuit is determined by the input frequency. The

configuration shown in Figure 15 would be suitable for a baseband application.

ADT1-1WT

100 nF

INP

Analog

input

50 Ω

100 nF

INM

VCM

100 nF

005aaa108

Fig 15. Single transformer configuration suitable for baseband applications

The configuration shown in Figure 16 is recommended for high frequency applications. In

both cases, the choice of transformer is a compromise between cost and performance.

ADT1-1WT

100 nF

INP

100 nF

50 Ω

Analog

input

100 Ω

100 nF

INM

VCM

100 nF

005aaa109

Fig 16. Dual transformer configuration suitable for high intermediate frequency

application

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

20 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

11.3 System reference and power management

11.3.1 Internal/external references

The ADC1415S has a stable and accurate built-in internal reference voltage to adjust the

ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and

SENSE (programmable in 1 dB steps between 0 dB and 6 dB via control bits

INTREF[2:0] when bit INTREF_EN = logic 1; see Table 21) See Figure 18 to Figure 21.

The equivalent reference circuit is shown in Figure 17. External reference is also possible

by providing a voltage on pin VREF as described in Figure 20.

REFT

REFERENCE

AMP

REFB

VREF

EXT_ref

BANDGAP

REFERENCE

EXT_ref

BUFFER

ADC CORE

SENSE

SELECTION

LOGIC

005aaa164

Fig 17. Reference equivalent schematic

If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or

externally as detailed in Table 11.

Table 11. Reference selection

Selection

SPI bit

SENSE pin

VREF pin

Full-scale (p-p)

INTREF_EN

internal

(Figure 18)

AGND

330 pF capacitor to AGND 2 V

internal

(Figure 19)

pin VREF connected to pin SENSE and

via a 330 pF capacitor to AGND

1 V

external

(Figure 20)

V_DDA(3V)

external voltage between

0.5 V and 1 V^[1]

1 V to 2 V

internal via SPI

(Figure 21)

pin VREF connected to pin SENSE and

via 330 pF capacitor to AGND

[1] The voltage on pin VREF is doubled internally to generate the internal reference voltage.

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

21 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

VREF

330

330 pF

REFERENCE

EQUIVALENT

SCHEMATIC

EQUIVALENT

SCHEMATIC

SENSE

005aaa116

005aaa117

Fig 18. Internal reference, 2 V (p-p) full scale

Fig 19. Internal reference, 1 V (p-p) full scale

VREF

0.1 μF

330 pF

REFERENCE

EQUIVALENT

SCHEMATIC

REFERENCE

EQUIVALENT

SCHEMATIC

SENSE

VDDA

005aaa119

005aaa118

Fig 20. External reference, 1 V (p-p) to 2 V (p-p)

full-scale

Fig 21. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)

full-scale

Figure 18 to Figure 21 illustrate how to connect the SENSE and VREF pins to select the

required reference voltage source.

11.3.2 Programmable full-scale

The full-scale is programmable between 1 V (peak-to-peak) to 2 V (peak-to-peak)

(see Table 12).

Table 12. Reference SPI Gain Control

INTREF

000

Gain

Full-scale (p-p)

2 V

0 dB

001

1 dB

2 dB

3 dB

4 dB

5 dB

6 dB

reserved

1.78 V

1.59 V

1.42 V

1.26 V

1.12 V

1 V

010

011

100

101

110

111

11.3.3 Common-mode output voltage (V_O(cm)

)

A 0.1 F filter capacitor should be connected between pin VCM and ground.

11.3.4 Biasing

The common-mode input voltage (V_I(cm)) on pins INP and INM is set internally. The input

buffer bias current can be set to one of three levels (high, medium or low) via the SPI (see

Table 22).

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

22 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

11.4 Clock input

11.4.1 Drive modes

The ADC1415S can be driven differentially (LVPECL). It can also be driven by a

single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal

connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or

CLKM (pin CLKP should be connected to ground via a capacitor).

CLKP

CLKM

LVCMOS

clock input

CLKP

CLKM

LVCMOS

clock input

005aaa174

005aaa053

a. Rising edge LVCMOS

b. Falling edge LVCMOS

Fig 22. LVCMOS single-ended clock input

CLKP

CLKM

Sine

clock input

CLKP

Sine

clock input

CLKM

005aaa173

005aaa054

a. Sine clock input

b. Sine clock input (with transformer)

CLKP

CLKM

LVPECL

clock input

005aaa172

c. LVPECL clock input

Fig 23. Differential clock input

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

23 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

11.4.2 Equivalent input circuit

The equivalent circuit of the input clock buffer is shown in Figure 24. The common-mode

voltage of the differential input stage is set via internal 5 k resistors.

Package

ESD

Parasitics

CLKP

cm(clk)

SE_SEL SE_SEL

5 kΩ

CLKM

005aaa056

V_cm(clk)= common-mode voltage of the differential input stage.

Fig 24. Equivalent input circuit

Single-ended or differential clock inputs can be selected via the SPI interface

(see Table 20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via

control bit SE_SEL.

If single-ended is implemented without setting bit SE_SEL to the appropriate value, the

unused pin should be connected to ground via a capacitor.

11.4.3 Duty cycle stabilizer

The duty cycle stabilizer can improve the overall performance of the ADC by

compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is

active (bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty

cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled

(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and

55 %.

11.4.4 Clock input divider

The ADC1415S contains an input clock divider that divides the incoming clock by a factor

of 2 (when bit CLKDIV = logic 1; see Table 20). This feature allows the user to deliver a

higher clock frequency with better jitter performance, leading to a better SNR result once

acquisition has been performed.

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

24 of 40

ADC1415S series

Integrated Device Technology

11.5 Digital outputs

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

11.5.1 Digital output buffers: CMOS mode

The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to

logic_0 (see Table 23).

Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS

digital output buffer is shown in Figure 25. The buffer is powered by a separate

OGND/V_DDOto ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core.

Each buffer can be loaded by a maximum of 10 pF.

VDDO

Parasitics

ESD

Package

50 Ω

LOGIC

DRIVER

OGND

005aaa057

Fig 25. CMOS digital output buffer

The output resistance is 50  and is the combination of the an internal resistor and the

equivalent output resistance of the buffer. There is no need for an external damping

resistor. The drive strength of both data and DAV buffers can be programmed via the SPI

in order to adjust the rise and fall times of the output digital signals (see Table 30):

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

25 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

11.5.2 Digital output buffers: LVDS DDR mode

The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to

logic_1 (see Table 23).

VDDO

3.5 mA

typ

−

D P/D

x + 1

RECEIVER

100 Ω

D M/D M

x x + 1

−

OGND

005aaa058

Fig 26. LVDS DDR digital output buffer - externally terminated

Each output should be terminated externally with a 100  resistor (typical) at the receiver

side (Figure 26) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 27 and

Table 32).

VDDO

3.5 mA

typ

−

D P/D

x + 1

100 Ω

RECEIVER

D M/D M

x x + 1

−

OGND

005aaa059

Fig 27. LVDS DDR digital output buffer - internally terminated

The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via

the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic

voltage levels.

Table 13. LVDS DDR output register 2

LVDS_INT_TER[2:0]

Resistor value ()

000

001

010

011

100

no internal termination

300

180

110

150

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

26 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 13. LVDS DDR output register 2 …continued

LVDS_INT_TER[2:0]

Resistor value ()

101

110

111

100

11.5.3 DAta Valid (DAV) output clock

A data valid output clock signal (DAV) is provided that can be used to capture the data

delivered by the ADC1415S. Detailed timing diagrams for CMOS and LVDS DDR modes

are provided in Figure 4 and Figure 5 respectively.

11.5.4 Out-of-Range (OTR)

An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock

cycles. The OTR response can be speeded up by enabling Fast OTR (bit

FASTOTR = logic 1; see Table 29). In this mode, the latency of OTR is reduced to only

four clock cycles. The Fast OTR detection threshold (below full-scale) can be

programmed via bits FASTOTR_DET[2:0].

Table 14. Fast OTR register

FASTOTR_DET[2:0]

Detection level (dB)

20.56

000

001

010

011

100

101

110

111

16.12

11.02

7.82

5.49

3.66

2.14

0.86

11.5.5 Digital offset

By default, the ADC1415S delivers output code that corresponds to the analog input.

However it is possible to add a digital offset to the output code via the SPI (bits

DIG_OFFSET[5:0]; see Table 25).

11.5.6 Test patterns

For test purposes, the ADC1415S can be configured to transmit one of a number of

predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern

can be defined by the user (TESTPAT_USER; see Table 27 and Table 28) and is selected

when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted regardless of the

analog input.

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

27 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

11.5.7 Output codes versus input voltage

Table 15. Output codes

V_INP V_INM

< 1

Offset binary

Two’s complement

10 0000 0000 0000

10 0000 0000 0001

10 0000 0000 0010

10 0000 0000 0011

10 0000 0000 0100

....

OTR pin

00 0000 0000 0000

00 0000 0000 0001

00 0000 0000 0010

00 0000 0000 0011

00 0000 0000 0100

....

1

0.9998779

0.9997559

0.9996338

0.9995117

....

0.0002441

0.0001221

01 1111 1111 1110

01 1111 1111 1111

10 0000 0000 0000

10 0000 0000 0001

10 0000 0000 0010

....

11 1111 1111 1110

11 1111 1111 1111

00 0000 0000 0000

00 0000 0000 0001

00 0000 0000 0010

....

+0.0001221

+0.0002441

....

+0.9995117

+0.9996338

+0.9997559

+0.9998779

11 1111 1111 1011

11 1111 1111 1100

11 1111 1111 1101

11 1111 1111 1110

11 1111 1111 1111

01 1111 1111 1011

01 1111 1111 1100

01 1111 1111 1101

01 1111 1111 1110

01 1111 1111 1111

> +1

11.6 Serial Peripheral Interface (SPI)

11.6.1 Register description

The ADC1415S serial interface is a synchronous serial communications port that allows

easy interfacing with many commonly-used microprocessors. It provides access to the

registers that control the operation of the chip.

This interface is configured as a 3-wire type (SDIO as bidirectional pin)

Pin SCLK is the serial clock input and CS is the chip select pin.

Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is

transmitted (two instruction bytes and at least one data byte). The number of data bytes is

determined by the value of bits W1 and W2 (see Table 17).

Table 16. Instruction bytes for the SPI

MSB

LSB

Bit

Description

R/W^[1]

W1^[2]

W0^[2]

A12

A11

A10

[1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.

[2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 17).

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

28 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 17. Number of data bytes to be transferred after the instruction bytes

Number of bytes transmitted

1 byte

2 bytes

3 bytes

4 bytes or more

Bits A12 to A0 indicate the address of the register being accessed. In the case of a

multiple byte transfer, this address is the first register to be accessed. An address counter

is increased to access subsequent addresses.

The steps involved in a data transfer are as follows:

1. A falling edge on CS in combination with a rising edge on SCLK determine the start of

communications.

2. The first phase is the transfer of the 2-byte instruction.

3. The second phase is the transfer of the data which can vary in length but is always a

multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).

4. A rising edge on CS indicates the end of data transmission.

SCLK

SDIO

W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

R/W

Instruction bytes

005aaa062

Fig 28. SPI mode timing

11.6.2 Default modes at start-up

During circuit initialization it does not matter which output data standard has been

selected. At power-up, the device enters Pin control mode.

A falling edge on CS triggers a transition to SPI control mode. When the ADC1415S

enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by

the level on pin SDIO (see Figure 29). Once in SPI control mode, the output data standard

can be changed via bit LVDS/CMOS in Table 23.

When the ADC1415S enters SPI control mode, the output data format (two’s complement

or offset binary) is determined by the level on pin SCLK (gray code can only be selected

via the SPI). Once in SPI control mode, the output data format can be changed via bit

DATA_FORMAT[1:0] in Table 23.

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

29 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

SCLK

(Data fo

rmat)

SDIO

(CMOS LVDS DDR)

Offset binary, LVDS DDR

default mode at start-up

005aaa063

Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR

SCLK

(Data fo

rmat)

SDIO

(CMOS LVDS DDR)

two's complement, CMOS

default mode at start-up

005aaa064

Fig 30. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

30 of 40

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

11.6.3 Register allocation map

Table 18. Register allocation map

Add Register name

Hex

R/W

Bit definition

Default

Bin

Bit 7

Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0005 Reset and

operating mode

R/W

SW_RST

RESERVED[2:0]

OP_MODE[1:0]

0000 0000

0006 Clock

SE_SEL

DIFF_SE

INTREF_EN

CLKDIV

DCS_EN

0000 0001

0000 0000

0000 0011

0000 0000

0008 Internal reference R/W

INTREF[2:0]

IB_IBIAS[1:0]

0010 Input buffer

R/W

0011 Output data

standard.

LVDS_

CMOS

OUTBUF

OUTBUS_SWAP

DATA_FORMAT[1:0]

0012 Output clock

0013 Offset

R/W

DAVINV

DAVPHASE[2:0]

0000 1110

0000 0000

0000 1110

0000 0000

DIG_OFFSET[5:0]

0014 Test pattern 1

0015 Test pattern 2

0016 Test pattern 3

0017 Fast OTR

TESTPAT_SEL[2:0]

TESTPAT_USER[13:6]

TESTPAT_USER[5:0]

FASTOTR

FASTOTR_DET[2:0]

0020 CMOS output

DAV_DRV[1:0]

DATAI_x2_EN

DATA_DRV[1:0]

DATAI[1:0]

0021 LVDS DDR O/P 1 R/W

DAVI_x2_

DAVI[1:0]

0022 LVDS DDR O/P 2 R/W

BIT_BYTE_

WISE

LVDS_INT_TER[2:0]

0000 0000

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 19. Reset and operating mode control register (address 0005h) bit description

Default values are highlighted.

Bit

Symbol

Access

Value

Description

SW_RST

R/W

reset digital section

no reset

performs a reset on SPI registers

reserved

6 to 4

3 to 2

1 to 0

RESERVED[2:0]

000

not used

OP_MODE[1:0]

R/W

operating mode

normal (Power-up)

Power-down

Sleep

normal (Power-up)

Table 20. Clock control register (address 0006h) bit description

Default values are highlighted.

Bit

7 to 5

Symbol

Access

Value

Description

000

not used

SE_SEL

R/W

single-ended clock input pin select

CLKM

CLKP

DIFF_SE

R/W

differential/single ended clock input select

fully differential

single-ended

not used

CLKDIV

R/W

clock input divide by 2

disabled

enabled

DCS_EN

duty cycle stabilizer

disabled

enabled

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

32 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 21. Internal reference control register (address 0008h) bit description

Default values are highlighted.

Bit

7 to 4

Symbol

Access

Value

Description

0000

not used

INTREF_EN

R/W

programmable internal reference enable

disable

active

2 to 0

INTREF[2:0]

R/W

programmable internal reference

0 dB (FS = 2 V)

000

001

010

011

100

101

110

111

1 dB (FS = 1.78 V)

2 dB (FS = 1.59 V)

3 dB (FS = 1.42 V)

4 dB (FS = 1.26 V)

5 dB (FS = 1.12 V)

6 dB (FS = 1 V)

reserved

Table 22. Input buffer control register (address 0010h) bit description

Default values are highlighted.

Bit

Symbol

Access

Value

Description

not used

7 to 2

1 to 0

000000

IB_IBIAS[1:0]

R/W

input buffer bias current

not used

medium

low

high

Table 23. Output data standard control register (address 0011h) bit description

Default values are highlighted.

Bit

7 to 5

Symbol

Access

Value

Description

000

not used

LVDS_CMOS

R/W

output data standard: LVDS DDR or CMOS

CMOS

LVDS DDR

OUTBUF

R/W

output buffers enable

output enabled

output disabled (high Z)

output bus swapping

OUTBUS_SWAP

no swapping

output bus is swapped (MSB becomes LSB and vice versa)

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

33 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 23. Output data standard control register (address 0011h) bit description …continued

Default values are highlighted.

Bit

Symbol

Access

Value

Description

1 to 0

DATA_FORMAT[1:0] R/W

output data format

offset binary

two’s complement

gray code

offset binary

Table 24. Output clock register (address 0012h) bit description

Default values are highlighted.

Bit

7 to 4

Symbol

Access

Value

Description

0000

not used

DAVINV

R/W

output clock data valid (DAV) polarity

normal

inverted

2 to 0

DAVPHASE[2:0]

R/W

DAV phase select

000

001

010

011

100

101

110

111

output clock shifted (ahead) by 3 ns

output clock shifted (ahead) by 2.5 ns

output clock shifted (ahead) by 2 ns

output clock shifted (ahead) by 1.5 ns

output clock shifted (ahead) by 1 ns

output clock shifted (ahead) by 0.5 ns

default value as defined in timing section

output clock shifted (delayed) by 0.5 ns

Table 25. Offset register (address 0013h) bit description

Default values are highlighted.

Bit

Symbol

Access

Value

Description

7 to 6

5 to 0

not used

DIG_OFFSET[5:0]

R/W

digital offset adjustment

011111

...

+31 LSB

...

000000

...

100000

32 LSB

Table 26. Test pattern register 1 (address 0014h) bit description

Default values are highlighted.

Bit

Symbol

Access

Value

Description

7 to 3

00000

not used

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

34 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 26. Test pattern register 1 (address 0014h) bit description …continued

Default values are highlighted.

Bit

Symbol

Access

Value

Description

2 to 0

TESTPAT_SEL[2:0]

R/W

digital test pattern select

000

001

010

011

100

101

110

111

off

mid scale

FS

+FS

toggle ‘1111..1111’/’0000..0000’

custom test pattern

‘1010..1010.’

‘010..1010’

Table 27. Test pattern register 2 (address 0015h) bit description

Default values are highlighted.

Bit

Symbol

Access

Value

Description

7 to 0

TESTPAT_USER[13:6]

R/W

00000000 custom digital test pattern (bits 13 to 6)

Table 28. Test pattern register 3 (address 0016h) bit description

Default values are highlighted.

Bit

Symbol

Access

Value

000000

Description

7 to 2

1 to 0

TESTPAT_USER[5:0]

R/W

custom digital test pattern (bits 5 to 0)

not used

Table 29. Fast OTR register (address 0017h) bit description

Default values are highlighted.

Bit

7 to 4

Symbol

Access

Value

Description

not used

0000

FASTOTR

R/W

fast Out-of-Range (OTR) detection

disabled

enabled

2 to 0

FASTOTR_DET[2:0] R/W

set fast OTR detect level

20.56 dB

000

001

010

011

100

101

110

111

16.12 dB

11.02 dB

7.82 dB

5.49 dB

3.66 dB

2.14 dB

0.86 dB

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

35 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 30. CMOS output register (address 0020h) bit description

Default values are highlighted.

Bit

Symbol

Access

Value

Description

7 to 4

3 to 2

0000

not used

DAV_DRV[1:0]

R/W

drive strength for DAV CMOS output buffer

low

medium

high

very high

1 to 0

DATA_DRV[1:0] R/W

drive strength for DATA CMOS output buffer

low

medium

high

very high

Table 31. LVDS DDR output register 1 (address 0021h) bit description

Default values are highlighted.

Bit

7 to 6

Symbol

Access

Value

Description

not used

DAVI_x2_EN

R/W

double LVDS current for DAV LVDS buffer

disabled

enabled

4 to 3

DAVI[1:0]

R/W

LVDS current for DAV LVDS buffer

3.5 mA

4.5 mA

1.25 mA

2.5 mA

DATAI_x2_EN

DATAI[1:0]

R/W

double LVDS current for DATA LVDS buffer

disabled

enabled

1 to 0

LVDS current for DATA LVDS buffer

3.5 mA

4.5 mA

1.25 mA

2.5 mA

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

36 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 32. LVDS DDR output register 2 (address 0022h) bit description

Default values are highlighted.

Bit

7 to 4

Symbol

Access

Value

Description

0000

not used

BIT/BYTE_WISE

R/W

DDR mode for LVDS output

bit wise (even data bits output on DAV rising edge / odd data

bits output on DAV falling edge)

byte wise (MSB data bits output on DAV rising edge / LSB data

bits output on DAV falling edge)

2 to 0

LVDS_INTTER[2:0]

R/W

internal termination for LVDS buffer (DAV and DATA)

000

001

010

011

100

101

110

111

no internal termination

300 

180 

110 

150 

100 

81 

60 

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

37 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

12. Package outline

HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;

40 terminals; body 6 x 6 x 0.85 mm

SOT618-6

terminal 1

index area

detail X

1/2 e

terminal 1

index area

2.5

scale

5 mm

Dimensions

Unit

(1)

max 1.00 0.05 0.30

6.1 4.55 6.1 4.55

0.5

mm nom 0.85 0.02 0.21 0.2 6.0 4.40 6.0 4.40 0.5 4.5 4.5 0.4 0.1 0.05 0.05 0.1

min 0.80 0.00 0.18 5.9 4.25 5.9 4.25 0.3

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot618-6_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

- - -

09-02-23

09-03-04

SOT618-6

MO-220

Fig 31. Package outline SOT618-6 (HVQFN40)

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

38 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

13. Revision history

Table 33. Revision history

Document ID

Release date

Data sheet status

Change Supersedes

notice

ADC1415S_SER v.5

ADC1415S_SER v.4

Modifications:

20120702

20101217

Product data sheet

ADC1415S_SER v.4

ADC1415S_SER v.3

• Data sheet status changed from Preliminary to Product.

• Text and drawings updated throughout entire data sheet.

• Section 10.4 “Typical characteristics” added to the data sheet.

ADC1415S_SER v.3

20100412

Preliminary data sheet

Objective data sheet

ADC1415S065_080_105_125_2

ADC1415S065_080_105_125_2 20090604

ADC1415S065_080_105_125_1 20090528

ADC1415S065_080_105_125_1

14. Contact information

For more information or sales office addresses, please visit: http://www.idt.com

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

39 of 40

ADC1415S series

Integrated Device Technology

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

15. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

11.3

System reference and power management. . 21

Internal/external references . . . . . . . . . . . . . . 21

Programmable full-scale . . . . . . . . . . . . . . . . 22

Common-mode output voltage (V_O(cm)) . . . . . 22

Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 23

Equivalent input circuit. . . . . . . . . . . . . . . . . . 24

Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 24

Clock input divider . . . . . . . . . . . . . . . . . . . . . 24

Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . 25

Digital output buffers: CMOS mode . . . . . . . . 25

Digital output buffers: LVDS DDR mode . . . . 26

DAta Valid (DAV) output clock . . . . . . . . . . . . 27

Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . 27

Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . 27

Output codes versus input voltage. . . . . . . . . 28

Serial Peripheral Interface (SPI) . . . . . . . . . . 28

Default modes at start-up. . . . . . . . . . . . . . . . 29

11.3.1

11.3.2

11.3.3

11.3.4

11.4

11.4.1

11.4.2

11.4.3

11.4.4

11.5

11.5.1

11.5.2

11.5.3

11.5.4

11.5.5

11.5.6

11.5.7

11.6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal characteristics . . . . . . . . . . . . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

Dynamic characteristics . . . . . . . . . . . . . . . . . 10

Clock and digital output timing . . . . . . . . . . . . 12

SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typical characteristics . . . . . . . . . . . . . . . . . . 16

10.1

10.2

10.3

10.4

11.1

11.1.1

11.1.2

11.1.3

11.1.4

11.2

Application information. . . . . . . . . . . . . . . . . . 17

Device control. . . . . . . . . . . . . . . . . . . . . . . . . 17

SPI and Pin control modes. . . . . . . . . . . . . . . 17

Operating mode selection. . . . . . . . . . . . . . . . 18

Selecting the output data standard. . . . . . . . . 18

Selecting the output data format. . . . . . . . . . . 18

Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 18

Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 20

11.6.1

11.6.2

11.6.3

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 38

Revision history . . . . . . . . . . . . . . . . . . . . . . . 39

Contact information . . . . . . . . . . . . . . . . . . . . 39

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11.2.1

11.2.2

ADC1415S_SER 5

Product data sheet

Rev. 05 — 2 July 2012

40 of 40

ADC1415S105HN-C1相关文章

配单直通车

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

ADC1415S105HN-C1产品参数

型号:	ADC1415S105HN-C1
Brand Name：	Integrated Device Technology
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	INTEGRATED DEVICE TECHNOLOGY INC
零件包装代码：	VFQFPN
包装说明：	6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT618-6, HVQFN-40
针数：	40
制造商包装代码：	NLG40
Reach Compliance Code：	compliant
风险等级：	5.83
Is Samacsys：	N
最大模拟输入电压：	2 V
转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	S-PQCC-N40
JESD-609代码：	e3
最大线性误差 (EL)：	0.03%
湿度敏感等级：	3
位数：	14
功能数量：	1
端子数量：	40
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出位码：	OFFSET BINARY
封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCN
封装等效代码：	LCC40,.24SQ,20
封装形状：	SQUARE
封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260
电源：	3,5 V
认证状态：	Not Qualified
子类别：	Analog to Digital Converters
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

电子百科

产品导航

产品型号ADC1415S105HN-C1的Datasheet PDF文件预览

ADC1415S105HN-C1相关产品

ADC1415S105HN-C1相关文章

IC37:专业IC行业平台