欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
  •  
  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • ADF4351BCPZ-RL7
  • 数量-
  • 厂家-
  • 封装-
  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
更多
  • ADF4351BCPZ-RL7图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量3000 
  • 厂家ADI/亚德诺 
  • 封装LFCSP-32 
  • 批号21+ 
  • 羿芯诚只做原装 原厂渠道 价格优势
  • QQ:2881498351QQ:2881498351 复制
  • 0755-22968581 QQ:2881498351
  • ADF4351BCPZ-RL7图
  • 集好芯城

     该会员已使用本站13年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量27404 
  • 厂家ADI(亚德诺) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • ADF4351BCPZ-RL7图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量22000 
  • 厂家ADI/亚德诺 
  • 封装LFCSP32 
  • 批号23+ 
  • 只做原装现货假一罚十
  • QQ:2103443489QQ:2103443489 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
  • ADF4351BCPZ-RL7图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量26495 
  • 厂家ADI 
  • 封装QFN32 
  • 批号22+ 
  • 全新进口原装
  • QQ:1327510916QQ:1327510916 复制
    QQ:1220223788QQ:1220223788 复制
  • 0755-28767101 QQ:1327510916QQ:1220223788
  • ADF4351BCPZ-RL7图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量3725 
  • 厂家ADI 
  • 封装LFCSP-32 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • ADF4351BCPZ-RL7图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量8000 
  • 厂家ADI(亚德诺) 
  • 封装LFCSP 
  • 批号22+ 
  • 宗天技术 原装现货/假一赔十
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • ADF4351BCPZ-RL7图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量26980 
  • 厂家ADI/亚德诺 
  • 封装LFCSP-32 
  • 批号21+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • ADF4351BCPZ-RL7图
  • 深圳市恒嘉威智能科技有限公司

     该会员已使用本站7年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量12578 
  • 厂家ADI/亚德诺 
  • 封装LFCSP32 
  • 批号21+ 
  • 原装恒嘉威价格最实在
  • QQ:1036846627QQ:1036846627 复制
    QQ:2274045202QQ:2274045202 复制
  • -0755-23942980 QQ:1036846627QQ:2274045202
  • ADF4351BCPZ-RL7图
  • 深圳市惠诺德电子有限公司

     该会员已使用本站7年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量29500 
  • 厂家ADI 
  • 封装原厂正品 
  • 批号21+ 
  • 只做原装现货代理
  • QQ:1211267741QQ:1211267741 复制
    QQ:1034782288QQ:1034782288 复制
  • 159-7688-9073 QQ:1211267741QQ:1034782288
  • ADF4351BCPZ-RL7图
  • 深圳市华兴微电子有限公司

     该会员已使用本站16年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量5188 
  • 厂家原厂原装 
  • 封装N/A 
  • 批号23+ 
  • 优势订货,实单专线请联系后面QQ或电话
  • QQ:604502381QQ:604502381 复制
  • 0755-83002105 QQ:604502381
  • ADF4351BCPZ-RL7图
  • 深圳市炎凯科技有限公司

     该会员已使用本站7年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量15000 
  • 厂家AD 
  • 封装LFCSP-32 
  • 批号24+ 
  • 全新原装,特价,假一罚十
  • QQ:354696650QQ:354696650 复制
    QQ:2850471056QQ:2850471056 复制
  • 0755-89587732 QQ:354696650QQ:2850471056
  • ADF4351BCPZ-RL7图
  • 深圳市广百利电子有限公司

     该会员已使用本站6年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量18500 
  • 厂家ADI(亚德诺) 
  • 封装LFCSP-32 
  • 批号23+ 
  • ★★全网低价,原装原包★★
  • QQ:1483430049QQ:1483430049 复制
  • 0755-83235525 QQ:1483430049
  • ADF4351BCPZ-RL7图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • ADF4351BCPZ-RL7 现货库存
  • 数量98500 
  • 厂家ADI/亚德诺 
  • 封装LFSCP32 
  • 批号23+ 
  • 真实库存全新原装正品!专业配单
  • QQ:308365177QQ:308365177 复制
  • 0755-13418564337 QQ:308365177
  • ADF4351BCPZ-RL7图
  • 深圳市芳益电子科技有限公司

     该会员已使用本站10年以上
  • ADF4351BCPZ-RL7 热卖库存
  • 数量6100 
  • 厂家ADI 
  • 封装QFN32 
  • 批号2023+ 
  • 原装正品 现货库存低价出售 欢迎加QQ咨询
  • QQ:498361569QQ:498361569 复制
    QQ:389337416QQ:389337416 复制
  • 0755-13631573466 QQ:498361569QQ:389337416
  • ADF4351BCPZ-RL7图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • ADF4351BCPZ-RL7
  • 数量5300 
  • 厂家ADI(亚德诺) 
  • 封装LFCSP-32 
  • 批号21+ 
  • 全新原装正品,现货库存欢迎咨询
  • QQ:1300774727QQ:1300774727 复制
  • 13714410484 QQ:1300774727
  • ADF4351BCPZ-RL7图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • ADF4351BCPZ-RL7
  • 数量85000 
  • 厂家ADI 
  • 封装LFSCP32 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • ADF4351BCPZ-RL7图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • ADF4351BCPZ-RL7
  • 数量98500 
  • 厂家AD 
  • 封装原厂封装 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • ADF4351BCPZ-RL7图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • ADF4351BCPZ-RL7
  • 数量12787 
  • 厂家ADI/亚德诺 
  • 封装LFCSP32 
  • 批号24+ 
  • 原装原厂 现货现卖
  • QQ:562765057QQ:562765057 复制
    QQ:370820820QQ:370820820 复制
  • 0755-84509636 QQ:562765057QQ:370820820
  • ADF4351BCPZ-RL7图
  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
  • ADF4351BCPZ-RL7
  • 数量8635 
  • 厂家Analog Devices Inc. 
  • 封装32-LFCSP-VQ(5x5) 
  • 批号23+ 
  • 时钟/定时 - 时钟发生器原装现货
  • QQ:892152356QQ:892152356 复制
  • 0755-82777852 QQ:892152356
  • ADF4351BCPZ-RL7图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • ADF4351BCPZ-RL7
  • 数量23508 
  • 厂家ADI/亚德诺 
  • 封装LFCSP32 
  • 批号21+ 
  • 原装现货供应样品批量支持/接受订货/半导体&元器件
  • QQ:2881664480QQ:2881664480 复制
  • 0755-83532193 QQ:2881664480
  • ADF4351BCPZ-RL7图
  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • ADF4351BCPZ-RL7
  • 数量5680 
  • 厂家ADI 
  • 封装LFSCP32 
  • 批号23+ 
  • 原装正品长期供货
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
  • ADF4351BCPZ-RL7图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • ADF4351BCPZ-RL7
  • 数量6626 
  • 厂家ADI/亚德诺 
  • 封装LFCSP-32 
  • 批号21+ 
  • 羿芯诚只做原装 原厂渠道 价格优势
  • QQ:2881498351QQ:2881498351 复制
  • 0755-22968581 QQ:2881498351
  • ADF4351BCPZ-RL7图
  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • ADF4351BCPZ-RL7
  • 数量12245 
  • 厂家ADI/亚德诺 
  • 封装QFN32 
  • 批号22+ 
  • 现货,原厂原装假一罚十!
  • QQ:2885659458QQ:2885659458 复制
    QQ:2885657384QQ:2885657384 复制
  • 0755-83952260 QQ:2885659458QQ:2885657384
  • ADF4351BCPZ-RL7图
  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • ADF4351BCPZ-RL7
  • 数量37000 
  • 厂家ADI 
  • 封装LFCSP 
  • 批号24+ 
  • 公司原装现货可含税!假一罚十!
  • QQ:2885637848QQ:2885637848 复制
    QQ:2885658492QQ:2885658492 复制
  • 0755-84502810 QQ:2885637848QQ:2885658492
  • ADF4351BCPZ-RL7图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • ADF4351BCPZ-RL7
  • 数量8500 
  • 厂家原厂品牌 
  • 封装原厂封装 
  • 批号新年份 
  • 羿芯诚只做原装长期供,支持实单
  • QQ:2880123150QQ:2880123150 复制
  • 0755-82570600 QQ:2880123150
  • ADF4351BCPZ-RL7图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • ADF4351BCPZ-RL7
  • 数量5600 
  • 厂家ADI/亚德诺 
  • 封装LFSCP32 
  • 批号23+ 
  • 100%深圳原装现货库存
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
  • ADF4351BCPZ-RL7图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • ADF4351BCPZ-RL7
  • 数量1000 
  • 厂家ADI/亚德诺 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • ADF4351BCPZ-RL7图
  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • ADF4351BCPZ-RL7
  • 数量15000 
  • 厂家ADI 
  • 封装SMD 
  • 批号2018+ 
  • 一级代理ADI品牌价格绝对优势
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • ADF4351BCPZ-RL7图
  • 集好芯城

     该会员已使用本站13年以上
  • ADF4351BCPZ-RL7
  • 数量12787 
  • 厂家ADI/亚德诺 
  • 封装LFCSP32 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • ADF4351BCPZ-RL7?图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • ADF4351BCPZ-RL7?
  • 数量16300 
  • 厂家ADI 
  • 封装LFSCP32 
  • 批号23+ 
  • 全新原装正品现货
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • ADF4351BCPZ-RL7图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • ADF4351BCPZ-RL7
  • 数量11631 
  • 厂家ADI/亚德诺 
  • 封装QFN32 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • ADF4351BCPZ-RL7图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • ADF4351BCPZ-RL7
  • 数量12500 
  • 厂家ADI/亚德诺 
  • 封装LFCSP 
  • 批号23+ 
  • 只做原装正品假一罚十
  • QQ:2103443489QQ:2103443489 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
  • ADF4351BCPZ-RL7图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • ADF4351BCPZ-RL7
  • 数量7162 
  • 厂家ADI(亚德诺) 
  • 封装LFCSP-32 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • ADF4351BCPZ-RL7图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • ADF4351BCPZ-RL7
  • 数量30000 
  • 厂家ADI 
  • 封装LFCSP 
  • 批号23+ 
  • 代理全新原装现货,价格优势
  • QQ:1774550803QQ:1774550803 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82777855 QQ:1774550803QQ:2924695115
  • ADF4351BCPZ-RL7图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • ADF4351BCPZ-RL7
  • 数量1791 
  • 厂家ADI 
  • 封装LFCSP-32 
  • 批号24+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • ADF4351BCPZ-RL7图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • ADF4351BCPZ-RL7
  • 数量26700 
  • 厂家ADI(亚德诺) 
  • 封装▊原厂封装▊ 
  • 批号▊ROHS环保▊ 
  • 十年以上分销商原装进口件服务型企业0755-83790645
  • QQ:2881664479QQ:2881664479 复制
  • 755-83790645 QQ:2881664479
  • ADF4351BCPZ-RL7图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • ADF4351BCPZ-RL7
  • 数量54751 
  • 厂家AD 
  • 封装LFSCP32 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • ADF4351BCPZ-RL7图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • ADF4351BCPZ-RL7
  • 数量12500 
  • 厂家ADI/亚德诺 
  • 封装LFCSP-32 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • ADF4351BCPZ-RL7图
  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • ADF4351BCPZ-RL7
  • 数量8800 
  • 厂家ADI/亚德诺 
  • 封装LFSCP32 
  • 批号最新批号 
  • 原装现货零成本有接受价格就出
  • QQ:3533288158QQ:3533288158 复制
    QQ:408391813QQ:408391813 复制
  • 0755-84876394 QQ:3533288158QQ:408391813
  • ADF4351BCPZ-RL7图
  • 深圳市昌和盛利电子有限公司

     该会员已使用本站11年以上
  • ADF4351BCPZ-RL7
  • 数量13500 
  • 厂家ADI【原装正品】 
  • 封装LFCSP-32 
  • 批号▊ NEW ▊ 
  • ▊▊★【100%全新原装正品】★长期供应,量大可订,价格优惠!
  • QQ:1551106297QQ:1551106297 复制
    QQ:3059638860QQ:3059638860 复制
  • 0755-23125986 QQ:1551106297QQ:3059638860

产品型号ADF4351BCPZ-RL7的概述

芯片ADF4351BCPZ-RL7的概述 ADF4351BCPZ-RL7是由德州仪器(Analog Devices)公司生产的一款高性能频率合成器和相位锁定环(PLL)。它特别设计用于无线通信、卫星接收和测量系统等高频应用,能够提供频宽达4400MHz的输出频率。ADF4351提供了灵活的频率合成方案,支持多种频率输出模式,因此被广泛应用于各类射频(RF)和微波应用中。 芯片ADF4351BCPZ-RL7的详细参数 ADF4351BCPZ-RL7的主要参数包括: - 频率范围:300 MHz 至 4.4 GHz - 频率分辨率:1 Hz - 调谐范围:最大调谐范围为8.1 GHz - 功率输出:+5 dBm(典型) - 供电电压:提供选择范围,通常在3.0 V 至 5.5 V之间 - 相位噪声:-90 dBc/Hz(在10 kHz偏频) - 温度范围:-40°C 至 +85°C - 接...

产品型号ADF4351BCPZ-RL7的Datasheet PDF文件预览

Wideband Synthesizer  
with Integrated VCO  
ADF4351  
Data Sheet  
FEATURES  
GENERAL DESCRIPTION  
Output frequency range: 35 MHz to 4400 MHz  
Fractional-N synthesizer and integer-N synthesizer  
Low phase noise VCO  
The ADF4351 allows implementation of fractional-N or integer-N  
phase-locked loop (PLL) frequency synthesizers when used with  
an external loop filter and external reference frequency.  
Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output  
Typical jitter: 0.3 ps rms  
Typical EVM at 2.1 GHz: 0.4%  
Power supply: 3.0 V to 3.6 V  
Logic compatibility: 1.8 V  
Programmable dual-modulus prescaler of 4/5 or 8/9  
Programmable output power level  
RF output mute function  
The ADF4351 has an integrated voltage controlled oscillator (VCO)  
with a fundamental output frequency ranging from 2200 MHz to  
4400 MHz. In addition, divide-by-1/-2/-4/-8/-16/-32/-64 circuits  
allow the user to generate RF output frequencies as low as 35 MHz.  
For applications that require isolation, the RF output stage can be  
muted. The mute function is both pin- and software-controllable.  
An auxiliary RF output is also available, which can be powered  
down when not in use.  
3-wire serial interface  
Control of all on-chip registers is through a simple 3-wire interface.  
The device operates with a power supply ranging from 3.0 V to  
3.6 V and can be powered down when not in use.  
Analog and digital lock detect  
Switched bandwidth fast lock mode  
Cycle slip reduction  
APPLICATIONS  
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,  
GSM, PCS, DCS, DECT)  
Test equipment  
Wireless LANs, CATV equipment  
Clock generation  
FUNCTIONAL BLOCK DIAGRAM  
SDV  
AV  
DV  
V
R
V
VCO  
DD  
DD  
DD  
P
SET  
MULTIPLEXER  
MUXOUT  
10-BIT R  
COUNTER  
÷2  
DIVIDER  
×2  
REF  
DOUBLER  
IN  
LOCK  
DETECT  
FAST LOCK  
SWITCH  
SW  
LD  
CLK  
DATA  
LE  
DATA REGISTER  
FUNCTION  
LATCH  
CHARGE  
PUMP  
CP  
OUT  
PHASE  
COMPARATOR  
V
V
TUNE  
REF  
V
VCO  
CORE  
COM  
TEMP  
INTEGER  
VALUE  
FRACTION  
VALUE  
MODULUS  
VALUE  
RF  
RF  
A+  
A–  
OUT  
OUT  
OUTPUT  
STAGE  
THIRD-ORDER  
FRACTIONAL  
INTERPOLATOR  
÷1/2/4/8/16/  
32/64  
PDB  
RF  
RF  
RF  
B+  
B–  
OUTPUT  
STAGE  
OUT  
OUT  
N COUNTER  
MULTIPLEXER  
ADF4351  
AGND  
DGND  
CP  
SD  
GND  
A
GNDVCO  
CE  
GND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2012 Analog Devices, Inc. All rights reserved.  
 
 
 
 
ADF4351  
Data Sheet  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Register 1 ..................................................................................... 18  
Register 2 ..................................................................................... 18  
Register 3 ..................................................................................... 19  
Register 4 ..................................................................................... 20  
Register 5 ..................................................................................... 20  
Register Initialization Sequence ............................................... 20  
RF Synthesizer—A Worked Example ...................................... 21  
Reference Doubler and Reference Divider ............................. 21  
12-Bit Programmable Modulus................................................ 21  
Cycle Slip Reduction for Faster Lock Times........................... 22  
Spurious Optimization and Fast Lock..................................... 22  
Fast Lock Timer and Register Sequences................................ 22  
Fast Lock Example ..................................................................... 22  
Fast Lock Loop Filter Topology................................................ 23  
Spur Mechanisms ....................................................................... 23  
Spur Consistency and Fractional Spur Optimization ........... 24  
Phase Resync............................................................................... 24  
Applications Information .............................................................. 25  
Direct Conversion Modulator .................................................. 25  
Interfacing to the ADuC70xx and the ADSP-BF527............. 26  
PCB Design Guidelines for a Chip Scale Package ................. 26  
Output Matching........................................................................ 27  
Outline Dimensions....................................................................... 28  
Ordering Guide .......................................................................... 28  
Applications....................................................................................... 1  
General Description ......................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Timing Characteristics ................................................................ 5  
Absolute Maximum Ratings............................................................ 6  
Transistor Count........................................................................... 6  
Thermal Resistance ...................................................................... 6  
ESD Caution.................................................................................. 6  
Pin Configuration and Function Descriptions............................. 7  
Typical Performance Characteristics ............................................. 9  
Circuit Description......................................................................... 11  
Reference Input Section............................................................. 11  
RF N Divider............................................................................... 11  
Phase Frequency Detector (PFD) and Charge Pump............ 11  
MUXOUT and Lock Detect...................................................... 12  
Input Shift Registers................................................................... 12  
Program Modes .......................................................................... 12  
VCO.............................................................................................. 12  
Output Stage................................................................................ 13  
Register Maps.................................................................................. 14  
Register 0 ..................................................................................... 18  
REVISION HISTORY  
5/12—Revision 0: Initial Version  
Rev. 0 | Page 2 of 28  
 
Data Sheet  
ADF4351  
SPECIFICATIONS  
AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating  
temperature range is −40°C to +85°C.  
Table 1.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
REFIN CHARACTERISTICS  
Input Frequency  
Input Sensitivity  
10  
0.7  
250  
AVDD  
MHz  
V p-p  
pF  
For f < 10 MHz, ensure slew rate > 21 V/µs  
Biased at AVDD/2; ac coupling ensures AVDD/2 bias  
Input Capacitance  
10  
Input Current  
60  
µA  
PHASE FREQUENCY DETECTOR (PFD)  
Phase Detector Frequency  
32  
45  
90  
MHz  
MHz  
MHz  
Fractional-N  
Integer-N (band select enabled)  
Integer-N (band select disabled)  
CHARGE PUMP  
ICP Sink/Source1  
RSET = 5.1 kΩ  
High Value  
Low Value  
RSET Range  
Sink and Source Current Matching  
ICP vs. VCP  
5
mA  
mA  
kΩ  
%
%
%
0.312  
3.9  
1.5  
10  
2
1.5  
2
0.5 V ≤ VCP ≤ 2.5 V  
0.5 V ≤ VCP ≤ 2.5 V  
VCP = 2.0 V  
ICP vs. Temperature  
LOGIC INPUTS  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input Current, IINH/IINL  
Input Capacitance, CIN  
LOGIC OUTPUTS  
Output High Voltage, VOH  
Output High Current, IOH  
Output Low Voltage, VOL  
POWER SUPPLIES  
AVDD  
V
V
µA  
pF  
0.6  
1
3.0  
DVDD − 0.4  
V
µA  
V
CMOS output selected  
IOL = 500 µA  
500  
0.4  
3.0  
3.6  
27  
V
DVDD, VVCO, SDVDD, VP  
AVDD  
21  
6 to 36  
70  
21  
7
These voltages must equal AVDD  
2
DIDD + AIDD  
mA  
mA  
mA  
mA  
µA  
Output Dividers  
Each output divide-by-2 consumes 6 mA  
RF output stage is programmable  
2
IVCO  
80  
26  
10  
2
IRFOUT  
Low Power Sleep Mode  
RF OUTPUT CHARACTERISTICS  
VCO Output Frequency  
Minimum VCO Output Frequency  
Using Dividers  
2200  
34.375  
4400  
MHz  
MHz  
Fundamental VCO mode  
2200 MHz fundamental output and  
divide-by-64 selected  
VCO Sensitivity, KV  
40  
1
90  
−19  
−20  
−13  
−10  
MHz/V  
MHz/V  
kHz  
dBc  
dBc  
Frequency Pushing (Open-Loop)  
Frequency Pulling (Open-Loop)  
Harmonic Content (Second)  
Into 2.00 VSWR load  
Fundamental VCO output  
Divided VCO output  
Fundamental VCO output  
Divided VCO output  
Harmonic Content (Third)  
dBc  
dBc  
Rev. 0 | Page 3 of 28  
 
ADF4351  
Data Sheet  
Parameter  
Min  
Typ  
−4  
5
Max  
Unit  
dBm  
dBm  
dB  
Test Conditions/Comments  
Minimum RF Output Power3  
Maximum RF Output Power3  
Output Power Variation  
Programmable in 3 dB steps  
1
Minimum VCO Tuning Voltage  
Maximum VCO Tuning Voltage  
NOISE CHARACTERISTICS  
VCO Phase Noise Performance  
0.5  
2.5  
V
V
VCO noise is measured in open-loop conditions  
10 kHz offset from 2.2 GHz carrier  
100 kHz offset from 2.2 GHz carrier  
1 MHz offset from 2.2 GHz carrier  
5 MHz offset from 2.2 GHz carrier  
10 kHz offset from 3.3 GHz carrier  
100 kHz offset from 3.3 GHz carrier  
1 MHz offset from 3.3 GHz carrier  
5 MHz offset from 3.3 GHz carrier  
10 kHz offset from 4.4 GHz carrier  
100 kHz offset from 4.4 GHz carrier  
1 MHz offset from 4.4 GHz carrier  
5 MHz offset from 4.4 GHz carrier  
PLL loop BW = 500 kHz  
−89  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
−114  
−134  
−148  
−86  
−111  
−134  
−145  
−83  
−110  
−131  
−145  
Normalized Phase Noise Floor  
4
(PNSYNTH  
)
−220  
−221  
dBc/Hz  
dBc/Hz  
ABP = 6 ns  
ABP = 3 ns  
5
Normalized 1/f Noise (PN1_f  
)
10 kHz offset; normalized to 1 GHz  
ABP = 6 ns  
ABP = 3 ns  
−116  
−118  
−100  
0.27  
dBc/Hz  
dBc/Hz  
dBc/Hz  
ps  
In-Band Phase Noise  
Integrated RMS Jitter6  
3 kHz from 2111.28 MHz carrier  
Spurious Signals Due to PFD  
Frequency  
−80  
dBc  
Level of Signal with RF Mute Enabled  
−40  
dBm  
1 ICP is internally modified to maintain constant loop gain over the frequency range.  
2 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 25 MHz; fRF = 4.4 GHz.  
3 Using 50 Ω resistors to VVCO, into a 50 Ω load. Power measured with auxiliary RF output disabled. The current consumption of the auxiliary output is the same as for the  
main output.  
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider  
value) and 10 log fPFD. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: PNSYNTH = PNTOT − 10 log(fPFD) − 20 log N.  
5 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)  
and at a frequency offset (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.  
6 fREFIN = 122.88 MHz; fPFD = 30.72 MHz; VCO frequency = 4222.56 MHz; RFOUT = 2111.28 MHz; N = 137; loop BW = 60 kHz; ICP = 2.5 mA; low noise mode. The noise was  
measured with an EVAL-ADF4351EB1Z and the Rohde & Schwarz FSUP signal source analyzer.  
Rev. 0 | Page 4 of 28  
Data Sheet  
ADF4351  
TIMING CHARACTERISTICS  
AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless  
otherwise noted.  
Table 2.  
Parameter  
Limit  
20  
10  
10  
25  
25  
10  
20  
Unit  
Description  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
LE setup time  
DATA to CLK setup time  
DATA to CLK hold time  
CLK high duration  
CLK low duration  
CLK to LE setup time  
LE pulse width  
Timing Diagram  
t4  
t5  
CLK  
t2  
t3  
DB2  
(CONTROL BIT C3)  
DB1  
DB0 (LSB)  
(CONTROL BIT C1)  
DB31 (MSB)  
DB30  
DATA  
LE  
(CONTROL BIT C2)  
t7  
t1  
t6  
LE  
Figure 2. Timing Diagram  
Rev. 0 | Page 5 of 28  
 
 
 
ADF4351  
Data Sheet  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C, unless otherwise noted.  
This device is a high performance RF integrated circuit with an  
ESD rating of <1.5 kV and is ESD sensitive. Proper precautions  
should be taken for handling and assembly.  
Table 3.  
Parameter  
AVDD to GND1  
Rating  
TRANSISTOR COUNT  
−0.3 V to +3.9 V  
−0.3 V to +0.3 V  
−0.3 V to +3.9 V  
−0.3 V to +0.3 V  
−0.3 V to VDD + 0.3 V  
−0.3 V to VDD + 0.3 V  
−0.3 V to VDD + 0.3 V  
−40°C to +85°C  
−65°C to +125°C  
150°C  
AVDD to DVDD  
The transistor count for the ADF4351 is 36,955 (CMOS) and  
986 (bipolar).  
VVCO to GND1  
VVCO to AVDD  
THERMAL RESISTANCE  
Digital I/O Voltage to GND1  
Analog I/O Voltage to GND1  
REFIN to GND1  
Thermal impedance (θJA) is specified for a device with the  
exposed pad soldered to GND.  
Operating Temperature Range  
Storage Temperature Range  
Maximum Junction Temperature  
Reflow Soldering  
Table 4. Thermal Resistance  
Package Type  
θJA  
Unit  
32-Lead LFCSP (CP-32-2)  
27.3  
°C/W  
Peak Temperature  
Time at Peak Temperature  
260°C  
40 sec  
ESD CAUTION  
1 GND = AGND = DGND = CPGND = SDGND = AGNDVCO = 0 V.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Rev. 0 | Page 6 of 28  
 
 
 
 
Data Sheet  
ADF4351  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
24  
23  
22  
21  
20  
19  
18  
17  
V
V
R
A
CLK  
DATA  
LE  
CE  
SW  
1
2
REF  
PIN 1  
COM  
INDICATOR  
3
4
SET  
ADF4351  
GNDVCO  
5
6
7
8
V
TOP VIEW  
TUNE  
VP  
(Not to Scale)  
TEM  
A
V
P
CP  
OUT  
GND  
GNDVCO  
VCO  
CP  
NOTES  
1. THE LFCSP HAS AN EXPOSED PAD THAT  
MUST BE CONNECTED TO GND.  
Figure 3. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
CLK  
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high  
impedance CMOS input.  
2
3
4
DATA  
LE  
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high  
impedance CMOS input.  
Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into the register that is  
selected by the three control bits. This input is a high impedance CMOS input.  
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.  
A logic high on this pin powers up the device, depending on the status of the power-down bits.  
CE  
5
6
SW  
VP  
Fast Lock Switch. A connection should be made from the loop filter to this pin when using the fast lock mode.  
Charge Pump Power Supply. VP must have the same value as AVDD. Place decoupling capacitors to the ground  
plane as close to this pin as possible.  
7
CPOUT  
Charge Pump Output. When enabled, this output provides ICP to the external loop filter. The output of the  
loop filter is connected to VTUNE to drive the internal VCO.  
8
9
10  
CPGND  
AGND  
AVDD  
Charge Pump Ground. This output is the ground return pin for CPOUT  
Analog Ground. Ground return pin for AVDD  
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog ground  
.
.
plane as close to this pin as possible. AVDD must have the same value as DVDD  
.
11, 18, 21  
12  
AGNDVCO  
RFOUTA+  
VCO Analog Ground. Ground return pins for the VCO.  
VCO Output. The output level is programmable. The VCO fundamental output or a divided-down version is  
available.  
13  
RFOUTA−  
RFOUTB+  
RFOUTB−  
VVCO  
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided-  
down version is available.  
Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided-down  
version is available.  
Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a  
divided-down version is available.  
Power Supply for the VCO. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog  
14  
15  
16, 17  
19  
ground plane as close to these pins as possible. VVCO must have the same value as AVDD  
.
TEMP  
Temperature Compensation Output. Place decoupling capacitors to the ground plane as close to this pin as  
possible.  
20  
VTUNE  
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT  
output voltage.  
Rev. 0 | Page 7 of 28  
 
ADF4351  
Data Sheet  
Pin No.  
Mnemonic  
Description  
22  
RSET  
Connecting a resistor between this pin and ground sets the charge pump output current. The nominal voltage  
bias at the RSET pin is 0.55 V. The relationship between ICP and RSET is as follows:  
ICP = 25.5/RSET  
where:  
RSET = 5.1 kΩ.  
ICP = 5 mA.  
23  
VCOM  
Internal Compensation Node. Biased at half the tuning range. Place decoupling capacitors to the ground plane  
as close to this pin as possible.  
24  
25  
VREF  
LD  
Reference Voltage. Place decoupling capacitors to the ground plane as close to this pin as possible.  
Lock Detect Output Pin. A logic high output on this pin indicates PLL lock. A logic low output indicates loss  
of PLL lock.  
26  
27  
28  
PDBRF  
DGND  
DVDD  
RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.  
Digital Ground. Ground return pin for DVDD  
.
Digital Power Supply. DVDD must have the same value as AVDD. Place decoupling capacitors to the ground  
plane as close to this pin as possible.  
29  
30  
REFIN  
Reference Input. This CMOS input has a nominal threshold of AVDD/2 and a dc equivalent input resistance of  
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.  
Multiplexer Output. The multiplexer output allows the lock detect value, the N divider value, or the R counter  
value to be accessed externally.  
MUXOUT  
31  
32  
SDGND  
SDVDD  
Digital Σ-Δ Modulator Ground. Ground return pin for the Σ-Δ modulator.  
Power Supply Pin for the Digital Σ-Δ Modulator. SDVDD must have the same value as AVDD. Place decoupling  
capacitors to the ground plane as close to this pin as possible.  
EP  
Exposed Pad Exposed Pad. The LFCSP has an exposed pad that must be connected to GND.  
Rev. 0 | Page 8 of 28  
Data Sheet  
ADF4351  
TYPICAL PERFORMANCE CHARACTERISTICS  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
–40  
–50  
DIV1  
DIV2  
DIV4  
DIV8  
DIV16  
DIV32  
DIV64  
–60  
–70  
–80  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
1k  
10k  
100k  
1M  
10M  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 4. Open-Loop VCO Phase Noise, 2.2 GHz  
Figure 7. Closed-Loop Phase Noise, Fundamental VCO and Dividers,  
VCO = 2.2 GHz, PFD = 25 MHz, Loop Filter Bandwidth = 63 kHz  
–40  
–90  
DIV1  
–50  
–60  
DIV2  
DIV4  
DIV8  
–100  
DIV16  
DIV32  
DIV64  
–70  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
–80  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
1k  
10k  
100k  
1M  
10M  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 5. Open-Loop VCO Phase Noise, 3.3 GHz  
Figure 8. Closed-Loop Phase Noise, Fundamental VCO and Dividers,  
VCO = 3.3 GHz, PFD = 25 MHz, Loop Filter Bandwidth = 63 kHz  
–40  
–50  
–90  
DIV1  
DIV2  
DIV4  
DIV8  
DIV16  
DIV32  
DIV64  
–100  
–110  
–120  
–60  
–70  
–80  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–130  
–140  
–150  
–160  
–170  
1k  
10k  
100k  
1M  
10M  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 6. Open-Loop VCO Phase Noise, 4.4 GHz  
Figure 9. Closed-Loop Phase Noise, Fundamental VCO and Dividers,  
VCO = 4.4 GHz, PFD = 25 MHz, Loop Filter Bandwidth = 63 kHz  
Rev. 0 | Page 9 of 28  
 
ADF4351  
Data Sheet  
–60  
–70  
–60  
–70  
–80  
–80  
–90  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–160  
1k  
10k  
100k  
1M  
10M  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 13. Fractional-N Spur Performance, Low Noise Mode, LTE Band;  
RFOUT = 2646.96 MHz, REFIN = 122.88 MHz, PFD = 30.72 MHz; Loop Filter  
Bandwidth = 60 kHz, Channel Spacing = 240 kHz; Phase Word = 9,  
RMS Phase Error = 0.28°, RMS Jitter = 0.29 ps, EVM = 0.49%  
Figure 10. Fractional-N Spur Performance, Low Noise Mode, W-CDMA Band;  
RFOUT = 2111.28 MHz, REFIN = 122.88 MHz, PFD = 30.72 MHz, Output Divide-by-2  
Selected; Loop Filter Bandwidth = 60 kHz, Channel Spacing = 240 kHz;  
RMS Phase Error = 0.21°, RMS Jitter = 0.27 ps, EVM = 0.37%  
–60  
–70  
–60  
–70  
–80  
–80  
–90  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
1k  
10k  
100k  
1M  
10M  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 11. Fractional-N Spur Performance, Low Spur Mode, W-CDMA Band;  
RFOUT = 2111.28 MHz, REFIN = 122.88 MHz, PFD = 30.72 MHz, Output Divide-by-2  
Selected; Loop Filter Bandwidth = 60 kHz, Channel Spacing = 240 kHz;  
RMS Phase Error = 0.37°, RMS Jitter = 0.49 ps, EVM = 0.64%  
Figure 14. Fractional-N Spur Performance, Low Spur Mode, LTE Band;  
RFOUT = 2646.96 MHz, REFIN = 122.88 MHz, PFD = 30.72 MHz;  
Loop Filter Bandwidth = 60 kHz, Channel Spacing = 240 kHz;  
RMS Phase Error = 0.56°, RMS Jitter = 0.59 ps, EVM = 0.98%  
–60  
–70  
–60  
–70  
–80  
–80  
–90  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
1k  
10k  
100k  
1M  
10M  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 15. Fractional-N Spur Performance, Low Noise Mode, W-CDMA Band;  
RFOUT = 2646.96 MHz, REFIN = 122.88 MHz, PFD = 30.72 MHz;  
Loop Filter Bandwidth = 20 kHz, Channel Spacing = 240 kHz;  
RMS Phase Error = 0.35°, RMS Jitter = 0.36 ps, EVM = 0.61%  
Figure 12. Fractional-N Spur Performance, Low Noise Mode, W-CDMA Band;  
RFOUT = 2111.28 MHz, REFIN = 122.88 MHz, PFD = 30.72 MHz, Output Divide-by-2  
Selected; Loop Filter Bandwidth = 20 kHz, Channel Spacing = 240 kHz;  
RMS Phase Error = 0.25°, RMS Jitter = 0.32 ps, EVM = 0.44%  
Rev. 0 | Page 10 of 28  
 
 
Data Sheet  
ADF4351  
CIRCUIT DESCRIPTION  
The PFD frequency (fPFD) equation is  
PFD = REFIN × [(1 + D)/(R × (1 + T))]  
REFERENCE INPUT SECTION  
f
(2)  
The reference input stage is shown in Figure 16. The SW1 and  
SW2 switches are normally closed. The SW3 switch is normally  
open. When power-down is initiated, SW3 is closed, and SW1  
and SW2 are opened. In this way, no loading of the REFIN pin  
occurs during power-down.  
where:  
REFIN is the reference input frequency.  
D is the REFIN doubler bit (0 or 1).  
R is the preset divide ratio of the binary 10-bit programmable  
reference counter (1 to 1023).  
POWER-DOWN  
CONTROL  
T is the REFIN divide-by-2 bit (0 or 1).  
100k  
SW2  
NC  
Integer-N Mode  
TO R COUNTER  
REF  
IN  
NC  
SW1  
If FRAC = 0 and the DB8 (LDF) bit in Register 2 is set to 1, the  
synthesizer operates in integer-N mode. The DB8 bit in Register 2  
should be set to 1 for integer-N digital lock detect.  
BUFFER  
SW3  
NO  
R Counter  
Figure 16. Reference Input Stage  
The 10-bit R counter allows the input reference frequency  
(REFIN) to be divided down to produce the reference clock  
to the PFD. Division ratios from 1 to 1023 are allowed.  
RF N DIVIDER  
The RF N divider allows a division ratio in the PLL feedback  
path. The division ratio is determined by the INT, FRAC, and  
MOD values, which build up this divider (see Figure 17).  
PHASE FREQUENCY DETECTOR (PFD) AND  
CHARGE PUMP  
RF N DIVIDER  
N = INT + FRAC/MOD  
FROM  
VCO OUTPUT/  
OUTPUT DIVIDERS  
The phase frequency detector (PFD) takes inputs from the  
R counter and N counter and produces an output proportional  
to the phase and frequency difference between them. Figure 18  
is a simplified schematic of the phase frequency detector.  
UP  
TO PFD  
N COUNTER  
THIRD-ORDER  
FRACTIONAL  
INTERPOLATOR  
HIGH  
D1  
Q1  
U1  
CLR1  
INT  
VALUE  
FRAC  
VALUE  
MOD  
VALUE  
+IN  
CHARGE  
PUMP  
CP  
U3  
DELAY  
DOWN  
OUT  
Figure 17. RF N Divider  
INT, FRAC, MOD, and R Counter Relationship  
The INT, FRAC, and MOD values, in conjunction with the  
R counter, make it possible to generate output frequencies that  
are spaced by fractions of the PFD frequency. For more informa-  
tion, see the RF Synthesizer—A Worked Example section.  
CLR2  
D2 Q2  
HIGH  
U2  
–IN  
Figure 18. PFD Simplified Schematic  
The RF VCO frequency (RFOUT) equation is  
The PFD includes a programmable delay element that sets the  
width of the antibacklash pulse (ABP). This pulse ensures that  
there is no dead zone in the PFD transfer function. Bit DB22 in  
Register 3 (R3) is used to set the ABP as follows:  
RFOUT = fPFD × (INT + (FRAC/MOD))  
where:  
RFOUT is the output frequency of the voltage controlled oscillator  
(1)  
(VCO).  
When Bit DB22 is set to 0, the ABP width is programmed to  
6 ns, the recommended value for fractional-N applications.  
When Bit DB22 is set to 1, the ABP width is programmed to  
3 ns, the recommended value for integer-N applications.  
INT is the preset divide ratio of the binary 16-bit counter (23 to  
65,535 for the 4/5 prescaler; 75 to 65,535 for the 8/9 prescaler).  
FRAC is the numerator of the fractional division (0 to MOD − 1).  
MOD is the preset fractional modulus (2 to 4095).  
For integer-N applications, the in-band phase noise is improved  
by enabling the shorter pulse width. The PFD frequency can  
operate up to 90 MHz in this mode. To operate with PFD  
frequencies higher than 45 MHz, VCO band select must be dis-  
abled by setting the phase adjust bit (DB28) to 1 in Register 1.  
Rev. 0 | Page 11 of 28  
 
 
 
 
 
 
 
 
ADF4351  
Data Sheet  
MUXOUT AND LOCK DETECT  
PROGRAM MODES  
The multiplexer output on the ADF4351 allows the user to access  
various internal points on the chip. The state of MUXOUT is  
controlled by the M3, M2, and M1 bits in Register 2 (see Figure 26).  
Figure 19 shows the MUXOUT section in block diagram form.  
Table 6 and Figure 23 through Figure 29 show how the program  
modes are set up in the ADF4351.  
The following settings in the ADF4351 are double buffered: phase  
value, modulus value, reference doubler, reference divide-by-2,  
R counter value, and charge pump current setting. Before the part  
uses a new value for any double-buffered setting, the following  
two events must occur:  
DV  
DD  
THREE-STATE OUTPUT  
DV  
DD  
1. The new value is latched into the device by writing to the  
appropriate register.  
2. A new write is performed on Register 0 (R0).  
DGND  
R COUNTER OUTPUT  
N DIVIDER OUTPUT  
MUX  
CONTROL  
MUXOUT  
ANALOG LOCK DETECT  
For example, any time that the modulus value is updated,  
Register 0 (R0) must be written to, to ensure that the modulus  
value is loaded correctly. The divider select value in Register 4  
(R4) is also double buffered, but only if the DB13 bit of  
Register 2 (R2) is set to 1.  
DIGITAL LOCK DETECT  
RESERVED  
DGND  
Figure 19. MUXOUT Schematic  
VCO  
INPUT SHIFT REGISTERS  
The VCO core in the ADF4351 consists of three separate VCOs,  
each of which uses 16 overlapping bands, as shown in Figure 20,  
to allow a wide frequency range to be covered without a large  
VCO sensitivity (KV) and resultant poor phase noise and spur-  
ious performance.  
The ADF4351 digital section includes a 10-bit RF R counter,  
a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit  
modulus counter. Data is clocked into the 32-bit shift register  
on each rising edge of CLK. The data is clocked in MSB first.  
Data is transferred from the shift register to one of six latches  
on the rising edge of LE. The destination latch is determined by  
the state of the three control bits (C3, C2, and C1) in the shift  
register. As shown in Figure 2, the control bits are the three LSBs:  
DB2, DB1, and DB0. Table 6 shows the truth table for these bits.  
Figure 23 summarizes how the latches are programmed.  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
Table 6. Truth Table for the C3, C2, and C1 Control Bits  
Control Bits  
C3  
0
C2  
0
C1  
0
Register  
Register 0 (R0)  
Register 1 (R1)  
Register 2 (R2)  
Register 3 (R3)  
Register 4 (R4)  
Register 5 (R5)  
0
0
1
0
1
0
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
0
1
1
FREQUENCY (GHz)  
1
0
0
Figure 20. VTUNE vs. Frequency  
1
0
1
The correct VCO and band are selected automatically by the  
VCO and band select logic at power-up or whenever Register 0  
(R0) is updated.  
VCO and band selection take 10 PFD cycles multiplied by the  
value of the band select clock divider. The VCO VTUNE is discon-  
nected from the output of the loop filter and is connected to an  
internal reference voltage.  
Rev. 0 | Page 12 of 28  
 
 
 
 
 
 
 
Data Sheet  
ADF4351  
The R counter output is used as the clock for the band select  
logic. A programmable divider is provided at the R counter  
output to allow division by an integer from 1 to 255; the divider  
value is set using Bits[DB19:DB12] in Register 4 (R4). When the  
required PFD frequency is higher than 125 kHz, the divide ratio  
should be set to allow enough time for correct band selection.  
OUTPUT STAGE  
The RFOUTA+ and RFOUTA− pins of the ADF4351 are connected  
to the collectors of an NPN differential pair driven by buffered  
outputs of the VCO, as shown in Figure 22.  
RF  
A+  
RF  
A–  
OUT  
OUT  
Band selection takes 10 cycles of the PFD frequency, equal to  
80 µs. If faster lock times are required, Bit DB23 in Register 3  
(R3) must be set to 1. This setting allows the user to select a  
higher band select clock frequency of up to 500 kHz, which  
speeds up the minimum band select time to 20 µs. For phase  
adjustments and small (<1 MHz) frequency adjustments, the  
user can disable VCO band selection by setting Bit DB28 in  
Register 1 (R1) to 1. This setting selects the phase adjust feature.  
BUFFER/  
DIVIDE-BY-1/-2/-4/-8/  
-16/-32/-64  
VCO  
Figure 22. Output Stage  
To allow the user to optimize the power dissipation vs. the  
output power requirements, the tail current of the differential  
pair is programmable using Bits[DB4:DB3] in Register 4 (R4).  
Four current levels can be set. These levels give output power  
levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, using a 50 Ω  
resistor to AVDD and ac coupling into a 50 Ω load. Alternatively,  
both outputs can be combined in a 1 + 1:1 transformer or a 180°  
microstrip coupler (see the Output Matching section).  
After band selection, normal PLL action resumes. The nominal  
value of KV is 40 MHz/V when the N divider is driven from the  
VCO output or from this value divided by D. D is the output  
divider value if the N divider is driven from the RF divider output  
(selected by programming Bits[DB22:DB20] in Register 4). The  
ADF4351 contains linearization circuitry to minimize any vari-  
ation of the product of ICP and KV to keep the loop bandwidth  
constant.  
If the outputs are used individually, the optimum output stage  
consists of a shunt inductor to VVCO. The unused complementary  
output must be terminated with a similar circuit to the used output.  
The VCO shows variation of KV as the VTUNE varies within the  
band and from band to band. For wideband applications cover-  
ing a wide frequency range (and changing output dividers), a  
value of 40 MHz/V provides the most accurate KV because this  
value is closest to an average value. Figure 21 shows how KV  
varies with fundamental VCO frequency, along with an average  
value for the frequency band. Users may prefer this figure when  
using narrow-band designs.  
An auxiliary output stage exists on the RFOUTB+ and RFOUTB−  
pins, providing a second set of differential outputs that can be  
used to drive another circuit. The auxiliary output stage can be  
used only if the primary outputs are enabled. If the auxiliary  
output stage is not used, it can be powered down.  
Another feature of the ADF4351 is that the supply current to  
the RF output stage can be shut down until the part achieves  
lock, as measured by the digital lock detect circuitry. This  
feature is enabled by setting the mute till lock detect (MTLD)  
bit in Register 4 (R4).  
80  
70  
60  
50  
40  
30  
20  
10  
0
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
FREQUENCY (GHz)  
Figure 21. VCO Sensitivity (KV) vs. Frequency  
Rev. 0 | Page 13 of 28  
 
 
 
ADF4351  
Data Sheet  
REGISTER MAPS  
REGISTER 0  
CONTROL  
BITS  
16-BIT INTEGER VALUE (INT)  
12-BIT FRACTIONAL VALUE (FRAC)  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
N16 N15 N14 N13 N12 N11 N10  
N9  
N8  
N7  
N6  
N5  
N4  
N3  
N2  
N1  
F12 F11  
F10  
F9  
F8  
F7  
F6  
F5  
F4  
F3  
F2  
F1 C3(0) C2(0) C1(0)  
REGISTER 1  
CONTROL  
BITS  
1
1
RESERVED  
12-BIT PHASE VALUE (PHASE)  
12-BIT MODULUS VALUE (MOD)  
DBR  
DBR  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
PH1 PR1 P12 P11 P10  
P9  
P8  
P7  
P6  
P5  
P4  
P3  
P2  
P1  
M12 M11 M10  
M9  
M8  
M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)  
REGISTER 2  
LOW  
CHARGE  
PUMP  
CURRENT  
SETTING  
NOISE AND  
LOW SPUR  
MODES  
1
CONTROL  
BITS  
1
MUXOUT  
10-BIT R COUNTER  
DBR  
DBR  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
L2  
L1  
M3  
M2  
M1 RD2 RD1 R10  
R9  
R8  
R7  
R6  
R5  
R4  
R3  
R2  
R1  
D1  
CP4 CP3 CP2 CP1 U6  
U5  
U4  
U3  
U2  
U1 C3(0) C2(1) C1(0)  
REGISTER 3  
CLK  
DIV  
MODE  
RESERVED  
RESERVED  
CONTROL  
BITS  
12-BIT CLOCK DIVIDER VALUE  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
0
0
0
0
0
F4  
F3  
F2  
0
0
F1  
0
C2  
C1  
D12 D11 D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1 C3(0) C2(1) C1(1)  
REGISTER 4  
2
DBB  
AUX  
OUTPUT  
POWER  
RF DIVIDER  
SELECT  
OUTPUT  
POWER  
RESERVED  
CONTROL  
BITS  
8-BIT BAND SELECT CLOCK DIVIDER VALUE  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
0
0
0
0
0
D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1 C3(1) C2(0) C1(0)  
REGISTER 5  
LD PIN  
MODE  
CONTROL  
BITS  
RESERVED  
RESERVED  
RESERVED  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
D15 D14 C3(1) C2(0) C1(1)  
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
DBR = DOUBLE-BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.  
DBB = DOUBLE-BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH.  
Figure 23. Register Summary  
Rev. 0 | Page 14 of 28  
 
 
Data Sheet  
ADF4351  
CONTROL  
BITS  
16-BIT INTEGER VALUE (INT)  
12-BIT FRACTIONAL VALUE (FRAC)  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
N16  
N15  
N14  
N13  
N12  
N11  
N10  
N9  
N8  
N7  
N6  
N5  
N4  
N3  
N2  
N1  
F12  
F11  
F10  
F9  
F8  
F7  
F6  
F5  
F4  
F3  
F2  
F1 C3(0) C2(0) C1(0)  
F12  
F11 ... F2  
F1  
FRACTIONAL VALUE (FRAC)  
N16  
N15  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
N5  
N4  
N3  
N2  
N1  
INTEGER VALUE (INT)  
0
0
0
0
.
0
0
0
0
.
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
0
0
1
1
.
0
1
0
1
.
0
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
NOT ALLOWED  
1
NOT ALLOWED  
2
NOT ALLOWED  
3
...  
.
0
0
0
.
0
0
0
.
1
1
1
.
0
0
1
.
1
1
0
.
1
1
0
.
0
1
0
.
NOT ALLOWED  
23  
.
.
.
.
.
24  
.
.
.
.
.
...  
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092  
4093  
4094  
4095  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
65,533  
65,534  
65,535  
INTmin = 75 WITH PRESCALER = 8/9  
Figure 24. Register 0 (R0)  
CONTROL  
BITS  
RESERVED  
12-BIT PHASE VALUE (PHASE)  
DBR  
12-BIT MODULUS VALUE (MOD)  
DBR  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
PH1  
PR1 P12  
P11  
P10  
P9  
P8  
P7  
P6  
P5  
P4  
P3  
P2  
P1  
M12 M11 M10  
M9  
M8  
M7 M6  
M5  
M4  
M3  
M2  
M1 C3(0) C2(0) C1(1)  
P12  
P11 ... P2  
P1  
0
1
0
1
.
PHASE VALUE (PHASE)  
M12  
M11 ... M2  
M1  
INTERPOLATOR MODULUS (MOD)  
0
0
0
0
.
0
0
0
0
.
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
0
0
1
1
.
0
0
0
.
0
0
.
...  
...  
...  
...  
...  
...  
...  
...  
...  
1
1
.
0
1
.
2
3
1 (RECOMMENDED)  
.
2
.
.
.
.
.
3
.
.
.
.
.
.
PH1 PHASE ADJ  
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092  
4093  
4094  
4095  
0
1
OFF  
ON  
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092  
4093  
4094  
4095  
PR1 PRESCALER  
0
1
4/5  
8/9  
Figure 25. Register 1 (R1)  
Rev. 0 | Page 15 of 28  
 
 
ADF4351  
Data Sheet  
CHARGE  
PUMP  
CURRENT  
SETTING  
LOW  
NOISE AND  
LOW SPUR  
MODES  
CONTROL  
BITS  
MUXOUT  
10-BIT R COUNTER  
DBR  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
L2  
L1  
M3  
M2  
M1 RD2 RD1 R10  
R9  
R8  
R7  
R6  
R5  
R4  
R3  
R2  
R1  
D1  
CP4 CP3 CP2 CP1 U6  
U5  
U4  
U3  
U2  
U1 C3(0) C2(1) C1(0)  
REFERENCE  
RD2  
COUNTER  
RESET  
DOUBLE BUFFER  
R4 [DB22:DB20]  
U1  
L2  
0
L1  
NOISE MODE  
DOUBLER  
D1  
U6  
0
LDF  
0
1
DISABLED  
ENABLED  
0
1
0
1
LOW NOISE MODE  
RESERVED  
FRAC-N  
INT-N  
0
1
DISABLED  
ENABLED  
0
1
DISABLED  
ENABLED  
0
1
1
RESERVED  
RD1 REFERENCE DIVIDE-BY-2  
CP  
1
LOW SPUR MODE  
I
(mA)  
CP  
U2  
U5  
LDP  
THREE-STATE  
0
1
DISABLED  
ENABLED  
CP4  
CP3  
CP2  
CP1  
5.1kΩ  
0
1
10ns  
6ns  
0
1
DISABLED  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.31  
0.63  
0.94  
1.25  
1.56  
1.88  
2.19  
2.50  
2.81  
3.13  
3.44  
3.75  
4.06  
4.38  
4.69  
5.00  
ENABLED  
R10  
R9  
... R2  
R1  
R COUNTER (R)  
U3  
POWER-DOWN  
DISABLED  
U4  
0
PD POLARITY  
NEGATIVE  
POSITIVE  
0
0
.
0
0
.
...  
...  
...  
...  
...  
...  
...  
...  
...  
0
1
.
1
0
.
1
0
1
2
ENABLED  
1
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1020  
1021  
1022  
1023  
M3  
M2  
0
M1  
0
OUTPUT  
0
0
0
0
1
1
1
1
THREE-STATE OUTPUT  
0
1
DV  
DD  
1
0
DGND  
1
1
R COUNTER OUTPUT  
N DIVIDER OUTPUT  
ANALOG LOCK DETECT  
DIGITAL LOCK DETECT  
RESERVED  
0
0
0
1
1
0
1
1
Figure 26. Register 2 (R2)  
CLK  
DIV  
MODE  
CONTROL  
BITS  
RESERVED  
12-BIT CLOCK DIVIDER VALUE  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
0
0
0
0
0
F4  
F3  
F2  
0
F1  
0
C2  
C1  
D12 D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1 C3(0) C2(1) C1(1)  
0
D12  
D11 ... D2  
D1  
CLOCK DIVIDER VALUE  
CYCLE SLIP  
REDUCTION  
F1  
0
0
0
0
.
0
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
...  
0
0
1
1
.
0
1
0
1
.
0
0
1
DISABLED  
ENABLED  
0
0
0
.
1
2
3
BAND SELECT  
CLOCK MODE  
CHARGE  
.
F4  
F2  
CANCELATION  
.
.
.
.
.
C2  
0
C1  
0
CLOCK DIVIDER MODE  
CLOCK DIVIDER OFF  
FAST LOCK ENABLE  
RESYNC ENABLE  
RESERVED  
0
1
LOW  
HIGH  
0
1
DISABLED  
ENABLED  
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092  
4093  
4094  
4095  
0
1
ANTIBACKLASH  
PULSE WIDTH  
1
0
F3  
1
1
0
1
6ns (FRAC-N)  
3ns (INT-N)  
Figure 27. Register 3 (R3)  
Rev. 0 | Page 16 of 28  
 
 
Data Sheet  
ADF4351  
AUX  
OUTPUT  
POWER  
RF DIVIDER  
SELECT  
OUTPUT  
POWER  
CONTROL  
BITS  
RESERVED  
DBB  
8-BIT BAND SELECT CLOCK DIVIDER VALUE  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
0
0
0
0
0
D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1 C3(1) C2(0) C1(0)  
FEEDBACK  
SELECT  
VCO  
D13  
D2  
0
D1  
0
OUTPUT POWER  
D9  
POWER-DOWN  
0
1
–4dBm  
–1dBm  
+2dBm  
+5dBm  
DIVIDED  
0
1
VCO POWERED UP  
FUNDAMENTAL  
0
1
VCO POWERED DOWN  
1
0
MUTE TILL  
D12  
D11  
D10  
RF DIVIDER SELECT  
1
1
D8  
0
LOCK DETECT  
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
÷1  
MUTE DISABLED  
MUTE ENABLED  
D3  
0
RF OUT  
÷2  
1
DISABLED  
ENABLED  
÷4  
1
÷8  
AUX OUTPUT  
D7  
SELECT  
÷16  
÷32  
÷64  
D5  
D4  
0
AUX OUTPUT POWER  
–4dBm  
0
1
DIVIDED OUTPUT  
FUNDAMENTAL  
0
0
1
1
1
–1dBm  
0
+2dBm  
D6  
0
AUX OUT  
BS8  
BS7  
... BS2  
BS1  
BAND SELECT CLOCK DIVIDER  
1
+5dBm  
DISABLED  
ENABLED  
0
0
.
0
0
.
...  
...  
...  
...  
...  
...  
...  
...  
...  
0
1
.
1
0
.
1
1
2
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252  
253  
254  
255  
Figure 28. Register 4 (R4)  
LD PIN  
MODE  
CONTROL  
BITS  
RESERVED  
RESERVED  
RESERVED  
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
0
0
0
0
0
D15  
D14  
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C3(1) C2(0) C1(1)  
D15  
0
D14  
0
LOCK DETECT PIN OPERATION  
LOW  
0
1
DIGITAL LOCK DETECT  
1
0
LOW  
HIGH  
1
1
Figure 29. Register 5 (R5)  
Rev. 0 | Page 17 of 28  
 
 
ADF4351  
Data Sheet  
12-Bit Phase Value  
REGISTER 0  
Bits[DB26:DB15] control the phase word. The phase word must  
be less than the MOD value programmed in Register 1. The phase  
word is used to program the RF output phase from 0° to 360°  
with a resolution of 360°/MOD (see the Phase Resync section).  
Control Bits  
When Bits[C3:C1] are set to 000, Register 0 is programmed.  
Figure 24 shows the input data format for programming this  
register.  
In most applications, the phase relationship between the RF  
signal and the reference is not important. In such applications,  
the phase value can be used to optimize the fractional and sub-  
fractional spur levels. For more information, see the Spur  
Consistency and Fractional Spur Optimization section.  
16-Bit Integer Value (INT)  
The 16 INT bits (Bits[DB30:DB15]) set the INT value, which  
determines the integer part of the feedback division factor. The  
INT value is used in Equation 1 (see the INT, FRAC, MOD, and  
R Counter Relationship section). Integer values from 23 to  
65,535 are allowed for the 4/5 prescaler; for the 8/9 prescaler,  
the minimum integer value is 75.  
If neither the phase resync nor the spurious optimization func-  
tion is used, it is recommended that the phase word be set to 1.  
12-Bit Modulus Value (MOD)  
12-Bit Fractional Value (FRAC)  
The 12 MOD bits (Bits[DB14:DB3]) set the fractional modulus.  
The fractional modulus is the ratio of the PFD frequency to the  
channel step resolution on the RF output. For more information,  
see the 12-Bit Programmable Modulus section.  
The 12 FRAC bits (Bits[DB14:DB3]) set the numerator of the  
fraction that is input to the Σ-Δ modulator. This fraction, along  
with the INT value, specifies the new frequency channel that  
the synthesizer locks to, as shown in the RF Synthesizer—A  
Worked Example section. FRAC values from 0 to (MOD − 1)  
cover channels over a frequency range equal to the PFD refer-  
ence frequency.  
REGISTER 2  
Control Bits  
When Bits[C3:C1] are set to 010, Register 2 is programmed.  
Figure 26 shows the input data format for programming this  
register.  
REGISTER 1  
Control Bits  
When Bits[C3:C1] are set to 001, Register 1 is programmed.  
Figure 25 shows the input data format for programming this  
register.  
Low Noise and Low Spur Modes  
The noise mode on the ADF4351 is controlled by setting  
Bits[DB30:DB29] in Register 2 (see Figure 26). The noise mode  
allows the user to optimize a design either for improved spurious  
performance or for improved phase noise performance.  
Phase Adjust  
The phase adjust bit (Bit DB28) enables adjustment of the output  
phase of a given output frequency. When phase adjustment is  
enabled (Bit DB28 is set to 1), the part does not perform VCO  
band selection or phase resync when Register 0 is updated.  
When phase adjustment is disabled (Bit DB28 is set to 0), the  
part performs VCO band selection and phase resync (if phase  
resync is enabled in Register 3, Bits[DB16:DB15]) when Register 0  
is updated. Disabling VCO band selection is recommended only  
for fixed frequency applications or for frequency deviations of  
<1 MHz from the originally selected frequency.  
When the low spur mode is selected, dither is enabled. Dither  
randomizes the fractional quantization noise so that it resembles  
white noise rather than spurious noise. As a result, the part is  
optimized for improved spurious performance. Low spur mode  
is normally used for fast-locking applications when the PLL  
closed-loop bandwidth is wide. Wide loop bandwidth is a loop  
bandwidth greater than 1/10 of the RFOUT channel step resolu-  
tion (fRES). A wide loop filter does not attenuate the spurs to the  
same level as a narrow loop bandwidth.  
Prescaler Value  
For best noise performance, use the low noise mode option.  
When the low noise mode is selected, dither is disabled. This  
mode ensures that the charge pump operates in an optimum  
region for noise performance. Low noise mode is extremely  
useful when a narrow loop filter bandwidth is available. The  
synthesizer ensures extremely low noise, and the filter attenuates  
the spurs. Figure 10 through Figure 12 show the trade-offs in a  
typical W-CDMA setup for different noise and spur settings.  
The dual-modulus prescaler (P/P + 1), along with the INT,  
FRAC, and MOD values, determines the overall division  
ratio from the VCO output to the PFD input. The PR1 bit  
(DB27) in Register 1 sets the prescaler value.  
Operating at CML levels, the prescaler takes the clock from the  
VCO output and divides it down for the counters. The prescaler  
is based on a synchronous 4/5 core. When the prescaler is set to  
4/5, the maximum RF frequency allowed is 3.6 GHz. Therefore,  
when operating the ADF4351 above 3.6 GHz, the prescaler must  
be set to 8/9. The prescaler limits the INT value as follows:  
MUXOUT  
The on-chip multiplexer is controlled by Bits[DB28:DB26]  
(see Figure 26). Note that N counter output must be disabled  
for VCO band selection to operate correctly.  
Prescaler = 4/5: NMIN = 23  
Prescaler = 8/9: NMIN = 75  
Rev. 0 | Page 18 of 28  
 
 
 
 
Data Sheet  
ADF4351  
Reference Doubler  
For fractional-N applications, the recommended setting for  
Bits[DB8:DB7] is 00; for integer-N applications, the recom-  
mended setting for Bits[DB8:DB7] is 11.  
Setting the DB25 bit to 0 disables the doubler and feeds the REFIN  
signal directly into the 10-bit R counter. Setting this bit to 1 multi-  
plies the REFIN frequency by a factor of 2 before feeding it into  
the 10-bit R counter. When the doubler is disabled, the REFIN  
falling edge is the active edge at the PFD input to the fractional  
synthesizer. When the doubler is enabled, both the rising and  
falling edges of REFIN become active edges at the PFD input.  
Phase Detector Polarity  
The DB6 bit sets the phase detector polarity. When a passive  
loop filter or a noninverting active loop filter is used, this bit  
should be set to 1. If an active filter with an inverting charac-  
teristic is used, this bit should be set to 0.  
When the doubler is enabled and the low spur mode is selected,  
the in-band phase noise performance is sensitive to the REFIN duty  
cycle. The phase noise degradation can be as much as 5 dB for  
REFIN duty cycles outside a 45% to 55% range. The phase noise  
is insensitive to the REFIN duty cycle in the low noise mode and  
when the doubler is disabled.  
Power-Down (PD)  
The DB5 bit provides the programmable power-down mode.  
Setting this bit to 1 performs a power-down. Setting this bit to 0  
returns the synthesizer to normal operation. In software power-  
down mode, the part retains all information in its registers. The  
register contents are lost only if the supply voltages are removed.  
The maximum allowable REFIN frequency when the doubler is  
enabled is 30 MHz.  
When power-down is activated, the following events occur:  
Synthesizer counters are forced to their load state conditions.  
VCO is powered down.  
Charge pump is forced into three-state mode.  
Digital lock detect circuitry is reset.  
RFOUT buffers are disabled.  
RDIV2  
Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop  
between the R counter and the PFD, which extends the maximum  
REFIN input rate. This function allows a 50% duty cycle signal to  
appear at the PFD input, which is necessary for cycle slip reduction.  
Input registers remain active and capable of loading and  
latching data.  
10-Bit R Counter  
The 10-bit R counter (Bits[DB23:DB14]) allows the input reference  
frequency (REFIN) to be divided down to produce the reference  
clock to the PFD. Division ratios from 1 to 1023 are allowed.  
Charge Pump Three-State  
Setting the DB4 bit to 1 puts the charge pump into three-state  
mode. This bit should be set to 0 for normal operation.  
Double Buffer  
Counter Reset  
The DB13 bit enables or disables double buffering of  
Bits[DB22:DB20] in Register 4. For information about how  
double buffering works, see the Program Modes section.  
The DB3 bit is the reset bit for the R counter and the N counter  
of the ADF4351. When this bit is set to 1, the RF synthesizer  
N counter and R counter are held in reset. For normal opera-  
tion, this bit should be set to 0.  
Charge Pump Current Setting  
Bits[DB12:DB9] set the charge pump current. This value should  
be set to the charge pump current that the loop filter is designed  
with (see Figure 26).  
REGISTER 3  
Control Bits  
When Bits[C3:C1] are set to 011, Register 3 is programmed.  
Figure 27 shows the input data format for programming this  
register.  
Lock Detect Function (LDF)  
The DB8 bit configures the lock detect function (LDF). The LDF  
controls the number of PFD cycles monitored by the lock detect  
circuit to ascertain whether lock has been achieved. When DB8 is  
set to 0, the number of PFD cycles monitored is 40. When DB8  
is set to 1, the number of PFD cycles monitored is 5. It is recom-  
mended that the DB8 bit be set to 0 for fractional-N mode and  
to 1 for integer-N mode.  
Band Select Clock Mode  
Setting the DB23 bit to 1 selects a faster logic sequence of band  
selection, which is suitable for high PFD frequencies and is  
necessary for fast lock applications. Setting the DB23 bit to 0 is  
recommended for low PFD (<125 kHz) values. For the faster  
band select logic modes (DB23 set to 1), the value of the band  
select clock divider must be less than or equal to 254.  
Lock Detect Precision (LDP)  
The lock detect precision bit (Bit DB7) sets the comparison  
window in the lock detect circuit. When DB7 is set to 0, the  
comparison window is 10 ns; when DB7 is set to 1, the window  
is 6 ns. The lock detect circuit goes high when n consecutive  
PFD cycles are less than the comparison window value; n is set  
by the LDF bit (DB8). For example, with DB8 = 0 and DB7 = 0,  
40 consecutive PFD cycles of 10 ns or less must occur before  
digital lock detect goes high.  
Antibacklash Pulse Width (ABP)  
Bit DB22 sets the PFD antibacklash pulse width. When Bit DB22  
is set to 0, the PFD antibacklash pulse width is 6 ns. This setting is  
recommended for fractional-N use. When Bit DB22 is set to 1,  
the PFD antibacklash pulse width is 3 ns, which results in phase  
noise and spur improvements in integer-N operation. For  
fractional-N operation, the 3 ns setting is not recommended.  
Rev. 0 | Page 19 of 28  
 
ADF4351  
Data Sheet  
Charge Cancelation  
VCO Power-Down  
Setting the DB21 bit to 1 enables charge pump charge cancel-  
ation. This has the effect of reducing PFD spurs in integer-N  
mode. In fractional-N mode, this bit should be set to 0.  
Setting the DB11 bit to 0 powers the VCO up; setting this bit to 1  
powers the VCO down.  
Mute Till Lock Detect (MTLD)  
CSR Enable  
When the DB10 bit is set to 1, the supply current to the RF output  
stage is shut down until the part achieves lock, as measured by  
the digital lock detect circuitry.  
Setting the DB18 bit to 1 enables cycle slip reduction. CSR is  
a method for improving lock times. Note that the signal at the  
phase frequency detector (PFD) must have a 50% duty cycle for  
cycle slip reduction to work. The charge pump current setting  
must also be set to a minimum. For more information, see the  
Cycle Slip Reduction for Faster Lock Times section.  
AUX Output Select  
The DB9 bit sets the auxiliary RF output. If DB9 is set to 0, the  
auxiliary RF output is the output of the RF dividers; if DB9 is set  
to 1, the auxiliary RF output is the fundamental VCO frequency.  
Clock Divider Mode  
AUX Output Enable  
Bits[DB16:DB15] must be set to 10 to activate phase resync  
(see the Phase Resync section). These bits must be set to 01  
to activate fast lock (see the Fast Lock Timer and Register  
Sequences section). Setting Bits[DB16:DB15] to 00 disables  
the clock divider (see Figure 27).  
The DB8 bit enables or disables the auxiliary RF output. If DB8  
is set to 0, the auxiliary RF output is disabled; if DB8 is set to 1,  
the auxiliary RF output is enabled.  
AUX Output Power  
Bits[DB7:DB6] set the value of the auxiliary RF output power  
level (see Figure 28).  
12-Bit Clock Divider Value  
Bits[DB14:DB3] set the 12-bit clock divider value. This value  
is the timeout counter for activation of phase resync (see the  
Phase Resync section). The clock divider value also sets the  
timeout counter for fast lock (see the Fast Lock Timer and  
Register Sequences section).  
RF Output Enable  
The DB5 bit enables or disables the primary RF output. If DB5  
is set to 0, the primary RF output is disabled; if DB5 is set to 1,  
the primary RF output is enabled.  
REGISTER 4  
Output Power  
Control Bits  
Bits[DB4:DB3] set the value of the primary RF output power  
level (see Figure 28).  
When Bits[C3:C1] are set to 100, Register 4 is programmed.  
Figure 28 shows the input data format for programming this  
register.  
REGISTER 5  
Control Bits  
Feedback Select  
When Bits[C3:C1] are set to 101, Register 5 is programmed.  
Figure 29 shows the input data format for programming this  
register.  
The DB23 bit selects the feedback from the VCO output to the  
N counter. When this bit is set to 1, the signal is taken directly  
from the VCO. When this bit is set to 0, the signal is taken from  
the output of the output dividers. The dividers enable coverage  
of the wide frequency band (34.375 MHz to 4.4 GHz). When  
the dividers are enabled and the feedback signal is taken from  
the output, the RF output signals of two separately configured  
PLLs are in phase. This is useful in some applications where the  
positive interference of signals is required to increase the power.  
Lock Detect Pin Operation  
Bits[DB23:DB22] set the operation of the lock detect (LD) pin  
(see Figure 29).  
REGISTER INITIALIZATION SEQUENCE  
At initial power-up, after the correct application of voltages to  
the supply pins, the ADF4351 registers should be started in the  
following sequence:  
RF Divider Select  
Bits[DB22:DB20] select the value of the RF output divider (see  
Figure 28).  
1. Register 5  
2. Register 4  
3. Register 3  
4. Register 2  
5. Register 1  
6. Register 0  
Band Select Clock Divider Value  
Bits[DB19:DB12] set a divider for the band select logic clock input.  
By default, the output of the R counter is the value used to clock  
the band select logic, but, if this value is too high (>125 kHz), a  
divider can be switched on to divide the R counter output to a  
smaller value (see Figure 28).  
Rev. 0 | Page 20 of 28  
 
 
 
Data Sheet  
ADF4351  
RF SYNTHESIZER—A WORKED EXAMPLE  
REFERENCE DOUBLER AND REFERENCE DIVIDER  
The following equations are used to program the ADF4351  
synthesizer:  
The on-chip reference doubler allows the input reference signal  
to be doubled. Doubling the reference signal doubles the PFD  
comparison frequency, which improves the noise performance of  
the system. Doubling the PFD frequency usually improves noise  
performance by 3 dB. Note that in fractional-N mode, the PFD  
cannot operate above 32 MHz due to a limitation in the speed  
of the Σ-Δ circuit of the N divider. For integer-N applications,  
the PFD can operate up to 90 MHz.  
RFOUT = [INT + (FRAC/MOD)] × (fPFD/RF Divider)  
(3)  
where:  
RFOUT is the RF frequency output.  
INT is the integer division factor.  
FRAC is the numerator of the fractional division (0 to MOD − 1).  
MOD is the preset fractional modulus (2 to 4095).  
RF Divider is the output divider that divides down the  
VCO frequency.  
The reference divide-by-2 divides the reference signal by 2,  
resulting in a 50% duty cycle PFD frequency. This is necessary  
for the correct operation of the cycle slip reduction (CSR)  
function. For more information, see the Cycle Slip Reduction  
for Faster Lock Times section.  
fPFD = REFIN × [(1 + D)/(R × (1 + T))]  
(4)  
where:  
REFIN is the reference frequency input.  
D is the RF REFIN doubler bit (0 or 1).  
R is the RF reference division factor (1 to 1023).  
T is the reference divide-by-2 bit (0 or 1).  
12-BIT PROGRAMMABLE MODULUS  
The choice of modulus (MOD) depends on the reference signal  
(REFIN) available and the channel resolution (fRES) required at the  
RF output. For example, a GSM system with 13 MHz REFIN sets  
the modulus to 65. This means that the RF output resolution  
(fRES) is the 200 kHz (13 MHz/65) necessary for GSM. With  
dither off, the fractional spur interval depends on the selected  
modulus values (see Table 7).  
As an example, a UMTS system requires a 2112.6 MHz RF  
frequency output (RFOUT); a 10 MHz reference frequency input  
(REFIN) is available and a 200 kHz channel resolution (fRESOUT) is  
required on the RF output.  
Note that the ADF4351 VCO operates in the frequency range  
of 2.2 GHz to 4.4 GHz. Therefore, the RF divider of 2 should be  
used (VCO frequency = 4225.2 MHz, RFOUT = VCO frequency/  
RF divider = 4225.2 MHz/2 = 2112.6 MHz).  
Unlike most other fractional-N PLLs, the ADF4351 allows the  
user to program the modulus over a 12-bit range. When com-  
bined with the reference doubler and the 10-bit R counter, the  
12-bit modulus allows the user to set up the part in many  
different configurations for the application.  
It is also important where the loop is closed. In this example,  
the loop is closed before the output divider (see Figure 30).  
For example, consider an application that requires a 1.75 GHz  
RF frequency output with a 200 kHz channel step resolution.  
The system has a 13 MHz reference signal.  
fPFD  
RF  
OUT  
PFD  
VCO  
÷2  
One possible setup is to feed the 13 MHz reference signal  
directly into the PFD and to program the modulus to divide  
by 65. This results in the required 200 kHz resolution.  
N
DIVIDER  
Figure 30. Loop Closed Before Output Divider  
Another possible setup is to use the reference doubler to create  
26 MHz from the 13 MHz input signal. The 26 MHz is then fed  
into the PFD, and the modulus is programmed to divide by 130.  
This setup also results in 200 kHz resolution but offers superior  
phase noise performance over the first setup.  
Channel resolution (fRESOUT) of 200 kHz is required at the output  
of the RF divider. Therefore, the channel resolution at the output  
of the VCO (fRES) needs to be 2 × fRESOUT, that is, 400 kHz.  
MOD = REFIN/fRES  
MOD = 10 MHz/400 kHz = 25  
The programmable modulus is also very useful for multi-  
standard applications. For example, if a dual-mode phone  
requires PDC and GSM 1800 standards, the programmable  
modulus is of great benefit.  
From Equation 4,  
f
PFD = [10 MHz × (1 + 0)/1] = 10 MHz  
2112.6 MHz = 10 MHz × [(INT + (FRAC/25))/2]  
where:  
(5)  
(6)  
PDC requires 25 kHz channel step resolution, whereas GSM 1800  
requires 200 kHz channel step resolution. A 13 MHz reference  
signal can be fed directly to the PFD, and the modulus can be  
programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz).  
The modulus must be reprogrammed to 65 for GSM 1800 opera-  
tion (13 MHz/65 = 200 kHz).  
INT = 422.  
FRAC = 13.  
Rev. 0 | Page 21 of 28  
 
 
 
 
ADF4351  
Data Sheet  
It is important that the PFD frequency remain constant (in this  
example, 13 MHz). This allows the user to design one loop filter  
for both setups without encountering stability issues. Note that  
the ratio of the RF frequency to the PFD frequency principally  
affects the loop filter design, not the actual channel spacing.  
SPURIOUS OPTIMIZATION AND FAST LOCK  
Narrow loop bandwidths can filter unwanted spurious signals,  
but these bandwidths usually have a long lock time. A wider  
loop bandwidth achieves faster lock times but may lead to  
increased spurious signals inside the loop bandwidth.  
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES  
The fast lock feature can achieve the same fast lock time as the  
wider bandwidth but with the advantage of a narrow final loop  
bandwidth to keep spurs low.  
As described in the Low Noise and Low Spur Modes section, the  
ADF4351 contains a number of features that allow optimization  
for noise performance. However, in fast-locking applications,  
the loop bandwidth generally needs to be wide and, therefore,  
the filter does not provide much attenuation of the spurs. If the  
cycle slip reduction feature is enabled, the narrow loop band-  
width is maintained for spur attenuation, but faster lock times  
are still possible.  
FAST LOCK TIMER AND REGISTER SEQUENCES  
If the fast lock mode is used, a timer value must be loaded into  
the PLL to determine the duration of the wide bandwidth mode.  
When Bits[DB16:DB15] in Register 3 are set to 01 (fast lock  
enable), the timer value is loaded by the 12-bit clock divider  
value (Bits[DB14:DB3] in Register 3). The following sequence  
must be programmed to use fast lock:  
Cycle Slips  
Cycle slips occur in integer-N/fractional-N synthesizers when  
the loop bandwidth is narrow compared to the PFD frequency.  
The phase error at the PFD inputs accumulates too fast for the  
PLL to correct, and the charge pump temporarily pumps in the  
wrong direction. This slows down the lock time dramatically.  
The ADF4351 contains a cycle slip reduction feature that  
extends the linear range of the PFD, allowing faster lock times  
without modifications to the loop filter circuitry.  
1. Start the initialization sequence (see the Register Initialization  
Sequence section). This sequence occurs only once after  
powering up the part.  
2. Load Register 3 by setting Bits[DB16:DB15] to 01 and by  
setting the selected fast lock timer value (Bits[DB14:DB3]).  
The duration that the PLL remains in wide bandwidth mode  
is equal to the fast lock timer/fPFD  
.
When the circuitry detects that a cycle slip is about to occur, it  
turns on an extra charge pump current cell. This cell outputs a  
constant current to the loop filter or removes a constant current  
from the loop filter (depending on whether the VCO tuning  
voltage needs to increase or decrease to acquire the new  
frequency). The effect is that the linear range of the PFD is  
increased. Loop stability is maintained because the current is  
constant and is not a pulsed current.  
FAST LOCK EXAMPLE  
If a PLL has a reference frequency of 13 MHz, fPFD of 13 MHz,  
and a required lock time of 60 µs, the PLL is set to wide bandwidth  
mode for 20 µs. This example assumes a modulus of 65 for channel  
spacing of 200 kHz. The VCO calibration time of 20 µs must also  
be taken into account (achieved by programming the higher band  
select clock mode using Bit DB23 of Register 3).  
If the time set for the PLL lock time in wide bandwidth mode is  
20 µs, then  
If the phase error increases again to a point where another cycle  
slip is likely, the ADF4351 turns on another charge pump cell.  
This continues until the ADF4351 detects that the VCO fre-  
quency has exceeded the desired frequency. The extra charge  
pump cells are turned off one by one until all the extra charge  
pump cells are disabled and the frequency settles to the original  
loop filter bandwidth.  
Fast Lock Timer Value = (VCO Band Select Time +  
PLL Lock Time in Wide Bandwidth) × fPFD/MOD  
Fast Lock Timer Value = (20 µs + 20 µs) × 13 MHz/65 = 8  
Therefore, a value of 8 must be loaded into the clock divider  
value in Register 3 (see Step 2 in the Fast Lock Timer and  
Register Sequences section).  
Up to seven extra charge pump cells can be turned on. In most  
applications, seven cells are enough to eliminate cycle slips  
altogether, providing much faster lock times.  
Setting Bit DB18 in Register 3 to 1 enables cycle slip reduction.  
Note that the PFD requires a 45% to 55% duty cycle for CSR to  
operate correctly. If the REFIN frequency does not have a suitable  
duty cycle, enabling the RDIV2 mode (Bit DB24 in Register 2)  
ensures that the input to the PFD has a 50% duty cycle.  
Rev. 0 | Page 22 of 28  
 
 
 
 
Data Sheet  
ADF4351  
In low noise mode (dither off), the quantization noise from the  
Σ-Δ modulator appears as fractional spurs. The interval between  
spurs is fPFD/L, where L is the repeat length of the code sequence  
in the digital Σ-Δ modulator. For the third-order Σ-Δ modulator  
used in the ADF4351, the repeat length depends on the value of  
MOD (see Table 7).  
FAST LOCK LOOP FILTER TOPOLOGY  
To use fast lock mode, the damping resistor in the loop filter is  
reduced to one-fourth its value while in wide bandwidth mode.  
To achieve the wider loop filter bandwidth, the charge pump  
current increases by a factor of 16; to maintain loop stability,  
the damping resistor must be reduced by a factor of one-fourth.  
To enable fast lock, the SW pin is shorted to the AGND pin by  
setting Bits[DB16:DB15] in Register 3 to 01. The following two  
topologies are available:  
Table 7. Fractional Spurs with Dither Off (Low Noise Mode)  
Repeat  
Length  
MOD Value (Dither Off)  
Spur Interval  
MOD is divisible by 2, but not by 3 2 × MOD Channel step/2  
MOD is divisible by 3, but not by 2 3 × MOD Channel step/3  
The damping resistor (R1) is divided into two values  
(R1 and R1A) that have a ratio of 1:3 (see Figure 31).  
An extra resistor (R1A) is connected directly from SW, as  
shown in Figure 32. The extra resistor is calculated such  
that the parallel combination of the extra resistor and the  
damping resistor (R1) is reduced to one-fourth the original  
value of R1 (see Figure 32).  
MOD is divisible by 6  
MOD is not divisible by 2, 3, or 6  
6 × MOD Channel step/6  
MOD Channel step  
In low spur mode (dither on), the repeat length is extended  
to 221 cycles, regardless of the value of MOD, which makes the  
quantization error spectrum look like broadband noise. This  
may degrade the in-band phase noise at the PLL output by as  
much as 10 dB. For lowest noise, dither off is a better choice,  
particularly when the final loop bandwidth is low enough to  
attenuate even the lowest frequency fractional spur.  
ADF4351  
R2  
CP  
VCO  
OUT  
C1  
C2  
R1  
C3  
SW  
Integer Boundary Spurs  
R1A  
Another mechanism for fractional spur creation is the inter-  
actions between the RF VCO frequency and the reference  
frequency. When these frequencies are not integer related (the  
purpose of a fractional-N synthesizer), spur sidebands appear  
on the VCO output spectrum at an offset frequency that corre-  
sponds to the beat note, or difference frequency, between an  
integer multiple of the reference and the VCO frequency. These  
spurs are attenuated by the loop filter and are more noticeable  
on channels close to integer multiples of the reference, where  
the difference frequency can be inside the loop bandwidth (thus  
the name integer boundary spurs).  
Figure 31. Fast Lock Loop Filter Topology 1  
ADF4351  
R2  
CP  
VCO  
OUT  
C1  
C2  
R1  
C3  
R1A  
SW  
Reference Spurs  
Reference spurs are generally not a problem in fractional-N  
synthesizers because the reference offset is far outside the loop  
bandwidth. However, any reference feedthrough mechanism  
that bypasses the loop may cause a problem. Feedthrough of  
low levels of on-chip reference switching noise, coupling to the  
VCO, can result in reference spur levels as high as −80 dBc. The  
PCB layout must ensure adequate isolation between VCO circuitry  
and the input reference to avoid a possible feedthrough path on  
the board.  
Figure 32. Fast Lock Loop Filter Topology 2  
SPUR MECHANISMS  
This section describes the three different spur mechanisms that  
arise with a fractional-N synthesizer and how to minimize them  
in the ADF4351.  
Fractional Spurs  
The fractional interpolator in the ADF4351 is a third-order  
Σ-Δ modulator with a modulus (MOD) that is programmable  
to any integer value from 2 to 4095. In low spur mode (dither  
on), the minimum allowable value of MOD is 50. The Σ-Δ  
modulator is clocked at the PFD reference rate (fPFD), which  
allows PLL output frequencies to be synthesized at a channel  
step resolution of fPFD/MOD.  
Rev. 0 | Page 23 of 28  
 
 
 
 
 
ADF4351  
Data Sheet  
In the example shown in Figure 33, the PFD reference is 25 MHz  
and MOD = 125 for a 200 kHz channel spacing. tSYNC is set to  
400 µs by programming CLK_DIV_VALUE = 80.  
SPUR CONSISTENCY AND FRACTIONAL SPUR  
OPTIMIZATION  
With dither off, the fractional spur pattern due to the quantiza-  
tion noise of the Σ-Δ modulator also depends on the particular  
phase word with which the modulator is seeded.  
LE  
tSYNC  
SYNC  
(INTERNAL)  
The phase word can be varied to optimize the fractional and  
subfractional spur levels on any particular frequency. Thus, a  
lookup table of phase values corresponding to each frequency  
can be created for use when programming the ADF4351.  
LAST CYCLE SLIP  
FREQUENCY  
PLL SETTLES TO  
INCORRECT PHASE  
If a lookup table is not used, keep the phase word at a constant  
value to ensure consistent spur levels on any particular frequency.  
PLL SETTLES TO  
CORRECT PHASE  
AFTER RESYNC  
PHASE  
PHASE RESYNC  
The output of a fractional-N PLL can settle to any one of the  
MOD phase offsets with respect to the input reference, where  
MOD is the fractional modulus. The phase resync feature of  
the ADF4351 produces a consistent output phase offset with  
respect to the input reference. This phase offset is necessary in  
applications where the output phase and frequency are important,  
such as digital beamforming. See the Phase Programmability  
section to program a specific RF output phase when using  
phase resync.  
–100  
0
100 200 300 400 500 600 700 800 900 1000  
TIME (µs)  
Figure 33. Phase Resync Example  
Phase Programmability  
The phase word in Register 1 controls the RF output phase. As  
this word is swept from 0 to MOD, the RF output phase sweeps  
over a 360° range in steps of 360°/MOD. In many applications,  
it is advisable to disable VCO band selection by setting Bit DB28  
in Register 1 (R1) to 1. This setting selects the phase adjust feature.  
Phase resync is enabled by setting Bits[DB16:DB15] in  
Register 3 to 10. When phase resync is enabled, an internal  
timer generates sync signals at intervals of tSYNC given by the  
following formula:  
High PFD Frequencies  
VCO band selection is required to ensure that the correct VCO  
band is chosen for the relevant frequency. VCO band selection  
can operate with PFD frequencies up to 45 MHz using the high  
VCO band select mode (set Bit DB23 in Register 3 to 1).  
tSYNC = CLK_DIV_VALUE × MOD × tPFD  
where:  
CLK_DIV_VALUE is the decimal value programmed in  
Bits[DB14:DB3] of Register 3. This value can be any integer  
from 1 to 4095.  
For PFD frequencies higher than 45 MHz, it is recommended  
that the user perform the following steps:  
1. Program the desired VCO frequency with phase adjustment  
disabled (set Bit DB28 in Register 1 to 0). Ensure that the  
PFD frequency is less than 45 MHz.  
MOD is the modulus value programmed in Bits[DB14:DB3]  
of Register 1 (R1).  
t
PFD is the PFD reference period.  
2. After the correct frequency is achieved, enable phase adjust-  
ment (set Bit DB28 in Register 1 to 1).  
When a new frequency is programmed, the second sync pulse  
after the LE rising edge is used to resynchronize the output  
phase to the reference. The tSYNC time must be programmed to  
a value that is at least as long as the worst-case lock time. This  
guarantees that the phase resync occurs after the last cycle slip  
in the PLL settling transient.  
3. PFD frequencies higher than 32 MHz are permissible only  
with integer-N applications; therefore, set the antibacklash  
pulse width to 3 ns (set Bit DB22 in Register 3 to 1).  
4. Using the desired PFD frequency, program the appropriate  
values for the reference R and feedback N counters.  
Using this procedure, the lowest rms in-band phase noise can  
be achieved.  
Rev. 0 | Page 24 of 28  
 
 
 
 
Data Sheet  
ADF4351  
APPLICATIONS INFORMATION  
The LO ports of the ADL5375 can be driven differentially from  
the complementary RFOUTA outputs of the ADF4351. This setup  
provides better performance than a single-ended LO driver and  
eliminates the use of a balun to convert from a single-ended LO  
input to the more desirable differential LO input for the ADL5375.  
The typical rms phase noise (100 Hz to 5 MHz) of the LO in this  
configuration is 0.61° rms.  
DIRECT CONVERSION MODULATOR  
Direct conversion architectures are increasingly being used  
to implement base station transmitters. Figure 34 shows how  
Analog Devices, Inc., parts can be used to implement such a  
system.  
Figure 34 shows the AD9788 TxDAC® used with the ADL5375.  
The use of dual integrated DACs, such as the AD9788 with its  
specified 2% FSR and 0.001% FSR gain and offset character-  
istics, ensures minimum error contribution (over temperature)  
from this portion of the signal chain.  
The ADL5375 accepts LO drive levels from −6 dBm to +6 dBm.  
The optimum LO power can be software programmed on the  
ADF4351, which allows levels from −4 dBm to +5 dBm from  
each output.  
The local oscillator (LO) is implemented using the ADF4351. The  
low-pass filter was designed using ADIsimPLL™ for a channel  
spacing of 200 kHz and a closed-loop bandwidth of 35 kHz.  
The RF output is designed to drive a 50 Ω load, but it must be  
ac-coupled, as shown in Figure 34. If the I and Q inputs are  
driven in quadrature by 2 V p-p signals, the resulting output  
power from the ADL5375 modulator is approximately 2 dBm.  
51  
51Ω  
OUT1_P  
OUT1_N  
LOW-PASS  
FILTER  
MODULATED  
DIGITAL  
DATA  
AD9788  
TxDAC  
OUT2_P  
OUT2_N  
LOW-PASS  
FILTER  
51Ω  
51Ω  
V
V
LOCK  
DETECT  
VCO  
DD  
16  
17  
26  
30  
25  
28  
DV  
10  
AV  
4
6
32  
MUXOUT LD  
V
PDB  
SDV  
DD  
CE  
V
P
VCO  
RF  
DD  
DD  
ADL5375  
1nF 1nF  
IBBP  
IBBN  
f
REF  
RF  
B+ 14  
29  
51Ω  
REFIN  
IN  
OUT  
V
VCO  
RF  
B–  
15  
OUT  
1
2
3
CLK  
3.9nH 3.9nH  
DATA  
LE  
1nF  
LOIP  
LOIN  
12  
13  
RF  
RF  
A+  
A–  
OUT  
OUT  
V
QUADRATURE  
PHASE  
SPLITTER  
LPF  
LPF  
RFOUT  
DSOP  
ADF4351  
22  
R
SET  
4.7kΩ  
1nF  
20  
7
TUNE  
680Ω  
QBBP  
QBBN  
CP  
OUT  
39nF  
2700pF  
1200pF  
SW  
REF  
24  
5
360Ω  
CP  
SD  
A
V
V
GND  
GND AGND  
31  
GNDVCO DGND TEMP COM  
8
9
11 18 21  
27 19 23  
10pF  
0.1µF 10pF  
10pF  
0.1µF  
0.1µF  
Figure 34. Direct Conversion Modulator  
Rev. 0 | Page 25 of 28  
 
 
 
ADF4351  
Data Sheet  
ADSP-BF527 Interface  
INTERFACING TO THE ADuC70xx AND  
THE ADSP-BF527  
Figure 36 shows the interface between the ADF4351 and the  
Blackfin® ADSP-BF527 digital signal processor (DSP). The  
ADF4351 needs a 32-bit serial word for each latch write. The  
easiest way to accomplish this using the Blackfin family is to  
use the autobuffered transmit mode of operation with alternate  
framing. This mode provides a means for transmitting an entire  
block of serial data before an interrupt is generated.  
The ADF4351 has a simple SPI-compatible serial interface for  
writing to the device. The CLK, DATA, and LE pins control the  
data transfer. When LE goes high, the 32 bits that were clocked  
into the appropriate register on each rising edge of CLK are  
transferred to the appropriate latch. See Figure 2 for the timing  
diagram and Table 6 for the register address table.  
ADuC70xx Interface  
ADF4351  
ADSP-BF527  
SCK  
MOSI  
GPIO  
CLK  
DATA  
LE  
Figure 35 shows the interface between the ADF4351 and the  
ADuC70xx family of analog microcontrollers. The ADuC70xx  
family is based on an AMR7 core, but the same interface can be  
used with any 8051-based microcontroller.  
CE  
I/O PORTS  
MUXOUT  
(LOCK DETECT)  
ADF4351  
ADuC70xx  
SCLOCK  
MOSI  
CLK  
Figure 36. ADSP-BF527 to ADF4351 Interface  
DATA  
LE  
Set up the word length for eight bits and use four memory  
locations for each 32-bit word. To program each 32-bit latch,  
store the four 8-bit bytes, enable the autobuffered mode, and  
write to the transmit register of the DSP. This last operation  
initiates the autobuffer transfer. Make sure that the SPI timing  
requirements listed in Table 2 are adhered to.  
CE  
I/O PORTS  
MUXOUT  
(LOCK DETECT)  
Figure 35. ADuC70xx to ADF4351 Interface  
The microcontroller is set up for SPI master mode with CPHA =  
0. To initiate the operation, the I/O port driving LE is brought  
low. Each latch of the ADF4351 needs a 32-bit word, which is  
accomplished by writing four 8-bit bytes from the micro-  
controller to the device. After the fourth byte is written, the  
LE input should be brought high to complete the transfer.  
PCB DESIGN GUIDELINES FOR A CHIP SCALE  
PACKAGE  
The lands on the chip scale package (CP-32-2) are rectangular.  
The PCB pad for these lands must be 0.1 mm longer than the  
package land length and 0.05 mm wider than the package land  
width. Each land must be centered on the pad to ensure that the  
solder joint size is maximized.  
When power is first applied to the ADF4351, the part requires  
six writes (one each to R5, R4, R3, R2, R1, and R0) for the output  
to become active.  
The bottom of the chip scale package has a central exposed thermal  
pad. The thermal pad on the PCB must be at least as large as the  
exposed pad. On the PCB, there must be a minimum clearance  
of 0.25 mm between the thermal pad and the inner edges of the  
pad pattern to ensure that shorting is avoided.  
I/O port lines on the microcontroller are also used to control  
the power-down input (CE) and to detect lock (MUXOUT  
configured as lock detect and polled by the port input).  
When operating in the mode described, the maximum SPI  
transfer rate of the ADuC70xx is 20 Mbps. This means that  
the maximum rate at which the output frequency can be  
changed is 833 kHz. If using a faster SPI clock, make sure that  
the SPI timing requirements listed in Table 2 are adhered to.  
Thermal vias can be used on the PCB thermal pad to improve  
the thermal performance of the package. If vias are used, they  
must be incorporated into the thermal pad at 1.2 mm pitch grid.  
The via diameter must be between 0.3 mm and 0.33 mm, and  
the via barrel must be plated with 1 oz. of copper to plug the via.  
Rev. 0 | Page 26 of 28  
 
 
 
 
Data Sheet  
ADF4351  
V
VCO  
OUT  
OUTPUT MATCHING  
3.9nF  
For optimum operation, the output of the ADF4351 can be  
matched in a number of ways; the most basic method is to con-  
nect a 50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is  
connected in series, as shown in Figure 37. Because the resistor  
is not frequency dependent, this method provides a good broad-  
band match. When connected to a 50 Ω load, this circuit typically  
gives a differential output power equal to the value selected by  
Bits[DB4:DB3] in Register 4 (R4).  
RF  
1nF  
50Ω  
Figure 38. Optimum Output Stage  
If differential outputs are not needed, the unused output can be  
terminated, or both outputs can be combined using a balun.  
A balun using discrete inductors and capacitors can be imple-  
mented with the architecture shown in Figure 39. The LC balun  
comprises Component L1 and Component C1. L2 provides a dc  
path for RFOUTA−, and Capacitor C2 is used for dc blocking.  
V
VCO  
50Ω  
RF  
OUT  
100pF  
50Ω  
V
VCO  
L2  
L1  
Figure 37. Simple Output Stage  
RF  
RF  
A+  
A–  
OUT  
OUT  
C2  
C1  
L1  
A better solution is to use a shunt inductor (acting as an RF choke)  
to VVCO. This solution gives a better match and, therefore, more  
output power.  
50Ω  
C1  
Experiments have shown that the circuit shown in Figure 38  
provides an excellent match to 50 Ω for the W-CDMA UMTS  
Band 1 (2110 MHz to 2170 MHz). The maximum output power  
in this case is approximately 5 dBm. Both single-ended archi-  
tectures can be examined using the EVAL-ADF4351EB1Z  
evaluation board.  
Figure 39. LC Balun for the ADF4351  
Table 8. LC Balun Components  
Frequency  
Range (MHz)  
RF Choke  
Inductor L2 (nH)  
DC Blocking  
Capacitor C2 (pF)  
Measured Output  
Power (dBm)  
Inductor L1 (nH)  
Capacitor C1 (pF)  
137 to 300  
300 to 460  
400 to 600  
600 to 900  
860 to 1240  
1200 to 1600  
1600 to 3600  
2800 to 3800  
100  
51  
30  
18  
12  
5.6  
3.3  
2.2  
10  
5.6  
5.6  
4
2.2  
1.2  
0.7  
0.5  
390  
180  
120  
68  
39  
15  
1000  
120  
120  
120  
10  
10  
10  
10  
9
10  
10  
10  
9
9
8
10  
10  
8
Rev. 0 | Page 27 of 28  
 
 
 
 
ADF4351  
Data Sheet  
OUTLINE DIMENSIONS  
5.00  
BSC SQ  
0.60 MAX  
0.60 MAX  
PIN 1  
INDICATOR  
25  
32  
1
24  
0.50  
BSC  
PIN 1  
INDICATOR  
4.75  
BSC SQ  
3.25  
3.10 SQ  
2.95  
EXPOSED  
PAD  
17  
8
16  
9
0.50  
0.40  
0.30  
0.25 MIN  
TOP VIEW  
BOTTOM VIEW  
3.50 REF  
0.80 MAX  
0.65 TYP  
12° MAX  
1.00  
0.85  
0.80  
0.05 MAX  
0.02 NOM  
FOR PROPER CONNECTION OF  
THE EXPOSED PAD, REFER TO  
THE PIN CONFIGURATION AND  
FUNCTION DESCRIPTIONS  
COPLANARITY  
0.08  
0.30  
0.25  
0.18  
SEATING  
PLANE  
SECTION OF THIS DATA SHEET.  
0.20 REF  
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2  
Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
5 mm × 5 mm Body, Very Thin Quad  
(CP-32-2)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model1  
Temperature Range  
−40°C to +85°C  
−40°C to +85°C  
Package Description  
Package Option  
ADF4351BCPZ  
ADF4351BCPZ-RL7  
EVAL-ADF4351EB1Z  
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
Evaluation Board  
CP-32-2  
CP-32-2  
1 Z = RoHS Compliant Part.  
©2012 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D09800-0-5/12(0)  
Rev. 0 | Page 28 of 28  
 
 
配单直通车
ADF4351BCPZ-RL7产品参数
型号:ADF4351BCPZ-RL7
Brand Name:Analog Devices Inc
是否无铅: 含铅
是否Rohs认证: 符合
生命周期:Active
零件包装代码:QFN
包装说明:HVQCCN, LCC32,.2SQ,20
针数:32
制造商包装代码:CP-32-7
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:1.24
其他特性:SELECTABLE 8/9 PRESCALER
模拟集成电路 - 其他类型:PHASE LOCKED LOOP
JESD-30 代码:S-XQCC-N32
JESD-609代码:e3
长度:5 mm
湿度敏感等级:3
功能数量:1
端子数量:32
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:UNSPECIFIED
封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20
封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260
电源:3.3 V
认证状态:Not Qualified
座面最大高度:1 mm
子类别:PLL or Frequency Synthesis Circuits
最大供电电流 (Isup):27 mA
最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V
表面贴装:YES
温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)
端子形式:NO LEAD
端子节距:0.5 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:40
宽度:5 mm
Base Number Matches:1
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!