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Low Voltage, 1.15 V to 5.5 V, 8-Channel

Bidirectional Logic Level Translators

ADG3308/ADG3308-1

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

CCY

CCA

Bidirectional logic level translation

Operates from 1.15 V to 5.5 V

Low quiescent current < 1 μA

No direction pin

ADG3308/ADG3308-1/

ADG3308-2

A1

A2

A3

A4

A5

A6

A7

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

APPLICATIONS

Low voltage ASIC level translation

Smart card readers

Cell phones and cell phone cradles

Portable communication devices

Telecommunications equipment

Network switches and routers

Storage systems (SAN/NAS)

Computing/server applications

GPS

A8

Portable POS systems

EN

Low cost serial interfaces

GND

Figure 1.

GENERAL DESCRIPTION

The ADG3308/ADG3308-1/ADG3308-2 are bidirectional level

translators containing eight bidirectional channels. They can be

used in multivoltage digital system applications, such as a data

transfer between a low voltage DSP controller and a higher

voltage device. The internal architecture allows the device to

perform bidirectional level translation without an additional

signal to set the direction in which the translation takes place.

The ADG3308 is available in a compact 20-lead TSSOP and

a 20-lead LFCSP, the ADG3308-1 is available in a 20-ball

WLCSP, and the ADG3308-2 is available in a backside-coated

20-ball WLCSP. The EN pin is referred to the V_CCYsupply

voltage for the ADG3308 and to the V_CCAsupply voltage for the

ADG3308-1 and ADG3308-2.

The ADG3308/ADG3308-1/ADG3308-2 are guaranteed to

operate over the 1.15 V to 5.5 V supply voltage range and the

extended −40°C to +85°C temperature range.

The voltage applied to V_CCAsets the logic levels on the A side

of the device, and V_CCYsets the levels on the Y side. For proper

operation, V_CCAmust always be less than V_CCY. The V_CCA

compatible logic signals applied to the A side of the device

appear as V_CCYcompatible levels on the Y side. Similarly, V_CCY

compatible logic levels applied to the Y side of the device appear

as V_CCAcompatible logic levels on the A side.

PRODUCT HIGHLIGHTS

1. Bidirectional logic level translation.

2. Fully guaranteed over the 1.15 V to 5.5 V supply range.

3. No direction pin.

The enable pin (EN) provides three-state operation on both the

A side and the Y side pins. When the EN pin is pulled low, the

terminals on both sides of the device are in the high impedance

state. For normal operation, EN should be driven high.

4. Packages: 20-lead TSSOP and 20-lead LFCSP (ADG3308),

20-ball WLCSP (ADG3308-1), and backside-coated 20-ball

WLCSP (ADG3308-2).

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

ADG3308/ADG3308-1

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 16

Level Translator Architecture ................................................... 16

Input Driving Requirements..................................................... 16

Output Load Requirements ...................................................... 16

Enable Operation ....................................................................... 16

Power Supplies............................................................................ 16

Data Rate ..................................................................................... 17

Applications..................................................................................... 18

Layout Guidelines....................................................................... 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 20

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Test Circuits ..................................................................................... 12

Terminology .................................................................................... 15

REVISION HISTORY

9/07—Rev. B to Rev. C

Updated Outline Dimensions....................................................... 19

7/07—Rev. A to Rev. B

Added Backside-Coated WLCSP Package ......................Universal

Changes to Input Driving Requirements Section ...................... 16

Updated Outline Dimensions....................................................... 19

Changes to Ordering Guide .......................................................... 20

7/06—Rev. 0 to Rev. A

Added WLCSP Package…………………………..……Universal

Added Figure 4………………………………………………......7

Updated Outline Dimensions……………………………….…19

Changes to Ordering Guide………………………………....…19

1/05—Revision 0: Initial Version

Rev. C | Page 2 of 20

ADG3308/ADG3308-1

SPECIFICATIONS

V_CCY= 1.65 V to 5.5 V, V_CCA= 1.15 V to V_CCY, GND = 0 V. All specifications T_MINto T_MAX, unless otherwise noted. ¹

Table 1.

Parameter

Symbol Conditions

Min

Typ²Max

Unit

LOGIC INPUTS/OUTPUTS

A Side

Input High Voltage³

V_IHA

V_ILA

V_OHA

V_OLA

C_A

V_CCA= 1.15 V

V_CCA= 1.2 V to 5.5 V

V_CCA− 0.3

0.65 × V_CCA

V

pF

μA

Input Low Voltage³

Output High Voltage

Output Low Voltage

Capacitance³

0.35 × V_CCA

V_Y= V_CCY, I_OH= 20 μA, see Figure 29

V_Y= 0 V, I_OL= 20 μA, see Figure 29

f = 1 MHz, EN = 0, see Figure 34

V_CCA− 0.4

0.4

1

10

Leakage Current

I_{LA, HIGH-Z}V_A= 0 V or V_CCA, EN = 0, see Figure 31

Y Side

Input High Voltage³

Input Low Voltage³

Output High Voltage

Output Low Voltage

Capacitance³

Leakage Current

Enable (EN)

Input High Voltage³

V_IHY

V_ILY

V_OHY

V_OLY

C_Y

I_{LY, HIGH-Z}

0.65 × V_CCY

V_CCY− 0.4

V

pF

μA

0.35 × V_CCY

V_A= V_CCA, I_OH= 20 μA, see Figure 30

V_A= 0 V, I_OL= 20 μA, see Figure 30

f = 1 MHz, EN = 0, see Figure 35

V_Y= 0 V or V_CCY, EN = 0, see Figure 32

0.4

1

6.8

V_IHEN

ADG3308 (TSSOP, LFCSP)

ADG3308-1/ADG3308-2 (WLCSP)

0.65 × V_CCY

V_CCA− 0.3

0.65 × V_CCA

V

V_CCA= 1.15 V

V_CCA= 1.2 V to 5.5 V

Input Low Voltage³

ADG3308 (TSSOP, LFCSP)

ADG3308-1/ADG3308-2 (WLCSP)

Leakage Current

V_ILEN

0.35 × V_CCY

0.35 × V_CCA

1

V

μA

pF

μs

I_LEN

C_EN

t_EN

V_EN= 0 V or V_CCY, V_A= 0 V, see Figure 33

Capacitance³

4.5

1

Enable Time³

R_S= R_T= 50 Ω, V_A= 0 V or

V_CCA(A→Y), V_Y= 0 V or V_CCY(Y→A),

see Figure 36

1.8

SWITCHING CHARACTERISTICS³

3.3 V 0.3 V ≤ V_CCA≤ V_CCY, V_CCY= 5 V 0.5 V

A→Y Level Translation

Propagation Delay

R_S= R_T= 50 Ω, C_L= 50 pF, see Figure 37

6

2

10

ns

t_{P, A →Y}

Rise Time

3.5

ns

t_{R, A→Y}

Fall Time

ns

t_{F, A→Y}

Maximum Data Rate

Channel-to-Channel Skew

Part-to-Part Skew

50

Mbps

ns

D_{MAX, A→Y}

t_{SKEW, A→Y}

t_{PPSKEW, A→Y}

2

4

3

ns

R_S= R_T= 50 Ω, C_L= 15 pF, see Figure 38

Y→A Level Translation

Propagation Delay

Rise Time

4

1

3

7

3

7

ns

t_{P, Y →A}

ns

t_{R, Y→A}

Fall Time

ns

t_{F, Y→A}

Maximum Data Rate

Channel-to-Channel Skew

Part-to-Part Skew

50

Mbps

ns

D_{MAX, Y→A}

t_{SKEW, Y→A}

t_{PPSKEW, Y→A}

2

3.5

2

ns

Rev. C | Page 3 of 20

ADG3308/ADG3308-1

Parameter

Symbol Conditions

R_S= R_T= 50 Ω, C_L= 50 pF, see Figure 37

Min

Typ²Max

Unit

1.8 V 0.15 V ≤ V_CCA≤ V_CCY, V_CCY= 3.3 V 0.3 V

A→Y Level Translation

Propagation Delay

Rise Time

8

2

11

5

ns

t_{P, A →Y}

ns

t_{R, A→Y}

Fall Time

5

ns

t_{F, A→Y}

Maximum Data Rate

Channel-to-Channel Skew

Part-to-Part Skew

50

Mbps

ns

D_{MAX, A→Y}

t_{SKEW, A→Y}

t_{PPSKEW, A→Y}

2

4

ns

R_S= R_T= 50 Ω, C_L= 15 pF, see Figure 38

Y→A Level Translation

Propagation Delay

Rise Time

5

2

8

ns

t_{P, Y →A}

3.5

ns

t_{R, Y→A}

Fall Time

ns

t_{F, Y→A}

Maximum Data Rate

Channel-to-Channel Skew

Part-to-Part Skew

50

Mbps

ns

D_{MAX, Y→A}

t_{SKEW, Y→A}

t_{PPSKEW, Y→A}

2

3

ns

1.15 V to 1.3 V ≤ V_CCA≤ V_CCY, V_CCY= 3.3 V 0.3 V

A→Y Level Translation

Propagation Delay

Rise Time

R_S= R_T= 50 Ω, C_L= 50 pF, see Figure 37

9

3

2

18

5

ns

t_{P, A →Y}

ns

t_{R, A→Y}

Fall Time

5

ns

t_{F, A→Y}

Maximum Data Rate

Channel-to-Channel Skew

Part-to-Part Skew

40

Mbps

ns

D_{MAX, A→Y}

t_{SKEW, A→Y}

t_{PPSKEW, A→Y}

2

5

10

ns

R_S= R_T= 50 Ω, C_L= 15 pF, see Figure 38

Y→A Level Translation

Propagation Delay

Rise Time

5

2

9

4

ns

t_{P, Y →A}

ns

t_{R, Y→A}

Fall Time

ns

t_{F, Y→A}

Maximum Data Rate

Channel-to-Channel Skew

Part-to-Part Skew

40

Mbps

ns

D_{MAX, Y→A}

t_{SKEW, Y→A}

t_{PPSKEW, Y→A}

2

4

ns

1.15 V to 1.3 V ≤ V_CCA≤ V_CCY, V_CCY= 1.8 V 0.3 V

A→Y Level Translation

Propagation Delay

Rise Time

R_S= R_T= 50 Ω, C_L= 50 pF, see Figure 37

12

7

25

12

5

ns

t_{P, A →Y}

ns

t_{R, A→Y}

Fall Time

3

ns

t_{F, A→Y}

Maximum Data Rate

Channel-to-Channel Skew

Part-to-Part Skew

25

Mbps

ns

D_{MAX, A→Y}

t_{SKEW, A→Y}

t_{PPSKEW, A→Y}

2

5

15

ns

R_S= R_T= 50 Ω, C_L= 15 pF, see Figure 38

Y→A Level Translation

Propagation Delay

Rise Time

14

5

35

16

6.5

ns

t_{P, Y →A}

ns

t_{R, Y→A}

Fall Time

2.5

ns

t_{F, Y→A}

Maximum Data Rate

Channel-to-Channel Skew

Part-to-Part Skew

25

Mbps

ns

D_{MAX, Y→A}

t_{SKEW, Y→A}

t_{PPSKEW, Y→A}

3

6.5

23.5

ns

Rev. C | Page 4 of 20

ADG3308/ADG3308-1

Parameter

Symbol Conditions

R_S= R_T= 50 Ω, C_L= 50 pF, see Figure 37

Min

Typ²Max

Unit

2.5 V 0.2 V ≤ V_CCA≤ V_CCY, V_CCY= 3.3 V 0.3 V

A→Y Level Translation

Propagation Delay

Rise Time

7

10

4

ns

t_{P, A →Y}

2.5

2

ns

t_{R, A→Y}

Fall Time

5

ns

t_{F, A→Y}

Maximum Data Rate

Channel-to-Channel Skew

Part-to-Part Skew

Y→A Level Translation

Propagation Delay

Rise Time

60

Mbps

ns

D_{MAX, A→Y}

t_{SKEW, A→Y}

t_{PPSKEW, A→Y}

1.5

2

4

ns

R_S= R_T= 50 Ω, C_L= 15 pF, see Figure 38

5

1

3

8

4

5

ns

t_{P, Y →A}

ns

t_{R, Y→A}

Fall Time

ns

t_{F, Y→A}

Maximum Data Rate

Channel-to-Channel Skew

Part-to-Part Skew

60

Mbps

ns

D_{MAX, Y→A}

t_{SKEW, Y→A}

t_{PPSKEW, Y→A}

2

3

ns

POWER REQUIREMENTS

Power Supply Voltages

V_CCA

V_CCY

I_CCA

V_CCA≤ V_CCY

1.15

1.65

5.5

1

V

μA

Quiescent Power Supply Current

V_A= 0 V or V_CCA, V_Y= 0 V or V_CCY

_CCA= V_CCY= 5.5 V, EN = V_CCY

,

0.17

0.27

V

I_CCY

V_A= 0 V or V_CCA, V_Y= 0 V or V_CCY

V_CCA= V_CCY= 5.5 V, EN = V_CCY

1

μA

Three-State Mode Power Supply Current

I_HIGH-ZA

I_HIGH-ZY

V_CCA= V_CCY= 5.5 V, EN = 0

0.1

1

μA

¹Temperature range is −40°C to +85°C (B Version) for the TSSOP, the LFCSP, the WLCSP, and the backside-coated WLCSP.

²All typical values are at T_A= 25°C, unless otherwise noted.

³Guaranteed by design; not subject to production test.

Rev. C | Page 5 of 20

ADG3308/ADG3308-1

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 2.

Parameter

Rating

V_CCAto GND

−0.3 V to +7 V

V_CCYto GND

V_CCAto +7 V

Digital Inputs (A)

Digital Inputs (Y)

EN to GND

−0.3 V to (V_CCA+ 0.3 V)

−0.3 V to (V_CCY+ 0.3 V)

−0.3 V to +7 V

Only one absolute maximum rating may be applied at any

one time.

Operating Temperature Range

Extended Industrial Range (B Version) −40°C to +85°C

Storage Temperature Range

Junction Temperature

−65°C to +150°C

150°C

ESD CAUTION

θ_JAThermal Impedance

20-Lead TSSOP

78°C/W

20-Lead LFCSP

20-Ball WLCSP

30.4°C/W

100°C/W

20-Ball Backside-Coated WLCSP

Lead Temperature, Soldering (10 sec)

IR Reflow, Peak Temperature (<20 sec)

100°C/W

300°C

260°C (+0°C/−5°C)

Rev. C | Page 6 of 20

ADG3308/ADG3308-1

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

BALL a1

INDICATOR

1

2

3

4

a

b

c

d

e

V

Y1

A1

V

CCA

CCY

1

2

20

19

18

17

16

15

14

13

12

11

V

CCY

CCA

A1

Y2

Y4

Y6

Y8

Y3

Y5

A3

A5

A7

EN

A2

A4

A6

A8

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

GND

PIN 1

3

A2

A3

A4

A5

A6

A7

A8

EN

INDICATOR

1

15 Y3

14 Y4

13 Y5

12 Y6

11 Y7

A2

A3 2

A4

A5

A6

4

ADG3308

TOP VIEW

(Not to Scale)

ADG3308

TOP VIEW

(Not to Scale)

3

4

5

6

Y7

7

8

GND

9

THE EXPOSED PAD CAN BE TIED TO

GND OR IT CAN BE LEFT FLOATING.

10

ADG3308-1/

ADG3308-2

TOP VIEW

DO NOT TIE IT TO V

OR V .

CCA

CCY

(Not to Scale)

(BALLS AT THE BOTTOM)

Figure 2. 20-Lead TSSOP

Figure 3. 20-Lead LFCSP

Figure 4. 20-Ball WLCSP

Table 3. Pin Function Descriptions

Pin/Ball No.

TSSOP

LFCSP

WLCSP

Mnemonic

Description

1

19

a4

V_CCA

Power Supply. Power supply voltage input for the A1 I/O pin to the A8 I/O pin

(1.15 V ≤ V_CCA< V_CCY).

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

2

3

4

5

6

7

8

a3

b4

b3

c4

c3

d4

d3

e4

e3

e2

e1

d2

d1

c2

c1

b2

b1

a2

a1

A1

A2

A3

A4

A5

A6

A7

A8

EN

GND

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

V_CCY

Input/Output A1. Referenced to V_CCA

Input/Output A2. Referenced to V_CCA

Input/Output A3. Referenced to V_CCA

Input/Output A4. Referenced to V_CCA

Input/Output A5. Referenced to V_CCA

Input/Output A6. Referenced to V_CCA

Input/Output A7. Referenced to V_CCA

Input/Output A8. Referenced to V_CCA

Active High Enable Input.

.

9

Ground.

10

11

12

13

14

15

16

17

18

Input/Output Y8. Referenced to V_CCY

Input/Output Y7. Referenced to V_CCY

Input/Output Y6. Referenced to V_CCY

Input/Output Y5. Referenced to V_CCY

Input/Output Y4. Referenced to V_CCY

Input/Output Y3. Referenced to V_CCY

Input/Output Y2. Referenced to V_CCY

Input/Output Y1. Referenced to V_CCY

.

Power Supply. Power supply voltage input for the Y1 I/O pin to the Y8 I/O pin

(1.65 V ≤ V_CCY≤ 5.5 V).

Rev. C | Page 7 of 20

ADG3308/ADG3308-1

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

3.0

2.5

2.0

1.5

1.0

0.5

0

T

= 25°C

T

= 25°C

A

1 CHANNEL

C

1 CHANNEL

C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

= 50pF

= 15pF

L

V

= 3.3V, V

CCY

= 5V

CCA

V

= 3.3V, V = 5V

CCY

CCA

V

= 1.8V, V

= 3.3V

CCA

CCY

V

= 1.8V, V

= 3.3V

CCA

CCY

V

= 1.2V, V

= 1.8V

40

V

= 1.2V, V

CCY

= 1.8V

CCA

CCY

CCA

25

DATA RATE (Mbps)

0

5

10

15

20

30

35

40

45

50

0

5

10

15

20

25

30

35

45

50

DATA RATE (Mbps)

Figure 5. I_CCAvs. Data Rate (A→Y Level Translation)

Figure 8. I_CCYvs. Data Rate (Y→A Level Translation)

10

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

T

= 25°C

A

T

= 25°C

A

1 CHANNEL

C

1 CHANNEL

V

9

8

7

6

5

4

3

2

1

0

= 50pF

L

= 1.2V

= 1.8V

CCA

CCY

20Mbps

V

= 3.3V, V

= 5V

CCA

CCY

10Mbps

5Mbps

V

= 1.8V, V

= 3.3V

CCA

CCY

V

= 1.2V, V

= 1.8V

CCA

CCY

1Mbps

53

0

5

10

15

20

25

30

35

40

45

50

13

23

33

43

63

73

DATA RATE (Mbps)

CAPACITIVE LOAD (pF)

Figure 9. I_CCYvs. Capacitive Load at Pin Y

for A→Y (1.2 V→1.8 V) Level Translation

Figure 6. I_CCYvs. Data Rate (A→Y Level Translation)

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

3.0

2.5

2.0

1.5

1.0

0.5

0

T

= 25°C

T

= 25°C

A

1 CHANNEL

C

1 CHANNEL

V

= 15pF

= 1.2V

= 1.8V

L

CCA

CCY

V

= 3.3V, V = 5V

CCY

CCA

20Mbps

10Mbps

V

= 1.8V, V

= 3.3V

CCA

CCY

5Mbps

1Mbps

V

= 1.2V, V

CCY

= 1.8V

CCA

0

5

10

15

20

25

30

35

40

45

50

13

23

33

CAPACITIVE LOAD (pF)

43

53

DATA RATE (Mbps)

Figure 10. I_CCAvs. Capacitive Load at Pin A

for Y→A (1.8 V→1.2 V) Level Translation

Figure 7. I_CCAvs. Data Rate (Y→A Level Translation)

Rev. C | Page 8 of 20

ADG3308/ADG3308-1

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

T

= 25°C

A

T = 25°C

A

1 CHANNEL

V

50Mbps

= 1.8V

= 3.3V

CCA

CCY

V

= 3.3V

= 5V

CCA

CCY

50Mbps

30Mbps

20Mbps

30Mbps

20Mbps

10Mbps

5Mbps

10Mbps

5Mbps

63

13

23

33

43

53

73

13

23

33

43

53

CAPACITIVE LOAD (pF)

Figure 11. I_CCYvs. Capacitive Load at Pin Y

Figure 14. I_CCAvs. Capacitive Load at Pin A

for A→Y (1.8 V→3.3 V) Level Translation

for Y→A (5 V→3.3 V) Level Translation

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

10

T

= 25°C

T = 25°C

A

1 CHANNEL

DATA RATE = 50kbps

A

1 CHANNEL

V

9

8

7

6

5

4

3

2

1

0

= 1.8V

= 3.3V

V

= 1.2V, V = 1.8V

CCY

CCA

CCY

CCA

50Mbps

V

= 1.8V, V

= 3.3V, V

= 3.3V

= 5V

30Mbps

CCA

CCY

20Mbps

10Mbps

V

CCA

CCY

5Mbps

13

23

33

43

53

13

23

33

43

53

63

73

CAPACITIVE LOAD (pF)

Figure 12. I_CCAvs. Capacitive Load at Pin A

for Y→A (3.3 V→1.8 V) Level Translation

Figure 15. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation)

4.0

12

T

= 25°C

T

= 25°C

A

1 CHANNEL

DATA RATE = 50kbps

1 CHANNEL

V

50Mbps

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

= 3.3V

= 5V

CCA

CCY

V

= 1.2V, V

= 1.8V

10

8

CCA

CCY

30Mbps

20Mbps

V

= 1.8V, V

= 3.3V

CCA

CCY

6

4

V

= 3.3V, V

= 5V

CCA

CCY

10Mbps

5Mbps

2

0

13

23

33

43

53

63

73

23

33

43

53

63

73

CAPACITIVE LOAD (pF)

Figure 16. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation)

Figure 13. I_CCYvs. Capacitive Load at Pin Y

for A→Y (3.3 V→5 V) Level Translation

Rev. C | Page 9 of 20

ADG3308/ADG3308-1

10

12

10

8

T

= 25°C

T

= 25°C

A

V

= 1.2V, V

= 1.8V

CCA

CCY

1 CHANNEL

DATA RATE = 50kbps

1 CHANNEL

DATA RATE = 50kbps

9

8

7

6

5

4

3

2

1

0

V

= 1.2V, V

= 1.8V

CCA

CCY

6

V

= 1.8V, V

= 3.3V

CCA

CCY

4

V

= 1.8V, V

= 3.3V

CCA

CCY

2

V

= 3.3V, V

63

= 5V

73

CCA

CCY

V

= 3.3V, V

= 5V

CCA

CCY

0

13

23

33

43

53

13

18

23

28

33

38

43

48

53

CAPACITIVE LOAD (pF)

Figure 20. Propagation Delay (t_PHL) vs. Capacitive Load

Figure 17. Rise Time vs. Capacitive Load at Pin A (Y→A Level Translation)

at Pin Y (A→Y Level Translation)

9

8

7

6

5

4

3

2

1

0

4.0

T

= 25°C

T

= 25°C

A

1 CHANNEL

DATA RATE = 50kbps

1 CHANNEL

DATA RATE = 50kbps

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= 1.2V, V

= 1.8V

CCA

CCY

V

= 1.2V, V

= 1.8V

CCA

CCY

V

= 1.8V, V

= 3.3V

= 5V

CCA

CCY

V

= 1.8V, V

= 3.3V

V

= 3.3V, V

CCA

CCY

CCA

CCY

V

= 3.3V, V

43

= 5V

CCA

CCY

13

18

23

28

33

38

48

53

13

18

23

28

33

38

43

48

53

CAPACITIVE LOAD (pF)

Figure 21. Propagation Delay (t_PLH) vs. Capacitive Load

Figure 18. Fall Time vs. Capacitive Load at Pin A (Y→A Level Translation)

at Pin A (Y→A Level Translation)

9

8

7

6

5

4

3

2

1

0

14

T

= 25°C

A

T

= 25°C

A

1 CHANNEL

DATA RATE = 50kbps

1 CHANNEL

DATA RATE = 50kbps

12

10

8

V

= 1.2V, V

= 1.8V

CCA

CCY

V

= 1.2V, V

= 1.8V

CCA

CCY

6

V

= 1.8V, V

= 3.3V

CCA

CCY

V

= 1.8V, V

= 3.3V

CCA

CCY

4

V

= 3.3V, V

= 5V

CCA

CCY

V

= 3.3V, V

= 5V

CCA

CCY

2

0

13

18

23

28

33

38

43

48

53

13

23

33

43

53

63

73

CAPACITIVE LOAD (pF)

Figure 19. Propagation Delay (t_PLH) vs. Capacitive Load

Figure 22. Propagation Delay (t_PHL) vs. Capacitive Load

at Pin Y (A→Y Level Translation)

at Pin A (Y→A Level Translation)

Rev. C | Page 10 of 20

ADG3308/ADG3308-1

T

= 25°C

A

T

= 25°C

A

DATA RATE = 25Mbps

C

1 CHANNEL

DATA RATE = 50Mbps

C

1 CHANNEL

= 50pF

L

= 15pF

L

400mV/DIV

5ns/DIV

400mV/DIV

3ns/DIV

Figure 23. Eye Diagram at Y Output

Figure 26. Eye Diagram at A Output

(1.2 V→1.8 V Level Translation, 25 Mbps)

(3.3 V→1.8 V Level Translation, 50 Mbps)

T

= 25°C

C

= 50pF

T

= 25°C

A

L

A

DATA RATE = 25Mbps

1 CHANNEL

DATA RATE = 50Mbps

= 50pF

C

L

1 CHANNEL

1V/DIV

200mV/DIV

3ns/DIV

5ns/DIV

Figure 24. Eye Diagram at A Output

Figure 27. Eye Diagram at Y Output

(1.8 V→1.2 V Level Translation, 25 Mbps)

(3.3 V→5 V Level Translation, 50 Mbps)

T

= 25°C

T

= 25°C

C = 50pF

L

A

DATA RATE = 50Mbps

= 15pF

DATA RATE = 50Mbps 1 CHANNEL

C

L

1 CHANNEL

500mV/DIV

3ns/DIV

800mV/DIV

Figure 25. Eye Diagram at Y Output

Figure 28. Eye Diagram at A Output

(1.8 V→3.3 V Level Translation, 50 Mbps)

(5 V→3.3 V Level Translation, 50 Mbps)

Rev. C | Page 11 of 20

ADG3308/ADG3308-1

TEST CIRCUITS

EN

V

ADG3308/

V

CCA

ADG3308-1

ADG3308-2

/

CCY

ADG3308/

V

CCY

CCA

ADG3308-1

/

0.1µF

ADG3308-2

0.1µF

Ax

Yx

K2

Yx

Ax

K1

GND

K

EN

A

GND

I

OH

OL

Figure 29. V_OH/V_OLVoltages at Pin A

Figure 33. EN Pin Leakage Current

EN

ADG3308/

V

CCA

V

CCY

ADG3308-1

/

EN

V

ADG3308/

ADG3308-2

V

CCA

Ax

0.1µF

ADG3308-1

/

0.1µF

CCY

ADG3308-2

K2

x A

Yx

K1

GND

CAPACITANCE

METER

GND

I

OH

I

OL

Figure 30. V_OH/V_OLVoltages at Pin Y

Figure 34. Capacitance at Pin A

EN

ADG3308/

V

CCY

CCA

CCY

ADG3308-1

/

CCA

ADG3308-1

/

ADG3308-2

0.1µF

Ax

Yx

Ax

Yx

A

K

CAPACITANCE

METER

GND

Figure 31. Three-State Leakage Current at Pin A

Figure 35. Capacitance at Pin Y

EN

ADG3308/

V

CCA

Ax

V

CCY

ADG3308-1

/

ADG3308-2

0.1µF

K

Yx

A

GND

Figure 32. Three-State Leakage Current at Pin Y

Rev. C | Page 12 of 20

ADG3308/ADG3308-1

A→Y DIRECTION

V

CCA

ADG3308/

ADG3308-1

ADG3308-2

CCY

/

+

0.1µF

10µF

0.1µF

10µF

1MΩ

V

Ax

x Y

V

A

Y

K1

K2

50pF

1MΩ

SIGNAL SOURCE

EN

GND

Z

= 50Ω

R

S

0

V

EN

50Ω

R

T

50Ω

Y→A DIRECTION

V

CCA

CCY

ADG3308/

ADG3308-1

/

+

0.1µF

10µF

ADG3308-2

0.1µF

10µF

1MΩ

V

Ax

x Y

V

A

Y

K1

1MΩ

K2

15pF

SIGNAL SOURCE

EN

GND

Z

= 50Ω

R

S

0

V

EN

50Ω

R

T

50Ω

V

CCY

t_EN1

V

EN

0V

V

/V

CCA CCY

V

/V

A

Y

A

0V

V

/V

CCY CCA

90%

V /V

Y

0V

V

CCY

t_EN2

V

EN

0V

V

/V

Y

A

V

/V

CCA CCY

0V

V

/V

CCY CCA

V /V

Y

A

10%

0V

NOTES

1. t_ENIS WHICHEVER IS LARGER BETWEEN t_EN1AND t_EN2

IN BOTH A→Y AND Y→A DIRECTIONS.

Figure 36. Enable Time

Rev. C | Page 13 of 20

ADG3308/ADG3308-1

EN

V

ADG3308/

V

+

CCA

CCY

ADG3308-1

/

ADG3308-2

+

SIGNAL

SOURCE

0.1µF

= 50Ω

10µF

0.1µF

10µF

Z

R

S

0

V

x Y

A

x A

Y

R

50Ω

T

50pF

GND

V

A

50%

90%

t_{P, A→Y}

V

Y

50%

10%

t_{F, A→Y}

t_{R, A→Y}

Figure 37. Switching Characteristics (A→Y Level Translation)

EN

ADG3308/

V

CCA

ADG3308-1

/

CCY

ADG3308-2

+

SIGNAL

SOURCE

0.1µF

10µF

0.1µF

x Y

Z

0

= 50Ω

R

S

x A

V

R

A

Y

50Ω

T

15pF

50Ω

GND

V

Y

50%

90%

t_{P, Y→A}

V

A

50%

10%

t_{F, Y→A}

t_{R, Y→A}

Figure 38. Switching Characteristics (Y→A Level Translation)

Rev. C | Page 14 of 20

ADG3308/ADG3308-1

TERMINOLOGY

V_IHA

D_{MAX, A→Y}

Logic input high voltage at Pin A1 to Pin A8.

Guaranteed data rate when translating logic levels in the A→Y

direction under the driving and loading conditions specified in

Table 1.

V_ILA

Logic input low voltage at Pin A1 to Pin A8.

t_{SKEW, A→Y}

V_OHA

Difference between propagation delays on any two channels

when translating logic levels in the A→Y direction.

Logic output high voltage at Pin A1 to Pin A8.

V_OLA

t_{PPSKEW, A→Y}

Logic output low voltage at Pin A1 to Pin A8.

Difference in propagation delay between any one channel and

the same channel on a different part (under same driving/

loading conditions) when translating in the A→Y direction.

C_A

Capacitance measured at Pin A1 to Pin A8 (EN = 0).

I_{LA, HIGH-Z}

t_{P, Y → A}

Leakage current at Pin A1 to Pin A8 when EN = 0 (high

impedance state at Pin A1 to Pin A8).

Propagation delay when translating logic levels in the Y→A

direction.

V_IHY

t_{R, Y→A}

Logic input high voltage at Pin Y1 to Pin Y8.

Rise time when translating logic levels in the Y→A direction.

V_ILY

t_{F, Y→A}

Logic input low voltage at Pin Y1 to Pin Y8.

Fall time when translating logic levels in the Y→A direction.

V_OHY

D_{MAX, Y→A}

Logic output high voltage at Pin Y1 to Pin Y8.

Guaranteed data rate when translating logic levels in the Y→A

direction under the driving and loading conditions specified in

Table 1.

V_OLY

Logic output low voltage at Pin Y1 to Pin Y8.

C_Y

t_{SKEW, Y→A}

Capacitance measured at Pin Y1 to Pin Y8 (EN = 0).

Difference between propagation delays on any two channels

when translating logic levels in the Y→A direction.

I_{LY, HIGH-Z}

Leakage current at Pin Y1 to Pin Y8 when EN = 0 (high

impedance state at Pin Y1 to Pin Y8).

t_{PPSKEW, Y→A}

Difference in propagation delay between any one channel and

the same channel on a different part (under same driving/

loading conditions) when translating in the Y→A direction.

V_IHEN

Logic input high voltage at the EN pin.

V_CCA

V_ILEN

V_CCAsupply voltage.

Logic input low voltage at the EN pin.

V_CCY

C_EN

V_CCYsupply voltage.

Capacitance measured at EN pin.

I_CCA

I_LEN

V_CCAsupply current.

Enable (EN) pin leakage current.

I_CCY

t_EN

V_CCYsupply current.

Three-state enable time for Pin A1 to Pin A8/Pin Y1 to Pin Y8.

I_HIGH-ZA

t_{P, A → Y}

V_CCAsupply current during three-state mode (EN = 0).

Propagation delay when translating logic levels in the A→Y

direction.

I_HIGH-ZY

V_CCYsupply current during three-state mode (EN = 0).

t_{R, A→Y}

Rise time when translating logic levels in the A→Y direction.

t_{F, A→Y}

Fall time when translating logic levels in the A→Y direction.

Rev. C | Page 15 of 20

ADG3308/ADG3308-1

THEORY OF OPERATION

The ADG3308/ADG3308-1/ADG3308-2 level translators allow

the level shifting necessary for data transfer in a system where

multiple supply voltages are used. The device requires two

supplies, V_CCAand V_CCY(V_CCA≤ V_CCY). These supplies set the

logic levels on each side of the device. When driving the A pins,

the device translates the V_CCAcompatible logic levels to V_CCY

compatible logic levels available at the Y pins. Similarly, because

the device is capable of bidirectional translation, when driving

the Y pins the V_CCYcompatible logic levels are translated to the

V_CCAcompatible logic levels available at the A pins. When

EN = 0, the A1 pin to the A8 pin and the Y1 pin to the Y8 pin

are three-stated. When EN is driven high, the ADG3308/

ADG3308-1/ADG3308-2 go into normal operation mode and

perform level translation.

INPUT DRIVING REQUIREMENTS

To ensure correct operation of the ADG3308/ADG3308-1/

ADG3308-2, the circuit that drives the input of the device

should be able to ensure rise/fall times of less than 3 ns when

driving a load consisting of a 6 kΩ resistor in parallel with the

input capacitance of the ADG3308/ADG3308-1/ADG3308-2

channel.

OUTPUT LOAD REQUIREMENTS

The ADG3308/ADG3308-1/ADG3308-2 level translators are

designed to drive CMOS-compatible loads. If current-driving

capability is required, it is recommended to use buffers between

the ADG3308/ADG3308-1/ADG3308-2 outputs and the load.

ENABLE OPERATION

LEVEL TRANSLATOR ARCHITECTURE

The ADG3308/ADG3308-1/ADG3308-2 provide three-state

operation at the A I/O pins and the Y I/O pins by using the

enable (EN) pin, as shown in Table 4.

The ADG3308/ADG3308-1/ADG3308-2 consist of eight

bidirectional channels. Each channel can translate logic levels

in either the A→Y or the Y→A direction. They use a one-shot

accelerator architecture, ensuring excellent switching charac-

teristics. Figure 39 shows a simplified block diagram of a

bidirectional channel.

Table 4. Truth Table

EN

Y I/O Pins

A I/O Pins

0

1

High-Z¹

Normal operation²

V

CCA

CCY

¹High impedance state.

²In normal operation, the ADG3308/ADG3308-1/ADG3308-2 perform level

translation.

T1

T2

6kΩ

When EN = 0, the ADG3308/ADG3308-1/ADG3308-2 enter

into three-state mode. In this mode, the current consumption

from both the V_CCAand V_CCYsupplies is reduced, allowing the

user to save power, which is critical, especially in battery-

operated systems. The EN input pin can only be driven with

U1

U2

P

Y

A

ONE-SHOT GENERATOR

N

V

_CCYcompatible logic levels for the ADG3308, whereas the

ADG3308-1/ADG3308-2 can be driven with either V_CCA- or

_CCYcompatible logic levels.

U4

U3

6kΩ

V

POWER SUPPLIES

T4

T3

For proper operation of the device, the voltage applied to the

V_CCAmust always be less than or equal to the voltage applied

to V_CCY. To meet this condition, the recommended power-up

sequence is V_CCYfirst and then V_CCA. The ADG3308/ADG3308-1/

ADG3308-2 operate properly only after both supply voltages

reach their nominal values. It is not recommended to use the part

in a system where, during power-up, V_CCAmay be greater than

Figure 39. Simplified Block Diagram of an

ADG3308/ADG3308-1/ADG3308-2 Channel

The logic level translation in the A→Y direction is performed

using a level translator (U1) and an inverter (U2), whereas the

translation in the Y→A direction is performed using the U3

inverter and U4 inverter. The one-shot generator detects a rising

or falling edge present on either the A side or the Y side of the

channel. It sends a short pulse that turns on the PMOS transistors

(T1 and T2) for a rising edge, or the NMOS transistors (T3 and

T4) for a falling edge. This charges/discharges the capacitive load

faster, resulting in fast rise and fall times.

V

_CCYdue to a significant increase in the current taken from the

_CCAsupply. For optimum performance, the V_CCAand V_CCYpins

should be decoupled to GND as close as possible to the device.

The inputs of the unused channels (A or Y) should be tied to

their corresponding V_CCrail (V_CCAor V_CCY) or to GND.

Rev. C | Page 16 of 20

ADG3308/ADG3308-1

DATA RATE

The maximum data rate at which the device is guaranteed to

operate is a function of the V_CCAand V_CCYsupply voltage

combination and the load capacitance. It represents the maximum

frequency of a square wave that can be applied to the I/O pins,

ensuring that the device operates within the data sheet

specifications in terms of output voltage (V_OLand V_OH) and

power dissipation (the junction temperature does not exceed the

value specified under the Absolute Maximum Ratings section).

Table 5 shows the guaranteed data rates at which the ADG3308/

ADG3308-1/ADG3308-2 can operate in both directions (A→Y

level translation or Y→A level translation) for various V_CCAand

V_CCYsupply combinations.

Table 5. Guaranteed Data Rates¹

V_CCY

3.3 V (3.0 V to 3.6 V)

40 Mbps

V_CCA

1.8 V (1.65 V to 1.95 V)

2.5 V (2.3 V to 2.7 V)

30 Mbps

45 Mbps

5 V (4.5 V to 5.5 V)

40 Mbps

50 Mbps

1.2 V (1.15 V to 1.3 V)

1.8 V (1.65 V to 1.95 V)

2.5 V (2.3 V to 2.7 V)

3.3 V (3.0 V to 3.6 V)

5 V (4.5 V to 5.5 V)

25 Mbps

50 Mbps

60 Mbps

¹The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction.

Rev. C | Page 17 of 20

ADG3308/ADG3308-1

APPLICATIONS

The ADG3308/ADG3308-1/ADG3308-2 are designed for digital

circuits that operate at different supply voltages; therefore, logic

level translation is required. The lower voltage logic signals are

connected to the A pins, and the higher voltage logic signals to

the Y pins. The ADG3308/ADG3308-1/ADG3308-2 can provide

level translation in both directions (A→Y or Y→A) on all eight

channels, eliminating the need for a level translator IC for each

direction. The internal architecture allows the ADG3308/

ADG3308-1/ADG3308-2 to perform bidirectional level

translation without an additional signal to set the direction in

which the translation is made. It also allows simultaneous data

flow in both directions on the same part, for example, when two

channels translate in the A→Y direction while the other two

translate in the Y→A direction. This simplifies the design by

eliminating the timing requirements for the direction signal

and reduces the number of ICs used for level translation.

100nF

ADG3308/

ADG3308-1

ADG3308-2

/

V

CCY

CCA

A1

A2

A3

A4

A5

A6

A7

A8

3.3V

1.8V

I/O 1

I/O

1

2

3

Y1

L

H

I/O 2

L

Y2

Y3

I/O 3

L

I/O 4

L

I/O

CS

4

5

6

7

8

Y4

Y5

Y6

Y7

Y8

EN

H

I/O 5

L

I/O 6

L

I/O 7

L

I/O 8

L

GND

100nF

Figure 40 shows an application where a 3.3 V microprocessor

can read or write data to and from a 1.8 V peripheral device

using an 8-bit bus.

ADG3308/

ADG3308-1

ADG3308-2

/

V

CCY

CCA

A1

1.8V

I/O 1

L

Y1

100nF

V

I/O 2

L

Y2

Y3

A2

A3

A4

A5

A6

A7

A8

V

I/O 3

L

CCY

CCA

3.3V

1.8V

I/O 4

L

Y4

Y5

Y6

Y7

Y8

EN

I/O 1

L

Y1

A1

I/O

1

H

I/O 5

L

ADG3308/

ADG3308-1

/

I/O 6

L

ADG3308-2

I/O 7

L

I/O 2

L

Y2

Y3

A2

I/O

2

3

H

I/O 8

L

GND

A3

I/O 3

L

H

Figure 41. 1.8 V to 3.3 V Level Translation Circuit

Using the Three-State Feature

Y4

Y5

A4

A5

I/O 4

L

I/O

4

5

H

I/O 5

L

I/O

H

LAYOUT GUIDELINES

As with any high speed digital IC, the printed circuit board

layout is important in the overall performance of the circuit. Care

should be taken to ensure proper power supply bypass and

return paths for the high speed signals. Each V_CCpin (V_CCAand

I/O 6

L

Y6

A6

A7

6

7

8

H

I/O 7

L

Y7

Y8

EN

A8

I/O 8

L

V

_CCY) should be bypassed using low effective series resistance

(ESR) and effective series inductance (ESI) capacitors placed as

close as possible to the V_CCAand V_CCYpins. The parasitic induc-

tance of the high speed signal track can cause significant overshoot.

This effect can be reduced by keeping the length of the tracks as

short as possible. A solid copper plane for the return path

(GND) is also recommended.

GND

Figure 40. 1.8 V to 3.3 V 8-Bit Level Translation Circuit

When the application requires level translation between

a microprocessor and multiple peripheral devices, the

ADG3308/ADG3308-1/ADG3308-2 I/O pins can be three-

stated by setting EN = 0. This feature allows the ADG3308/

ADG3308-1/ADG3308-2 to share the data buses with other

devices without causing contention issues. Figure 41 shows an

application where a 3.3 V microprocessor is connected to 1.8 V

peripheral devices using the three-state feature.

Rev. C | Page 18 of 20

ADG3308/ADG3308-1

OUTLINE DIMENSIONS

6.60

6.50

6.40

20

11

10

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

COPLANARITY

0.10

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AC

Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

0.60 MAX

4.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

15

16

20

1

5

0.50

BSC

PIN 1

INDICATOR

2.25

2.10 SQ

1.95

3.75

BCS SQ

EXPOSED

PAD

(BOTTOM VIEW)

10

6

11

0.75

0.60

0.50

TOP VIEW

0.25 MIN

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.20 REF

0.30

0.23

0.18

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

Figure 43. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-20-1)

Dimensions shown in millimeters

Rev. C | Page 19 of 20

ADG3308/ADG3308-1

2.06

2.00

1.94

0.65

0.59

0.53

4

3

2

1

A

B

C

D

E

A1 BALL

IDENTIFIER

2.56

2.50

2.44

0.50 BSC

PITCH

0.36

0.32

0.28

0.24

0.20

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

Figure 44. 20-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-20-2)

Dimensions shown in millimeters

0.645

0.585

2.06

2.00

1.94

0.525

0.042

0.040

0.037

4

3

2

1

A

B

C

D

E

A1 BALL

IDENTIFIER

2.56

2.50

2.44

0.50 BSC

PITCH

0.36

0.32

0.28

0.24

0.20

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

Figure 45. Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-20-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

RU-20

ADG3308BRUZ¹

−40°C to +85°C

20-Lead Thin Shrink Small Outline Package [TSSOP]

20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

20-Ball Wafer Level Chip Scale Package [WLCSP]

ADG3308BRUZ-REEL¹

ADG3308BRUZ-REEL7¹

ADG3308BCPZ-REEL¹

ADG3308BCPZ-REEL7¹

ADG3308BCBZ-1-RL7¹

ADG3308BCBZ-1-REEL¹

ADG3308BCBZ-2-RL7¹

ADG3308BCBZ-2-REEL¹

RU-20

CP-20-1

CB-20-2

CB-20-3

Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP]

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D04865-0-9/07(C)

Rev. C | Page 20 of 20

型号:	ADG3308BRUZ
Brand Name：	Analog Devices Inc
是否无铅：	含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	ANALOG DEVICES INC
零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP20,.25
针数：	20
制造商包装代码：	RU-20
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	0.68
接口集成电路类型：	INTERFACE CIRCUIT
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e3
长度：	6.5 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP20,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	1.2/5,1.8/5 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Other Interface ICs
最大供电电压：	5.5 V
最小供电电压：	1.15 V
标称供电电压：	1.8 V
电源电压1-最大：	5.5 V
电源电压1-分钟：	1.65 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	4.4 mm
Base Number Matches：	1

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