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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • ADG3308BRUZ
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  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • ADG3308BRUZ图
  • 集好芯城

     该会员已使用本站13年以上
  • ADG3308BRUZ 现货库存
  • 数量14850 
  • 厂家ADI(亚德诺) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
  • QQ:3008092965QQ:3008092965 复制
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  • 0755-83239307 QQ:3008092965QQ:3008092965
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  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • ADG3308BRUZ 现货库存
  • 数量8800 
  • 厂家ADI 
  • 封装11856 
  • 批号最新批号 
  • 原装现货零成本有接受价格就出
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    QQ:408391813QQ:408391813 复制
  • 0755-84876394 QQ:3533288158QQ:408391813
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  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • ADG3308BRUZ 现货库存
  • 数量6851 
  • 厂家ADI 
  • 封装20TSSOP 
  • 批号24+ 
  • 全新原装现货,可开增值税发票,欢迎询购!
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    QQ:221698708QQ:221698708 复制
  • 0755-83222787 QQ:1950791264QQ:221698708
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  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • ADG3308BRUZ 现货库存
  • 数量9000 
  • 厂家 
  • 封装查无型号 
  • 批号24+ 
  • 原装假一赔百,深圳现货,北美、新加坡可发货
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  • 755-83950019 QQ:800888908
  • ADG3308BRUZ图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • ADG3308BRUZ 现货库存
  • 数量8000 
  • 厂家ADI(亚德诺) 
  • 封装NA 
  • 批号22+ 
  • 宗天技术 原装现货/假一赔十
  • QQ:444961496QQ:444961496 复制
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  • 0755-88601327 QQ:444961496QQ:2824256784
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • ADG3308BRUZ 现货库存
  • 数量26980 
  • 厂家ADI 
  • 封装SOP 
  • 批号21+ 
  • 新到现货、一手货源、当天发货、bom配单
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  • 0755-84507451 QQ:1435424310
  • ADG3308BRUZ图
  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • ADG3308BRUZ 现货库存
  • 数量500 
  • 厂家ADI/亚德诺 
  • 封装 
  • 批号20+ 
  • 绝对全新原装现货,欢迎来电查询
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  • 0755-83229772 QQ:215672808
  • ADG3308BRUZ图
  • 深圳市华兴微电子有限公司

     该会员已使用本站16年以上
  • ADG3308BRUZ 现货库存
  • 数量5188 
  • 厂家ADI 
  • 封装N/A 
  • 批号23+ 
  • 优势订货,实单专线请联系后面QQ或电话
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  • 0755-83002105 QQ:604502381
  • ADG3308BRUZ-REEL7图
  • 深圳市科庆电子有限公司

     该会员已使用本站16年以上
  • ADG3308BRUZ-REEL7 现货库存
  • 数量1000 
  • 厂家ADI 
  • 封装SOP 
  • 批号23+ 
  • 现货只售原厂原装可含13%税
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  • 0755 QQ:2850188252QQ:2850188256
  • ADG3308BRUZ-REEL7图
  • 深圳市广百利电子有限公司

     该会员已使用本站6年以上
  • ADG3308BRUZ-REEL7 现货库存
  • 数量18500 
  • 厂家ADI(亚德诺) 
  • 封装TSSOP-20 
  • 批号23+ 
  • ★★全网低价,原装原包★★
  • QQ:1483430049QQ:1483430049 复制
  • 0755-83235525 QQ:1483430049
  • ADG3308BRUZ图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • ADG3308BRUZ 现货库存
  • 数量98500 
  • 厂家ADI/亚德诺 
  • 封装TSSOP20 
  • 批号23+ 
  • 真实库存全新原装正品!专业配单
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  • 0755-13418564337 QQ:308365177
  • ADG3308BRUZ图
  • 深圳市宏诺德电子科技有限公司

     该会员已使用本站8年以上
  • ADG3308BRUZ 现货热卖
  • 数量9800 
  • 厂家ADI 
  • 封装TSSOP20 
  • 批号22+ 
  • 全新进口原厂原装,优势现货库存,有需要联系电话:15817309912 QQ:783839662
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  • 0755- QQ:84556259QQ:783839662
  • ADG3308BRUZ-REEL7图
  • 深圳市华兴微电子有限公司

     该会员已使用本站16年以上
  • ADG3308BRUZ-REEL7 热卖库存
  • 数量1000 
  • 厂家ADI 
  • 封装N/A 
  • 批号2150+ 
  • 公司现货,实单专线请联系后面QQ或电话
  • QQ:604502381QQ:604502381 复制
  • 0755-83002105 QQ:604502381
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  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • ADG3308BRUZ
  • 数量7600 
  • 厂家ADI/亚德诺 
  • 封装TSSOP20 
  • 批号21+ 
  • 全新原装正品,库存现货实报
  • QQ:1300774727QQ:1300774727 复制
  • 13714410484 QQ:1300774727
  • ADG3308BRUZ图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • ADG3308BRUZ
  • 数量35898 
  • 厂家AnalogDevicesInc 
  • 封装20-TSSOP 
  • 批号21+ 
  • ■原装现货长期供应电子元器件代理经销WWW.ZN-IC.COM
  • QQ:2881664480QQ:2881664480 复制
  • 0755-83532193 QQ:2881664480
  • ADG3308BRUZ图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • ADG3308BRUZ
  • 数量3000 
  • 厂家AD 
  • 封装SZSTOCK 
  • 批号23+ 
  • 全新原装正品现货
  • QQ:1245773710QQ:1245773710 复制
    QQ:867789136QQ:867789136 复制
  • 0755-82772189 QQ:1245773710QQ:867789136
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  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • ADG3308BRUZ
  • 数量8500 
  • 厂家原厂品牌 
  • 封装原厂封装 
  • 批号新年份 
  • 羿芯诚只做原装长期供,支持实单
  • QQ:2880123150QQ:2880123150 复制
  • 0755-82570600 QQ:2880123150
  • ADG3308BRUZ图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • ADG3308BRUZ
  • 数量5600 
  • 厂家ADI/亚德诺 
  • 封装TSSOP20 
  • 批号23+ 
  • 100%深圳原装现货库存
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • ADG3308BRUZ
  • 数量3450 
  • 厂家ADI/亚德诺 
  • 封装NA/ 
  • 批号23+ 
  • 原装现货,当天可交货,原型号开票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • ADG3308BRUZ图
  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • ADG3308BRUZ
  • 数量15000 
  • 厂家ADI 
  • 封装SSOP 
  • 批号2018+ 
  • ADI一级代理商专营进口原装现货假一赔十
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • ADG3308BRUZ图
  • 集好芯城

     该会员已使用本站13年以上
  • ADG3308BRUZ
  • 数量17449 
  • 厂家ADI/亚德诺 
  • 封装TSSOP-20 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • ADG3308BRUZ图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • ADG3308BRUZ
  • 数量15862 
  • 厂家AD 
  • 封装TSSOP 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • ADG3308BRUZ图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • ADG3308BRUZ
  • 数量15862 
  • 厂家AD 
  • 封装TSSOP 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • ADG3308BRUZ图
  • 深圳市雅维特电子有限公司

     该会员已使用本站15年以上
  • ADG3308BRUZ
  • 数量5000 
  • 厂家AD 
  • 封装深圳原装现货0755-83975781 
  • 批号原厂原装 
  • QQ:767621813QQ:767621813 复制
    QQ:1152937841QQ:1152937841 复制
  • 0755-83975781 QQ:767621813QQ:1152937841
  • ADG3308BRUZ图
  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
  • ADG3308BRUZ
  • 数量2015 
  • 厂家ADI 
  • 封装SOP/DIP 
  • 批号21998 
  • ★一级代理AD原装现货,特价热卖!★
  • QQ:2752732883QQ:2752732883 复制
    QQ:240616963QQ:240616963 复制
  • 0755-25165869 QQ:2752732883QQ:240616963
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • ADG3308BRUZ
  • 数量30000 
  • 厂家ADI/亚德诺 
  • 封装SSOP 
  • 批号23+ 
  • 只做原装现货假一罚十
  • QQ:2103443489QQ:2103443489 复制
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  • 0755-82702619 QQ:2103443489QQ:2924695115
  • ADG3308BRUZ-REEL7图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • ADG3308BRUZ-REEL7
  • 数量12048 
  • 厂家ADI(亚德诺) 
  • 封装TSSOP20 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • ADG3308BRUZ-REEL7图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • ADG3308BRUZ-REEL7
  • 数量30000 
  • 厂家ADI 
  • 封装TSSOP 
  • 批号23+ 
  • 代理全新原装现货,价格优势
  • QQ:1774550803QQ:1774550803 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82777855 QQ:1774550803QQ:2924695115
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  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • ADG3308BRUZ
  • 数量98622 
  • 厂家ADI/亚德诺 
  • 封装TSSOP-20 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
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  • ADG3308BRUZ-REEL图
  • 首天国际(深圳)集团有限公司

     该会员已使用本站17年以上
  • ADG3308BRUZ-REEL
  • 数量10000 
  • 厂家ADI 
  • 封装原厂封装 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 0755-82807088 QQ:528164397QQ:1318502189
  • ADG3308BRUZ图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • ADG3308BRUZ
  • 数量26700 
  • 厂家ADI(亚德诺) 
  • 封装▊原厂封装▊ 
  • 批号▊ROHS环保▊ 
  • 十年以上分销商原装进口件服务型企业0755-83790645
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • ADG3308BRUZ
  • 数量24316 
  • 厂家ADI 
  • 封装TSSOP 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
  • QQ:364510898QQ:364510898 复制
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  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • ADG3308BRUZ
  • 数量12500 
  • 厂家ADI/亚德诺 
  • 封装TSSOP-20 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • ADG3308BRUZ图
  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • ADG3308BRUZ
  • 数量8800 
  • 厂家ADI/亚德诺 
  • 封装TSSOP20 
  • 批号最新批号 
  • 原装现货零成本有接受价格就出
  • QQ:3533288158QQ:3533288158 复制
    QQ:408391813QQ:408391813 复制
  • 0755-84876394 QQ:3533288158QQ:408391813
  • ADG3308BRUZ-REEL7图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • ADG3308BRUZ-REEL7
  • 数量82000 
  • 厂家ADI实单优价 
  • 封装TSSOP20 
  • 批号2023+ 
  • 原装原包现货支持实单
  • QQ:2885134554QQ:2885134554 复制
    QQ:2885134398QQ:2885134398 复制
  • 0755-22669259 QQ:2885134554QQ:2885134398
  • ADG3308BRUZ图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • ADG3308BRUZ
  • 数量12300 
  • 厂家ADI/亚德诺 
  • 封装TSSOP 
  • 批号24+ 
  • ★原装真实库存★13点税!
  • QQ:2353549508QQ:2353549508 复制
    QQ:2885134615QQ:2885134615 复制
  • 0755-83201583 QQ:2353549508QQ:2885134615
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • ADG3308BRUZ
  • 数量3817 
  • 厂家ADI 
  • 封装20TSSOP 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
    QQ:2881894393QQ:2881894393 复制
  • 0755-82556029 QQ:2881894392QQ:2881894393
  • ADG3308BRUZ图
  • 深圳市欧立现代科技有限公司

     该会员已使用本站12年以上
  • ADG3308BRUZ
  • 数量5000 
  • 厂家ADI 
  • 封装TSSOP 
  • 批号24+ 
  • ★★专业IC现货,诚信经营,市场最优价★★
  • QQ:1950791264QQ:1950791264 复制
    QQ:2216987084QQ:2216987084 复制
  • 0755-83222787 QQ:1950791264QQ:2216987084

产品型号ADG3308BRUZ的概述

ADG3308BRUZ 芯片概述 ADG3308BRUZ是Analog Devices公司推出的一款高性能、双向电压翻转开关。此芯片采用CMOS工艺制造,具有低功耗、高速和宽工作电压范围的特性,广泛应用于数据通信用途,尤其是在数字信号处理(DSP)、微控制器(MCU)和其他低电压应用中。ADG3308BRUZ具备八个开关通道,能够有效地在不同逻辑电平之间进行转换,确保信号的完整性和稳定性。 功能与特点 ADG3308BRUZ具有极低的导通电阻和快速的开关速度,适用于多种场合,具有如下主要特点: 1. 低导通电阻:在给定的工作条件下,ADG3308BRUZ的导通电阻非常低,从而保证了信号不会因开关的因而导致显著失真。 2. 宽输入电压范围:该芯片支持逻辑电平的翻转,如从1.8V到5V的转换,使得ADG3308BRUZ非常适合不同电压域之间的应用。 3. 双向传输能力:ADG3308BRU...

产品型号ADG3308BRUZ的Datasheet PDF文件预览

Low Voltage, 1.15 V to 5.5 V, 8-Channel  
Bidirectional Logic Level Translators  
ADG3308/ADG3308-1  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
V
V
CCY  
CCA  
Bidirectional logic level translation  
Operates from 1.15 V to 5.5 V  
Low quiescent current < 1 μA  
No direction pin  
ADG3308/ADG3308-1/  
ADG3308-2  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
APPLICATIONS  
Low voltage ASIC level translation  
Smart card readers  
Cell phones and cell phone cradles  
Portable communication devices  
Telecommunications equipment  
Network switches and routers  
Storage systems (SAN/NAS)  
Computing/server applications  
GPS  
A8  
Portable POS systems  
EN  
Low cost serial interfaces  
GND  
Figure 1.  
GENERAL DESCRIPTION  
The ADG3308/ADG3308-1/ADG3308-2 are bidirectional level  
translators containing eight bidirectional channels. They can be  
used in multivoltage digital system applications, such as a data  
transfer between a low voltage DSP controller and a higher  
voltage device. The internal architecture allows the device to  
perform bidirectional level translation without an additional  
signal to set the direction in which the translation takes place.  
The ADG3308 is available in a compact 20-lead TSSOP and  
a 20-lead LFCSP, the ADG3308-1 is available in a 20-ball  
WLCSP, and the ADG3308-2 is available in a backside-coated  
20-ball WLCSP. The EN pin is referred to the VCCY supply  
voltage for the ADG3308 and to the VCCA supply voltage for the  
ADG3308-1 and ADG3308-2.  
The ADG3308/ADG3308-1/ADG3308-2 are guaranteed to  
operate over the 1.15 V to 5.5 V supply voltage range and the  
extended −40°C to +85°C temperature range.  
The voltage applied to VCCA sets the logic levels on the A side  
of the device, and VCCY sets the levels on the Y side. For proper  
operation, VCCA must always be less than VCCY. The VCCA  
compatible logic signals applied to the A side of the device  
appear as VCCY compatible levels on the Y side. Similarly, VCCY  
compatible logic levels applied to the Y side of the device appear  
as VCCA compatible logic levels on the A side.  
PRODUCT HIGHLIGHTS  
1. Bidirectional logic level translation.  
2. Fully guaranteed over the 1.15 V to 5.5 V supply range.  
3. No direction pin.  
The enable pin (EN) provides three-state operation on both the  
A side and the Y side pins. When the EN pin is pulled low, the  
terminals on both sides of the device are in the high impedance  
state. For normal operation, EN should be driven high.  
4. Packages: 20-lead TSSOP and 20-lead LFCSP (ADG3308),  
20-ball WLCSP (ADG3308-1), and backside-coated 20-ball  
WLCSP (ADG3308-2).  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.  
 
ADG3308/ADG3308-1  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Theory of Operation ...................................................................... 16  
Level Translator Architecture ................................................... 16  
Input Driving Requirements..................................................... 16  
Output Load Requirements ...................................................... 16  
Enable Operation ....................................................................... 16  
Power Supplies............................................................................ 16  
Data Rate ..................................................................................... 17  
Applications..................................................................................... 18  
Layout Guidelines....................................................................... 18  
Outline Dimensions....................................................................... 19  
Ordering Guide .......................................................................... 20  
Applications....................................................................................... 1  
Functional Block Diagram .............................................................. 1  
General Description......................................................................... 1  
Product Highlights ........................................................................... 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Absolute Maximum Ratings............................................................ 6  
ESD Caution.................................................................................. 6  
Pin Configurations and Function Descriptions ........................... 7  
Typical Performance Characteristics ............................................. 8  
Test Circuits ..................................................................................... 12  
Terminology .................................................................................... 15  
REVISION HISTORY  
9/07—Rev. B to Rev. C  
Updated Outline Dimensions....................................................... 19  
7/07—Rev. A to Rev. B  
Added Backside-Coated WLCSP Package ......................Universal  
Changes to Input Driving Requirements Section ...................... 16  
Updated Outline Dimensions....................................................... 19  
Changes to Ordering Guide .......................................................... 20  
7/06—Rev. 0 to Rev. A  
Added WLCSP Package…………………………..……Universal  
Added Figure 4………………………………………………......7  
Updated Outline Dimensions……………………………….…19  
Changes to Ordering Guide………………………………....…19  
1/05—Revision 0: Initial Version  
Rev. C | Page 2 of 20  
 
ADG3308/ADG3308-1  
SPECIFICATIONS  
VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. 1  
Table 1.  
Parameter  
Symbol Conditions  
Min  
Typ2 Max  
Unit  
LOGIC INPUTS/OUTPUTS  
A Side  
Input High Voltage3  
VIHA  
VIHA  
VILA  
VOHA  
VOLA  
CA  
VCCA = 1.15 V  
VCCA = 1.2 V to 5.5 V  
VCCA − 0.3  
0.65 × VCCA  
V
V
V
V
V
pF  
μA  
Input Low Voltage3  
Output High Voltage  
Output Low Voltage  
Capacitance3  
0.35 × VCCA  
VY = VCCY, IOH = 20 μA, see Figure 29  
VY = 0 V, IOL = 20 μA, see Figure 29  
f = 1 MHz, EN = 0, see Figure 34  
VCCA − 0.4  
0.4  
1
10  
Leakage Current  
ILA, HIGH-Z VA = 0 V or VCCA, EN = 0, see Figure 31  
Y Side  
Input High Voltage3  
Input Low Voltage3  
Output High Voltage  
Output Low Voltage  
Capacitance3  
Leakage Current  
Enable (EN)  
Input High Voltage3  
VIHY  
VILY  
VOHY  
VOLY  
CY  
ILY, HIGH-Z  
0.65 × VCCY  
VCCY − 0.4  
V
V
V
V
pF  
μA  
0.35 × VCCY  
VA = VCCA, IOH = 20 μA, see Figure 30  
VA = 0 V, IOL = 20 μA, see Figure 30  
f = 1 MHz, EN = 0, see Figure 35  
VY = 0 V or VCCY, EN = 0, see Figure 32  
0.4  
1
6.8  
VIHEN  
ADG3308 (TSSOP, LFCSP)  
ADG3308-1/ADG3308-2 (WLCSP)  
0.65 × VCCY  
VCCA − 0.3  
0.65 × VCCA  
V
V
V
VCCA = 1.15 V  
VCCA = 1.2 V to 5.5 V  
Input Low Voltage3  
ADG3308 (TSSOP, LFCSP)  
ADG3308-1/ADG3308-2 (WLCSP)  
Leakage Current  
VILEN  
0.35 × VCCY  
0.35 × VCCA  
1
V
V
μA  
pF  
μs  
ILEN  
CEN  
tEN  
VEN = 0 V or VCCY, VA = 0 V, see Figure 33  
Capacitance3  
4.5  
1
Enable Time3  
RS = RT = 50 Ω, VA = 0 V or  
VCCA (AY), VY = 0 V or VCCY (YA),  
see Figure 36  
1.8  
SWITCHING CHARACTERISTICS3  
3.3 V 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V 0.5 V  
AY Level Translation  
Propagation Delay  
RS = RT = 50 Ω, CL = 50 pF, see Figure 37  
6
2
2
10  
ns  
tP, A Y  
Rise Time  
3.5  
3.5  
ns  
tR, AY  
Fall Time  
ns  
tF, AY  
Maximum Data Rate  
Channel-to-Channel Skew  
Part-to-Part Skew  
50  
Mbps  
ns  
DMAX, AY  
tSKEW, AY  
tPPSKEW, AY  
2
4
3
ns  
RS = RT = 50 Ω, CL = 15 pF, see Figure 38  
YA Level Translation  
Propagation Delay  
Rise Time  
4
1
3
7
3
7
ns  
tP, Y A  
ns  
tR, YA  
Fall Time  
ns  
tF, YA  
Maximum Data Rate  
Channel-to-Channel Skew  
Part-to-Part Skew  
50  
Mbps  
ns  
DMAX, YA  
tSKEW, YA  
tPPSKEW, YA  
2
3.5  
2
ns  
Rev. C | Page 3 of 20  
 
 
ADG3308/ADG3308-1  
Parameter  
Symbol Conditions  
RS = RT = 50 Ω, CL = 50 pF, see Figure 37  
Min  
Typ2 Max  
Unit  
1.8 V 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V  
AY Level Translation  
Propagation Delay  
Rise Time  
8
2
2
11  
5
ns  
tP, A Y  
ns  
tR, AY  
Fall Time  
5
ns  
tF, AY  
Maximum Data Rate  
Channel-to-Channel Skew  
Part-to-Part Skew  
50  
Mbps  
ns  
DMAX, AY  
tSKEW, AY  
tPPSKEW, AY  
2
4
4
ns  
RS = RT = 50 Ω, CL = 15 pF, see Figure 38  
YA Level Translation  
Propagation Delay  
Rise Time  
5
2
2
8
ns  
tP, Y A  
3.5  
3.5  
ns  
tR, YA  
Fall Time  
ns  
tF, YA  
Maximum Data Rate  
Channel-to-Channel Skew  
Part-to-Part Skew  
50  
Mbps  
ns  
DMAX, YA  
tSKEW, YA  
tPPSKEW, YA  
2
3
3
ns  
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V  
AY Level Translation  
Propagation Delay  
Rise Time  
RS = RT = 50 Ω, CL = 50 pF, see Figure 37  
9
3
2
18  
5
ns  
tP, A Y  
ns  
tR, AY  
Fall Time  
5
ns  
tF, AY  
Maximum Data Rate  
Channel-to-Channel Skew  
Part-to-Part Skew  
40  
Mbps  
ns  
DMAX, AY  
tSKEW, AY  
tPPSKEW, AY  
2
5
10  
ns  
RS = RT = 50 Ω, CL = 15 pF, see Figure 38  
YA Level Translation  
Propagation Delay  
Rise Time  
5
2
2
9
4
4
ns  
tP, Y A  
ns  
tR, YA  
Fall Time  
ns  
tF, YA  
Maximum Data Rate  
Channel-to-Channel Skew  
Part-to-Part Skew  
40  
Mbps  
ns  
DMAX, YA  
tSKEW, YA  
tPPSKEW, YA  
2
4
4
ns  
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V 0.3 V  
AY Level Translation  
Propagation Delay  
Rise Time  
RS = RT = 50 Ω, CL = 50 pF, see Figure 37  
12  
7
25  
12  
5
ns  
tP, A Y  
ns  
tR, AY  
Fall Time  
3
ns  
tF, AY  
Maximum Data Rate  
Channel-to-Channel Skew  
Part-to-Part Skew  
25  
Mbps  
ns  
DMAX, AY  
tSKEW, AY  
tPPSKEW, AY  
2
5
15  
ns  
RS = RT = 50 Ω, CL = 15 pF, see Figure 38  
YA Level Translation  
Propagation Delay  
Rise Time  
14  
5
35  
16  
6.5  
ns  
tP, Y A  
ns  
tR, YA  
Fall Time  
2.5  
ns  
tF, YA  
Maximum Data Rate  
Channel-to-Channel Skew  
Part-to-Part Skew  
25  
Mbps  
ns  
DMAX, YA  
tSKEW, YA  
tPPSKEW, YA  
3
6.5  
23.5  
ns  
Rev. C | Page 4 of 20  
ADG3308/ADG3308-1  
Parameter  
Symbol Conditions  
RS = RT = 50 Ω, CL = 50 pF, see Figure 37  
Min  
Typ2 Max  
Unit  
2.5 V 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V  
AY Level Translation  
Propagation Delay  
Rise Time  
7
10  
4
ns  
tP, A Y  
2.5  
2
ns  
tR, AY  
Fall Time  
5
ns  
tF, AY  
Maximum Data Rate  
Channel-to-Channel Skew  
Part-to-Part Skew  
YA Level Translation  
Propagation Delay  
Rise Time  
60  
Mbps  
ns  
DMAX, AY  
tSKEW, AY  
tPPSKEW, AY  
1.5  
2
4
ns  
RS = RT = 50 Ω, CL = 15 pF, see Figure 38  
5
1
3
8
4
5
ns  
tP, Y A  
ns  
tR, YA  
Fall Time  
ns  
tF, YA  
Maximum Data Rate  
Channel-to-Channel Skew  
Part-to-Part Skew  
60  
Mbps  
ns  
DMAX, YA  
tSKEW, YA  
tPPSKEW, YA  
2
3
3
ns  
POWER REQUIREMENTS  
Power Supply Voltages  
VCCA  
VCCY  
ICCA  
VCCA ≤ VCCY  
1.15  
1.65  
5.5  
5.5  
1
V
V
μA  
Quiescent Power Supply Current  
VA = 0 V or VCCA, VY = 0 V or VCCY  
CCA = VCCY = 5.5 V, EN = VCCY  
,
,
0.17  
0.27  
V
ICCY  
VA = 0 V or VCCA, VY = 0 V or VCCY  
VCCA = VCCY = 5.5 V, EN = VCCY  
1
μA  
Three-State Mode Power Supply Current  
IHIGH-ZA  
IHIGH-ZY  
VCCA = VCCY = 5.5 V, EN = 0  
VCCA = VCCY = 5.5 V, EN = 0  
0.1  
0.1  
1
1
μA  
μA  
1 Temperature range is −40°C to +85°C (B Version) for the TSSOP, the LFCSP, the WLCSP, and the backside-coated WLCSP.  
2 All typical values are at TA = 25°C, unless otherwise noted.  
3 Guaranteed by design; not subject to production test.  
Rev. C | Page 5 of 20  
 
ADG3308/ADG3308-1  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C, unless otherwise noted.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Table 2.  
Parameter  
Rating  
VCCA to GND  
−0.3 V to +7 V  
VCCY to GND  
VCCA to +7 V  
Digital Inputs (A)  
Digital Inputs (Y)  
EN to GND  
−0.3 V to (VCCA + 0.3 V)  
−0.3 V to (VCCY + 0.3 V)  
−0.3 V to +7 V  
Only one absolute maximum rating may be applied at any  
one time.  
Operating Temperature Range  
Extended Industrial Range (B Version) −40°C to +85°C  
Storage Temperature Range  
Junction Temperature  
−65°C to +150°C  
150°C  
ESD CAUTION  
θJA Thermal Impedance  
20-Lead TSSOP  
78°C/W  
20-Lead LFCSP  
20-Ball WLCSP  
30.4°C/W  
100°C/W  
20-Ball Backside-Coated WLCSP  
Lead Temperature, Soldering (10 sec)  
IR Reflow, Peak Temperature (<20 sec)  
100°C/W  
300°C  
260°C (+0°C/−5°C)  
Rev. C | Page 6 of 20  
 
 
ADG3308/ADG3308-1  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
BALL a1  
INDICATOR  
1
2
3
4
a
b
c
d
e
V
Y1  
A1  
V
CCA  
CCY  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
V
CCY  
CCA  
A1  
Y2  
Y4  
Y6  
Y8  
Y3  
Y5  
A3  
A5  
A7  
EN  
A2  
A4  
A6  
A8  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
GND  
PIN 1  
3
A2  
A3  
A4  
A5  
A6  
A7  
A8  
EN  
INDICATOR  
1
15 Y3  
14 Y4  
13 Y5  
12 Y6  
11 Y7  
A2  
A3 2  
A4  
A5  
A6  
4
ADG3308  
TOP VIEW  
(Not to Scale)  
ADG3308  
TOP VIEW  
(Not to Scale)  
3
4
5
5
6
Y7  
7
8
GND  
9
THE EXPOSED PAD CAN BE TIED TO  
GND OR IT CAN BE LEFT FLOATING.  
10  
ADG3308-1/  
ADG3308-2  
TOP VIEW  
DO NOT TIE IT TO V  
OR V .  
CCA  
CCY  
(Not to Scale)  
(BALLS AT THE BOTTOM)  
Figure 2. 20-Lead TSSOP  
Figure 3. 20-Lead LFCSP  
Figure 4. 20-Ball WLCSP  
Table 3. Pin Function Descriptions  
Pin/Ball No.  
TSSOP  
LFCSP  
WLCSP  
Mnemonic  
Description  
1
19  
a4  
VCCA  
Power Supply. Power supply voltage input for the A1 I/O pin to the A8 I/O pin  
(1.15 V ≤ VCCA < VCCY).  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
20  
1
2
3
4
5
6
7
8
a3  
b4  
b3  
c4  
c3  
d4  
d3  
e4  
e3  
e2  
e1  
d2  
d1  
c2  
c1  
b2  
b1  
a2  
a1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
EN  
GND  
Y8  
Y7  
Y6  
Y5  
Y4  
Y3  
Y2  
Y1  
VCCY  
Input/Output A1. Referenced to VCCA  
Input/Output A2. Referenced to VCCA  
Input/Output A3. Referenced to VCCA  
Input/Output A4. Referenced to VCCA  
Input/Output A5. Referenced to VCCA  
Input/Output A6. Referenced to VCCA  
Input/Output A7. Referenced to VCCA  
Input/Output A8. Referenced to VCCA  
Active High Enable Input.  
.
.
.
.
.
.
.
.
9
Ground.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
Input/Output Y8. Referenced to VCCY  
Input/Output Y7. Referenced to VCCY  
Input/Output Y6. Referenced to VCCY  
Input/Output Y5. Referenced to VCCY  
Input/Output Y4. Referenced to VCCY  
Input/Output Y3. Referenced to VCCY  
Input/Output Y2. Referenced to VCCY  
Input/Output Y1. Referenced to VCCY  
.
.
.
.
.
.
.
.
Power Supply. Power supply voltage input for the Y1 I/O pin to the Y8 I/O pin  
(1.65 V ≤ VCCY ≤ 5.5 V).  
Rev. C | Page 7 of 20  
 
ADG3308/ADG3308-1  
TYPICAL PERFORMANCE CHARACTERISTICS  
1.0  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
T
= 25°C  
T
= 25°C  
A
A
1 CHANNEL  
C
1 CHANNEL  
C
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
= 50pF  
= 15pF  
L
L
V
= 3.3V, V  
CCY  
= 5V  
CCA  
V
= 3.3V, V = 5V  
CCY  
CCA  
V
= 1.8V, V  
= 3.3V  
CCA  
CCY  
V
= 1.8V, V  
= 3.3V  
CCA  
CCY  
V
= 1.2V, V  
= 1.8V  
40  
V
= 1.2V, V  
CCY  
= 1.8V  
CCA  
CCY  
CCA  
25  
DATA RATE (Mbps)  
0
5
10  
15  
20  
30  
35  
40  
45  
50  
0
5
10  
15  
20  
25  
30  
35  
45  
50  
DATA RATE (Mbps)  
Figure 5. ICCA vs. Data Rate (AY Level Translation)  
Figure 8. ICCY vs. Data Rate (YA Level Translation)  
10  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
T
= 25°C  
A
T
= 25°C  
A
1 CHANNEL  
C
1 CHANNEL  
V
V
9
8
7
6
5
4
3
2
1
0
= 50pF  
L
= 1.2V  
= 1.8V  
CCA  
CCY  
20Mbps  
V
= 3.3V, V  
= 5V  
CCA  
CCY  
10Mbps  
5Mbps  
V
= 1.8V, V  
= 3.3V  
CCA  
CCY  
V
= 1.2V, V  
= 1.8V  
CCA  
CCY  
1Mbps  
53  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
13  
23  
33  
43  
63  
73  
DATA RATE (Mbps)  
CAPACITIVE LOAD (pF)  
Figure 9. ICCY vs. Capacitive Load at Pin Y  
for AY (1.2 V1.8 V) Level Translation  
Figure 6. ICCY vs. Data Rate (AY Level Translation)  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
T
= 25°C  
T
= 25°C  
A
A
1 CHANNEL  
C
1 CHANNEL  
V
V
= 15pF  
= 1.2V  
= 1.8V  
L
CCA  
CCY  
V
= 3.3V, V = 5V  
CCY  
CCA  
20Mbps  
10Mbps  
V
= 1.8V, V  
= 3.3V  
CCA  
CCY  
5Mbps  
1Mbps  
V
= 1.2V, V  
CCY  
= 1.8V  
CCA  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
13  
23  
33  
CAPACITIVE LOAD (pF)  
43  
53  
DATA RATE (Mbps)  
Figure 10. ICCA vs. Capacitive Load at Pin A  
for YA (1.8 V1.2 V) Level Translation  
Figure 7. ICCA vs. Data Rate (YA Level Translation)  
Rev. C | Page 8 of 20  
 
ADG3308/ADG3308-1  
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
T
= 25°C  
A
T = 25°C  
A
1 CHANNEL  
1 CHANNEL  
V
V
50Mbps  
= 1.8V  
= 3.3V  
CCA  
CCY  
V
V
= 3.3V  
= 5V  
CCA  
CCY  
50Mbps  
30Mbps  
20Mbps  
30Mbps  
20Mbps  
10Mbps  
5Mbps  
10Mbps  
5Mbps  
63  
13  
23  
33  
43  
53  
73  
13  
23  
33  
43  
53  
CAPACITIVE LOAD (pF)  
CAPACITIVE LOAD (pF)  
Figure 11. ICCY vs. Capacitive Load at Pin Y  
Figure 14. ICCA vs. Capacitive Load at Pin A  
for AY (1.8 V3.3 V) Level Translation  
for YA (5 V3.3 V) Level Translation  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
10  
T
= 25°C  
T = 25°C  
A
1 CHANNEL  
DATA RATE = 50kbps  
A
1 CHANNEL  
V
V
9
8
7
6
5
4
3
2
1
0
= 1.8V  
= 3.3V  
V
= 1.2V, V = 1.8V  
CCY  
CCA  
CCY  
CCA  
50Mbps  
V
= 1.8V, V  
= 3.3V, V  
= 3.3V  
= 5V  
30Mbps  
CCA  
CCY  
20Mbps  
10Mbps  
V
CCA  
CCY  
5Mbps  
13  
23  
33  
43  
53  
13  
23  
33  
43  
53  
63  
73  
CAPACITIVE LOAD (pF)  
CAPACITIVE LOAD (pF)  
Figure 12. ICCA vs. Capacitive Load at Pin A  
for YA (3.3 V1.8 V) Level Translation  
Figure 15. Rise Time vs. Capacitive Load at Pin Y (AY Level Translation)  
4.0  
12  
T
= 25°C  
T
= 25°C  
A
A
1 CHANNEL  
DATA RATE = 50kbps  
1 CHANNEL  
V
V
50Mbps  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
= 3.3V  
= 5V  
CCA  
CCY  
V
= 1.2V, V  
= 1.8V  
10  
8
CCA  
CCY  
30Mbps  
20Mbps  
V
= 1.8V, V  
= 3.3V  
CCA  
CCY  
6
4
V
= 3.3V, V  
= 5V  
CCA  
CCY  
10Mbps  
5Mbps  
2
0
13  
13  
23  
33  
43  
53  
63  
73  
23  
33  
43  
53  
63  
73  
CAPACITIVE LOAD (pF)  
CAPACITIVE LOAD (pF)  
Figure 16. Fall Time vs. Capacitive Load at Pin Y (AY Level Translation)  
Figure 13. ICCY vs. Capacitive Load at Pin Y  
for AY (3.3 V5 V) Level Translation  
Rev. C | Page 9 of 20  
ADG3308/ADG3308-1  
10  
12  
10  
8
T
= 25°C  
T
= 25°C  
A
A
V
= 1.2V, V  
= 1.8V  
CCA  
CCY  
1 CHANNEL  
DATA RATE = 50kbps  
1 CHANNEL  
DATA RATE = 50kbps  
9
8
7
6
5
4
3
2
1
0
V
= 1.2V, V  
= 1.8V  
CCA  
CCY  
6
V
= 1.8V, V  
= 3.3V  
CCA  
CCY  
4
V
= 1.8V, V  
= 3.3V  
CCA  
CCY  
2
V
= 3.3V, V  
63  
= 5V  
73  
CCA  
CCY  
V
= 3.3V, V  
= 5V  
CCA  
CCY  
0
13  
23  
33  
43  
53  
13  
18  
23  
28  
33  
38  
43  
48  
53  
CAPACITIVE LOAD (pF)  
CAPACITIVE LOAD (pF)  
Figure 20. Propagation Delay (tPHL) vs. Capacitive Load  
Figure 17. Rise Time vs. Capacitive Load at Pin A (YA Level Translation)  
at Pin Y (AY Level Translation)  
9
8
7
6
5
4
3
2
1
0
4.0  
T
= 25°C  
T
= 25°C  
A
A
1 CHANNEL  
DATA RATE = 50kbps  
1 CHANNEL  
DATA RATE = 50kbps  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
V
= 1.2V, V  
= 1.8V  
CCA  
CCY  
V
= 1.2V, V  
= 1.8V  
CCA  
CCY  
V
= 1.8V, V  
= 3.3V  
= 5V  
CCA  
CCY  
V
= 1.8V, V  
= 3.3V  
V
= 3.3V, V  
CCA  
CCY  
CCA  
CCY  
V
= 3.3V, V  
43  
= 5V  
CCA  
CCY  
13  
18  
23  
28  
33  
38  
48  
53  
13  
18  
23  
28  
33  
38  
43  
48  
53  
CAPACITIVE LOAD (pF)  
CAPACITIVE LOAD (pF)  
Figure 21. Propagation Delay (tPLH) vs. Capacitive Load  
Figure 18. Fall Time vs. Capacitive Load at Pin A (YA Level Translation)  
at Pin A (YA Level Translation)  
9
8
7
6
5
4
3
2
1
0
14  
T
= 25°C  
A
T
= 25°C  
A
1 CHANNEL  
DATA RATE = 50kbps  
1 CHANNEL  
DATA RATE = 50kbps  
12  
10  
8
V
= 1.2V, V  
= 1.8V  
CCA  
CCY  
V
= 1.2V, V  
= 1.8V  
CCA  
CCY  
6
V
= 1.8V, V  
= 3.3V  
CCA  
CCY  
V
= 1.8V, V  
= 3.3V  
CCA  
CCY  
4
V
= 3.3V, V  
= 5V  
CCA  
CCY  
V
= 3.3V, V  
= 5V  
CCA  
CCY  
2
0
13  
18  
23  
28  
33  
38  
43  
48  
53  
13  
23  
33  
43  
53  
63  
73  
CAPACITIVE LOAD (pF)  
CAPACITIVE LOAD (pF)  
Figure 19. Propagation Delay (tPLH) vs. Capacitive Load  
Figure 22. Propagation Delay (tPHL) vs. Capacitive Load  
at Pin Y (AY Level Translation)  
at Pin A (YA Level Translation)  
Rev. C | Page 10 of 20  
ADG3308/ADG3308-1  
T
= 25°C  
A
T
= 25°C  
A
DATA RATE = 25Mbps  
C
1 CHANNEL  
DATA RATE = 50Mbps  
C
1 CHANNEL  
= 50pF  
L
= 15pF  
L
400mV/DIV  
5ns/DIV  
400mV/DIV  
3ns/DIV  
Figure 23. Eye Diagram at Y Output  
Figure 26. Eye Diagram at A Output  
(1.2 V1.8 V Level Translation, 25 Mbps)  
(3.3 V1.8 V Level Translation, 50 Mbps)  
T
= 25°C  
C
= 50pF  
T
= 25°C  
A
L
A
DATA RATE = 25Mbps  
1 CHANNEL  
DATA RATE = 50Mbps  
= 50pF  
C
L
1 CHANNEL  
1V/DIV  
200mV/DIV  
3ns/DIV  
5ns/DIV  
Figure 24. Eye Diagram at A Output  
Figure 27. Eye Diagram at Y Output  
(1.8 V1.2 V Level Translation, 25 Mbps)  
(3.3 V5 V Level Translation, 50 Mbps)  
T
= 25°C  
T
= 25°C  
C = 50pF  
L
A
A
DATA RATE = 50Mbps  
= 15pF  
DATA RATE = 50Mbps 1 CHANNEL  
C
L
1 CHANNEL  
500mV/DIV  
3ns/DIV  
3ns/DIV  
800mV/DIV  
Figure 25. Eye Diagram at Y Output  
Figure 28. Eye Diagram at A Output  
(1.8 V3.3 V Level Translation, 50 Mbps)  
(5 V3.3 V Level Translation, 50 Mbps)  
Rev. C | Page 11 of 20  
ADG3308/ADG3308-1  
TEST CIRCUITS  
EN  
V
ADG3308/  
V
CCA  
ADG3308-1  
ADG3308-2  
/
CCY  
ADG3308/  
V
V
CCY  
CCA  
ADG3308-1  
/
0.1µF  
0.1µF  
ADG3308-2  
0.1µF  
0.1µF  
Ax  
Yx  
K2  
Yx  
Ax  
K1  
GND  
K
EN  
A
GND  
I
I
OH  
OL  
Figure 29. VOH/VOL Voltages at Pin A  
Figure 33. EN Pin Leakage Current  
EN  
ADG3308/  
V
CCA  
V
CCY  
ADG3308-1  
/
EN  
V
ADG3308/  
ADG3308-2  
V
CCA  
Ax  
0.1µF  
ADG3308-1  
/
0.1µF  
CCY  
ADG3308-2  
K2  
x A  
Yx  
Yx  
K1  
GND  
CAPACITANCE  
METER  
GND  
I
OH  
I
OL  
Figure 30. VOH/VOL Voltages at Pin Y  
Figure 34. Capacitance at Pin A  
EN  
EN  
ADG3308/  
ADG3308/  
V
V
V
V
CCY  
CCA  
CCY  
ADG3308-1  
/
CCA  
ADG3308-1  
/
ADG3308-2  
ADG3308-2  
0.1µF  
0.1µF  
Ax  
Yx  
Ax  
Yx  
A
K
CAPACITANCE  
METER  
GND  
GND  
Figure 31. Three-State Leakage Current at Pin A  
Figure 35. Capacitance at Pin Y  
EN  
ADG3308/  
V
CCA  
Ax  
V
CCY  
ADG3308-1  
/
ADG3308-2  
0.1µF  
0.1µF  
K
Yx  
A
GND  
Figure 32. Three-State Leakage Current at Pin Y  
Rev. C | Page 12 of 20  
 
 
 
 
 
 
ADG3308/ADG3308-1  
AY DIRECTION  
V
V
CCA  
ADG3308/  
ADG3308-1  
ADG3308-2  
CCY  
/
+
+
0.1µF  
10µF  
0.1µF  
10µF  
1M  
V
Ax  
x Y  
V
A
Y
K1  
K2  
50pF  
1MΩ  
SIGNAL SOURCE  
EN  
GND  
Z
= 50Ω  
R
S
0
V
EN  
50Ω  
R
T
50Ω  
YA DIRECTION  
V
V
CCA  
CCY  
ADG3308/  
ADG3308-1  
/
+
+
0.1µF  
10µF  
ADG3308-2  
0.1µF  
10µF  
1MΩ  
V
Ax  
x Y  
V
A
Y
K1  
1MΩ  
K2  
15pF  
SIGNAL SOURCE  
EN  
GND  
Z
= 50Ω  
R
S
0
V
EN  
50Ω  
R
T
50Ω  
V
CCY  
tEN1  
V
EN  
0V  
V
/V  
CCA CCY  
V
/V  
A
Y
A
0V  
V
/V  
CCY CCA  
90%  
V /V  
Y
0V  
V
CCY  
tEN2  
V
EN  
0V  
V
/V  
Y
A
V
/V  
CCA CCY  
0V  
V
/V  
CCY CCA  
V /V  
Y
A
10%  
0V  
NOTES  
1. tEN IS WHICHEVER IS LARGER BETWEEN tEN1 AND tEN2  
IN BOTH AY AND YA DIRECTIONS.  
Figure 36. Enable Time  
Rev. C | Page 13 of 20  
 
ADG3308/ADG3308-1  
EN  
V
ADG3308/  
V
+
CCA  
CCY  
ADG3308-1  
/
ADG3308-2  
+
SIGNAL  
SOURCE  
0.1µF  
= 50  
10µF  
0.1µF  
10µF  
Z
R
S
0
V
V
x Y  
A
x A  
Y
R
50Ω  
50Ω  
T
50pF  
GND  
V
A
50%  
90%  
tP, AY  
tP, AY  
V
Y
50%  
10%  
tF, AY  
tR, AY  
Figure 37. Switching Characteristics (AY Level Translation)  
EN  
ADG3308/  
V
V
CCA  
ADG3308-1  
/
CCY  
ADG3308-2  
+
+
SIGNAL  
SOURCE  
0.1µF  
10µF  
10µF  
0.1µF  
x Y  
Z
0
= 50  
R
S
x A  
V
V
R
A
Y
50Ω  
T
15pF  
50Ω  
GND  
V
Y
50%  
90%  
tP, YA  
tP, YA  
V
A
50%  
10%  
tF, YA  
tR, YA  
Figure 38. Switching Characteristics (YA Level Translation)  
Rev. C | Page 14 of 20  
 
 
ADG3308/ADG3308-1  
TERMINOLOGY  
VIHA  
DMAX, A→Y  
Logic input high voltage at Pin A1 to Pin A8.  
Guaranteed data rate when translating logic levels in the A→Y  
direction under the driving and loading conditions specified in  
Table 1.  
VILA  
Logic input low voltage at Pin A1 to Pin A8.  
tSKEW, A→Y  
VOHA  
Difference between propagation delays on any two channels  
when translating logic levels in the A→Y direction.  
Logic output high voltage at Pin A1 to Pin A8.  
VOLA  
tPPSKEW, A→Y  
Logic output low voltage at Pin A1 to Pin A8.  
Difference in propagation delay between any one channel and  
the same channel on a different part (under same driving/  
loading conditions) when translating in the A→Y direction.  
CA  
Capacitance measured at Pin A1 to Pin A8 (EN = 0).  
ILA, HIGH-Z  
tP, Y → A  
Leakage current at Pin A1 to Pin A8 when EN = 0 (high  
impedance state at Pin A1 to Pin A8).  
Propagation delay when translating logic levels in the Y→A  
direction.  
VIHY  
tR, Y→A  
Logic input high voltage at Pin Y1 to Pin Y8.  
Rise time when translating logic levels in the Y→A direction.  
VILY  
tF, Y→A  
Logic input low voltage at Pin Y1 to Pin Y8.  
Fall time when translating logic levels in the Y→A direction.  
VOHY  
DMAX, Y→A  
Logic output high voltage at Pin Y1 to Pin Y8.  
Guaranteed data rate when translating logic levels in the Y→A  
direction under the driving and loading conditions specified in  
Table 1.  
VOLY  
Logic output low voltage at Pin Y1 to Pin Y8.  
CY  
tSKEW, Y→A  
Capacitance measured at Pin Y1 to Pin Y8 (EN = 0).  
Difference between propagation delays on any two channels  
when translating logic levels in the Y→A direction.  
ILY, HIGH-Z  
Leakage current at Pin Y1 to Pin Y8 when EN = 0 (high  
impedance state at Pin Y1 to Pin Y8).  
tPPSKEW, Y→A  
Difference in propagation delay between any one channel and  
the same channel on a different part (under same driving/  
loading conditions) when translating in the Y→A direction.  
VIHEN  
Logic input high voltage at the EN pin.  
VCCA  
VILEN  
VCCA supply voltage.  
Logic input low voltage at the EN pin.  
VCCY  
CEN  
VCCY supply voltage.  
Capacitance measured at EN pin.  
ICCA  
ILEN  
VCCA supply current.  
Enable (EN) pin leakage current.  
ICCY  
tEN  
VCCY supply current.  
Three-state enable time for Pin A1 to Pin A8/Pin Y1 to Pin Y8.  
IHIGH-ZA  
tP, A → Y  
VCCA supply current during three-state mode (EN = 0).  
Propagation delay when translating logic levels in the A→Y  
direction.  
IHIGH-ZY  
VCCY supply current during three-state mode (EN = 0).  
tR, A→Y  
Rise time when translating logic levels in the A→Y direction.  
tF, A→Y  
Fall time when translating logic levels in the A→Y direction.  
Rev. C | Page 15 of 20  
 
ADG3308/ADG3308-1  
THEORY OF OPERATION  
The ADG3308/ADG3308-1/ADG3308-2 level translators allow  
the level shifting necessary for data transfer in a system where  
multiple supply voltages are used. The device requires two  
supplies, VCCA and VCCY (VCCA ≤ VCCY). These supplies set the  
logic levels on each side of the device. When driving the A pins,  
the device translates the VCCA compatible logic levels to VCCY  
compatible logic levels available at the Y pins. Similarly, because  
the device is capable of bidirectional translation, when driving  
the Y pins the VCCY compatible logic levels are translated to the  
VCCA compatible logic levels available at the A pins. When  
EN = 0, the A1 pin to the A8 pin and the Y1 pin to the Y8 pin  
are three-stated. When EN is driven high, the ADG3308/  
ADG3308-1/ADG3308-2 go into normal operation mode and  
perform level translation.  
INPUT DRIVING REQUIREMENTS  
To ensure correct operation of the ADG3308/ADG3308-1/  
ADG3308-2, the circuit that drives the input of the device  
should be able to ensure rise/fall times of less than 3 ns when  
driving a load consisting of a 6 kΩ resistor in parallel with the  
input capacitance of the ADG3308/ADG3308-1/ADG3308-2  
channel.  
OUTPUT LOAD REQUIREMENTS  
The ADG3308/ADG3308-1/ADG3308-2 level translators are  
designed to drive CMOS-compatible loads. If current-driving  
capability is required, it is recommended to use buffers between  
the ADG3308/ADG3308-1/ADG3308-2 outputs and the load.  
ENABLE OPERATION  
LEVEL TRANSLATOR ARCHITECTURE  
The ADG3308/ADG3308-1/ADG3308-2 provide three-state  
operation at the A I/O pins and the Y I/O pins by using the  
enable (EN) pin, as shown in Table 4.  
The ADG3308/ADG3308-1/ADG3308-2 consist of eight  
bidirectional channels. Each channel can translate logic levels  
in either the A→Y or the Y→A direction. They use a one-shot  
accelerator architecture, ensuring excellent switching charac-  
teristics. Figure 39 shows a simplified block diagram of a  
bidirectional channel.  
Table 4. Truth Table  
EN  
Y I/O Pins  
A I/O Pins  
0
1
High-Z1  
High-Z1  
Normal operation2  
Normal operation2  
V
V
CCA  
CCY  
1 High impedance state.  
2 In normal operation, the ADG3308/ADG3308-1/ADG3308-2 perform level  
translation.  
T1  
T2  
6k  
When EN = 0, the ADG3308/ADG3308-1/ADG3308-2 enter  
into three-state mode. In this mode, the current consumption  
from both the VCCA and VCCY supplies is reduced, allowing the  
user to save power, which is critical, especially in battery-  
operated systems. The EN input pin can only be driven with  
U1  
U2  
P
Y
A
ONE-SHOT GENERATOR  
N
V
CCY compatible logic levels for the ADG3308, whereas the  
ADG3308-1/ADG3308-2 can be driven with either VCCA- or  
CCY compatible logic levels.  
U4  
U3  
6kΩ  
V
POWER SUPPLIES  
T4  
T3  
For proper operation of the device, the voltage applied to the  
VCCA must always be less than or equal to the voltage applied  
to VCCY. To meet this condition, the recommended power-up  
sequence is VCCY first and then VCCA. The ADG3308/ADG3308-1/  
ADG3308-2 operate properly only after both supply voltages  
reach their nominal values. It is not recommended to use the part  
in a system where, during power-up, VCCA may be greater than  
Figure 39. Simplified Block Diagram of an  
ADG3308/ADG3308-1/ADG3308-2 Channel  
The logic level translation in the A→Y direction is performed  
using a level translator (U1) and an inverter (U2), whereas the  
translation in the Y→A direction is performed using the U3  
inverter and U4 inverter. The one-shot generator detects a rising  
or falling edge present on either the A side or the Y side of the  
channel. It sends a short pulse that turns on the PMOS transistors  
(T1 and T2) for a rising edge, or the NMOS transistors (T3 and  
T4) for a falling edge. This charges/discharges the capacitive load  
faster, resulting in fast rise and fall times.  
V
V
CCY due to a significant increase in the current taken from the  
CCA supply. For optimum performance, the VCCA and VCCY pins  
should be decoupled to GND as close as possible to the device.  
The inputs of the unused channels (A or Y) should be tied to  
their corresponding VCC rail (VCCA or VCCY) or to GND.  
Rev. C | Page 16 of 20  
 
 
 
ADG3308/ADG3308-1  
DATA RATE  
The maximum data rate at which the device is guaranteed to  
operate is a function of the VCCA and VCCY supply voltage  
combination and the load capacitance. It represents the maximum  
frequency of a square wave that can be applied to the I/O pins,  
ensuring that the device operates within the data sheet  
specifications in terms of output voltage (VOL and VOH) and  
power dissipation (the junction temperature does not exceed the  
value specified under the Absolute Maximum Ratings section).  
Table 5 shows the guaranteed data rates at which the ADG3308/  
ADG3308-1/ADG3308-2 can operate in both directions (A→Y  
level translation or Y→A level translation) for various VCCA and  
VCCY supply combinations.  
Table 5. Guaranteed Data Rates1  
VCCY  
3.3 V (3.0 V to 3.6 V)  
40 Mbps  
VCCA  
1.8 V (1.65 V to 1.95 V)  
2.5 V (2.3 V to 2.7 V)  
30 Mbps  
45 Mbps  
5 V (4.5 V to 5.5 V)  
40 Mbps  
50 Mbps  
50 Mbps  
50 Mbps  
1.2 V (1.15 V to 1.3 V)  
1.8 V (1.65 V to 1.95 V)  
2.5 V (2.3 V to 2.7 V)  
3.3 V (3.0 V to 3.6 V)  
5 V (4.5 V to 5.5 V)  
25 Mbps  
50 Mbps  
60 Mbps  
1 The load capacitance used is 50 pF when translating in the AY direction and 15 pF when translating in the YA direction.  
Rev. C | Page 17 of 20  
 
 
ADG3308/ADG3308-1  
APPLICATIONS  
The ADG3308/ADG3308-1/ADG3308-2 are designed for digital  
circuits that operate at different supply voltages; therefore, logic  
level translation is required. The lower voltage logic signals are  
connected to the A pins, and the higher voltage logic signals to  
the Y pins. The ADG3308/ADG3308-1/ADG3308-2 can provide  
level translation in both directions (A→Y or Y→A) on all eight  
channels, eliminating the need for a level translator IC for each  
direction. The internal architecture allows the ADG3308/  
ADG3308-1/ADG3308-2 to perform bidirectional level  
translation without an additional signal to set the direction in  
which the translation is made. It also allows simultaneous data  
flow in both directions on the same part, for example, when two  
channels translate in the A→Y direction while the other two  
translate in the Y→A direction. This simplifies the design by  
eliminating the timing requirements for the direction signal  
and reduces the number of ICs used for level translation.  
100nF  
100nF  
ADG3308/  
ADG3308-1  
ADG3308-2  
/
V
V
CCY  
CCA  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
3.3V  
1.8V  
I/O 1  
I/O  
I/O  
I/O  
1
2
3
Y1  
L
H
H
H
I/O 2  
L
Y2  
Y3  
I/O 3  
L
I/O 4  
L
I/O  
I/O  
I/O  
I/O  
I/O  
CS  
4
5
6
7
8
Y4  
Y5  
Y6  
Y7  
Y8  
EN  
H
H
H
H
H
I/O 5  
L
I/O 6  
L
I/O 7  
L
I/O 8  
L
GND  
GND  
GND  
100nF  
100nF  
Figure 40 shows an application where a 3.3 V microprocessor  
can read or write data to and from a 1.8 V peripheral device  
using an 8-bit bus.  
ADG3308/  
ADG3308-1  
ADG3308-2  
/
V
V
CCY  
CCA  
A1  
1.8V  
I/O 1  
L
Y1  
100nF  
100nF  
V
I/O 2  
L
Y2  
Y3  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
I/O 3  
L
CCY  
CCA  
3.3V  
1.8V  
I/O 4  
L
Y4  
Y5  
Y6  
Y7  
Y8  
EN  
I/O 1  
L
Y1  
A1  
I/O  
1
H
I/O 5  
L
ADG3308/  
ADG3308-1  
/
I/O 6  
L
ADG3308-2  
I/O 7  
L
I/O 2  
L
Y2  
Y3  
A2  
I/O  
I/O  
2
3
H
I/O 8  
L
GND  
GND  
A3  
I/O 3  
L
H
Figure 41. 1.8 V to 3.3 V Level Translation Circuit  
Using the Three-State Feature  
Y4  
Y5  
A4  
A5  
I/O 4  
L
I/O  
4
5
H
I/O 5  
L
I/O  
I/O  
I/O  
I/O  
H
LAYOUT GUIDELINES  
As with any high speed digital IC, the printed circuit board  
layout is important in the overall performance of the circuit. Care  
should be taken to ensure proper power supply bypass and  
return paths for the high speed signals. Each VCC pin (VCCA and  
I/O 6  
L
Y6  
A6  
A7  
6
7
8
H
H
H
I/O 7  
L
Y7  
Y8  
EN  
A8  
I/O 8  
L
V
CCY) should be bypassed using low effective series resistance  
(ESR) and effective series inductance (ESI) capacitors placed as  
close as possible to the VCCA and VCCY pins. The parasitic induc-  
tance of the high speed signal track can cause significant overshoot.  
This effect can be reduced by keeping the length of the tracks as  
short as possible. A solid copper plane for the return path  
(GND) is also recommended.  
GND  
GND  
GND  
Figure 40. 1.8 V to 3.3 V 8-Bit Level Translation Circuit  
When the application requires level translation between  
a microprocessor and multiple peripheral devices, the  
ADG3308/ADG3308-1/ADG3308-2 I/O pins can be three-  
stated by setting EN = 0. This feature allows the ADG3308/  
ADG3308-1/ADG3308-2 to share the data buses with other  
devices without causing contention issues. Figure 41 shows an  
application where a 3.3 V microprocessor is connected to 1.8 V  
peripheral devices using the three-state feature.  
Rev. C | Page 18 of 20  
 
 
 
ADG3308/ADG3308-1  
OUTLINE DIMENSIONS  
6.60  
6.50  
6.40  
20  
11  
10  
4.50  
4.40  
4.30  
6.40 BSC  
1
PIN 1  
0.65  
BSC  
1.20 MAX  
0.15  
0.05  
0.20  
0.09  
0.75  
0.60  
0.45  
8°  
0°  
0.30  
0.19  
COPLANARITY  
0.10  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-153-AC  
Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP]  
(RU-20)  
Dimensions shown in millimeters  
0.60 MAX  
4.00  
BSC SQ  
0.60 MAX  
PIN 1  
INDICATOR  
15  
16  
20  
1
5
0.50  
BSC  
PIN 1  
INDICATOR  
2.25  
2.10 SQ  
1.95  
3.75  
BCS SQ  
EXPOSED  
PAD  
(BOTTOM VIEW)  
10  
6
11  
0.75  
0.60  
0.50  
TOP VIEW  
0.25 MIN  
0.80 MAX  
0.65 TYP  
12° MAX  
1.00  
0.85  
0.80  
0.05 MAX  
0.02 NOM  
COPLANARITY  
0.08  
0.20 REF  
0.30  
0.23  
0.18  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1  
Figure 43. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
4 mm × 4 mm Body, Very Thin Quad  
(CP-20-1)  
Dimensions shown in millimeters  
Rev. C | Page 19 of 20  
 
ADG3308/ADG3308-1  
2.06  
2.00  
1.94  
0.65  
0.59  
0.53  
4
3
2
1
A
B
C
D
E
A1 BALL  
IDENTIFIER  
2.56  
2.50  
2.44  
0.50 BSC  
PITCH  
0.36  
0.32  
0.28  
0.28  
0.24  
0.20  
TOP VIEW  
(BALL SIDE DOWN)  
BOTTOM VIEW  
(BALL SIDE UP)  
Figure 44. 20-Ball Wafer Level Chip Scale Package [WLCSP]  
(CB-20-2)  
Dimensions shown in millimeters  
0.645  
0.585  
2.06  
2.00  
1.94  
0.525  
0.042  
0.040  
0.037  
4
3
2
1
A
B
C
D
E
A1 BALL  
IDENTIFIER  
2.56  
2.50  
2.44  
0.50 BSC  
PITCH  
0.36  
0.32  
0.28  
0.28  
0.24  
0.20  
TOP VIEW  
(BALL SIDE DOWN)  
BOTTOM VIEW  
(BALL SIDE UP)  
Figure 45. Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP]  
(CB-20-3)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model  
Temperature Range  
Package Description  
Package Option  
RU-20  
RU-20  
ADG3308BRUZ1  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
20-Lead Thin Shrink Small Outline Package [TSSOP]  
20-Lead Thin Shrink Small Outline Package [TSSOP]  
20-Lead Thin Shrink Small Outline Package [TSSOP]  
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
20-Ball Wafer Level Chip Scale Package [WLCSP]  
20-Ball Wafer Level Chip Scale Package [WLCSP]  
ADG3308BRUZ-REEL1  
ADG3308BRUZ-REEL71  
ADG3308BCPZ-REEL1  
ADG3308BCPZ-REEL71  
ADG3308BCBZ-1-RL71  
ADG3308BCBZ-1-REEL1  
ADG3308BCBZ-2-RL71  
ADG3308BCBZ-2-REEL1  
RU-20  
CP-20-1  
CP-20-1  
CB-20-2  
CB-20-2  
CB-20-3  
CB-20-3  
Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP]  
Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP]  
1 Z = RoHS Compliant Part.  
©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D04865-0-9/07(C)  
Rev. C | Page 20 of 20  
 
 
 
配单直通车
ADG3308BRUZ产品参数
型号:ADG3308BRUZ
Brand Name:Analog Devices Inc
是否无铅: 含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:ANALOG DEVICES INC
零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25
针数:20
制造商包装代码:RU-20
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:0.68
接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:R-PDSO-G20
JESD-609代码:e3
长度:6.5 mm
湿度敏感等级:1
功能数量:1
端子数量:20
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260
电源:1.2/5,1.8/5 V
认证状态:Not Qualified
座面最大高度:1.2 mm
子类别:Other Interface ICs
最大供电电压:5.5 V
最小供电电压:1.15 V
标称供电电压:1.8 V
电源电压1-最大:5.5 V
电源电压1-分钟:1.65 V
表面贴装:YES
温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:40
宽度:4.4 mm
Base Number Matches:1
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