ADM232LAR应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

+5 V Powered

CMOS RS-232 Drivers/Receivers

a

ADM223/ADM230L–ADM241L

AD M232L TYP ICAL O P ERATING CIRCUIT

FEATURES

Single 5 V Pow er Supply

Meets All EIA-232-E and V.28 Specifications

120 kB/ s Data Rate

On-Board DC-DC Converters

؎9 V Output Sw ing w ith +5 V Supply

Sm all 1 ␮F Capacitors

Low Pow er Shutdow n ≤1 ␮A

Receivers Active in Shutdow n (ADM223)

ESD > 2 kV

؎30 V Receiver Input Levels

Latch-Up FREE

+5V INPUT

1

3

4

16

2

C1+ +5V TO +10V

VOLTAGE

V

CC

V+

1µF

6.3V

1µF

6.3V

1µF

6.3V

DOUBLER

C1–

C2+

+10V TO –10V

1µF

16V

V– 6

VOLTAGE

1µF

16V

5 C2–

11

INVERTER

14

7

T1

T2

T1

OUT

IN

RS-232

OUTPUTS

TTL/CMOS

INPUTS*

10

12

9

T2

OUT

IN

Plug-In Upgrade for MAX223/ 230-241

Plug-In Upgrade for AD230–AD241

R1

R2

13

8

R1

R2

R1

R2

IN

OUT

TTL/CMOS

OUTPUTS

RS-232

INPUTS**

APPLICATIONS

Com puters

Peripherals

Modem s

OUT

GND

15

ADM232L

Printers

Instrum ents

*INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT

All members of the ADM230L family, except the ADM231L

and the ADM239L, include two internal charge pump voltage

converters that allow operation from a single +5 V supply.

T hese converters convert the +5 V input power to the ±10 V

required for RS-232 output levels. T he ADM231L and

ADM239L are designed to operate from +5 V and +12 V sup-

plies. An internal +12 V to –12 V charge pump voltage con-

verter generates the –12 V supply.

GENERAL D ESCRIP TIO N

T he ADM2xx family of line drivers/receivers is intended for all

EIA-232-E and V.28 communications interfaces, especially in

applications where ±12 V is not available. T he ADM223,

ADM230L, ADM235L, ADM236L and ADM241L feature a

low power shutdown mode that reduces power dissipation to

less than 5 µW, making them ideally suited for battery powered

equipment. T wo receivers remain enabled during shutdown on

the ADM223. T he ADM233L and ADM235L do not require

any external components and are particularly useful in applica-

tions where printed circuit board space is critical.

T he ADM2xxL is an enhanced upgrade for the AD2xx family

featuring lower power consumption, faster slew rate and opera-

tion with smaller (1 µF) capacitors.

Table I. Selection Table

No. of

RS-232

D rivers

No. of

RS-232

Receivers

Low P ower

Shutdown

(SD )

TTL

P art

Num ber

P ower

Supply Voltage

External

Capacitors

Three-State No. of

EN

P ins

ADM223

ADM230L +5 V

ADM231L +5 V & +7.5 V to +13.2 V

ADM232L +5 V

ADM233L +5 V

ADM234L +5 V

ADM235L +5 V

ADM236L +5 V

ADM237L +5 V

+5 V

4

5

2

4

5

4

5

4

3

4

5

0

2

0

5

3

4

5

4

2

4

Yes (SD)

Yes

No

Yes (EN)

No

28

20

14

16

20

16

24

28

None

4

None

4

2

4

No

Yes

No

Yes

No

Yes

ADM238L +5 V

ADM239L +5 V & +7.5 V to +13.2 V

ADM241L +5 V

Yes

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

V = +5 V ؎ 10% (ADM223, 31L,

32L, 34L, 36L, 38L, 39L, 41L);

CC

ADM223/ADM230L–ADM241L–SPECIFICATIONS

V = +5 V ؎ 5% (ADM230L, 33L, 35L, 37L); V+ = 7.5 V to 13.2 V (ADM231L & ADM239L); C1–C4 = 1.0 ␮F Ceramic. All Specifications T_MINto

CC

T_MAXunless otherwise noted.)

P aram eter

Min Typ Max Units Test Conditions/Com m ents

Output Voltage Swing

V_CCPower Supply Current

±5

±9

2

3.5

0.4

1.5

1

Volts All T ransmitter Outputs Loaded with 3 kΩ to Ground

3.0

6

1

4

5

mA

µA

V

µA

V

No Load, All T_INS= V_CC(Except ADM223)

No Load, All T_INS= GND

ADM231L, ADM239L

V+ Power Supply Current

Shutdown Supply Current

No Load, V+ = 12 V ADM231L & ADM239L Only

Input Logic T hreshold Low, V_INL

Input Logic T hreshold High, V_INH

Logic Pull-Up Current

RS-232 Input Voltage Range

RS-232 Input T hreshold Low

RS-232 Input T hreshold High

RS-232 Input Hysteresis

0.8

T_IN, EN, SD, EN, SD

T_IN= 0 V

2.0

10

25

+30

–30

0.8

1.2

1.7

0.5

5

V

2.4

1.0

7

0.2

3

RS-232 Input Resistance

kΩ

V

T T L/CMOS Output Voltage Low, V_OL

T T L/CMOS Output Voltage High, V_OH

T T L/CMOS Output Leakage Current

0.4

3.5

I_OUT= –1.0 mA

0.05 ±5

250

µA

ns

EN = V_CC, 0 V ≤ R_OUT≤ V_CC

ADM223, ADM235L, ADM236L, ADM239L, ADM241L

(Figure 25. C_L= 150 pF)

Output Enable T ime (T_EN

)

Output Disable T ime (T_DIS

)

50

ns

ADM223, ADM235L, ADM236L, ADM239L, ADM241L

(Figure 25. R_L= 1 kΩ)

Propagation Delay

0.5

25

µs

RS-232 to T T L

Instantaneous Slew Rate¹

30

V/µs C_L= 10 pF, R_L= 3-7 kΩ, T _A= +25°C

T ransition Region Slew Rate

5

V/µs R_L= 3 kΩ, C_L= 2500 pF

Measured from +3 V to –3 V or –3 V to +3 V

V_CC= V+ = V– = 0 V, V_OUT= ±2 V

Output Resistance

300

Ω

RS-232 Output Short Circuit Current

±10

mA

NOT E

¹Sample tested to ensure compliance.

Specifications subject to change without notice.

ABSO LUTE MAXIMUM RATINGS*

(T _A= 25°C unless otherwise noted)

T hermal Impedance, θ_JA

N-14 DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140°C/W

N-16 DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135°C/W

N-20 DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W

N-24 DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W

N-24A DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W

R-16 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105°C/W

R-20 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105°C/W

R-24 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W

R-28 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W

RS-28 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100°C/W

Q-14 Cerdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105°C/W

Q-16 Cerdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100°C/W

Q-20 Cerdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100°C/W

Q-24 Cerdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W

D-24 Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50°C/W

Operating T emperature Range

Commercial (J Version) . . . . . . . . . . . . . . . . . . . 0 to +70°C

Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage T emperature Range . . . . . . . . . . . –65°C to + 150°C

Lead T emperature, Soldering . . . . . . . . . . . . . . . . . . +300°C

Vapour Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2000 V

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V_CC– 0.3 V) to +14 V

V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –14 V

Input Voltages

T _IN. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V_CC+ 0.3 V)

R_IN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V

Output Voltages

T _OUT. . . . . . . . . . . . . . . . . . (V+, + 0.3 V) to (V–, – 0.3 V)

R_OUT. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V_CC+ 0.3 V)

Short Circuit Duration

T _OUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous

Power Dissipation

N-14 DIP (Derate 10 mW/°C above +70°C) . . . . . 800 mW

N-16 DIP (Derate 10.5 mW/°C above +70°C) . . . 840 mW

N-20 DIP (Derate 11 mW/°C above +70°C) . . . . . 890 mW

N-24 DIP (Derate 13.5 mW/°C above +70°C) . . 1000 mW

N-24A DIP (Derate 13.5 mW/°C above +70°C) . . 500 mW

R-16 SOIC (Derate 9 mW/°C above +70°C) . . . . . 760 mW

R-20 SOIC (Derate 9.5 mW/°C above +70°C) . . . 800 mW

R-24 SOIC (Derate 12 mW/°C above +70°C) . . . . 850 mW

R-28 SOIC (Derate 12.5 mW/°C above +70°C) . . 900 mW

RS-28 SSOP (Derate 10 mW/°C above +70°C) . . . 900 mW

Q-14 Cerdip (Derate 10 mW/°C above +70°C) . . . 720 mW

Q-16 Cerdip (Derate 10 mW/°C above +70°C) . . . 800 mW

Q-20 Cerdip (Derate 11.2 mW/°C above +70°C) . . . 890 mW

Q-24 Cerdip (Derate 12.5 mW/°C above +70°C) . . 1000 mW

D-24 Ceramic (Derate 20 mW/°C above +70°C) . . 1000 mW

*T his is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of this specifi-

cation is not implied. Exposure to absolute maximum rating conditions for

extended periods of time may affect reliability.

–2–

REV. 0

ADM223/ADM230L–ADM241L

O RD ERING GUID E

Tem perature

Range

P ackage

O ption*

Tem perature

Range

P ackage

O ption*

Tem perature

Range

P ackage

O ption*

Model

AD M223

AD M230L

AD M231L

ADM223AR

ADM223ARS –40°C to +85°C

–40°C to +85°C

R-28

RS-28

ADM230LJN

ADM230LJR

ADM230LAN

ADM230LAR

ADM230LAQ

0°C to +70°C

–40°C to +85°C

N-20

R-20

N-20

R-20

Q-20

ADM231LJN

ADM231LJR

ADM231LAN –40°C to +85°C N-14

ADM231LAR –40°C to +85°C R-16

ADM231LAQ –40°C to +85°C Q-14

0°C to +70°C

N-14

R-16

AD M232L

AD M233L

AD M234L

ADM232LJN

ADM232LJR

ADM232LAN –40°C to +85°C

ADM232LAR –40°C to +85°C

ADM232LAQ –40°C to +85°C

0°C to +70°C

N-16

R-16

N-16

R-16

Q-16

ADM233LJN

ADM233LAN

0°C to +70°C

–40°C to +85°C

N-20

ADM234LJN

ADM234LJR

ADM234LAN –40°C to +85°C N-16

ADM234LAR –40°C to +85°C R-16

ADM234LAQ –40°C to +85°C Q-16

0°C to +70°C

N-16

R-16

AD M235L

AD M236L

AD M237L

ADM235LJN

ADM235LAN –40°C to +85°C

ADM235LAQ –40°C to +85°C

0°C to +70°C

N-24A

D-24

ADM236LJN

ADM236LJR

ADM236LAN

ADM236LAR

ADM236LAQ

0°C to +70°C

–40°C to +85°C

N-24

R-24

N-24

R-24

Q-24

ADM237LJN

ADM237LJR

ADM237LAN –40°C to +85°C N-24

ADM237LAR –40°C to +85°C R-24

ADM237LAQ –40°C to +85°C Q-24

0°C to +70°C

N-24

R-24

AD M238L

AD M239L

AD M241L

ADM238LJN

ADM238LJR

ADM238LAN –40°C to +85°C

ADM238LAR –40°C to +85°C

ADM238LAQ –40°C to +85°C

0°C to +70°C

N-24

R-24

N-24

R-24

Q-24

ADM239LJN

ADM239LJR

ADM239LAN

ADM239LAR

ADM239LAQ

0°C to +70°C

–40°C to +85°C

N-24

R-24

N-24

R-24

Q-24

ADM241LJR

ADM241LAR –40°C to +85°C R-28

ADM241LJRS 0°C to +70°C RS-28

ADM241LARS –40°C to +85°C RS-28

0°C to +70°C

R-28

*D = Ceramic DIP; N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC); RS = Small Shrink Outline Package (SSOP).

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADM223/ADM230L–ADM241L features proprietary ESD protection circuitry, permanent

damage may occur on devices subjected to high energy electrostatic discharges. T herefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–3–

ADM223/ADM230L–ADM241L

+5V INPUT

7

1

2

20

19

18

17

16

15

14

T4

T3

OUT

IN

OUT

V

8

C1+

C1–

+5V TO +10V

VOLTAGE

DOUBLER

CC

T1

T5

1µF

6.3V

1µF

6.3V

10

9

3

T2

V+

V–

NC

SD

OUT

4

T2

T1

11

12

IN

C2+

C2–

+10V TO –10V

VOLTAGE

INVERTER

1µF

16V

13

1µF

16V

ADM230L

TOP VIEW

(Not to Scale)

5

T5

OUT

GND

6

T4

T3

IN

5

4

2

3

T1

IN

T1

T2

T3

T4

T5

T1

OUT

7

V

CC

C1+

V+

13 V–

12

11 C2+

8

T2

T3

T4

T2

T3

T4

T5

IN

9

C2–

TTL/CMOS

INPUTS

RS-232

OUTPUTS

14

15

1

IN

*

10

C1–

20

NC = NO CONNECT

T5

IN

19

18

16

17

OUT

Figure 1. ADM230L DIP/SOIC Pin Configuration

NC

SD

GND

ADM230L

6

*INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

D IP

Figure 2. ADM230L Typical Operating Circuit

C1+

C1–

V–

14

13

12

11

1

V+

V

2

3

CC

GND

T1

ADM231L

TOP VIEW

(Not to Scale)

+5V INPUT

1µF

4

5

6

7

T2

OUT

R2

IN

10 R1

IN

R1

9

R2

OUT

13

V

CC

T2

IN

8

T1

IN

1

2

14

3

+7.5V TO 13.2V

C+

C–

V+

V–

1µF

16V

+12V TO –12V

VOLTAGE

CONVERTER

1µF

16V

SO IC

8

11

4

T1

T2

T1

T2

IN

T1

T2

R1

R2

OUT

IN

TTL/CMOS

INPUTS

RS-232

OUTPUTS

V+

V

1

2

3

4

5

6

7

8

16

15

14

C1+

C1–

V–

*

IN

7

9

6

CC

GND

10

R1

R2

R1

R2

OUT

RS-232

INPUTS**

TTL/CMOS

OUTPUTS

ADM231L

TOP VIEW

(Not to Scale)

13 T1

12 R1

T2

OUT

5

IN

R2

IN

GND

12

ADM231L

11 R1

R2

OUT

IN

OUT

T2

IN

10

9

T1

NC

*

INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT

NC

NC = NO CONNECT

Figure 4. ADM231L Typical Operating Circuit (DIP Pinout)

Figure 3. ADM231L DIP & SOIC Pin Configurations

REV. 0

–4–

ADM223/ADM230L–ADM241L

+5V INPUT

1µF

6.3V

1

3

+5V TO +10V

VOLTAGE

DOUBLER

V

CC

16

2

C1+

C1–

1µF

6.3V

1µF

16

15

V

6.3V

1

2

3

4

5

6

7

8

C1+

V+

CC

V+

V–

GND

C2+

C2–

4

5

+10V TO –10V

VOLTAGE

INVERTER

1µF

16V

6

C1–

14 T1

13 R1

12 R1

1µF

16V

OUT

C2+

C2–

V–

ADM232L

TOP VIEW

(Not to Scale)

IN

11

10

T1

T2

R1

14

7

T1

T2

IN

T1

T2

OUT

TTL/CMOS

INPUTS

RS-232

OUTPUTS

*

11

10

9

T1

T2

IN

OUT

T2

OUT

IN

R1

13

8

12

9

OUT

IN

R2

IN

OUT

RS-232

INPUTS**

TTL/CMOS

OUTPUTS

R2

OUT

R2

IN

GND

15

ADM232L

Figure 5. ADM232L DIP/SOIC Pin Configuration

*

INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT

Figure 6. ADM232L Typical Operating Circuit

+5V INPUT

7

V

CC

2

1

T1

T2

5

18

4

T1

T2

T1

1

2

IN

T1

T2

20

19

R2

OUT

IN

OUT

TTL/CMOS

INPUTS

RS-232

OUTPUTS

*

IN

OUT

R1

3

18 T2

OUT

R1

OUT

R1

3

IN

V–

R1

4

17

16

15

14

13

12

11

IN

RS-232

INPUTS**

TTL/CMOS

OUTPUTS

ADM233L

TOP VIEW

(Not to Scale)

T1

5

C2–

C2+

V+

OUT

R2

OUT

20

19

R2

6

GND

DO NOT MAKE

CONNECTIONS TO

THESE PINS

8

C1+

C1–

V–

11

15

10

16

C2+

V

7

CC

13

12

17

14

8

C1+

C1–

V–

INTERNAL

–10V POWER

SUPPLY

C2–

GND

9

ADM233L

V–

10

C2–

C2+

INTERNAL

+10V POWER

SUPPLY

V+

GND

6

GND

9

*

INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT

Figure 7. ADM233L DIP Pin Configuration

Figure 8. ADM233L Typical Operating Circuit

REV. 0

–5–

ADM223/ADM230L–ADM241L

+5V INPUT

6

7

9

V

CC

C1+

C1–

+5V TO +10V

VOLTAGE

DOUBLER

1µF

6.3V

1µF

6.3V

8

V+

V–

T1

T2

16 T3

1

2

3

4

5

6

7

8

OUT

10

11

C2+

C2–

+10V TO –10V

VOLTAGE

INVERTER

15

14

T4

OUT

12

1µF

16V

1µF

16V

T2

IN

T1

13 T3

12 V–

ADM234L

TOP VIEW

(Not to Scale)

IN

T1

T2

T3

T4

1

4

3

T1

T2

T3

T1

IN

OUT

GND

T2

T3

T4

IN

2

C2–

C2+

C1–

V

11

10

9

CC

RS-232

OUTPUTS

TTL/CMOS

INPUTS*

C1+

V+

13

14

16

15

IN

T4

GND

5

ADM234L

*INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

Figure 9. ADM234L DIP/SOIC Pin Configuration

Figure 10. ADM234L Typical Operating Circuit

+5V INPUT

1µF

12

V

CC

T1

T2

8

7

IN

3

T1

T2

T3

T4

T1

T2

OUT

T4

T3

T1

T2

1

24 R3

OUT

IN

4

2

R3

OUT

23

TTL/CMOS

INPUTS*

RS-232

OUTPUTS

T3

IN

T4

IN

T3

T4

T5

15

16

3

4

22 T5

IN

SD

EN

21

20

1

R2

5

IN

T5

IN

22

9

T5

OUT

19

10

R2

6

ADM235L

TOP VIEW

(Not to Scale)

19 T5

OUT

R1

OUT

R2

OUT

R3

OUT

R4

OUT

IN

T2

7

18 R4

17 R4

16 T4

IN

T1

8

OUT

R2

6

R2

5

R1

9

OUT

IN

TTL/CMOS

OUTPUTS

RS-232

INPUTS**

R3

R4

23

17

R3

R4

24

18

IN

R1

10

11

12

15 T3

IN

GND

14

R5

IN

OUT

V

13 R5

CC

IN

14

20

R5

SD

R5

IN

OUT

EN

13

21

GND

11

ADM235L

*INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT

Figure 11. ADM235L DIP Pin Configuration

Figure 12. ADM235L Typical Operating Circuit

REV. 0

–6–

ADM223/ADM230L–ADM241L

+5V INPUT

10

12

C1+

C1–

9

V

CC

+5V TO +10V

VOLTAGE

DOUBLER

1µF

6.3V

1µF

6.3V

1µF

V+ 11

13

14

T3

T1

24 T4

C2+

C2–

1

+10V TO –10V

VOLTAGE

INVERTER

OUT

1µF

16V

V–

15

2

1µF

16V

2

23

R2

OUT

IN

3

4

T2

22 R2

OUT

7

6

T1

T2

T1

T2

T3

T1

OUT

IN

SD

R1

21

20

IN

OUT

T2

OUT

3

1

R1

T2

5

EN

RS-232

OUTPUTS

TTL/CMOS

INPUTS

6

ADM236L

TOP VIEW

(Not to Scale)

19 T4

*

IN

18

T3

T4

R1

R2

T3

T4

OUT

T3

18

T1

7

24

4

T4

19

5

OUT

GND

8

17 R3

16 R3

OUT

V

9

R1

CC

IN

OUT

IN

C1+

V–

10

11

12

15

14

13

TTL/CMOS

OUTPUTS

RS-232

INPUTS**

R2

R3

23

22

17

20

C2–

C2+

V+

R3

16

21

R3

IN

C1–

OUT

EN

SD

GND

ADM236L

8

*

INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT

Figure 13. ADM236L DIP/SOIC Pin Configuration

Figure 14. ADM236L Typical Operating Circuit

+5V INPUT

10

V

+5V TO +10V

VOLTAGE

DOUBLER

C1+

9

CC

1µF

6.3V

1µF

6.3V

1µF

12 C1–

V+ 11

C2+

C2–

13

14

+10V TO –10V

VOLTAGE

INVERTER

T3

T1

24 T4

1

1µF

16V

OUT

15

V–

1µF

16V

2

23

R2

OUT

IN

3

4

T2

22 R2

OUT

IN

T1

T2

T3

T4

T1

7

6

2

3

T1

T2

IN

OUT

R1

21

20

T5

IN

OUT

T2

OUT

R1

T2

5

OUT

IN

TTL/CMOS

INPUTS

RS-232

OUTPUTS

6

ADM237L

TOP VIEW

(Not to Scale)

19 T4

T3

T4

IN

1

T3

T4

18

19

OUT

*

T1

7

18

IN

24

OUT

GND

8

17 R3

16 R3

OUT

20

21

T5

OUT

T5

R1

R2

V

9

CC

IN

C1+

V–

10

11

12

15

14

13

R1

R2

4

5

OUT

IN

C2–

C2+

V+

TTL/CMOS

OUTPUTS

RS-232

INPUTS**

R2

R3

23

16

22

17

C1–

R3

IN

OUT

GND

ADM237L

8

*

INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT

Figure 15. ADM237L DIP/SOIC Pin Configuration

Figure 16. ADM237L Typical Operating Circuit

REV. 0

–7–

ADM223/ADM230L–ADM241L

+5V INPUT

9

C1+

V

CC

10

+5V TO +10V

VOLTAGE

DOUBLER

1µF

6.3V

1µF

6.3V

12 C1–

V+ 11

T2

T1

24 T3

1

13

14

C2+

C2–

+10V TO –10V

VOLTAGE

INVERTER

OUT

1µF

16V

V–

15

2

1µF

16V

2

23

R3

OUT

IN

R2

3

4

22 R3

IN

OUT

IN

5

T1

T2

T1

T2

T3

T1

OUT

IN

R2

21

20

T4

OUT

T2

OUT

18

19

1

T1

IN

5

OUT

IN

TTL/CMOS

INPUTS

RS-232

OUTPUTS

*

R1

6

ADM238L

TOP VIEW

(Not to Scale)

19 T3

18 T2

OUT

24

T3

T4

R1

R2

T3

T4

OUT

R1

IN

7

IN

T4

21

6

20

7

OUT

GND

8

17 R4

16 R4

OUT

V

R1

R2

9

OUT

IN

CC

IN

C1+

V–

10

11

12

15

14

13

4

3

R2

TTL/CMOS

OUTPUTS

RS-232

INPUTS**

C2–

C2+

V+

22

17

R3

R4

23

16

R3

R4

R3

R4

IN

OUT

C1–

IN

GND

8

ADM238L

*

INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT

Figure 17. ADM238L DIP/SOIC Pin Configuration

Figure 18. ADM238L Typical Operating Circuit

+5V INPUT

1µF

V

4

5

8

CC

6

7

+12V TO –12V

VOLTAGE

INVERTER

C1+

C1–

1µF

16V

+7.5V TO +13.2V

INPUT

V+

V–

R1

24 T1

1

OUT

IN

1µF

16V

R1

2

23

T2

IN

GND

3

4

22 R2

OUT

T1

T2

T1

T2

T1

IN

24

23

19

20

13

2

OUT

V

21

20

R2

T2

CC

IN

RS-232

OUTPUTS

TTL/CMOS

INPUTS

T2

OUT

V+

C+

5

*

OUT

6

ADM239L

TOP VIEW

(Not to Scale)

19 T1

16

1

T3

R1

R2

T3

OUT

R3

7

18

C–

V–

IN

R1

R2

OUT

IN

8

17 R3

16 T3

OUT

R2

21

22

R5

IN

9

IN

NC

R5

10

11

12

15

14

13

TTL/CMOS

OUTPUTS

RS-232

INPUTS**

OUT

18

12

R3

R4

R3

R4

17

11

R3

R4

OUT

IN

R4

EN

T3

R4

IN

OUT

10

14

R5

9

IN

OUT

EN

NC = NO CONNECT

15

NC

GND

ADM239L

3

*

INTERNAL 400kΩ PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5kΩ PULL-DOWN RESISTOR ON EACH RS-232 INPUT

Figure 19. ADM239L DIP/SOIC Pin Configuration

Figure 20. ADM239L Typical Operating Circuit

REV. 0

–8–

ADM223/ADM230L–ADM241L

+5V INPUT

12

14

11

13

V

C1+

C1–

+5V TO +10V

VOLTAGE

DOUBLER

CC

1µF

6.3V

1µF

16V

1µF

V+

1

2

28 T4

T3

T1

T2

OUT

15 C2+

+10V TO –10V

VOLTAGE

INVERTER

17

V–

R3

27

26

25

24

23

22

21

20

19

1µF

16V

OUT

IN

1µF

16V

16

7

C2–

3

R3

SD

OUT

R2

4

2

3

T1

T2

T1

T2

T3

T4

R1

R2

R3

R4

R5

T1

IN

OUT

IN

OUT

R2

5

EN

R4

6

T2

TTL/CMOS

RS-232

OUTPUTS

T2

6

IN

INPUTS

*

20

21

8

1

28

9

T3

T4

OUT

T1

7

R4

ADM241L

TOP VIEW

(Not to Scale)

IN

OUT

T4

T3

R1

8

IN

OUT

R1

9

IN

R1

R2

OUT

IN

GND

10

11

12

13

14

R5

OUT

IN

4

5

R2

V

18 R5

CC

RS-232

INPUTS**

TTL/CMOS

OUTPUTS

26

22

27

23

R3

R4

R3

R4

C1+

V–

OUT

IN

17

16

15

V+

C2–

C2+

C1–

19

24

18

25

R5

SD

R5

IN

OUT

EN

ADM241L

GND

10

*

INTERNAL 400k Ω PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5k Ω PULL-DOWN RESISTOR ON EACH RS-232 INPUT

Figure 21. ADM241L SOIC/SSOP Pin Configuration

Figure 22. ADM241L Typical Operating Circuit

+5V INPUT

12

14

11

13

V

C1+

C1–

+5V TO +10V

VOLTAGE

DOUBLER

CC

1µF

6.3V

1µF

16V

1µF

1

2

28 T4

T3

T1

T2

OUT

V+

R3

27

26

25

24

23

22

21

20

19

OUT

IN

15 C2+

+10V TO –10V

VOLTAGE

INVERTER

17

V–

1µF

16V

1µF

16V

3

R3

SD

OUT

16

7

C2–

R2

4

IN

OUT

2

3

T1

T2

T3

T4

R1

R2

T1

T2

T1

IN

OUT

R2

5

EN

R4

T2

6

T2

IN

TTL/CMOS

RS-232

OUTPUTS

INPUTS

*

T1

7

R4

ADM223

TOP VIEW

(Not to Scale)

IN

OUT

20

21

8

1

28

9

T3

T4

OUT

T4

T3

R1

8

IN

OUT

T4

R1

9

IN

R1

R2

GND

10

11

12

13

14

R5

OUT

IN

OUT

IN

V

18 R5

CC

4

5

R2

C1+

V–

17

16

15

RS-232

INPUTS**

TTL/CMOS

OUTPUTS

26

22

27

23

R3

R4

R5

R3

R4

R3

R4

OUT

IN

V+

C2–

C2+

C1–

19

24

18

25

R5

SD

R5

IN

OUT

EN

ADM223

GND

10

*

INTERNAL 400k Ω PULL-UP RESISTOR ON EACH TTL/CMOS INPUT

**INTERNAL 5k Ω PULL-DOWN RESISTOR ON EACH RS-232 INPUT

NOTE: RECEIVERS R4 AND R5 REMAIN ACTIVE IN SHUTDOWN.

Figure 23. ADM223 SOIC/SSOP Pin Configuration

Figure 24. ADM223 Typical Operating Circuit

REV. 0

–9–

ADM223/ADM230L–ADM241L

P IN FUNCTIO N D ESCRIP TIO N

Mnem onic

Function

V_CC

V+

Power Supply Input 5 V ± 10% (+5 V ± 5% ADM233L, ADM235L).

Internally generated positive supply (+10 V nominal) on all parts except ADM231L and ADM239L.

ADM231L, ADM239L requires external 7.5 V to 13.2 V supply.

V–

Internally generated negative supply (–10 V nominal).

GND

C+

Ground pin. Must be connected to 0 V.

(ADM231L and ADM239L only). External capacitor (+ terminal) is connected to this pin.

(ADM231L and ADM239L only). External capacitor (– terminal) is connected to this pin.

C–

C1+

(ADM230L, ADM232L, ADM234L, ADM236L, ADM237L, ADM238L, ADM241L) External capacitor (+ terminal)

is connected to this pin.

(ADM233L) T he capacitor is connected internally and no external connection to this pin is required.

C1–

C2+

C2–

T_IN

(ADM230L, ADM232L, ADM234L, ADM236L, ADM237L, ADM238L, ADM241L) External capacitor (– terminal)

is connected to this pin.

(ADM233L) T he capacitor is connected internally and no external connection to this pin is required.

(ADM230L, ADM232L, ADM234L, ADM236L, ADM237L, ADM238L, ADM241L) External capacitor (+ terminal)

is connected to this pin.

(ADM233L) Internal capacitor connections, Pins 11 and 15 must be connected together.

(ADM230L, ADM232L, ADM234L, ADM236L, ADM237L, ADM238L, ADM241L) External capacitor (– terminal)

is connected to this pin.

(ADM233L) Internal capacitor connections, Pins 10 and 16 must be connected together.

T ransmitter (Driver) Inputs. T hese inputs accept T T L/CMOS levels. An internal 400 kΩ pull-up resistor to V_CCis

connected on each input.

T _OUT

R_IN

T ransmitter (Driver) Outputs. T hese are RS-232 levels (typically ±10 V).

Receiver Inputs. These inputs accept RS-232 signal levels. An internal 5 kΩ pull-down resistor to GND is connected on

each input.

R_OUT

Receiver Outputs. T hese are T T L/CMOS levels.

EN/EN

Enable Input. Active low on ADM235L, ADM236L, ADM239L, ADM241L. Active high ADM223. This input is used

to enable/disable the receiver outputs. With EN = low (EN = high ADM223), the receiver outputs are enabled. With

EN = high (EN = low ADM223), the outputs are placed in a high impedance state. T his facility is useful for

connecting to microprocessor systems.

SD/SD

Shutdown Input. Active high on ADM235L, ADM236L, ADM241L. Active low on ADM223. With SD = high on the

ADM235L, ADM236L, ADM241L, the charge pump is disabled, the receiver outputs are placed in a high impedance

state and the driver outputs are turned off. With SD low on the ADM223, the charge pump is disabled, the driver

outputs are turned off and all receivers except R4 and R5 are placed in a high impedance state. In shutdown, the power

consumption reduces to 5 µW.

NC

No Connect. No connections are required to this pin.

Table I. AD M235L, AD M236L, AD M241L Truth Table

Table II. AD M223 Truth Table

Transm itters Receivers

Transm itters

T1–T5

Receivers

R1–R5

SD EN

Status

SD EN Status

T1–T4

R1–R3 R4, R5

0

1

0

1

0

Normal Operation

Shutdown

Enabled

Disabled

Enabled

Disabled

0

1

0

1

0

1

Shutdown

Normal Operation Enabled

Disabled

Disabled Disabled

Disabled Enabled

Disabled Disabled

Enabled Enabled

REV. 0

–10–

ADM223/ADM230L–ADM241L

10

8

10

8

V+

V

(1 O/P LOADED)

OUT

| V– |

6

4

2

0

V

(ALL O/Ps LOADED)

OUT

6

4

0

10

20

— mA

30

40

3.0

4.0

5.0

I

V

– V

OUT

CC

Figure 25. Charge Pum p V+, V– vs. Current

Figure 27. Transm itter Output Voltage vs. V_CC

12

10

18

16

T

HIGH

OUT

14

12

8

6

4

2

0

T

LOW

OUT

10

8

6

4

2

4

– mA

6

8

0

500

1000

1500

2000

2500

I

OUT

CAPACITIVE LOAD – pF

Figure 28. Transm itter Output Voltage vs. Current

Figure 26. Transm itter Slew Rate vs. Load Capacitance

300

200

100

V– (UNLOADED)

V– (LOADED)

V+ (UNLOADED)

V+ (LOADED)

0

3

4

5

V

CC

– V

Figure 29. Charge Pum p Im pedance vs. V_CC

REV. 0

–11–

ADM223/ADM230L–ADM241L

A3

0.8 V

A3

0.8 V

100

90

100

90

10

0%

H

O

^B_w5

1ms

^B_w5

L

5µs

O

5V

L

Figure 30. Charge Pum p, V+, V– Exiting Shutdown

Figure 31. Transm itter Output Loaded Slew Rate

A3

0.8 V

100

90

10

0%

H

O

^B_w5

1µs

5V

L

Figure 32. Transm itter Output Unloaded Slew Rate

GENERAL INFO RMATIO N

CIRCUIT D ESCRIP TIO N

T he ADM223/ADM230L–ADM241L family of RS-232 drivers/

receivers are designed to solve interface problems by meeting

the EIA-232-E specifications while using a single digital +5 V

supply. T he EIA-232-E standard requires transmitters which

will deliver ±5 V minimum on the transmission channel and

receivers which can accept signal levels down to ±3 V. T he

ADM223/ADM230L–ADM241L meet these requirements by

integrating step up voltage converters and level shifting trans-

mitters and receivers onto the same chip. CMOS technology is

used to keep the power dissipation to an absolute minimum. A

comprehensive range of transmitter/receiver combinations is

available to cover most communications needs.

T he internal circuitry in the ADM230L–ADM241L consists of

three main sections. T hese are:

(a) A charge pump voltage converter

(b) RS-232 to T T L/CMOS receivers

(c) T T L/CMOS to RS-232 transmitters

Char ge P um p D C-D C Voltage Conver ter

T he charge pump voltage converter consists of an oscillator and

a switching matrix. T he converter generates a ±10 V supply

from the input 5 V level. T his is done in two stages using a

switched capacitor technique as illustrated in Figures 33 and 34.

First, the 5 V input supply is doubled to 10 V using capacitor

C1 as the charge storage element. T he 10 V level is then in-

verted to generate –10 V using C2 as the storage element.

T he ADM223, ADM230L, ADM235L, ADM236L and

ADM241L are particularly useful in battery powered systems as

they feature a low power shutdown mode which reduces power

dissipation to less than 5 µW.

S1

S3

V

V+ = 2V

CC

C1

C3

T he ADM233L and ADM235L are designed for applications

where space saving is important as the charge pump capacitors

are molded into the package.

S2

S4

GND

V

CC

INTERNAL

OSCILLATOR

T he ADM231L and ADM239L include only a negative charge

pump converter and are intended for applications where a posi-

tive 12 V is available.

Figure 33. Charge-Pum p Voltage Doubler

To facilitate sharing a common line or for connection to a micro-

processor data bus the ADM235L, ADM236L, ADM239L and

ADM241L feature an enable (EN, EN) function. When disabled,

the receiver outputs are placed in a high impedance state.

REV. 0

–12–

ADM223/ADM230L–ADM241L

S1

S2

S3

S4

Enable Input

GND

V+

T he ADM235, ADM239, ADM241L and ADM223 feature an

enable input used to enable or disable the receiver outputs. T he

enable input is active low on the ADM235L, ADM239L,

ADM241L and active high on the ADM223. Refer to T ables I

and II. When disabled, all receiver outputs are placed in a high

impedance state. T his function allows the outputs to be con-

nected directly to a microprocessor data bus. It can also be used

to allow receivers from different devices to share a common data

line. T he timing diagram for the enable function is shown in

Figure 35.

FROM

VOLTAGE

DOUBLER

C2

C4

GND

V– = – (V+)

INTERNAL

OSCILLATOR

Figure 34. Charge-Pum p Voltage Inverter

Capacitors C3 and C4 are used to reduce the output ripple.

T heir values are not critical and can be reduced if higher levels

of ripple are acceptable. T he charge pump capacitors C1 and

C2 may also be reduced at the expense of higher output imped-

ance on the V+ and V– supplies.

3V

EN*

0V

T he V+ and V– supplies may also be used to power external cir-

cuitry if the current requirements are small.

T

DIS

EN

V

– 0.1V

+ 0.1V

3.5V

0.8V

OH

Tr ansm itter (D r iver ) Section

R

OUT

T he drivers convert T T L/CMOS input levels into EIA-232-E

output levels. With V_CC= +5 V and driving a typical EIA-232-E

load, the output voltage swing is ±9 V. Even under worst case

conditions the drivers are guaranteed to meet the ±5 V

EIA-232-E minimum requirement.

VOL

*POLARITY OF EN IS REVERSED FOR ADM223.

Figure 35. Enable Tim ing

T he input threshold levels are both T T L and CMOS compat-

ible with the switching threshold set at V_CC/4. With a nominal

V_CC= 5 V the switching threshold is 1.25 V typical. Unused in-

puts may be left unconnected, as an internal 400 kΩ pull-up re-

sistor pulls them high forcing the outputs into a low state.

AP P LICATIO N H INTS

D r iving Long Cables

In accordance with the EIA-232-E standard, long cables are per-

missible provided that the total load capacitance does not exceed

2500 pF. For longer cables which do exceed this, then it is pos-

sible to trade off baud rate vs. cable length. Large load capaci-

tances cause a reduction in slew rate, and hence the maximum

transmission baud rate is decreased. The ADM230L-ADM241L

are designed so that the slew rate reduction with increasing load

capacitance is minimized.

As required by the EIA-232-E standard, the slew rate is limited

to less than 30 V/µs without the need for an external slew limit-

ing capacitor and the output impedance in the power-off state is

greater than 300 Ω.

Receiver Section

T he receivers are inverting level shifters which accept EIA-

232-E input levels (±5 V to ±15 V) and translate them into 5 V

T T L/CMOS levels. T he inputs have internal 5 kΩ pull-down

resistors to ground and are also protected against overvoltages of

up to ±30 V. T he guaranteed switching thresholds are 0.8 V

minimum and 2.4 V maximum which are well within the ±3 V

EIA-232-E requirement. T he low level threshold is deliberately

positive as it ensures that an unconnected input will be inter-

preted as a low level.

For the receivers, it is important that a high level of noise immu-

nity be inbuilt so that slow rise and fall times do not cause mul-

tiple output transitions as the signal passes slowly through the

transition region. T he ADM230L-ADM241L have 0.5 V of hys-

teresis to guard against this. T his ensures that, even in noisy en-

vironments, error-free reception can be achieved.

H igh Baud Rate O per ation

T he ADM230L-ADM241L feature high slew rates permitting

data transmission at rates well in excess of the EIA-232-E speci-

fication. T he drivers maintain ±5 V signal levels at data rates up

to 100-kB/s under worst-case loading conditions.

T he receivers have Schmitt trigger inputs with a hysteresis level

of 0.5 V. T his ensures error-free reception for both noisy inputs

and for inputs with slow transition times.

Shutdown (SD )

T he ADM223, ADM230L, ADM235L, ADM236L and

ADM241L feature a control input that may be used to disable

the part and reduce the power consumption to less than 5 µW.

T his is very useful in battery operated systems. During shut-

down the charge pump is turned off, the transmitters are dis-

abled and all receivers except R4 and R5 on the ADM223 are

put into a high-impedance disabled state. Receivers R4 and R5

on the ADM223 remain enabled during shutdown. T his feature

allows monitoring external activity such as ring indicator moni-

toring while the device is in a low power shutdown mode.

T he shutdown control input is active high on all parts except the

ADM223 where it is active low. Refer to T ables I and II.

REV. 0

–13–

ADM223/ADM230L–ADM241L

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

14-Lead P lastic D IP (N-14)

14-Lead Cer dip (Q -14)

14

1

8

14

8

0.280 (7.11)

0.240 (6.10)

PIN 1

0.271 (6.89)

0.240 (6.09)

PIN 1

7

1

0.325 (8.25)

0.795 (20.19)

0.725 (18.42)

0.300 (7.62)

REF

0.300 (7.62)

0.780 (19.81)

0.060 (1.52)

0.015 (0.38)

0.195 (4.95)

0.115 (2.93)

0.163 (4.14)

0.210

(5.33)

0.133 (3.378)

0.150

(3.81)

0.21 (5.33)

0.15 (3.81)

0.125

(3.17)

MIN

0.200 (5.05)

0.125 (3.18)

0.015 (0.381)

0.008 (0.204)

0.012 (0.305)

0.008 (0.203)

15

°

SEATING

PLANE

0.070 (1.77)

0.045 (1.15)

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

SEATING

PLANE

0

°

0.02 (0.5)

0.11 (2.79)

0.06 (1.52)

0.05 (1.27)

0.016 (0.406)

0.099 (2.28)

16-Lead P lastic D IP (N-16)

16-Lead Cer dip (Q -16)

16

1

9

0.280 (7.11)

0.240 (6.10)

16

1

9

PIN 1

0.271 (6.89)

0.240 (6.09)

PIN 1

8

0.325 (8.25)

0.300 (7.62)

0.840 (21.33)

0.745 (18.93)

0.300 (7.62)

REF

0.780 (19.81)

0.060 (1.52)

0.015 (0.38)

0.195 (4.95)

0.115 (2.93)

0.210

0.163 (4.14)

(5.33)

0.133 (3.378)

0.150

(3.81)

0.200 (5.05)

0.125 (3.18)

0.015 (0.381)

0.008 (0.204)

0.125

(3.17)

MIN

0.012 (0.305)

0.008 (0.203)

0.21 (5.33)

0.15 (3.81)

15°

0°

SEATING

PLANE

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

0.100

(2.54)

BSC

SEATING

PLANE

0.02 (0.5)

0.11 (2.79)

0.06 (1.52)

0.05 (1.27)

0.016 (0.406) 0.099 (2.28)

16-Lead SO IC (R-16)

9

16

0.299 (7.60)

0.291 (7.40)

0.419 (10.65)

0.404 (10.26)

PIN 1

8

1

0.107 (2.72)

0.089 (2.26)

0.413 (10.50)

0.348 (10.10)

0.364 (9.246)

0.344 (8.738)

0.045 (1.15)

0.020 (0.50)

0.010 (0.25)

0.004 (0.10)

0.018 (0.46)

0.014 (0.36)

0.015 (0.38)

0.007 (1.18)

0.050 (1.27)

BSC

REV. 0

–14–

ADM223/ADM230L–ADM241L

20-Lead P lastic D IP (N-20)

20-Lead Cer dip (Q -20)

20

11

20

1

11

0.280 (7.11)

0.28 (7.11)

PIN 1

0.240 (6.10)

10

0.24 (6.1)

10

1

0.97 (24.64)

0.32 (8.128)

0.29 (7.366)

1.060 (26.90)

0.925 (23.50)

0.325 (8.25)

0.300 (7.62)

0.935 (23.75)

0.060 (1.52)

0.015 (0.38)

0.18 (4.57)

0.195 (4.95)

0.115 (2.93)

0.20 (5.0)

0.210

(5.33)

0.125 (3.18)

0.14 (3.56)

0.150

(3.81)

0.011 (0.28)

0.009 (0.23)

0.015 (0.381)

0.008 (0.204)

0.15 (3.8)

0.200 (5.05)

0.125 (3.18)

15

°

SEATING

PLANE

0

°

SEATING

PLANE

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

0.070 (1.78)

0.045 (1.15)

0.02 (0.5)

0.07 (1.78)

0.05 (1.27)

0.11 (2.79)

0.09 (2.28)

0.016 (0.41)

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

24-Lead Cer am ic D IP (D -24)

20-Lead SO IC (R-20)

0.005 (0.13)

0.098 (2.49)

20

11

24

13

0.2992 (7.60)

0.2914 (7.40)

0.610 (15.49)

0.500 (12.70)

PIN 1

0.4193 (10.65)

1

12

0.3937 (10.00)

10

0.620 (15.75)

0.590 (14.99)

1

PIN 1

0.075 (1.91)

1.290 (32.77)

0.015 (0.38)

0.225

(5.72)

0.1043 (2.65)

0.015 (0.38)

0.008 (0.20)

0.5118 (13.00)

0.150

(3.81)

0.0926 (2.35)

0.200 (5.08)

0.120 (3.05)

0.0291 (0.74)

0.4961 (12.60)

x 45

°

0.0098 (0.25)

SEATING

PLANE

0.023 (0.58)

0.014 (0.36)

0.110 (2.79)

0.090 (2.29)

0.070 (1.78)

0.030 (0.76)

0.0500 (1.27)

8

0

°

0.0118 (0.30)

0.0040 (0.10)

0.0157 (0.40)

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0125 (0.32)

0.0091 (0.23)

24-Lead P lastic D IP (N-24A)

24-Lead P lastic D IP (N-24)

13

24

13

24

PIN 1

0.260 ± 0.001

0.55 (13.97)

0.53 (13.47)

(6.61 ± 0.03)

12

1

PIN 1

12

1

1.228 (31.19)

1.226 (31.14)

0.32 (8.128)

0.30 (7.62)

1.25 (31.75)

1.24 (31.5)

0.606 (15.4)

0.594 (15.09)

0.130 (3.30)

0.128 (3.25)

0.2

(5.08)

0.16 (4.07)

0.14 (3.56)

MAX

SEATING

PLANE

0.175

(4.45)

0.12 (3.05)

0.011 (0.28)

0.009 (0.23)

15

0

°

15

°

0.012 (0.305)

0.008 (0.203)

0.02 (0.5)

0.016 (0.41)

0.11 (2.79)

0.07 (1.78)

0°

SEATING

PLANE

0.02 (0.508)

0.015 (0.381)

0.105 (2.67)

0.095 (2.42)

0.065 (1.66)

0.045 (1.15)

0.09 (2.28)

0.05 (1.27)

NOTES

1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

2. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN PLATED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

REV. 0

–15–

24-Lead Cer dip (Q -24)

28-Lead SO IC (R-28)

13

24

1

PIN 1

0.295 (7.493)

MAX

28

1

15

0.299 (7.6)

12

0.291 (7.39)

0.320 (8.128)

0.290 (7.366)

1.290 (32.77) MAX

0.414 (10.52)

0.398 (10.10)

PIN 1

0.180

(4.572)

MAX

0.225

(5.715)

MAX

14

SEATING

PLANE

0.125

(3.175)

MIN

0.096 (2.44)

0.012 (0.305)

0.708 (18.02)

0.696 (17.67)

0.089 (2.26)

0.070 (1.778)

0.020 (0.508)

15

°

0.110 (2.794)

0.021 (0.533)

0.015 (0.381)

TYP

0.008 (0.203)

TYP

0.065 (1.651)

0.03 (0.76)

0.02 (0.51)

0.090 (2.286)

TYP

0.055 (1.397)

TYP

0°

1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.

0.042 (1.067)

0.018 (0.457)

2. CERDIP LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

6

0

°

0.01 (0.254)

0.006 (0.15)

0.019 (0.49)

0.014 (0.35)

0.05 (1.27)

BSC

0.013 (0.32)

0.009 (0.23)

1. LEAD NO. IDENTIFIED BY A DOT.

2. SOICLEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

24-Lead SO IC (R-24)

28-Lead SSO P (RS-28)

24

13

28

15

0.299 (7.6)

0.212 (5.38)

0.205 (5.207)

0.291 (7.39)

0.414 (10.52)

0.311 (7.9)

0.301 (7.64)

PIN 1

0.398 (10.10)

12

PIN 1

1

14

0.096 (2.44)

0.608 (15.45)

0.07 (1.78)

0.066 (1.67)

0.089 (2.26)

0.407 (10.34)

0.397 (10.08)

0.596 (15.13)

0.03 (0.76)

0.02 (0.51)

0.037 (0.94)

0.022 (0.559)

8

0

°

0.042 (1.067)

0.018 (0.447)

6°

0°

0.008 (0.203)

0.002 (0.050)

0.01 (0.254)

0.006 (0.15)

0.0256 (0.65)

BSC

0.05 (1.27)

BSC

0.019 (0.49)

0.014 (0.35)

0.009 (0.229)

0.005 (0.127)

0.013 (0.32)

0.009 (0.23)

1. LEAD NO. 1 IDENTIFIED BY A DOT.

2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

1. LEAD NO. 1 IDENTIFIED BY A DOT.

2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

–16–

型号:	ADM232LAR
Source Url Status Check Date：	2013-05-01 14:56:40.752
Brand Name：	Analog Devices Inc
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	SOIC
包装说明：	SOP, SOP16,.4
针数：	16
制造商包装代码：	RW-16
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	7.72
其他特性：	INTERNAL CHARGE PUMP
差分输出：	NO
驱动器位数：	2
高电平输入电流最大值：	0.000025 A
输入特性：	SCHMITT TRIGGER
接口集成电路类型：	LINE TRANSCEIVER
接口标准：	EIA-232-E; V.28
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0
长度：	10.3 mm
湿度敏感等级：	1
功能数量：	2
端子数量：	16
最高工作温度：	85 °C
最低工作温度：	-40 °C
最小输出摆幅：	10 V
输出特性：	TOTEM-POLE
最大输出低电流：	0.0032 A
输出极性：	INVERTED
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP16,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240
电源：	5 V
认证状态：	Not Qualified
最大接收延迟：
接收器位数：	2
座面最大高度：	2.65 mm
子类别：	Line Driver or Receivers
最大压摆率：	6 mA
最大供电电压：	5.5 V
最小供电电压：	4.5 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	7.5 mm
Base Number Matches：	1

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