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产品型号ADP1864AUJZ-R7的概述

芯片ADP1864AUJZ-R7概述 ADP1864AUJZ-R7是一款由Analog Devices, Inc.设计和生产的高性能电源管理集成电路（PMIC），广泛应用于各种电子设备中，特别是在需要高效率和灵活性的电源解决方案的场合。作为一款数字控制的降压转换器，ADP1864AUJZ-R7具有良好的电源转化效率和稳定的输出特性，能够满足复杂负载条件下的电源需求。 ADP1864AUJZ-R7集成了多种功能，包括高达4A的输出电流、可调节的输出电压范围以及丰富的监控和保护功能。这使得它既适合单一设备的应用，也可以在多个并行系统中使用，以便于处理更高的功率需求。该芯片还可以通过I2C接口进行配置和监控，赋予设计人员灵活的应用选择。通过采用先进的电流控制技术，ADP1864AUJZ-R7能够保持高效率，特别是在轻载条件下。此外，芯片内置了多种保护功能，诸如过流保护、过温保护和欠压锁定等，...

产品型号ADP1864AUJZ-R7的Datasheet PDF文件预览

Constant Frequency Current-Mode

Step-Down DC/DC Controller in TSOT

ADP1864

FEATURES

GENERAL DESCRIPTION

Wide input voltage range: 3.15 V to 14 V

Wide output voltage range: 0.8 V to input voltage

Pin-to-pin compatible with LTC1772, LTC3801

Up to 94% efficiency

0.8 V 1.25% reference accuracy over temperature

Internal soft start

The ADP1864 is a compact, inexpensive, constant-frequency

current-mode step-down DC-to-DC controller. The ADP1864

drives a P-channel MOSFET that regulates an output voltage as

low as 0.8 V with ±±2 accuracy, for up to 5 A load currents,

from input voltages as high as 14 V.

The ADP1864 provides system flexibility by allowing accurate

setting of the current limit with an external resistor, while the

output voltage is easily adjustable using two external resistors.

The ADP1864 includes an internal soft start to allow quick

power-up while preventing input inrush current. Additional

safety features include short-circuit protection, output over-

voltage protection, and input under voltage protection.

Current-mode control provides fast and stable load transient

performance, while the 580 kHz operating frequency allows a

small inductor to be used in the system. To further the life of a

battery source, the controller turns on the external P-channel

MOSFET 1002 of the duty cycle in dropout.

100% duty cycle for low dropout voltage

Current-mode operation for good line and load transient

response

7 μA shutdown current

235 μA quiescent supply current

Short-circuit and overvoltage protection

Small 6-lead TSOT package

APPLICATIONS

Wireless devices

1- to 3-cell Li-Ion battery-powered applications

Set-top boxes

Processor core power supplies

Hard disk drives

The ADP1864 operates over the −40°C to +85°C temperature

range and is available in a small, low profile, 6-lead TSOT

package.

MOSFET = FDC638P

VOUT = 2.5V

100

ADP1864

VIN = 3.3V to 10V

10μF

15kΩ

COMP

470pF

0.03Ω

3.3V

GND

5μH

80.6kΩ

2.5V, 2.0A

PGATE

4.2V

47μF

174kΩ

5.0V

0.01

0.1

1.0

10.0

EFFICIENCY vs. LOAD CURRENT FOR APPLICATION

Figure 1. Typical Applications Diagram

Figure 2. Efficiency vs. Load Current

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADP1864

TABLE OF CONTENTS

Features .............................................................................................. 1

Application Information................................................................ 10

Duty Cycle................................................................................... 10

Ripple Current ............................................................................ 10

Sense Resistor.............................................................................. 10

Inductor Value ............................................................................ 10

MOSFET...................................................................................... 11

Diode............................................................................................ 11

Input Capacitor........................................................................... 11

Output Capacitor........................................................................ 11

Feedback Resistors ..................................................................... 1±

Layout Considerations................................................................... 13

Example Applications Circuits ..................................................... 14

Outline Dimensions....................................................................... 15

Ordering Guide .......................................................................... 15

Applications....................................................................................... 1

General Description......................................................................... 1

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ........................................................................ 8

Loop Start-Up ............................................................................... 8

Short-Circuit Protection.............................................................. 9

Undervoltage Lockout (UVLO) ................................................. 9

Overvoltage Lockout Protection (OVP).................................... 9

Soft Start ........................................................................................ 9

REVISION HISTORY

10/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

ADP1864

SPECIFICATIONS

V_IN= 5 V, T_A= ±5°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

POWER SUPPLY

Input Voltage

V_IN

I_Q

I_SD

3.15

350

3.01

3.10

Quiescent Current

Shutdown Supply Current

Undervoltage Lockout Threshold

V_IN= 3.15 V to 14 V, GATE = IN

V_IN= 3.15 V to 14 V, COMP = GND

V_INfalling, T_A= −40°C to +85°C

V_INrising, T_A= −40°C to +85°C

235

2.90

3.00

μA

V_UVLO

2.75

2.85

ERROR AMPLIFIER

FB Input Current

I_FB

V_FB= 0.8 V

V_FB= 0.8 V, T_A= −40°C to +85°C

−20

−35

-2

Amplifier Transconductance

COMP Startup Threshold

COMP Shutdown Threshold

COMP Startup Current Source

FB Regulation Voltage

Overvoltage Protection Threshold

Overvoltage Protection Hysteresis

CURRENT SENSE

V_FB= 0.8 V, I_COMP

5 μA

0.24

0.67

0.3

0.6

0.8

μA

V_IN= 3.15 V to 14 V , T_A= −40°C to +85°

COMP = GND

V_IN= 3.15 V to 14 V , T_A= −40°C to +85°

Measured at FB

0.55

0.15

0.25

0.790

0.87

0.80

0.55

0.85

0.810

0.9

V_OVP

0.885

Peak Current Sense Voltage

Current Sense Gain

T_A= −40°C to +85°C

V_IN= 3.15 V to 14 V, T_A= −40°C to +85°C

V_CSto V_COMP

125

V/V

OUTPUT REGULATION

Line Regulation¹

Load Regulation²

V_IN= 3.15 V to 14 V, V_FB/V_IN

V_FB/V_COMP

0.12

−2

mV/V

OSCILLATOR

Oscillator Frequency

V_FB= 0.8 V

V_FB= 0 V

500

580

190

0.35

650

kHz

FB Frequency Foldback Threshold

GATE DRIVE

Gate Rise Time

Gate Fall Time

Minimum On Time

C_GATE= 3 nF

PGATE minimum low duration

190

1.1

SOFT START POWER-ON TIME

¹Line regulation is measured with the application circuit of Figure 1. Line regulation is specified as being the change in the FB voltage resulting from a 1 V change in the

IN voltage.

²Load regulation is measured using the application circuit from Figure 1. Load regulation is specified as the change in the FB voltage resulting from a 1 V change in

COMP voltage. The COMP voltage range is typically 0.9 V to 2.3 V for the minimum to maximum load current condition.

Rev. 0 | Page 3 of 16

ADP1864

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter

IN to GND

CS, PGATE to GND

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

−0.3 V to +16 V

−0.3 V to (V_IN+ 0.3 V)

−0.3 V to +6 V

315°C/W

FB, COMP to GND

θ_JA2-Layer (SEMI Standard Board)

θ_JA4-Layer (JEDEC Standard Board)

Operating Ambient Temperature

Operating Junction Temperature

Storage Temperature

186°C/W

−40°C to +85°C

−55°C to +125°C

−65°C to +150°C

Lead Temperature Range

Rework Temperature (J-STD-020B)

Peak Reflow Temperature

260°C

(20 sec to 40 sec, J-STD-020B)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page 4 of 16

ADP1864

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

COMP

GND

PGATE

ADP1864

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

COMP

Regulator Compensation Node. COMP is the output of the internal transconductance error amplifier. Connect a

series RC from COMP to GND to compensate for the control loop. Add an extra high frequency capacitor between

COMP and GND to further reduce switching jitter. The value of this is typically one tenth of the main

compensation capacitor. Pulling the COMP pin below 0.3 V disables the ADP1864 and turns off the external PFET.

GND

Analog Ground. Directly connect the compensation and feedback networks to GND, preferably with a small

analog GND plane. Connect GND to the power ground (PGND) plane with a narrow track at a single point close to

the GND pin. See the Layout Considerations section for more information.

Feedback Input. Connect a resistive voltage divider from the output voltage to FB to set the output voltage. The

regulation feedback voltage is 0.8 V. Place the feedback resistors as close as possible to the FB pin.

Current Sense Input. CS is the negative input of the current sense amplifier. It provides the current feedback signal

used to terminate the PWM on-time. Place a current sense resistor between IN and CS to set the current limit. The

current limit threshold is typically 125 mV.

Power Input. IN is the ADP1864 power supply and the positive input of the current sense amplifier. Connect IN

to the positive side of the input voltage source. Bypass IN to PGND with a 10 μF or larger capacitor, as close as

possible to the ADP1864. For additional high frequency noise reduction, add a 0.1 μF capacitor to PGND at the

IN pin.

Gate Drive Output. PGATE drives the gate of the external P-channel MOSFET. Connect PGATE to the gate of the

external MOSFET.

PGATE

Rev. 0 | Page 5 of 16

ADP1864

TYPICAL PERFORMANCE CHARACTERISTICS

0.81

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

= 5V

COMP RISING

0.805

0.80

COMP FALLING

0.795

0.79

–40

–20

100

120

–40

–20

100

120

TEMPERATURE (°C)

Figure 4. Reference Voltage vs. Temperature

Figure 7. COMP Shutdown Threshold vs. Temperature

2.52

2.50

2.48

2.46

2.44

2.42

2.40

600

590

580

570

560

550

= 5V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

–40

–20

100

120

LOAD (A)

TEMPERATURE (°C)

Figure 5. Normalized Oscillator Frequency vs. Temperature

Figure 8. Typical Load Regulation (V_IN= 5 V; See Figure 1)

3.1

2.52

3.05

2.515

2.51

3.0

2.95

2.9

UVLO RISE

UVLO FALL

2.85

2.8

2.505

2.50

2.75

2.7

–40

–20

100

120

TEMPERATURE (°C)

(V)

Figure 9. Typical Line Regulation vs. V_IN(I_LOAD= 1 A; See Figure 19)

Figure 6. UVLO Voltage vs. Temperature (V_INRising and V_INFalling)

Rev. 0 | Page 6 of 16

ADP1864

650

640

630

620

610

600

590

580

570

560

550

540

530

520

510

500

TEMPERATURE = 25°C

VIN = 16V

VIN = 5V

VIN = 3.15V

80 100

VIN = 4V

–40

–20

120

TEMPERATURE (°C)

(V)

Figure 10. I_SDvs. V_IN

Figure 12. Oscillator Frequency vs. V_IN

310

290

16V

12V

270

250

230

210

3.1V

190

–40

–20

100

120

TEMPERATURE (°C)

Figure 11. I_Qvs. V_IN

Rev. 0 | Page 7 of 16

ADP1864

THEORY OF OPERATION

The ADP1864 is a constant frequency (580 kHz), current-mode

buck controller. PGATE drives the gate of the external

P-channel FET. The duty cycle of the external FET dictates the

output voltage and the current supplied to the load.

The voltage at the COMP node is the output of the internal

error amplifier. The negative input of the error amplifier is the

output voltage scaled by an external resistive divider, while the

positive input to the error amplifier is driven by a 0.8 V band

gap reference. An increase in the load current causes a small

drop in the feedback voltage, in turn causing an increase in the

COMP voltage and therefore the duty cycle. The resulting

increase in the on-time of the FET provides the additional

current required by the load.

The peak inductor current is measured across the external sense

resistor, while the system output voltage is fed back through an

external resistor divider to the FB pin.

At the start of every oscillator cycle, PGATE turns on the

external FET, causing the inductor current, and therefore the

current sense amplifier voltage, to increase. The inductor

current increases until the current amplifier voltage equals the

voltage at the COMP pin. This resets the internal flip-flop,

causing PGATE to go high and turning off the external FET.

The inductor current decreases until the beginning of the next

oscillator period.

LOOP START-UP

Pulling the COMP pin to GND disables the ADP1864. When

the COMP pin is released from GND, an internal 0.6 μA

current source charges the external compensation capacitor

on the COMP node. Once the COMP voltage has charged to

0.67 V, the internal control blocks are enabled and COMP is

pulled up to its minimum normal operating voltage (0.9 V). As

the voltage at COMP continues to increase, the on-time of the

external FET increases to supply the required inductor current.

The loop stabilizes completely once COMP voltage is

sufficiently high to support the load current. The regulation

voltage at FB is 0.8 V.

VIN = 3.15V TO 14V

VIN

15mV

ICMP

VREF

0.8V

UVLO,

SWITCHING

VREF

UVLO

RSI

SLOPE

COMP

LOGIC AND

BLANKING

CIRCUIT

2.5V

PGATE

OSC

FREQUENCY

FOLDBACK

OVP

GND

0.35V

VREF

SHORT-CIRCUIT

DETECT

VIN

80mV

EAMP

VREF

0.8V

VFB

0.6μA

VIN

0.3V

SHDN

0.3V SHDN

CMP

COMP

ADP1864

0.8V

Figure 13. Functional Block Diagram

Rev. 0 | Page 8 of 16

ADP1864

SHORT-CIRCUIT PROTECTION

OVERVOLTAGE LOCKOUT PROTECTION (OVP)

If there is a short across the output load, the voltage at the

feedback pin (FB) drops rapidly. When the FB voltage drops

below 0.35 V, the ADP1864 reduces the oscillator frequency

to 190 kHz. The increase in the oscillator period allows the

inductor additional time to discharge, preventing the output

current from running away. Once the output short is removed

and the feedback voltage increases above the 0.35 V threshold,

the oscillator frequency returns to 580 kHz.

The ADP1864 provides an overvoltage protection feature to

protect the system against output short circuits to a higher

voltage supply. If the feedback voltage increases to 0.885 V,

PGATE is held high, turning the external FET off. The FET

continues to be held high until the voltage at FB decreases to

0.84 V, at which time the ADP1864 resumes normal operation.

SOFT START

The ADP1864 includes a soft start feature that limits the rate of

increase in inductor current once the part is enabled. Soft start

is activated when the input voltage is increased above the

UVLO threshold or COMP is released from GND. Soft start

limits the inrush current at the input and also limits the output

voltage overshoot. The soft start control slope is set internally.

UNDERVOLTAGE LOCKOUT (UVLO)

To prevent erratic operation when the input voltage drops

below the minimum acceptable voltage, the ADP1864 has an

undervoltage lockout (UVLO) feature. If the input voltage drops

below ±.90 V, PGATE is pulled high. The ADP1864 will

continue to draw its typical quiescent current. Current

consumption continues to drop toward the shutdown current as

input voltage is reduced. The ADP1864 is re-enabled and begins

switching once the IN voltage is increased above the UVLO

rising threshold (3.0 V).

Rev. 0 | Page 9 of 16

ADP1864

APPLICATION INFORMATION

1.05

0.95

0.85

0.75

0.65

0.55

0.45

0.35

DUTY CYCLE

To determine the worst case inductor ripple current, output

voltage ripple, and slope compensation factor, determine the

system maximum and minimum duty cycle. The duty cycle is

calculated by the equation

V_OUT+ V_D

V_IN+ V_D

DUTY CYCLE DC =

( )

where V_Dis the diode forward drop. A typical Schottky diode

has a forward voltage drop of 0.5 V.

RIPPLE CURRENT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

DUTY CYCLE

Choose the peak-to-peak inductor ripple current between ±02

and 402 of the maximum load current at the system’s highest

input voltage. A good starting point for a design is to pick the

peak-to-peak ripple current at 302 of the load current.

Figure 14. Slope Factor (SF) vs. Duty Ratio

INDUCTOR VALUE

The inductor value choice is important because it dictates the

inductor ripple and, therefore, the voltage ripple at the output.

When operating the part at greater than 402 duty cycle, keep

the inductor value low enough for the slope compensation to

remain effective.

ΔI_(PEAK)= 0.3 × I_LOAD(MAX)

SENSE RESISTOR

Choose the sense resistor value to provide the desired current

limit. The internal current comparator measures the peak

current (sum of load current and positive inductor ripple

current) and compares it against the current limit threshold.

The current sense resistor value is calculated by the equation

The inductor ripple current is inversely related to the inductor

value.

⎛

⎜

⎝

⎞

⎟

⎠

(

V_IN−V_OUT

)

V_OUT+ V_D

V_IN+ V_D

ΔI₍

)

PCSV

PEAK

L × f

R_SENSE

MIN )

(

ΔI₍

PEAK

)

I_LOAD

MAX )

(

Smaller inductor values are typically smaller in size and usually

less expensive, but increase the ripple current and the output

voltage ripple. Too large an inductor value results in added

expense and may impede effective load transient responses at

>402 duty cycle because it reduces the effect of slope

compensation.

where PCSV is the peak current sense voltage, typically 0.1±5 V.

To ensure the design provides the required output load current

over all system conditions, consider the variation in PCSV over

temperature (see the Specifications section) as well as increases

in ripple current due to inductor tolerance.

Start with the highest input voltage, and assume ripple current

is 302 of the maximum load current:

If the system is being operated with >402 duty cycle, incor-

porate the slope compensation factor into the calculation.

⎛

⎜

⎝

⎞

⎟

⎠

(

V_IN− V_OUT

)

V_OUT+ V_D

V_IN+ V_D

L =

SF × PCSV

0.3 × I_LOAD

₎× f

R_SENSE

MIN )

(

MAX

(

ΔI₍

PEAK

)

I_LOAD

MAX

)

(

From this starting point, modify the inductance to obtain the

right balance of size, cost, and output voltage ripple while

maintaining the inductor ripple current between ±02 and 402

of the maximum load current.

where SF is the slope factor correction ratio, taken from

Figure 14, at the system maximum duty cycle (minimum input

voltage).

Rev. 0 | Page 10 of 16

ADP1864

MOSFET

INPUT CAPACITOR

Choose the external P-channel MOSFET based on the following:

Vt (threshold voltage), maximum voltage and current ratings,

R_DS(ON), and gate charge.

The input capacitor provides a low impedance path for the

pulsed current drawn by the external P-channel FET. Choose an

input capacitor whose impedance at the switching frequency is

lower than the impedance of the voltage source (V_IN). The

preferred input capacitor is a 10μF ceramic capacitor due to its

low ESR and low impedance.

The minimum operating voltage of the ADP1864 is 3.15 V.

Choose a MOSFET with a Vt that is at least 1 V lower than the

minimum input supply voltage used in the application.

For all types of capacitors, make sure the ripple current rating of

the capacitor is greater than half of the maximum output load

current.

Ensure that the maximum ratings for MOSFET V_GSand V_DSare

a few volts greater than the maximum input voltage used with

the ADP1864.

Where space is limited, multiple capacitors can be placed in

parallel to meet the rms current requirement. Place the input

capacitor as close as possible to the IN pin of the ADP1864.

Estimate the rms current in the MOSFET under continuous

conduction mode by

⎛

⎜

⎝

⎞

⎟

⎠

(

V_OUT+V_D

)

OUTPUT CAPACITOR

I_MOSFET

RMS)

×I_LOAD

(

V_IN+V_D

)

The ESR and capacitance value of the output capacitor

determine the amount of output voltage ripple:

Derate the MOSFET current by at least ±02 to account for

inductor ripple and changes in the diode voltage.

⎛

⎜

⎝

⎞

⎟

⎠

ΔV ≅ ΔI ×

+ ESR_COUT

8 × f × C_OUT

The MOSFET power dissipation is the sum of the conducted

and the switching losses:

where f = oscillator frequency (typically 580 kHz).

PD_MOSFET

COND)

(

I_MOSFET(RMS)

)

(

1+T ×R_DS(ON)

)

(

Because the output capacitance is typically >40 μF, the ESR

dominates the voltage ripple. Ensure the output capacitor ripple

rating is greater than the maximum inductor ripple.

where T is 0.005/˚C × (MOSFET Junction Temperature − ±5˚C).

Ensure the maximum power dissipation calculated is signif-

icantly less than the maximum rating of the MOSFET.

⎛

⎜

⎝

⎞

⎟

⎠

(

V_OUT+ V_D

)

(

V_IN− V_OUT

)

I_rms

≅

± × 3

L × f ×V_IN

DIODE

The diode carries the inductor current during the off time of

the external FET. The average current of the diode is, therefore,

dependent on the duty cycle of the controller as well as the

output load current.

POSCAP capacitors from Sanyo offer a good size, ESR, ripple,

and current capability trade-off.

⎛

⎞

⎟

⎠

(

V_OUT+ V_D

)

⎜

I_DIODE₎= 1 −

× I_LOAD

(

⎜

(

V_IN+ V_D

)

⎝

where V_Dis the diode forward drop. A typical Schottky diode

has a 0.5 V forward drop.

A Schottky diode is recommended for best efficiency because

it has a low forward drop and faster switching speed than

junction diodes. If a junction diode is used it must be an

ultrafast recovery diode. The low forward drop reduces the

power losses during the FET off time, and fast switching speed

reduces the switching losses during PFET transitions.

Rev. 0 | Page 11 of 16

ADP1864

FEEDBACK RESISTORS

The feedback resistor ratio sets the output voltage of the system.

R1 + R2

0.8 V = V_OUT

(

V_OUT− 0.8

)

ADP1864

R1 = R± ×

VOUT

0.8

Choose 80.6 kΩ for R±. Using higher values for R± results in

reduced output voltage accuracy while lower values cause

increased voltage divider current, increasing quiescent current

consumption.

Figure 15. Two Feedback Resistors Used to Set Output Voltage

Rev. 0 | Page 12 of 16

ADP1864

LAYOUT CONSIDERATIONS

ADP1864

Layout is important with all switching regulators, but is

particularly important for high switching frequencies. Ensure

all high current paths are as wide as possible to minimize track

inductance, which causes spiking and electromagnetic inter-

ference (EMI). These paths are shown in bold in Figure 16.

Place the current sense resistor and the input capacitor(s) as

close to the IN pin as possible.

COMP

PGATE

VIN

GND

CIN

PGND

VOUT

Keep the PGND connections for the diode, input capacitor(s),

and output capacitor(s) as close together as possible on a wide

PGND plane. Connect the PGND and GND planes at a single

point with a narrow trace close to the ADP1864 GND

connection.

Figure 16. Application Circuit Showing High Current Paths (in Bold)

Ensure the feedback resistors are placed as close as possible

to the FB pin to prevent stray pickup. To prevent extra noise

pickup on the FB line, do not allow the feedback trace from

the output voltage to FB to pass right beside the drain of the

external PFET. Add an extra copper plane at the connection of

the FET drain and the cathode of the diode to help dissipate the

heat generated by losses in those components.

VIN

RCOMP

ADP1864

PGND

CCOMP

CIN

RFB2

PGND

VOUT

RFB1

MOSFET

Figure 17. Example of Layout for an ADP1864 3A Application

Rev. 0 | Page 13 of 16

ADP1864

EXAMPLE APPLICATIONS CIRCUITS

ADP1864

25kΩ

VIN = 4.5V to 5.5V

10μF

VIN = 3.15V to 14V

25kΩ

COMP

0.03Ω

10μF

470pF

68pF

470pF

68pF

GND

5μH

3.3μH

80.6kΩ

3.3V, 2.0A

2.5V, 2.0A

PGATE

47μF

255kΩ

174kΩ

RSENSE LRC-LR1206_01_R030-F

MOSFET FAIRCHILD SEMI FDC638P

INDUCTOR TOKO FDV0630-3R3M

DIODE SYNSEMI SK22

RSENSE LRC-LR1206_01_R030-F

MOSFET FAIRCHILD SEMI FDC658P

INDUCTOR SUMIDA CDRH6D38-5R0

DIODE VISHAY SSB43L

CIN LMK325BJ106KN

COUT SANYO POSCAP 6TPB47M

Figure 18.

Figure 19.

Rev. 0 | Page 14 of 16

ADP1864

OUTLINE DIMENSIONS

2.90 BSC

2.80 BSC

1.60 BSC

PIN 1

INDICATOR

0.95 BSC

1.90

BSC

0.90

0.87

0.84

1.00 MAX

0.20

0.08

8°

4°

0°

0.60

0.45

0.30

0.50

0.30

0.10 MAX

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

Figure 20. 6-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-6)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range Package Description

Package Option Branding

UJ-6 P0N

ADP1864AUJZ-R7¹

ADP1864-EVAL²

−40°C to +85°C

6-Lead Thin Small Outline Transistor Package (TSOT)

Evaluation Board

¹Z = Pb-free part.

²V_OUT2.5 V (variable), I_LOAD= 0 A to 3 A, V_IN= 3.15 V to 14 V.

Rev. 0 | Page 15 of 16

ADP1864

NOTES

registered trademarks are the property of their respective owners.

D05562–0–10/05(0)

Rev. 0 | Page 16 of 16

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ADP1864AUJZ-R7产品参数

型号:	ADP1864AUJZ-R7
Brand Name：	Analog Devices Inc
是否无铅：	含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	TSSOP
包装说明：	VSSOP, TSOP6,.11,37
针数：	6
制造商包装代码：	UJ-6
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	1.71
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	14 V
最小输入电压：	3.15 V
标称输入电压：	5 V
JESD-30 代码：	R-PDSO-G6
JESD-609代码：	e3
长度：	2.9 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	6
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	VSSOP
封装等效代码：	TSOP6,.11,37
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	SINGLE
最大切换频率：	650 kHz
温度等级：	AUTOMOTIVE
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.95 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	1.6 mm
Base Number Matches：	1

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