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产品型号ADS7804P的概述

ADS7804P芯片概述及详细说明一、概述 ADS7804P是一款高性能的模数转换器（ADC），其主要应用于各种数字信号处理和测量系统。该芯片由德州仪器（Texas Instruments）公司设计和生产，旨在提供高精度和高采样率的信号转换功能。ADS7804P的主要特点之一是其四通道输入能力，适合多种并行信号处理需求。这种模数转换器的最大采样率为100 kSPS，能够以十分精确的方式将模拟信号转换为数字信号，且具备优异的噪声性能和线性度。此外，ADS7804P支持单电源供电，电源电压范围为2.7V至5.25V，使其在设计中更为灵活。二、详细参数 2.1 核心参数 - 分辨率：12位 - 输入通道数量：4通道 - 采样率：最大100 kSPS - 转换时间：约为12 µs - DNL（差分非线性）：±1 LSB最大 - INL（积分非线性）：±1 LSB最大 - 供电电压范围...

产品型号ADS7804P的Datasheet PDF文件预览

ADS7804

DEMO BOARD

AVAILABLE

12-Bit 10µs Sampling CMOS

ANALOG-to-DIGITAL CONVERTER

DESCRIPTION

FEATURES

The ADS7804 is a complete 12-bit sampling A/D

using state-of-the-art CMOS structures. It contains a

complete 12-bit, capacitor-based, SAR A/D with S/H,

reference, clock, interface for microprocessor use, and

three-state output drivers.

● 100kHz min SAMPLING RATE

● STANDARD ±10V INPUT RANGE

● 72dB min SINAD WITH 45kHz INPUT

● ±0.45 LSB max INL

● DNL: 12 Bits “No Missing Codes”

● SINGLE +5V SUPPLY OPERATION

● PIN-COMPATIBLE WITH 16-BIT ADS7805

The ADS7804 is specified at a 100kHz sampling rate,

and guaranteed over the full temperature range. Laser-

trimmed scaling resistors provide an industry-

standard ±10V input range, while the innovative de-

sign allows operation from a single +5V supply, with

power dissipation under 100mW.

● USES INTERNAL OR EXTERNAL

REFERENCE

● COMPLETE WITH S/H, REF, CLOCK, ETC.

● FULL PARALLEL DATA OUTPUT

● 100mW max POWER DISSIPATION

● 28-PIN 0.3" PLASTIC DIP AND SOIC

The 28-pin ADS7804 is available in a plastic 0.3" DIP

and in an SOIC, both fully specified for operation over

the industrial –40°C to +85°C range.

R/C

Clock

BYTE

BUSY

Successive Approximation Register and Control Logic

CDAC

Output

Three

Latches

State

and

20kΩ

±10V Input

Parallel

Three

Data

10kΩ

4kΩ

State

Bus

Comparator

Drivers

CAP

Internal

+2.5V Ref

Buffer

4kΩ

REF

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

FAXLine: (800) 548-6133 (US/Canada Only)

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

•

Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1156C

Printed in U.S.A. February, 1996

SPECIFICATIONS

ELECTRICAL

At T_A= –40°C to +85°C, f_S= 100kHz, and V_DIG= V_ANA= +5V, using internal reference, unless otherwise specified.

ADS7804P, U

ADS7804PB, UB

TYP

PARAMETER

RESOLUTION

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

Bits

ANALOG INPUT

Voltage Ranges

Impedance

±10V

kΩ

Capacitance

THROUGHPUT SPEED

Conversion Time

Complete Cycle

5.7

µs

Acquire and Convert

Throughput Rate

100

kHz

DC ACCURACY

Integral Linearity Error

Differential Linearity Error

No Missing Codes

±0.9

±0.45

LSB⁽¹⁾

LSB

Bits

Guaranteed

0.1

Transition Noise⁽²⁾

LSB

Full Scale Error^(3,4)

Full Scale Error Drift

Full Scale Error^(3,4)

Full Scale Error Drift

Bipolar Zero Error⁽³⁾

Bipolar Zero Error Drift

Power Supply Sensitivity

(V_DIG= V_ANA= V_D)

±0.5

±10

±0.25

±10

ppm/°C

LSB

±7

±2

±5

Ext. 2.5000V Ref

+4.75V < V_D< +5.25V

±0.5

AC ACCURACY

Spurious-Free Dynamic Range

Total Harmonic Distortion

Signal-to-(Noise+Distortion)

Signal-to-Noise

_IN= 45kHz

dB⁽⁵⁾

kHz

f_IN= 45kHz

–80

_IN= 45kHz

Full-Power Bandwidth⁽⁶⁾

250

SAMPLING DYNAMICS

Aperture Delay

Aperture Jitter

Sufficient to meet AC specs

Transient Response

Overvoltage Recovery⁽⁷⁾

FS Step

µs

150

REFERENCE

Internal Reference Voltage

Internal Reference Source Current

(Must use external buffer.)

Internal Reference Drift

External Reference Voltage Range

for Specified Linearity

2.48

2.3

2.5

2.52

µA

2.5

ppm/°C

2.7

External Reference Current Drain

Ext. 2.5000V Ref

100

µA

DIGITAL INPUTS

Logic Levels

V_IL

V_IH

I_IL

–0.3

+2.0

+0.8

V_D+0.3V

±10

µA

I_IH

±10

DIGITAL OUTPUTS

Data Format

Data Coding

V_OL

Parallel 12 bits

Binary Two’s Complement

I_SINK= 1.6mA

I_SOURCE= 500µA

High-Z State,

+0.4

µA

V_OH

Leakage Current

±5

_OUT= 0V to V_DIG

High-Z State

Output Capacitance

DIGITAL TIMING

Bus Access Time

Bus Relinquish Time

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

ADS7804

SPECIFICATIONS (CONT)

ELECTRICAL

At T_A= –40°C to +85°C, f_S= 100kHz, and V_DIG= V_ANA= +5V, using internal reference, unless otherwise specified.

ADS7804P, U

ADS7804PB, UB

TYP

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

POWER SUPPLIES

Specified Performance

V_DIG

Must be ≤ V_ANA

+4.75

0.3

+5.25

V_ANA

+I_DIG

+I_ANA

Power Dissipation

f_S= 100kHz

100

TEMPERATURE RANGE

Specified Performance

Derated Performance

Storage

–40

–55

–65

+85

+125

+150

•

°C

Thermal Resistance (θ_JA

)

Plastic DIP

SOIC

°C/W

NOTES: (1) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7804, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and

temperatures. (3) As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full

Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes

the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which

Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input overvoltage.

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC

DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from

performance degradation to complete device failure. Burr-

Analog Inputs: V_IN............................................................................. ±25V

CAP ................................... +V_ANA+0.3V to AGND2 –0.3V

REF .......................................... Indefinite Short to AGND2

Momentary Short to V_ANA

Ground Voltage Differences: DGND, AGND1, AGND2 ................. ±0.3V

BrownCorporationrecommendsthatallintegrated circuitsbe

handled and stored using appropriate ESD protection

methods.

V_ANA....................................................................................................... 7V

V_DIGto V_ANA..................................................................................... +0.3V

V_DIG....................................................................................................... 7V

Digital Inputs ........................................................... –0.3V to +V_DIG+0.3V

Maximum Junction Temperature ................................................... +165°C

Internal Power Dissipation............................................................. 825mW

Lead Temperature (soldering, 10s)............................................... +300°C

PACKAGE INFORMATION

PACKAGE DRAWING

PRODUCT

PACKAGE

NUMBER⁽¹⁾

ADS7804P

ADS7804PB

ADS7804U

ADS7804UB

Plastic DIP

SOIC

246

217

SOIC

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix C of Burr-Brown IC Data Book.

ORDERING INFORMATION

MINIMUM

SIGNAL-TO-

MAXIMUM

LINEARITY

ERROR (LSB)

(NOISE +

DISTORTION)

RATIO (dB)

SPECIFICATION

TEMPERATURE

RANGE

PRODUCT

PACKAGE

ADS7804P

ADS7804PB

ADS7804U

ADS7804UB

±0.9

±0.45

±0.9

–40°C to +85°C

Plastic DIP

SOIC

±0.45

SOIC

ADS7804

DIGITAL

I/O

PIN #

NAME

V_IN

DESCRIPTION

Analog Input. See Figure 7.

AGND1

REF

CAP

AGND2

D15 (MSB)

D14

Analog Ground. Used internally as ground reference point.

Reference Input/Output. 2.2µF tantalum capacitor to ground.

Reference Buffer Capacitor. 2.2µF tantalum capacitor to ground.

Analog Ground.

Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.

Digital Ground.

D13

D12

D11

D10

DGND

Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.

LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.

Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH).

D0 (LSB)

BYTE

R/C

With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C

enables the parallel output.

Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.

BUSY

At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs

have been updated.

V_ANA

V_DIG

Analog Supply Input. Nominally +5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors.

Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ V_ANA

TABLE I. Pin Assignments.

PIN CONFIGURATION

CHARACTERIZATION CURVES

Call factory for updated data sheet which includes character-

V_IN

AGND1

REF

28 V_DIG

27 V_ANA

26 BUSY

25 CS

ization curves.

CAP

AGND2

D11 (MSB)

D10

24 R/C

23 BYTE

22 DZ

ADS7804

21 DZ

20 DZ

D7 10

D6 11

19 DZ

18 D0 (LSB)

17 D1

D5 12

D4 13

16 D2

DGND 14

15 D3

ADS7804

Table II for a summary of CS, R/C, and BUSY states and

Figures 3 through 5 for timing diagrams.

BASIC OPERATION

Figure 1 shows a basic circuit to operate the ADS7804 with

a full parallel data output. Taking R/C (pin 24) LOW for a

minimum of 40ns (6µs max) will initiate a conversion.

BUSY (pin 26) will go LOW and stay LOW until the

conversion is completed and the output registers are up-

dated. Data will be output in Binary Two’s Complement

with the MSB on pin 6. BUSY going HIGH can be used to

latch the data. All convert commands will be ignored while

BUSY is LOW.

CS and R/C are internally OR’d and level triggered. There

is not a requirement which input goes LOW first when

initiating a conversion. If, however, it is critical that CS or

R/C initiates conversion ‘n’, be sure the less critical input is

LOW at least 10ns prior to the initiating input.

To reduce the number of control pins, CS can be tied LOW

using R/C to control the read and convert modes. This will

have no effect when using the internal data clock in the serial

output mode. However, the parallel output will become

active whenever R/C goes HIGH. Refer to the Reading

Data section.

The ADS7804 will begin tracking the input signal at the end

of the conversion. Allowing 10µs between convert com-

mands assures accurate acquisition of a new signal.

The offset and gain are adjusted internally to allow external

trimming with a single supply. The external resistors com-

pensate for this adjustment and can be left out if the offset

and gain will be corrected in software (refer to the Calibra-

tion section).

R/C BUSY OPERATION

None. Databus is in Hi-Z state.

↓

Initiates conversion “n”. Databus remains

in Hi-Z state.

↓

↑

Initiates conversion “n”. Databus enters Hi-Z

state.

Conversion “n” completed. Valid data from

conversion “n” on the databus.

STARTING A CONVERSION

Enables databus with valid data from

conversion “n”.

The combination of CS (pin 25) and R/C (pin 24) LOW for

a minimum of 40ns immediately puts the sample/hold of the

ADS7804 in the hold state and starts conversion ‘n’. BUSY

(pin 26) will go LOW and stay LOW until conversion ‘n’ is

completed and the internal output register has been updated.

All new convert commands during BUSY LOW will be

ignored. CS and/or R/C must go HIGH before BUSY goes

HIGH or a new conversion will be initiated without suffi-

cient time to acquire a new signal.

Enables databus with valid data from

conversion “n-1”⁽¹⁾. Conversion n in process.

Enables databus with valid data from

conversion “n-1”⁽¹⁾. Conversion “n” in process.

New conversion initiated without acquisition

of a new signal. Data will be invalid. CS and/or

R/C must be HIGH when BUSY goes HIGH.

New convert commands ignored. Conversion

“n” in process.

The ADS7804 will begin tracking the input signal at the end

of the conversion. Allowing 10µs between convert com-

mands assures accurate acquisition of a new signal. Refer to

NOTE: (1) See Figures 2 and 3 for constraints on data valid from

conversion “n-1”.

Table II. Control Line Functions for “Read” and “Convert”.

200Ω

+5V

33.2kΩ

0.1µF

10µF

2.2µF

Convert Pulse

B15 (MSB)

B14

B0 (LSB)

40ns min

6µs max

ADS7804

B13

B12

B11

B10

FIGURE 1. Basic Operation.

ADS7804

PARALLEL OUTPUT (During a Conversion)

READING DATA

After conversion ‘n’ has been initiated, valid data from

conversion ‘n-1’ can be read and will be valid up to 16µs

after the start of conversion ‘n’. Do not attempt to read data

from 16µs after the start of conversion ‘n’ until BUSY (pin

26) goes HIGH; this may result in reading invalid data.

Refer to Table IV and Figures 3 and 5 for timing specifica-

tions.

The ADS7804 outputs full or byte-reading parallel data in

Binary Two’s Complement data output format. The parallel

output will be active when R/C (pin 24) is HIGH and CS

(pin 25) is LOW. Any other combination of CS and R/C will

tri-state the parallel output. Valid conversion data can be

read in a full parallel, 12-bit word or two 8-bit bytes on pins

6-13 and pins 15-22. BYTE (pin 23) can be toggled to read

both bytes within one conversion cycle. Refer to Table III

for ideal output codes and Figure 2 for bit locations relative

to the state of BYTE.

Note! For the best possible performance, data should not be

read during a conversion. The switching noise of the asyn-

chronous data transfer can cause digital feedthrough degrad-

ing the converter’s performance.

The number of control lines can be reduced by tieing CS

LOW while using R/C to initiate conversions and activate

the output mode of the converter. See Figure 3.

DIGITAL OUTPUT

BINARY TWO’S COMPLEMENT

DESCRIPTION

ANALOG INPUT

±10V

BINARY CODE

HEX CODE

Full Scale Range

Least Significant

Bit (LSB)

4.88mV

SYMBOL

DESCRIPTION

Convert Pulse Width

MIN TYP MAX UNITS

t₁

t₂

6000

+Full Scale

(10V – 1LSB)

9.99512V

0111 1111 1111

7FF

Data Valid Delay after R/C LOW

µs

Midscale

0000 0000 0000

1111 1111 1111

000

FFF

t₃

t₄

BUSY Delay from R/C LOW

BUSY LOW

µs

One LSB below

Midscale

–4.88mV

t₅

BUSY Delay after

End of Conversion

220

–Full Scale

–10V

1000 0000 0000

800

t₆

t₇

Aperture Delay

Conversion Time

µs

Table III. Ideal Input Voltages and Output Codes.

7.6

t₈

Acquisition Time

PARALLEL OUTPUT (After a Conversion)

t₉

Bus Relinquish Time

BUSY Delay after Data Valid

After conversion ‘n’ is completed and the output registers

have been updated, BUSY (pin 26) will go HIGH. Valid data

from conversion ‘n’ will be available on D11-D0 (pin 6-13

and 15-18 when BYTE is LOW). BUSY going HIGH can be

used to latch the data. Refer to Table IV and Figures 3 and

5 for timing specifications.

t₁₀

t₁₁

50 200

7.4

Previous Data Valid

after R/C LOW

t₇+ t₆

t₁₂

Throughput Time

R/C to CS Setup Time

Time Between Conversions

µs

t₁₃

t₁₄

Bus Access Time

and BYTE Delay

TABLE IV. Conversion Timing.

BYTE LOW

BYTE HIGH

+5V

Bit 11 (MSB)

Bit 10

Bit 9

Bit 3

Bit 2

LOW

Bit 0 (LSB)

Bit 1

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

ADS7804

Bit 1

Bit 8

Bit 0 (LSB)

LOW

Bit 7

Bit 6

LOW

Bit 5

LOW

Bit 4

Bit 2

LOW

Bit 10

Bit 11

Bit 3

FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).

ADS7804

t₁

R/C

BUSY

t₁₃

t₂

t₄

t₃

t₆

t₅

Convert

t₇

Acquire

t₈

Convert

Acquire

MODE

Data Valid

Hi-Z

Not Valid

Data Valid

t₁₀

Hi-Z

Data Valid

DATA BUS

t₉

t₁₁

FIGURE 3. Conversion Timing with Outputs Enabled after Conversion (CS Tied LOW.)

t₁₂

R/C

t₁

t₃

t₄

BUSY

MODE

t₆

Convert

t₇

Acquire

Hi-Z State

Data Valid

t₉

Hi-Z State

DATA BUS

t₁₄

FIGURE 4. Using CS to Control Conversion and Read Timing.

t₁₂

R/C

BYTE

Pins 6 - 13

Hi-Z

High Byte

t₁₄

Low Byte

Hi-Z

t₁₄

High Byte

t₉

Pins 15 - 22

Low Byte

Hi-Z

FIGURE 5. Using CS and BYTE to Control Data Bus.

ADS7804

INPUT RANGES

SOFTWARE CALIBRATION

The ADS7804 offers a standard ±10V input range. Figure 6

shows the necessary circuit connections for the ADS7804

with and without hardware trim. Offset and full scale error⁽¹⁾

specifications are tested and guaranteed with the fixed resis-

tors shown in Figure 6b. Adjustments for offset and gain are

described in the Calibration section of this data sheet.

To calibrate the offset and gain of the ADS7804 in software,

no external resistors are required. See the No Calibration

section for details on the effects of the external resistors. Refer

to Table V for range of offset and gain errors with and without

external resistors.

The offset and gain are adjusted internally to allow external

trimming with a single supply. The external resistors com-

pensate for this adjustment and can be left out if the offset

and gain will be corrected in software (refer to the Calibra-

tion section).

NO CALIBRATION

See Figure 6b for circuit connections. The external resistors

shown in Figure 6b may not be necessary in some applica-

tions. These resistors provide compensation for an internal

adjustment of the offset and gain which allows calibration

with a single supply. The nominal transfer function of the

ADS7804 will be bound by the shaded region seen in Figure

7 with a typical offset of –30mV and a typical gain error of

–1.5%. Refer to Table V for range of offset and gain errors

with and without external resistors.

The nominal input impedance of 23kΩ results from the

combination of the internal resistor network shown on the

front page of the product data sheet and the external resistors.

The input resistor divider network provides inherent overvolt-

age protection guaranteed to at least ±25V. The 1% resistors

used for the external circuitry do not compromise the accuracy

or drift of the converter. They have little influence relative to

the internal resistors, and tighter tolerances are not required.

WITH

EXTERNAL

RESISTORS

WITHOUT

EXTERNAL

RESISTORS

UNITS

NOTE: (1) Full scale error includes offset and gain errors measured at both +FS

and –FS.

BPZ

–10 < BPZ < 10

–2 < BPZ < 2

–45 < BPZ < 5

–8 < BPZ < 1

LSBs

Gain

Error

–0.5 < error < 0.5

–0.6 < error < –0.55

–0.45 < error < –0.3⁽¹⁾

% of FSR

–0.25 < error < 0.25⁽¹⁾

CALIBRATION

NOTE: (1) High Grade.

The ADS7804 can be trimmed in hardware or software. The

offset should be trimmed before the gain since the offset

directly affects the gain. To achieve optimum performance,

several iterations may be required.

TABLE VII. Bipolar Offset and Gain Errors With and

Without External Resistors.

HARDWARE CALIBRATION

To calibrate the offset and gain of the ADS7804, install the

proper resistors and potentiometers as shown in Figure 6a. The

calibration range is ±15mV for the offset and ±60mV for the

gain.

±10V With Hardware

±10V Without Hardware

Trim

200Ω

±10V

V_IN

33.2kΩ

AGND1

REF

AGND1

+5V

2.2µF

576kΩ

2.2µF

33.2kΩ

REF

50kΩ

Gain

Offset

CAP

50kΩ

AGND2

NOTE: Use 1% metal film resistors.

FIGURE 6. Circuit Diagram With and Without External Resistors.

ADS7804

Digital

Output

7FF

–10V

–9.99983V

–9.9998V

–50mV

Analog

Input

–15mV

9.9997V

9.999815V

+10V

Ideal Transfer Function

With External Resistors

Range of Transfer Function

Without External Resistors

800

FIGURE 7. Full Scale Transfer Function.

REFERENCE

The ADS7804 can operate with its internal 2.5V reference or

an external reference. By applying an external reference to

pin 5, the internal reference can be bypassed. The reference

voltage at REF is buffered internally with the output on CAP

(pin 4).

CAP

CAP (pin 4) is the output of the internal reference buffer. A

2.2µF capacitor should be placed as close to the CAP pin as

possible to provide optimum switching currents for the

CDAC throughout the conversion cycle and compensation

for the output of the internal buffer. Using a capacitor any

smaller than 1µF can cause the output buffer to oscillate and

may not have sufficient charge for the CDAC. Capacitor

values larger than 2.2µF will have little affect on improving

performance.

The internal reference has an 8 ppm/°C drift (typical) and

accounts for approximately 20% of the full scale error

(FSE = ±0.5% for low grade, ±0.25% for high grade).

REF

The output of the buffer is capable of driving up to 2mA of

current to a DC load. DC loads requiring more than 2mA of

current from the CAP pin will begin to degrade the linearity

of the ADS7804. Using an external buffer will allow the

internal reference to be used for larger DC loads and AC

loads. Do not attempt to directly drive an AC load with the

output voltage on CAP. This will cause performance degra-

dation of the converter.

REF (pin 3) is an input for an external reference or the output

for the internal 2.5V reference. A 2.2µF capacitor should be

connected as close to the REF pin as possible. The capacitor

and the output resistance of REF create a low pass filter to

bandlimit noise on the reference. Using a smaller value

capacitor will introduce more noise to the reference degrad-

ing the SNR and SINAD. The REF pin should not be used

to drive external AC or DC loads.

The range for the external reference is 2.3V to 2.7V and

determines the actual LSB size. Increasing the reference

voltage will increase the full scale range and the LSB size of

the converter which can improve the SNR.

ADS7804

SIGNAL CONDITIONING

LAYOUT

The FET switches used for the sample hold on many CMOS

A/D converters release a significant amount of charge injec-

tion which can cause the driving op amp to oscillate. The

FET switch on the ADS7804, compared to the FET switches

on other CMOS A/D converters, releases 5%-10% of the

charge. There is also a resistive front end which attenuates

any charge which is released. The end result is a minimal

requirement for the anti-alias filter on the front end. Any op

amp sufficient for the signal in an application will be

sufficient to drive the ADS7804.

POWER

For optimum performance, tie the analog and digital power

pins to the same +5V power supply and tie the analog and

digital grounds together. As noted in the electrical specifica-

tions, the ADS7804 uses 90% of its power for the analog

circuitry. The ADS7804 should be considered as an analog

component.

The +5V power for the A/D should be separate from the +5V

used for the system’s digital logic. Connecting V_DIG(pin 28)

directly to a digital supply can reduce converter performance

due to switching noise from the digital logic. For best

performance, the +5V supply can be produced from what-

ever analog supply is used for the rest of the analog signal

conditioning. If +12V or +15V supplies are present, a simple

+5V regulator can be used. Although it is not suggested, if

the digital supply must be used to power the converter, be

sure to properly filter the supply. Either using a filtered

digital supply or a regulated analog supply, both V_DIGand

V_ANAshould be tied to the same +5V source.

The resistive front end of the ADS7804 also provides a

guaranteed ±25V overvoltage protection. In most cases, this

eliminates the need for external input protection circuitry.

INTERMEDIATE LATCHES

The ADS7804 does have tri-state outputs for the parallel

port, but intermediate latches should be used if the bus will

be active during conversions. If the bus is not active during

conversion, the tri-state outputs can be used to isolate the

A/D from other peripherals on the same bus. Tri-state

outputs can also be used when the A/D is the only peripheral

on the data bus.

GROUNDING

Three ground pins are present on the ADS7804. DGND is

the digital supply ground. AGND2 is the analog supply

ground. AGND1 is the ground which all analog signals

internal to the A/D are referenced. AGND1 is more suscep-

tible to current induced voltage drops and must have the path

of least resistance back to the power supply.

Intermediate latches are beneficial on any monolithic A/D

converter. The ADS7804 has an internal LSB size of 610µV.

Transients from fast switching signals on the parallel port,

even when the A/D is tri-stated, can be coupled through the

substrate to the analog circuitry causing degradation of

converter performance. The effects of this phenomenon will

be more obvious when using the pin-compatible ADS7805

or any of the other 16-bit converters in the ADS Family. This

is due to the smaller internal LSB size of 38µV.

All the ground pins of the A/D should be tied to the analog

ground plane, separated from the system’s digital logic

ground, to achieve optimum performance. Both analog and

digital ground planes should be tied to the “system” ground

as near to the power supplies as possible. This helps to

prevent dynamic digital ground currents from modulating

the analog ground through a common impedance to power

ground.

APPLICATIONS

Call factory for updated data sheet which includes standard

DSP, microprocessor, and microcontroller interfaces.

ADS7804

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ADS7804P产品参数

型号:	ADS7804P
是否Rohs认证：	不符合
生命周期：	Transferred
包装说明：	PLASTIC, DIP-28
Reach Compliance Code：	unknown
风险等级：	5.76
Is Samacsys：	N
最大模拟输入电压：	10 V
最小模拟输入电压：	-10 V
最长转换时间：	8 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：	R-PDIP-T28
JESD-609代码：	e0
最大线性误差 (EL)：	0.022%
模拟输入通道数量：	1
位数：	12
功能数量：	1
端子数量：	28
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出位码：	2'S COMPLEMENT BINARY
输出格式：	PARALLEL, WORD
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP28,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
电源：	5 V
认证状态：	Not Qualified
采样速率：	0.1 MHz
采样并保持/跟踪并保持：	SAMPLE
子类别：	Analog to Digital Converters
标称供电电压：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
Base Number Matches：	1

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