ADS821U现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

ADS821

A

D

S

8

2

1

U

SBAS040B – DECEMBER 1995 – REVISED FEBRUARY 2005

10-Bit, 40MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

DESCRIPTION

FEATURES

● NO MISSING CODES

● INTERNAL REFERENCE

● LOW POWER: 380mW

● HIGH SNR: 58dB

The ADS821 is a low-power, monolithic 10-bit, 40MHz Ana-

log-to-Digital (A/D) converter utilizing a small geometry CMOS

process. This complete converter includes a 10-bit quantizer

with internal track-and-hold, reference, and a power-down

feature. It operates from a single +5V power supply and can

be configured to accept either differential or single-ended

input signals.

● INTERNAL TRACK-AND-HOLD

The ADS821 employs digital error correction to provide

excellent Nyquist differential linearity performance for de-

manding imaging applications. Its low distortion, high SNR,

and high oversampling capability give it the extra margin

needed for telecommunications and video applications.

APPLICATIONS

● VIDEO DIGITIZING

● ULTRASOUND IMAGING

● GAMMA CAMERAS

● SET-TOP BOXES

This high-performance converter is specified for AC and DC-

performance at a 40MHz sampling rate. The ADS821 is

available in an SO-28 package.

● CABLE MODEMS

● CCD IMAGING

Color Copiers

Scanners

Camcorders

CLK

MSBI

OE

Security Cameras

Fax Machines

● IF AND BASEBAND DIGITIZATION

● TEST INSTRUMENTATION

Timing

Circuitry

IN

Pipeline

A/D

Converter

10-Bit

Digital

Data

Error

Correction

Logic

3-State

Outputs

T&H

+3.25V

REFT

CM

REFB

+1.25V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

+V_S....................................................................................................... +6V

Analog Input ............................................................ 0V to (+V_S+ 300mV)

Logic Input ............................................................... 0V to (+V_S+ 300mV)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature .................................................................... +125°C

External Top Reference Voltage (REFT) ................................. +3.4V max

External Bottom Reference Voltage (REFB) ............................ +1.1V min

ESD damage can range from subtle performance degradation

tocompletedevicefailure. Precisionintegratedcircuitsmaybe

more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

NOTES: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may degrade

device reliability.

PACKAGE/ORDERING INFORMATION(1)

SPECIFIED

PACKAGE

DESIGNATOR

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE-LEAD

ADS821

SO-8

DW

–40°C to +85°C

ADS821U

Rails, 28

"

ADS821U/1K

Tape and Reel, 1000

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at

www.ti.com.

ELECTRICAL CHARACTERISTICS

At T_A= +25°C, V_S= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

ADS821U

PARAMETER

CONDITIONS

TEMP

MIN

TYP

MAX

UNITS

RESOLUTION

10

Bits

Specified Temperature Range

T_AMBIENT

–40

+85

°C

ANALOG INPUT

Differential Full-Scale Input Range

Common-Mode Voltage

Analog Input Bandwidth (–3dB)

Small-Signal

+1.25

+3.25

+2.25

V

–20dBFS⁽¹⁾Input

0dBFS Input

+25°C

400

65

MHz

Full-Power

Input Impedance

1.25 || 4

MΩ || pF

DIGITAL INPUT

Logic Family

Convert Command

TTL/HCT Compatible CMOS

Falling Edge

Start Conversion

ACCURACY⁽²⁾

Gain Error

+25°C

Full

±0.6

±1.1

±85

0.01

±2.1

0.02

±1.5

±2.5

%

Gain Drift

Power-Supply Rejection of Gain

Input Offset Error

ppm/°C

%FSR/%

%

∆ +V_S= ±5%

+25°C

Full

+25°C

0.15

±3.5

0.15

Power-Supply Rejection of Offset

%FSR/%

CONVERSION CHARACTERISTICS

Sample Rate

10k

40M

Sample/s

Data Latency

6.5

Convert Cycle

DYNAMIC CHARACTERISTICS

Differential Linearity Error

f = 500kHz

t_H= 13ns⁽³⁾

+25°C

0°C to +70°C

+25°C

0°C to +70°C

±0.5

±0.6

±0.5

±0.6

Tested

±0.5

±1.0

LSB

f = 12MHz

No Missing Codes

Integral Linearity Error at f = 500kHz

Spurious-Free Dynamic Range (SFDR)

f = 500kHz (–1dBFS input)

±2.0

LSB

+25°C

Full

+25°C

Full

60

54

58

54

70

67

63

62

dBFS

f = 12MHz (–1dBFS input)

NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) Refer to Timing

Diagram footnotes for the differential linearity performance conditions for the SO and SSOP packages. (4) IMD is referred to the larger of the two input signals.

If referred to the peak envelope signal (≈ 0dB), the intermodulation products will be 7dB lower. (5) Based on (SINAD – 1.76)/6.02. (6) No “rollover” of bits.

ADS821

2

SBAS040B

www.ti.com

ELECTRICAL CHARACTERISTICS (Cont.)

At T_A= +25°C, V_S= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

ADS821U

PARAMETER

CONDITIONS

TEMP

MIN

TYP

MAX

UNITS

DYNAMIC CHARACTERISTICS (Cont.)

2-Tone Intermodulation Distortion (IMD)⁽⁴⁾

f = 4.4MHz and 4.5MHz (–7dBFS each tone)

+25°C

Full

–61

–60

dBc

Signal-to-Noise Ratio (SNR)

f = 500kHz (–1dBFS input)

+25°C

Full

+25°C

Full

57

55

56

54

59

58

dB

f = 12MHz (–1dBFS input)

Signal-to-(Noise + Distortion) (SINAD)

f = 500kHz (–1dBFS input)

+25°C

Full

+25°C

Full

+25°C

56

52

53

50

58.5

58

57

56

0.5

dB

%

f = 12MHz (–1dBFS input)

Differential Gain Error

Differential Phase Error

Degrees

Effective Bits⁽⁵⁾

Aperture Delay Time

Aperture Jitter

NTSC or PAL

f_IN= 3.58MHz

NTSC or PAL

+25°C

0.1

7

+25°C

9.3

2

Bits

ns

+25°C

ps rms

Over-Voltage Recovery Time⁽⁶⁾

1.5x Full-Scale Input

+25°C

2

ns

OUTPUTS

TTL/HCT Compatible CMOS

SOB or BTC

Logic Family

Logic Coding

Logic Levels

Logic Selectable

Logic LOW,

C_L= 15pF max

Logic HIGH,

Full

0

0.4

V

+2.5

+V_S

C_L= 15pF max

3-State Enable Time

3-State Disable Time

20

2

40

10

ns

Full

POWER-SUPPLY REQUIREMENTS

Supply Voltage: +V_S

Supply Current: +I_S

Operating

Full

+25°C

Full

+25°C

Full

+4.75

+5

76

78

380

390

+5.25

88

90

440

450

75

V

mA

mW

°C/W

Power Consumption

Thermal Resistance, θ_JA

NOTES: (1) dBFS refers to dB below Full Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) Refer to Timing

Diagram footnotes for the differential linearity performance conditions for the SO and SSOP packages. (4) IMD is referred to the larger of the two input signals.

If referred to the peak envelope signal (≈ 0dB), the intermodulation products will be 7dB lower. (5) Based on (SINAD – 1.76)/6.02. (6) No “rollover” of bits.

ADS821

SBAS040B

3

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PIN DESCRIPTIONS

PIN CONFIGURATION

DESIGNATOR DESCRIPTION

Top View

SO

1

2

GND

B1

Ground

Bit 1, Most Significant Bit (MSB)

3

B2

Bit 2

4

5

6

7

8

9

10

11

12

13

14

15

16

17

B3

B4

B5

B6

B7

B8

B9

B10

DNC

GND

+V_S

CLK

+V_S

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

GND

Bit 1 (MSB)

Bit 2

1

2

3

4

5

6

7

8

9

28 GND

27 IN

26 IN

Bit 3

25 GND

24 +V_S

23 REFT

22 CM

21 REFB

20 +V_S

19 MSBI

18 OE

Bit 10, Least Significant Bit (LSB)

Do Not Connect

Ground

+5V Power Supply

Convert Clock Input, 50% Duty Cycle

+5V Power Supply

Bit 4

Bit 5

Bit 6

ADS821

Bit 7

18

OE

HIGH: High-Impedance State. LOW or Floating:

Normal Operation. Internal pull-down resistor.

Most Significant Bit Inversion, HIGH: MSB in-

verted for complementary output. LOW or Float-

ing: Straight output. Internal pull-down resistor.

+5V Power Supply

Bottom Reference Bypass. For external bypass-

ing of internal +1.25V reference.

Common-Mode Voltage. It is derived by (REFT +

REFB)/2.

Top Reference Bypass. For external bypassing

of internal +3.25V reference.

+5V Power Supply

Ground

Input

Bit 8

19

MSBI

Bit 9 10

Bit 10 (LSB) 11

DNC 12

20

21

+V_S

REFB

17 +V_S

DNC

13

16

CLK

22

23

CM

GND 14

15 +V_S

REFT

24

25

26

27

28

+V_S

GND

IN

GND

DNC: Do Not Connect

Complementary Input

Ground

TIMING DIAGRAM

t_CONV

t_L

t_H

Convert

Clock

t_D

DATA LATENCY

(6.5 Clock Cycles)

(1)

Hold

"N"

Hold

"N + 1"

Hold

"N + 2"

Hold

"N + 3"

Hold

"N + 6"

Track

"N + 4" "N + 5

Track

"

Internal

Track-and-Hold

t₂

Output

Data

Data Valid

N – 8

Data Valid

N – 7

Data Valid

N – 6

N – 5

N – 4

N – 3

N – 2

N – 1

N

t₁

Data Invalid

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t_CONV

t_L

t_H

t_D

t₁

Convert Clock Period

Clock Pulse LOW

Clock Pulse HIGH

Aperture Delay

Data Hold Time, C_L= 0pF

25

12

100µs

ns

12.5

2

12⁽²⁾

3.9

t₂

New Data Delay Time, C_L= 15pF max

12.5

NOTES: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates.

(2) t_Hmust be 13ns minimum if no missing codes is desired only for the conditions of t_CONV≤ 28ns

and f_IN< 2MHz for the SO package. For best performance in the SSOP package, t_Hmust be 13ns

minimum for all input frequencies and t_CONV≤ 28ns. Refer to the Clock Requirements for a possible

clock skew circuit for this condition.

ADS821

4

SBAS040B

www.ti.com

TYPICAL CHARACTERISTICS

At T_A= +25°C, V_S= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

SPECTRAL PERFORMANCE

0

–20

0

–20

f_IN= 5MHz

f_IN= 500kHz

–40

–60

–80

–100

–120

–100

–120

0

5

10

15

20

0

5

10

15

20

Frequency (MHz)

SPECTRAL PERFORMANCE

0

–20

0

–20

f_IN= 1MHz

_S= 10MHz

f_IN= 12MHz

f

–40

–60

–80

–100

–120

–100

–120

0

5

10

15

20

0

1.0

2.0

3.0

4.0

5.0

Frequency (MHz)

DIFFERENTIAL LINEARITY ERROR

f_IN= 500kHz

DIFFERENTIAL LINEARITY ERROR

f_IN= 12MHz

2.0

1.0

2.0

1.0

0

–1.0

–2.0

–1.0

–2.0

0

256

512

768

1024

0

256

512

768

1024

Code

ADS821

SBAS040B

5

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

At T_A= +25°C, V_S= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

2-TONE INTERMODULATION

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

SFDR

70

65

60

55

0

–20

f₁= 4.47MHz

f₂= 4.39MHz

–40

–60

–80

SNR

–100

–120

0.0

5.00

10.00

15.00

20.00

0.1

1

10

Frequency (MHz)

100

Frequency (MHz)

SWEPT POWER SFDR

SWEPT POWER SNR

f_IN= 12MHz

100

80

60

40

20

0

60

50

40

30

20

10

0

f_IN= 12MHz

–50

–40

–30

–20

–10

0

10

–50

–40

–30

–20

–10

0

10

Input Amplitude (dBm)

DYNAMIC PERFORMANCE vs

INTEGRAL LINEARITY ERROR

SINGLE-ENDED FULL-SCALE INPUT RANGE

4.0

2.0

65

60

55

50

45

40

f_IN= 500kHz

SFDR (f_IN= 12MHz)

SFDR (f_IN= 500kHz)

SNR (f_IN= 12MHz)

0

SNR (f_IN= 500kHz)

–2.0

–4.0

NOTE: REFT_EXTvaried, REFB is fixed at the internal

value of +1.25V.

0.0

0.20

0.40

0.60

0.80

1.0

2

3

4

Code

Single-Ended Full-Scale Input Range (Vp-p)

ADS821

6

SBAS040B

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

At T_A= +25°C, V_S= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

SPURIOUS-FREE DYNAMIC RANGE vs

TEMPERATURE

DYNAMIC PERFORMANCE vs

DIFFERENTIAL FULL-SCALE INPUT RANGE

80

70

60

50

75

70

65

60

55

70

f_IN= 500kHz

SFDR (f_IN= 500kHz)

SFDR (f_IN= 12MHz)

SNR (f_IN= 500kHz)

f_IN= 12MHz

SNR (f_IN= 12MHz)

NOTE: REFT_EXTvaried, REFB is fixed at internal

value of +1.25V.

–50

–25

0

25

50

75

100

2

3

4

Temperature (°C)

Differential Full-Scale Input Range (Vp-p)

SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE

f_IN= 500kHz

SIGNAL-TO-NOISE RATIO vs TEMPERATURE

f_IN= 500kHz

59

58

57

56

60

59

58

57

f_IN= 12MHz

f_IN= 10MHz

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

Temperature (°C)

SUPPLY CURRENT vs TEMPERATURE

POWER DISSIPATION vs TEMPERATURE

67

66

65

335

330

325

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

Temperature (°C)

ADS821

SBAS040B

7

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TYPICAL CHARACTERISTICS (Cont.)

At T_A= +25°C, V_S= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.

GAIN ERROR vs TEMPERATURE

OFFSET ERROR vs TEMPERATURE

0

–0.25

–0.5

–1.75

–2.0

–0.75

–1.0

–1.25

–2.25

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

Temperature (°C)

OUTPUT NOISE HISTOGRAM (NO SIGNAL)

TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH

1

1.2M

1M

0

–1

–2

–3

–4

–5

0.8M

0.6M

0.4M

0.2M

0.0

N – 2

N – 1

N

N + 1

N + 2

10k

100k

1M

10M

100M

1G

Frequency (Hz)

Code

ADS821

8

SBAS040B

www.ti.com

Op Amp

Bias

THEORY OF OPERATION

V_CM

The ADS821 is a high-speed, sampling A/D converter with

pipelining. It uses a fully differential architecture and digital

error correction to ensure 10-bit resolution. The differential

track-and-hold circuit is shown in Figure 1. The switches are

controlled by an internal clock that has a non-overlapping 2-

phase signal, φ1 and φ2. At the sampling time, the input

signal is sampled on the bottom plates of the input capaci-

tors. In the next clock phase, φ2, the bottom plates of the

input capacitors are connected together and the feedback

capacitors are switched to the op amp output. At this time,

the charge redistributes between C_Iand C_H, completing one

track-and-hold cycle. The differential output is a held DC

representation of the analog input at the sample time. The

track-and-hold circuit can also convert a single-ended input

signal into a fully differential signal for the quantizer.

φ1

C_H

φ2

C_I

IN

OUT

φ1

φ2

φ1

C_H

φ1

Input Clock (50%)

Op Amp

Bias

V_CM

Internal Non-Overlapping Clock

φ1 φ2 φ1

The pipelined quantizer architecture has 9 stages with each

stage containing a 2-bit quantizer and a 2-bit Digital-to-

Analog Converter (DAC), as shown in Figure 2. Each 2-bit

quantizer stage converts on the edge of the sub-clock, which

is twice the frequency of the externally applied clock. The

output of each quantizer is fed into its own delay line to

FIGURE 1. Input Track-and-Hold Configuration with Timing

Signals.

IN

Digital Delay

Input

T&H

IN

2-Bit

Flash

2-Bit

DAC

+

Stage 1

–

Σ

x2

Digital Delay

B1 (MSB)

2-Bit

Flash

2-Bit

DAC

B2

B3

B4

B5

B6

B7

B8

B9

Stage 2

+

–

Σ

x2

B10 (LSB)

Digital Delay

2-Bit

Flash

2-Bit

DAC

Stage 8

+

–

Σ

x2

2-Bit

Flash

Digital Delay

Stage 9

FIGURE 2. Pipeline A/D Converter Architecture.

ADS821

SBAS040B

9

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time-align it with the data created from the following quan-

tizer stages. This aligned data is fed into a digital error

correction circuit that can adjust the output data based on the

information found on the redundant bits. This technique gives

the ADS821 excellent differential linearity and ensures no

missing-codes at the 10-bit level.

•

For most applications, the clock duty should be set to

50%. For applications requiring no missing codes, how-

ever, a slight skew in the duty cycle will improve DNL

performance for conversion rates > 35MHz and input

frequencies < 2MHz (see Timing Diagram) in the SO

package. For the best performance in the SSOP pack-

age, the clock should be skewed under all input frequen-

cies with conversion rates > 35MHz. A possible method

for skewing the 50% duty cycle source is shown in Figure 4.

The output data is available in Straight Offset Binary (SOB) or

Binary Two’s Complement (BTC) format.

THE ANALOG INPUT AND INTERNAL REFERENCE

V_DD

The analog input of the ADS821 can be configured in various

ways and driven with different circuits, depending on the

nature of the signal and the level of performance desired. The

ADS821 has an internal reference that sets the full-scale

input range of the A/D converter. The differential input range

has each input centered around the common-mode of +2.25V,

with each of the two inputs having a full-scale range of +1.25V

to +3.25V. Since each input is 2Vp-p and 180° out-of-phase

with the other, a 4V differential input signal to the quantizer

results. As shown in Figure 3, the positive full-scale reference

(REFT) and the negative full-scale reference (REFB) are

brought out for external bypassing. In addition, the common-

mode (CM) voltage may be used as a reference to provide the

appropriate offset for the driving circuitry. However, care must

be taken not to appreciably load this reference node. For

more information regarding external references, single-ended

inputs, and ADS821 drive circuits, refer to the applications

section.

IC1, IC2 = ACT04

R_V

2kΩ

R_V= 217Ω, Typical

0.1µF

CLK_IN

CLK_OUT

IC1

IC2

FIGURE 4. Clock Skew Circuit.

DIGITAL OUTPUT DATA

The 10-bit output data is provided at CMOS logic levels. There

is a 6.5 clock cycle data latency from the start convert signal

to the valid output data. The standard output coding is Straight

Offset Binary where a full-scale input signal corresponds to all

“1’s” at the output. This condition is met with pin 19 LOW or

Floating due to an internal pull-down resistor. By applying a

high voltage to this pin, a BTC output will be provided where

the most significant bit is inverted. The digital outputs of the

ADS821 can be set to a high impedance state by driving OE

(pin 18) with a logic HIGH. Normal operation is achieved with

pin 18 LOW or Floating due to internal pull-down resistors. This

function is provided for testability purposes and is not meant to

drive digital buses directly or be dynamically changed during

the conversion process.

ADS821

+3.25V

REFT

23

0.1µF

2kΩ

To

Internal

CM

22

21

+2.25V

Comparators

2kΩ

REFB

0.1µF

+1.25V

OUTPUT CODE

SOB

PIN 19

FLOATING or LOW

BTC

PIN 19

HIGH

FIGURE 3. Internal Reference Structure.

DIFFERENTIAL INPUT⁽¹⁾

+FS (IN = +3.25V, IN = +1.25V)

+FS – 1LSB

+FS – 2LSB

+3/4 Full-Scale

+1/2 Full-Scale

+1/4 Full-Scale

+1LSB

Bipolar Zero (IN = IN = +2.25V)

–1LSB

–1/4 Full-Scale

1111111111

1111111110

1110000000

1100000000

1010000000

1000000001

1000000000

0111111111

0110000000

0100000000

0010000000

0000000001

0000000000

0111111111

0111111110

0110000000

0100000000

0010000000

0000000001

0000000000

1111111111

1110000000

1100000000

1010000000

1000000001

1000000000

CLOCK REQUIREMENTS

The CLK pin accepts a CMOS level clock input. Both the

rising and falling edges of the externally applied clock con-

trols the various interstage conversions in the pipeline. There-

fore, the clock signal’s jitter, rise-and-fall times and duty cycle

can affect conversion performance.

•

Low clock jitter is critical to SNR performance in fre-

–1/2 Full-Scale

–3/4 Full-Scale

–FS + 1LSB

–FS (IN = +1.25V, IN = +3.25V)

quency-domain signal environments.

•

Clock rise and fall times should be as short as possible

(< 2ns for best performance).

NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.

TABLE I. Coding Table for the ADS821.

ADS821

10

SBAS040B

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resistor of the OPA694 from the typical 402Ω to 360Ω

resulted in a wider bandwidth, thus improving distortion at

higher gains. The gain resistor was scaled to 120Ω, 75Ω, and

50Ω for each of the three gain settings. The two 330Ω

resistors set the RC time constant and the values can be

varied, although higher values will have the effect of moving

the corner frequency of the created high-pass filter down. In

Figure 6, the –3dB point is set at 4.2kHz.

APPLICATIONS

DRIVING THE ADS821

The ADS821 has a differential input with a common-mode of

+2.25V. For AC-coupled applications, the simplest way to

create this differential input is to drive the primary winding of

a transformer with a single-ended input. A differential output

is created on the secondary if the center tap is tied to the

common-mode (CM) voltage of +2.25V, as per Figure 5. This

transformer-coupled input arrangement provides good high-

frequency AC performance. It is important to select a trans-

former that gives low distortion and does not exhibit core

saturation at full-scale voltage levels. Since the transformer

does not appreciably load the ladder, there is no need to

buffer the CM output in this instance. In general, it is

advisable to keep the current draw from the CM output pin

below 0.5µA to avoid nonlinearity in the internal reference

ladder. A FET input operational amplifier such as the OPA130

can provide a buffered reference for driving external circuitry.

The analog IN and IN inputs should be bypassed with 22pF

capacitors to minimize track-and-hold glitches and to im-

prove high-input frequency performance.

Figure 7 illustrates another possible low-cost interface circuit

that utilizes resistors and capacitors in place of a transformer.

Depending on the signal bandwidth, the component values

should be carefully selected in order to maintain the perfor-

mance outlined in the data sheet. The input capacitors, C_IN,

and the input resistors, R_IN, create a high-pass filter with the

lower corner frequency at f_C= 1/(2πR_INC_IN). The corner

frequency can be reduced by either increasing the value of

R_INor C_IN. If the circuit operates with a 50Ω or 75Ω imped-

ance level, the resistors are fixed and only the value of the

capacitor can be increased. Usually AC-coupling capacitors

are electrolytic or tantalum capacitors with values of 1mF or

higher. It should be noted that these large capacitors become

inductive with increased input frequency, which could lead to

signal amplitude errors or oscillation. To maintain a low AC-

coupling impedance throughout the signal band, a small

value (e.g. 1µF) ceramic capacitor could be added in parallel

with the polarized capacitor.

Figure 6 shows an AC-coupled single-ended input interface

circuit using the low-cost, current feedback OPA694 as the

active gain stage. When testing this configuration in gains of

+4, +5.8, and +8.2, it was noted that reducing the feedback

Capacitors C_SH1and C_SH2are used to minimize current

glitches resulting from the switching in the input track-and-

hold stage and to improve signal-to-noise performance. These

capacitors can also be used to establish a low-pass filter and

effectively reduce the noise bandwidth. In order to create a

real pole, resistors R_SER1and R_SER2were added in series with

each input. The cut off frequency of the filter is determined by

f_C= 1/(2πR_SER• (C_SH+ C_ADC)) where R_SERis the resistor in

series with the input, C_SHis the external capacitor from the

input to ground, and C_ADCis the internal input capacitance of

the A/D converter (typically 4pF).

22 CM

0.1µF

26

27

IN

AC Input

Signal

ADS821

22pF

Mini-Circuits

TT1-6-KK81

or Equivalent

Resistors R₁and R₂are used to derive the necessary com-

mon-mode voltage from the buffered top and bottom refer-

ences. The total load of the resistor string should be selected

FIGURE 5. AC-Coupled, Single-Ended to Differential Drive

Circuit Using a Transformer.

+5V –5V

0.1 || 2.2

V_IN

OPA694

49.9Ω

IN

A₁

0.1µF

22pF

26

330Ω

I/O

ADS821

27

22

360Ω

IN

CM

+2.25V

0.1µF

R_G

0.1µF

FIGURE 6. Low-Cost, AC-Coupled, Single-Ended Input Circuit.

ADS821

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C₁

0.1µF

R₁

(1)

C_IN

0.1µF

R_SER1

49.9Ω

+3.25V

Top Reference

(6kΩ)

IN

C_SH1

22pF

R_IN1

25Ω

R₃

1kΩ

ADS8xx

V_CM

C₂

0.1µF

R_IN2

25Ω

(1)

C_IN

0.1µF

R_SER2

49.9Ω

C_SH2

22pF

+1.25V

Bottom Reference

R₂

(6kΩ)

NOTE: (1) indicates optional component.

C₃

0.1µF

FIGURE 7. AC-Coupled Differential Input Circuit.

EXTERNAL REFERENCES AND ADJUSTMENT OF

FULL-SCALE RANGE

so that the current does not exceed 1mA. Although the circuit

in Figure 7 uses two resistors of equal value so that the

common-mode voltage is centered between the top and bot-

tom reference (+2.25V), it is not necessary to do so. In all

cases the center point, V_CM, should be bypassed to ground in

order to provide a low-impedance AC ground.

The internal-reference buffers are limited to approximately

1mA of output current. As a result, these internal +1.25V and

+3.25V references may be overridden by external references

that have at least 18mA (at room temperature) of output drive

capability. In this instance, the common-mode voltage will be

set halfway between the two references. This feature can be

used to adjust the gain error, improve gain drift, or to change

the full-scale input range of the ADS821. Changing the full-

scale range to a lower value has the benefit of easing the

swing requirements of external input amplifiers. The external

references can vary as long as the value of the external top

reference (REFT_EXT) is less than or equal to +3.4V, the value

of the external bottom reference (REFB_EXT) is greater than or

equal to +1.1V, and the difference between the external

references are greater than or equal to 800mV.

If the signal needs to be DC-coupled to the input of the

ADS821, an operational amplifier input circuit is required. In

the differential input mode, any single-ended signal must be

modified to create a differential signal. This can be accom-

plished by using two operational amplifiers, one in the

noninverting mode for the input and the other amplifier in the

inverting mode for the complementary input. The low-distor-

tion circuit in Figure 8 will provide the necessary input shifting

required for signals centered around ground. It also employs

a diode for output level shifting to ensure a low-distortion

+3.25V output swing. See Figure 9 for another DC-coupled

circuit. Other amplifiers can be used in place of the OPA860

if the lowest distortion is not necessary. If output level shifting

circuits are not used, care must be taken to select opera-

tional amplifiers that give the necessary performance when

swinging to +3.25V with a ±5V supply operational amplifier.

The OPA620 and OPA621, or the lower power OPA650 or

OPA820 can be used in place of the OPA860 in Figure 8. In

that configuration, the OPA820 will typically swing to within

100mV of positive full scale.

For the differential configuration, the full-scale input range

will be set to the external reference values that are

selected. For the single-ended mode, the input range is

2 • (REFT_EXT– REFB_EXT), with the common-mode being

centered at (REFT_EXT+ REFB_EXT)/2. Refer to the Typical

Characteristics for expected performance versus full-scale

input range.

The circuit in Figure 11 works completely on a single +5V

supply. As a reference element, it uses the microPower

reference REF1004-2.5, which is set to a quiescent current

of 0.1mA. Amplifier A₂is configured as a follower to buffer the

+1.25V generated from the resistor divider. To provide the

necessary current drive, a pull-down resistor (R_P) is added.

The ADS821 can also be configured with a single-ended input

full-scale range of +0.25V to +4.25V by tying the complemen-

tary input to the common-mode reference voltage, see Figure 10.

This configuration will result in increased even-order harmon-

ics, especially at higher input frequencies. This tradeoff,

however, may be quite acceptable for time-domain applica-

tions. The driving amplifier must give adequate performance

with a +0.25V to +4.25V output swing in this case.

Amplifier A₁is configured as an adjustable gain stage, with

a range of approximately 1 to 1.32. The pull-up resistor again

relieves the op amp from providing the full current drive. The

value of the pull-up, pull-down resistors is not critical and can

be varied to optimize power consumption. The need for pull-

up, pull-down resistors depends only on the drive capability

of the selected drive amplifier and thus can be omitted.

ADS821

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+5V

604Ω

+5V

301Ω

BAS16⁽¹⁾

Optional

High Impedance

Input Amplifier

27 IN

301Ω

OPA842

301Ω

2.49kΩ

0.1µF

22pF

+5V⁽²⁾

0.1µF

+5V

–5V

604Ω

DC-Coupled

Input Signal

ADS821

OPA842

604Ω

49.9Ω

+2.25V

OPA130

2.49kΩ

22 CM

+5V

–5V

+5V

24.9Ω

301Ω

Input Level

Shift Buffer

301Ω

BAS16⁽¹⁾

0.1µF

26 IN

OPA842

22pF

604Ω

–5V

NOTES: (1) A Philips BAS16 diode or equivalent may be used.

(2) Supply bypassing not shown.

301Ω

FIGURE 8. A Low-Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit.

243Ω

1

2kΩ

–5V

3

2

B

E

DC-Coupled

Input Signal

C

V_OUT

26 IN

OTA

+1

6

1kΩ

22pF

OPA860

1nF

200Ω

8

5

+5V

ADS821

500Ω

1kΩ

2

3

50Ω

OPA130

1kΩ

22 CM

0.1µF

200Ω

C₁

15pF

8

5

2

3

E

V_OUT

27 IN

OTA

+1

200Ω

B

6

1

C

243Ω

22pF

–5V

OPA860

NOTE: Power supplies and bypassing not shown. The measured SNR performance with 12.5MHz input signal is 57dB with this driver circuit.

FIGURE 9. A Wideband DC-Coupled, Single-Ended to Differential Input Driver Circuit.

ADS821

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13

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results. Highly accurate phase-locked signal sources allow

high resolution FFT measurements to be made without using

data windowing functions. A low jitter signal generator, such as

the HP8644A for the test signal, phase-locked with a low jitter

HP8022A pulse generator for the A/D converter clock, gives

excellent results. Low-pass filtering (or bandpass filtering) of

test signals is absolutely necessary to test the low distortion of

the ADS821. Using a signal amplitude slightly lower than full

scale will allow a small amount of “headroom” so that noise or

DC offset voltage will not overrange the A/D converter and

cause clipping on signal peaks.

22 CM

0.1µF

ADS821

Single-Ended

Input Signal

26 IN

27 IN

22pF

Full-Scale = +0.25V to +4.25V with internal references.

FIGURE 10. Single-Ended Input Connection.

DYNAMIC PERFORMANCE DEFINITIONS

1. Signal-to-Noise-and-Distortion Ratio (SINAD):

PC-BOARD LAYOUT AND BYPASSING

A well-designed, clean PC-board layout will assure proper

operation and clean spectral response. Proper grounding

and bypassing, short lead lengths, and the use of ground

planes are particularly important for high-frequency circuits.

Multilayer PC-boards are recommended for best perfor-

mance but if carefully designed, a two-sided PC-board with

large, heavy ground planes can give excellent results. It is

recommended that the analog and digital ground pins of the

ADS821 be connected directly to the analog ground plane. In

our experience, this gives the most consistent results. The

A/D converter power-supply commons should be tied to-

gether at the analog ground plane. Power supplies should be

bypassed with 0.1µF ceramic capacitors as close to the pin

as possible.

Sinewave SignalPower

10 log

Noise + Harmonic Power (first 15 harmonics)

2. Signal-to-Noise Ratio (SNR):

Sinewave SignalPower

10 log

Noise Power

3. Intermodulation Distortion (IMD):

Highest IMD Pr oduct Power (to 5th−order)

10 log

Sinewave SignalPower

IMD is referenced to the larger of the test signals f₁or f₂. Five

“bins” either side of peak are used for calculation of funda-

mental and harmonic power. The “0” frequency bin (DC) is

not included in these calculations as it is of little importance

in dynamic signal processing applications.

DYNAMIC PERFORMANCE TESTING

The ADS821 is a high-performance converter and careful

attention to test techniques is necessary to achieve accurate

+5V

R_P

220Ω

A₁

Top

1/2

OPA2234

Reference

+5V

+2.5V to +3.25V

2kΩ

10kΩ

6.2kΩ

10kΩ

REF1004

10kΩ⁽¹⁾

A₂

+2.5V

0.1µF

+1.25V

1/2

Bottom

Reference

OPA2234

10kΩ

R_P

10kΩ⁽¹⁾

220Ω

NOTE: (1) Use parts alternatively for adjustment capability.

FIGURE 11. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp.

ADS821

14

SBAS040B

www.ti.com

FIGURE 12. ADS821 Interface Schematic with AC-Coupling and External Buffers.

ADS821

SBAS040B

15

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

14-Feb-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

SSOP

SOIC

Drawing

ADS821E

ADS821E/1K

ADS821U

OBSOLETE

ACTIVE

DB

28

None

Call TI

DB

Call TI

DW

28

CU SNPB

Level-3-220C-168 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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