ADSP-21161N
ELECTRICAL CHARACTERISTICS
Parameter Description
Test Conditions
Min
Max
Unit
VOH
VOL
IIH
IIL
IIHC
IILC
IIKH
IIKL
IIKH-OD
IIKL-OD
IILPU
IOZH
IOZL
IOZLPU1
IOZLPU2
IOZHPD1
IOZHPD2
IDD-INPEAK
High Level Output Voltage1
@ VDDEXT = Min, IOH = –2.0 mA2
@ VDDEXT = Min, IOL = 4.0 mA2
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 2.0 V
@ VDDEXT = Max, VIN = 0.8 V
@ VDDEXT = Max
2.4
V
V
Low Level Output Voltage1
0.4
10
10
35
35
High Level Input Current3, 4
Low Level Input Current3
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
CLKIN High Level Input Current5
CLKIN Low Level Input Current5
Keeper High Load Current6
–250
50
–300
300
–100
200
Keeper Low Load Current6
Keeper High Overdrive Current6, 7, 8
Keeper Low Overdrive Current6, 7, 8
Low Level Input Current Pull-Up4
Three-State Leakage Current9, 10, 11
Three-State Leakage Current9, 12, 13
Three-State Leakage Current Pull-Up110
Three-State Leakage Current Pull-Up211
Three-State Leakage Current Pull-Down112
Three-State Leakage Current Pull-Down213
Supply Current (Internal)14, 15
@ VDDEXT = Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = VDDEXT Max
tCCLK = 9.0 ns, VDDINT = Max
350
10
10
500
350
350
500
965
900
t
CCLK = 10.0 ns, VDDINT = Max
tCCLK = 9.0 ns, VDDINT = Max
CCLK = 10.0 ns, VDDINT = Max
tCCLK = 9.0 ns, VDDINT = Max
CCLK = 10.0 ns, VDDINT = Max
tCCLK = 9.0 ns, VDDINT = Max
CCLK = 10.0 ns, VDDINT = Max
IDD-INHIGH
IDD-INLOW
IDD-IDLE
Supply Current (Internal)15, 16
Supply Current (Internal)15, 17
Supply Current (Idle)15, 18
700
650
mA
mA
mA
t
535
500
t
425
400
t
AIDD
CIN
Supply Current (Analog)19
Input Capacitance20, 21
@ AVDD = Max
fIN = 1 MHz, TCASE = 25°C, VIN = 1.8 V
10
4.7
mA
pF
1
Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,
BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL,
TDO, CLKOUT, TIMEXP, RSTOUT.
2 See Output Drive Currents on Page 54 for typical drive current capabilities.
3 Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE,
SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN.
4 Applies to input pins with 20 k internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.
5 Applies to CLKIN only.
6 Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.
7 Current required to switch from kept high to low or from kept low to high.
8 Characterized, but not tested.
9 Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10,
BRST.
10Applies to three-statable pins with 20 kpull-ups: RD, WR, DMAG1, DMAG2, PA.
11Applies to three-statable pins with 50 k internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI.
12Applies to three-statable pins with 50 k internal pull-downs: LxDAT7–0 (below Revision1.2), LxCLK, LxACK. Use IOZHPD2 for Rev. 1.2 and higher.
13Applies to three-statable pins with 20 k internal pull-downs: LxDAT7-0 (Revision 1.2 and higher).
14The test program used to measure IDDINPEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 20.
15Current numbers are for VDDINT and AVDD supplies combined.
16
I
I
is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page 20.
is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 20.
DDINHIGH
17
DDINLOW
18Idle denotes ADSP-21161N state during execution of IDLE instruction. For more information, see Power Dissipation on Page 20.
19Characterized, but not tested.
20Applies to all signal pins.
21Guaranteed, but not tested.
Rev. C
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Page 18 of 60
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January 2013