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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • ADSP-21161NCCAZ100
  • 数量-
  • 厂家-
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  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • ADSP-21161NCCAZ100图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • ADSP-21161NCCAZ100 三甲现货
  • 数量1260 
  • 厂家ADI 
  • 封装原装现货 
  • 批号24+ 
  • 全新原装现货认证企业!
  • QQ:3003819484QQ:3003819484 复制
    QQ:3003818780QQ:3003818780 复制
  • 0755-88608527 QQ:3003819484QQ:3003818780
  • ADSP-21161NCCAZ100图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • ADSP-21161NCCAZ100 现货库存
  • 数量12500 
  • 厂家ADI/亚德诺 
  • 封装CSPBGA-225 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • ADSP-21161NCCAZ100图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • ADSP-21161NCCAZ100 现货库存
  • 数量2500 
  • 厂家AD 
  • 封装BGA 
  • 批号24+ 
  • 原装假一赔百,深圳现货,北美、新加坡可发货
  • QQ:800888908QQ:800888908 复制
  • 755-83950019 QQ:800888908
  • ADSP-21161NCCAZ100图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • ADSP-21161NCCAZ100 现货库存
  • 数量26980 
  • 厂家ADI 
  • 封装BGA 
  • 批号21+ 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • ADSP-21161NCCAZ100图
  • 深圳市欧昇科技有限公司

     该会员已使用本站2年以上
  • ADSP-21161NCCAZ100 现货库存
  • 数量12 
  • 厂家ADI/亚德诺 
  • 封装BGA 
  • 批号0702+ 
  • 只做原装现货实单可谈
  • QQ:2885528234QQ:2885528234 复制
  • -0755-83220848 QQ:2885528234
  • ADSP-21161NCCAZ100图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • ADSP-21161NCCAZ100 优势库存
  • 数量65694 
  • 厂家AD 
  • 封装BGA 
  • 批号24+ 
  • 绝对全新原装进口现货热卖,价格优势
  • QQ:198857245QQ:198857245 复制
  • 0755-82865294 QQ:198857245
  • ADSP-21161NCCAZ100图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • ADSP-21161NCCAZ100 优势库存
  • 数量4500 
  • 厂家AD 
  • 封装BGA 
  • 批号22+ 
  • 绝对全新原装!优势供货渠道!特价!请放心订购!
  • QQ:2355507168QQ:2355507168 复制
    QQ:2355507169QQ:2355507169 复制
  • 86-755-83219286 QQ:2355507168QQ:2355507169
  • ADSP-21161NCCAZ100图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • ADSP-21161NCCAZ100
  • 数量26700 
  • 厂家ADI(亚德诺) 
  • 封装▊原厂封装▊ 
  • 批号▊ROHS环保▊ 
  • 十年以上分销商原装进口件服务型企业0755-83790645
  • QQ:2881664479QQ:2881664479 复制
  • 755-83790645 QQ:2881664479
  • ADSP-21161NCCAZ100图
  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
  • ADSP-21161NCCAZ100
  • 数量8460 
  • 厂家ADI代理 
  • 封装原厂原封装 
  • 批号NEW 
  • 全新原装假一罚十热卖
  • QQ:1134344845QQ:1134344845 复制
    QQ:847984313QQ:847984313 复制
  • 86-0755-83536093 QQ:1134344845QQ:847984313
  • ADSP-21161NCCAZ100图
  • 深圳市华科泰电子商行

     该会员已使用本站13年以上
  • ADSP-21161NCCAZ100
  • 数量37 
  • 厂家AD 
  • 封装BGA 
  • 批号07+ 
  • 绝对原装现货特价
  • QQ:405945546QQ:405945546 复制
    QQ:1439873477QQ:1439873477 复制
  • 0755-82567800 QQ:405945546QQ:1439873477
  • ADSP-21161NCCAZ100图
  • 现代芯城(深圳)科技有限公司

     该会员已使用本站15年以上
  • ADSP-21161NCCAZ100
  • 数量54000 
  • 厂家一级代理 
  • 封装一级代理 
  • 批号一级代理 
  • 一级代理正品采购
  • QQ:3007226851QQ:3007226851 复制
    QQ:3007226849QQ:3007226849 复制
  • 0755-82542579 QQ:3007226851QQ:3007226849
  • ADSP-21161NCCAZ100图
  • 北京耐芯威科技有限公司

     该会员已使用本站13年以上
  • ADSP-21161NCCAZ100
  • 数量5000 
  • 厂家Analog Devices Inc. 
  • 封装225-CSPBGA(17x17) 
  • 批号21+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 86-010-010-62104931 QQ:2880824479QQ:1344056792
  • ADSP-21161NCCAZ100图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • ADSP-21161NCCAZ100
  • 数量
  • 厂家ADI/亚德诺 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • ADSP-21161NCCAZ100图
  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • ADSP-21161NCCAZ100
  • 数量5000 
  • 厂家Analog Devices Inc. 
  • 封装225-CSPBGA(17x17) 
  • 批号21+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 96-010-62104931 QQ:2880824479QQ:1344056792
  • ADSP-21161NCCAZ100图
  • 集好芯城

     该会员已使用本站13年以上
  • ADSP-21161NCCAZ100
  • 数量16589 
  • 厂家ADI/亚德诺 
  • 封装CSPBGA 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • ADSP-21161NCCAZ100图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • ADSP-21161NCCAZ100
  • 数量15862 
  • 厂家ADI 
  • 封装BGA 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • ADSP-21161NCCAZ100图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • ADSP-21161NCCAZ100
  • 数量15862 
  • 厂家ADI 
  • 封装BGA 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • ADSP-21161NCCAZ100图
  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • ADSP-21161NCCAZ100
  • 数量3000 
  • 厂家ADI 
  • 封装BGA225 
  • 批号23+ 
  • 全新原装正品现货
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
  • ADSP-21161NCCAZ100图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • ADSP-21161NCCAZ100
  • 数量30000 
  • 厂家ADI/亚德诺 
  • 封装BGA 
  • 批号23+ 
  • 只做原装现货假一罚十
  • QQ:2103443489QQ:2103443489 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
  • ADSP-21161NCCAZ100图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • ADSP-21161NCCAZ100
  • 数量3000 
  • 厂家ADI 
  • 封装CSPBGA225 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507162QQ:2355507162 复制
    QQ:2355507165QQ:2355507165 复制
  • 86-755-83616256 QQ:2355507162QQ:2355507165
  • ADSP-21161NCCAZ100图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • ADSP-21161NCCAZ100
  • 数量75200 
  • 厂家ADI/亚德诺 
  • 封装N/A 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • ADSP-21161NCCAZ100图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • ADSP-21161NCCAZ100
  • 数量85000 
  • 厂家ADI/亚德诺 
  • 封装CSPBGA-225 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • ADSP-21161NCCAZ100图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • ADSP-21161NCCAZ100
  • 数量12500 
  • 厂家ADI/亚德诺 
  • 封装CSPBGA-225 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 美驻深办0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • ADSP-21161NCCAZ100图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • ADSP-21161NCCAZ100
  • 数量5000 
  • 厂家Analog Devices Inc. 
  • 封装225-CSPBGA(17x17) 
  • 批号2024+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • ADSP-21161NCCAZ100图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • ADSP-21161NCCAZ100
  • 数量4035 
  • 厂家ADI 
  • 封装255-BGA,CSPBGA 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
    QQ:2881894392QQ:2881894392 复制
  • 0755- QQ:2881894393QQ:2881894392
  • ADSP-21161NCCAZ100图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • ADSP-21161NCCAZ100
  • 数量12300 
  • 厂家ADI/亚德诺 
  • 封装BGA225 
  • 批号24+ 
  • ★原装真实库存★13点税!
  • QQ:2353549508QQ:2353549508 复制
    QQ:2885134615QQ:2885134615 复制
  • 0755-83201583 QQ:2353549508QQ:2885134615
  • ADSP-21161NCCAZ100图
  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
  • ADSP-21161NCCAZ100
  • 数量5800 
  • 厂家AD 
  • 封装BGA 
  • 批号2024+ 
  • 全新原装现货,杜绝假货。
  • QQ:3003653665QQ:3003653665 复制
    QQ:1325513291QQ:1325513291 复制
  • 021-60341766 QQ:3003653665QQ:1325513291
  • ADSP-21161NCCAZ100图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • ADSP-21161NCCAZ100
  • 数量5000 
  • 厂家Analog Devices Inc. 
  • 封装225-CSPBGA(17x17) 
  • 批号2024+ 
  • 全新原装、现货库存,欢迎询价
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • ADSP-21161NCCAZ100图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • ADSP-21161NCCAZ100
  • 数量15300 
  • 厂家Analog Devices Inc. 
  • 封装255-BGA,CSPBGA 
  • 批号24+ 
  • 只做原装★真实库存★含13点增值税票!
  • QQ:2885134615QQ:2885134615 复制
    QQ:2353549508QQ:2353549508 复制
  • 0755-83201583 QQ:2885134615QQ:2353549508
  • ADSP-21161NCCAZ100图
  • 深圳市正信鑫科技有限公司

     该会员已使用本站12年以上
  • ADSP-21161NCCAZ100
  • 数量3603 
  • 厂家AD 
  • 封装原厂封装 
  • 批号22+ 
  • 原装正品★真实库存★价格优势★欢迎来电洽谈
  • QQ:1686616797QQ:1686616797 复制
    QQ:2440138151QQ:2440138151 复制
  • 0755-22655674 QQ:1686616797QQ:2440138151
  • ADSP-21161NCCAZ100图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • ADSP-21161NCCAZ100
  • 数量98500 
  • 厂家AD 
  • 封装BGA 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • ADSP-21161NCCAZ100图
  • 深圳市华芯盛世科技有限公司

     该会员已使用本站13年以上
  • ADSP-21161NCCAZ100
  • 数量865000 
  • 厂家ADI/亚德诺 
  • 封装CSPBGA-225 
  • 批号最新批号 
  • 一级代理,原装特价现货!
  • QQ:2881475757QQ:2881475757 复制
  • 0755-83225692 QQ:2881475757
  • ADSP-21161NCCAZ100图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • ADSP-21161NCCAZ100
  • 数量2500 
  • 厂家AD 
  • 封装BGA 
  • 批号2021+ 
  • 原装假一赔十!可提供正规渠道证明!
  • QQ:3003818780QQ:3003818780 复制
    QQ:3003819484QQ:3003819484 复制
  • 755-83950019 QQ:3003818780QQ:3003819484
  • ADSP-21161NCCAZ100图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • ADSP-21161NCCAZ100
  • 数量660000 
  • 厂家ADI(亚德诺)/LINEAR(凌特) 
  • 封装BGA-225 
  • 批号23+ 
  • 支持实单/只做原装
  • QQ:3008961398QQ:3008961398 复制
  • 0755-21006672 QQ:3008961398
  • ADSP-21161NCCAZ100图
  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • ADSP-21161NCCAZ100
  • 数量10000 
  • 厂家AD 
  • 封装BGA 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
  • QQ:1091796029QQ:1091796029 复制
    QQ:916896414QQ:916896414 复制
  • 0755-82772151 QQ:1091796029QQ:916896414
  • ADSP-21161NCCAZ100图
  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • ADSP-21161NCCAZ100
  • 数量5500 
  • 厂家AD 
  • 封装BGA 
  • 批号20+ 
  • 百分百原装正品 真实公司现货库存 本公司只做原装 可开13%增值税发票,支持样品,欢迎来电咨询!
  • QQ:1437347957QQ:1437347957 复制
    QQ:1205045963QQ:1205045963 复制
  • 0755-82343089 QQ:1437347957QQ:1205045963
  • ADSP-21161NCCAZ100图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • ADSP-21161NCCAZ100
  • 数量30000 
  • 厂家AD 
  • 封装CSPBGA 
  • 批号23+ 
  • 代理全新原装现货,价格优势
  • QQ:1774550803QQ:1774550803 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82777855 QQ:1774550803QQ:2924695115
  • ADSP-21161NCCAZ100图
  • 深圳市一呈科技有限公司

     该会员已使用本站9年以上
  • ADSP-21161NCCAZ100
  • 数量7361 
  • 厂家ADI/亚德诺 
  • 封装BGA 
  • 批号22+ 
  • ▉原装正品▉低价力挺实单全系列可订
  • QQ:3003797048QQ:3003797048 复制
    QQ:3003797050QQ:3003797050 复制
  • 0755-82779553 QQ:3003797048QQ:3003797050
  • ADSP-21161NCCAZ100图
  • 深圳市正纳电子有限公司

     该会员已使用本站2年以上
  • ADSP-21161NCCAZ100
  • 数量8000 
  • 厂家ADI(亚德诺) 
  • 封装N/A 
  • 批号22+ 
  • 原装现货★★★
  • QQ:2881664480QQ:2881664480 复制
  • 0755-82524192 QQ:2881664480
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产品型号ADSP-21161NCCAZ100的概述

ADSP-21161NCCAZ100 概述 ADSP-21161NCCAZ100 是由 Analog Devices 生产的一款数字信号处理器(DSP),它以其卓越的性能和灵活的设计,广泛用于各种信号处理应用,包括但不限于音频处理、图像处理、通信、雷达和控制系统。该 DSP 是 ADSP-21xxx 系列的一员,这一系列以高性能和多样的功能模块著称,ADSP-21161 特别适合要求高计算能力和高吞吐量的应用场景。 ADSP-21161NCCAZ100 拥有双发射和多通道的 SCSI 风格的数据传输接口,提供出色的集成度和可编程性。它具有强大的并列处理能力,可以极大地提高数据处理速度,为嵌入式应用提供支持。 芯片详细参数 ADSP-21161NCCAZ100 的主要技术参数如下: - 处理器架构: 超标量架构,提供并行运算能力。 - 时钟频率: 100 MHz。 - 数据宽度: 32 ...

产品型号ADSP-21161NCCAZ100的Datasheet PDF文件预览

SHARC Processor  
ADSP-21161N  
Integrated peripherals—integrated I/O processor, 1M bit on-  
chip dual-ported SRAM, SDRAM controller, glueless multi-  
processing features, and I/O ports (serial, link, external  
bus, SPI, and JTAG)  
ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit  
floating-point formats  
100 MHz/110 MHz core instruction rate  
Single-cycle instruction execution, including SIMD opera-  
tions in both computational units  
Up to 660 MFLOPs peak and 440 MFLOPs sustained  
performance  
SUMMARY  
High performance 32-Bit DSP—applications in audio, medi-  
cal, military, wireless communications, graphics, imaging,  
motor-control, and telephony  
Super Harvard Architecture—four independent buses for  
dual data fetch, instruction fetch, and nonintrusive zero-  
overhead I/O  
Code compatible with all other sharc family DSPs  
Single-instruction multiple-data (SIMD) computational archi-  
tecture—two 32-bit IEEE floating-point computation units,  
each with a multiplier, ALU, shifter, and register file  
Serial ports offer I2S support via 8 programmable and simul-  
taneous receive or transmit pins, which support up to 16  
transmit or 16 receive channels of audio  
225-ball 17 mm 17 mm CSP_BGA package  
DUAL-PORTED SRAM  
CORE PROCESSOR  
INSTRUCTION  
6
JTAG TEST  
AND EMULATION  
TWO INDEPENDENT  
DUAL-PORTED BLOCKS  
CACHE  
32 u 48-BIT  
TIMER  
I/O PORT  
PROCESSOR PORT  
ADDR DATA  
12  
8
GPIO  
FLAGS  
DATA  
DATA  
ADDR  
ADDR  
ADDR  
DATA  
DAG1  
8 u 4 u 32  
DAG2  
8 u 4 u 32  
PROGRAM  
SEQUENCER  
SDRAM  
CONTROLLER  
IOD  
64  
IOA  
18  
EXTERNAL PORT  
32  
32  
24  
32  
ADDR BUS  
MUX  
PM ADDRESS BUS  
DM ADDRESS BUS  
64  
64  
MULTIPROCESSOR  
INTERFACE  
BUS  
CONNECT  
(PX)  
PM DATA BUS  
DM DATA BUS  
DATA BUS  
MUX  
DATA  
REGISTER  
FILE  
(PEY)  
16 u 40-BIT  
DATA  
REGISTER  
FILE  
(PEX)  
16 u 40-BIT  
HOST PORT  
BARREL  
SHIFTER  
BARREL  
SHIFTER  
MULT  
MULT  
5
DMA  
CONTROLLER  
IOP  
REGISTERS  
(MEMORY MAPPED)  
ALU  
ALU  
16  
20  
4
SERIAL PORTS (4)  
CONTROL,  
STATUS, &  
DATA BUFFERS  
LINK PORTS (2)  
SPI PORTS (1)  
S
I/O PROCESSOR  
Figure 1. ADSP-21161N Functional Block Diagram  
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. C Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2013 Analog Devices, Inc. All rights reserved.  
www.analog.com  
ADSP-21161N  
TABLE OF CONTENTS  
Summary ............................................................... 1  
General Description ................................................. 3  
ADSP-21161N Family Core Architecture .................... 3  
ADSP-21161N Memory and I/O Interface Features ....... 5  
Development Tools ............................................... 9  
Additional Information ........................................ 10  
Related Signal Chains .......................................... 10  
Pin Function Descriptions ....................................... 11  
Boot Modes ....................................................... 16  
Specifications ........................................................ 17  
Operating Conditions .......................................... 17  
Electrical Characteristics ....................................... 18  
Package Information ........................................... 19  
Absolute Maximum Ratings ................................... 19  
ESD Caution ...................................................... 19  
Timing Specifications ........................................... 19  
Power Dissipation ............................................... 20  
Output Drive Currents ......................................... 54  
Test Conditions .................................................. 54  
Environmental Conditions .................................... 55  
225-Ball CSP_BGA Ball Configurations ....................... 56  
Outline Dimensions ................................................ 58  
Surface-Mount Design .......................................... 58  
Ordering Guide ..................................................... 58  
REVISION HISTORY  
1/13—Rev. B to Rev. C  
Updated Development Tools ...................................... 9  
Added section, Related Signal Chains .......................... 10  
Added footnote 3 to Table 16 in  
Memory Read — Bus Master .................................... 27  
Rev. C  
|
Page 2 of 60  
|
January 2013  
ADSP-21161N  
GENERAL DESCRIPTION  
The ADSP-21161N SHARC® DSP is a low cost derivative of the  
ADSP-21160 featuring Analog Devices Super Harvard Archi-  
tecture. Easing portability, the ADSP-21161N is source code  
compatible with the ADSP-21160 and with first generation  
ADSP-2106x SHARC processors in SISD (Single-Instruction,  
Single-Data) mode. Like other SHARC DSPs, the ADSP-  
21161N is a 32-bit processor that is optimized for high perfor-  
mance DSP applications. The ADSP-21161N includes a  
100 MHz or 110 MHz core, a dual-ported on-chip SRAM, an  
integrated I/O processor with multiprocessing support, and  
multiple internal buses to eliminate I/O bottlenecks.  
The block diagram of the ADSP-21161N on Page 1 illustrates  
the following architectural features:  
• Two processing elements, each made up of an ALU, multi-  
plier, shifter, and data register file  
• Data address generators (DAG1, DAG2)  
• Program sequencer with instruction cache  
• PM and DM buses capable of supporting four 32-bit data  
transfers between memory and the core every core proces-  
sor cycle  
• Interval timer  
As was first offered in the ADSP-21160, the ADSP-21161N  
offers a single-instruction multiple-data (SIMD) architecture.  
Using two computational units (ADSP-2106x SHARC proces-  
sors have one), the ADSP-21161N can double cycle  
performance versus the ADSP-2106x on a range of DSP  
algorithms.  
• On-Chip SRAM (1M bit)  
• SDRAM controller for glueless interface to SDRAMs  
• External port that supports:  
• Interfacing to off-chip memory peripherals  
• Glueless multiprocessing support for six  
ADSP-21161N SHARCs  
Fabricated in a state of the art, high speed, low power CMOS  
process, the ADSP-21161N has a 10 ns or 9 ns instruction cycle  
time. With its SIMD computational hardware running at  
110 MHz, the ADSP-21161N can perform 660 million floating-  
point operations per second. Table 1 shows performance bench-  
marks for the ADSP-21161N.  
• Host port read/write of IOP registers  
• DMA controller  
• Four serial ports  
These benchmarks provide single-channel extrapolations of  
measured dual-channel processing performance. For more  
information on benchmarking and optimizing DSP code, for  
both single and dual-channel processing, see the Analog Devices  
Inc. website.  
• Two link ports  
• SPI compatible interface  
• JTAG test access port  
• 12 general-purpose I/O pins  
Figure 2 shows a typical single-processor system. A multipro-  
cessing system appears in Figure 5 on Page 8.  
Table 1. Benchmarks  
100 MHz  
Instruction  
Rate  
110 MHz  
Instruction  
Rate  
ADSP-21161N FAMILY CORE ARCHITECTURE  
The ADSP-21161N includes the following architectural features  
of the ADSP-2116x family core. The ADSP-21161N is code  
compatible at the assembly level with the ADSP-21160,  
ADSP-21060, ADSP-21061, ADSP-21062, and ADSP-21065L.  
Benchmark Algorithm  
1024 Point Complex FFT  
(Radix 4, with Reversal)  
92 μs  
83.6 μs  
FIR Filter (Per Tap)  
IIR Filter (Per Biquad)  
Matrix Multiply (Pipelined)  
[3 3] [3 1]  
[4 4] [4 1]  
Divide (y/x)  
5 ns  
4.5 ns  
SIMD Computational Engine  
20 ns  
18.18 ns  
The ADSP-21161N contains two computational processing ele-  
ments that operate as a single-instruction multiple-data (SIMD)  
engine. The processing elements are referred to as PEX and  
PEY, and each contains an ALU, multiplier, shifter, and register  
file. PEX is always active, and PEY may be enabled by setting the  
PEYEN mode bit in the MODE1 register. When this mode is  
enabled, the same instruction is executed in both processing ele-  
ments, but each processing element operates on different data.  
This architecture is efficient at executing math intensive DSP  
algorithms.  
45 ns  
40.9 ns  
80 ns  
72.72 ns  
54.54 ns  
36.36 ns  
880M bytes/s  
60 ns  
Inverse Square Root  
DMA Transfers  
40 ns  
800M bytes/s  
The ADSP-21161N continues SHARC’s industry-leading stan-  
dards of integration for DSPs, combining a high performance  
32-bit DSP core with integrated, on-chip system features. These  
features include a 1M bit dual ported SRAM memory, host pro-  
cessor interface, I/O processor that supports 14 DMA channels,  
four serial ports, two link ports, SDRAM controller, SPI inter-  
face, external parallel bus, and glueless multiprocessing.  
Entering SIMD mode also has an effect on the way data is trans-  
ferred between memory and the processing elements. When in  
SIMD mode, twice the data bandwidth is required to sustain  
computational operation in the processing elements. Because of  
this requirement, entering SIMD mode also doubles the  
bandwidth between memory and the processing elements.  
Rev. C  
|
Page 3 of 60  
|
January 2013  
ADSP-21161N  
When using the DAGs to transfer data in SIMD mode, two data  
values are transferred with each access of memory or the regis-  
ter file.  
Data Register File  
A general-purpose data register file is contained in each pro-  
cessing element. The register files transfer data between the  
computation units and the data buses, and store intermediate  
results. These 10-port, 32-register (16 primary, 16 secondary)  
register files, combined with the SHARC enhanced Harvard  
architecture, allow unconstrained data flow between computa-  
tion units and internal memory. The registers in PEX are  
referred to as R0–R15 and in PEY as S0–S15.  
SIMD is supported only for internal memory accesses and is not  
supported for off-chip accesses.  
Independent, Parallel Computation Units  
Within each processing element is a set of computational units.  
The computational units consist of an arithmetic/logic unit  
(ALU), multiplier, and shifter. These units perform single-cycle  
instructions. The three units within each processing element are  
arranged in parallel, maximizing computational throughput.  
Single multifunction instructions execute parallel ALU and  
multiplier operations. In SIMD mode, the parallel ALU and  
multiplier operations occur in both processing elements. These  
computation units support IEEE 32-bit single-precision float-  
ing-point, 40-bit extended precision floating-point, and 32-bit  
fixed-point data formats.  
Single-Cycle Fetch of Instruction and Four Operands  
The ADSP-21161N features an enhanced Harvard architecture  
in which the data memory (DM) bus transfers data and the pro-  
gram memory (PM) bus transfers both instructions and data  
(see Figure 2). With the ADSP-21161N’s separate program and  
data memory buses and on-chip instruction cache, the proces-  
sor can simultaneously fetch four operands (two over each data  
bus) and an instruction (from the cache), all in a single cycle.  
ADSP-21161N  
CLKIN  
CLOCK  
XTAL  
2
CLK_CFG1-0  
CLKDBL  
EBOOT  
BMS  
CS  
BOOT  
EPROM  
(OPTIONAL)  
ADDR  
DATA  
LBOOT  
IRQ2-0  
BRST  
3
12  
FLAG11-0  
ADDR23-0  
ADDR  
TIMEXP  
RPBA  
ID2-0  
MEMORY  
AND  
PERIPHERALS  
(OPTIONAL)  
DATA47-16  
RD  
DATA  
OE  
WE  
LINK  
DEVICES  
(2 MAX)  
WR  
LXCLK  
ACK  
MS3-0  
ACK  
CS  
LXACK  
(OPTIONAL)  
LXDAT7-0  
RAS  
CAS  
RAS  
CAS  
SCLK0  
FS0  
D0A  
D0B  
SERIAL  
DEVICE  
(OPTIONAL)  
SDRAM  
(OPTIONAL)  
DQM  
DQM  
SDWE  
WE  
SDCLK1-0  
CLK  
SCLK1  
FS1  
D1A  
SERIAL  
DEVICE  
(OPTIONAL)  
SDCKE  
SDA10  
CKE  
A10  
CS  
D1B  
ADDR  
SCLK2  
FS2  
D2A  
D2B  
SERIAL  
DEVICE  
(OPTIONAL)  
DATA  
CLKOUT  
DMAR2-1  
DMA DEVICE  
(OPTIONAL)  
DMAG2-1  
SCLK3  
FS3  
D3A  
D3B  
SERIAL  
DEVICE  
(OPTIONAL)  
DATA  
CS  
HBR  
HOST  
PROCESSOR  
INTERFACE  
(OPTIONAL)  
HBG  
REDY  
SPICLK  
SPIDS  
SPI  
COMPATIBLE  
DEVICE  
(HOST OR SLAVE)  
BR6-1  
ADDR  
DATA  
MOSI  
MISO  
PA  
(OPTIONAL)  
SBTS  
RESET RSTOUT JTAG  
7
Figure 2. System Diagram  
Rev. C  
|
Page 4 of 60  
|
January 2013  
ADSP-21161N  
each memory block, assures single-cycle execution with two  
data transfers. In this case, the instruction must be available in  
the cache.  
Instruction Cache  
The ADSP-21161N includes an on-chip instruction cache that  
enables three-bus operation for fetching an instruction and four  
data values. The cache is selective—only the instructions whose  
fetches conflict with PM bus data accesses are cached. This  
cache enables full-speed execution of core, looped operations  
such as digital filter multiply-accumulates, and FFT butterfly  
processing.  
Off-Chip Memory and Peripherals Interface  
The ADSP-21161N’s external port provides the processor’s  
interface to off-chip memory and peripherals. The 62.7-M word  
off-chip address space (254.7-M word if all SDRAM) is included  
in the ADSP-21161N’s unified address space. The separate on-  
chip buses—for PM addresses, PM data, DM addresses, DM  
data, I/O addresses, and I/O data—are multiplexed at the exter-  
nal port to create an external system bus with a single 24-bit  
address bus and a single 32-bit data bus. Every access to external  
memory is based on an address that fetches a 32-bit word.  
When fetching an instruction from external memory, two 32-bit  
data locations are being accessed for packed instructions.  
Unused link port lines can also be used as additional data lines  
DATA15–DATA0, allowing single-cycle execution of instruc-  
tions from external memory, at up to 110 MHz. Figure 4 shows  
the alignment of various accesses to external memory.  
Data Address Generators With Hardware Circular Buffers  
The ADSP-21161N’s two data address generators (DAGs) are  
used for indirect addressing and implementing circular data  
buffers in hardware. Circular buffers allow efficient program-  
ming of delay lines and other data structures required in digital  
signal processing, and are commonly used in digital filters and  
Fourier transforms. The two DAGs of the ADSP-21161N con-  
tain sufficient registers to allow the creation of up to 32 circular  
buffers (16 primary register sets, 16 secondary). The DAGs  
automatically handle address pointer wrap-around, reduce  
overhead, increase performance, and simplify implementation.  
Circular buffers can start and end at any memory location.  
The external port supports asynchronous, synchronous, and  
synchronous burst accesses. Synchronous burst SRAM can be  
interfaced gluelessly. The ADSP-21161N also can interface glue-  
lessly to SDRAM. Addressing of external memory devices is  
facilitated by on-chip decoding of high-order address lines to  
generate memory bank select signals. The ADSP-21161N pro-  
vides programmable memory wait states and external memory  
acknowledge controls to allow interfacing to memory and  
peripherals with variable access, hold, and disable time  
requirements.  
Flexible Instruction Set  
The 48-bit instruction word accommodates a variety of parallel  
operations, for concise programming. For example, the  
ADSP-21161N can conditionally execute a multiply, an add,  
and a subtract in both processing elements, while branching, all  
in a single instruction.  
ADSP-21161N MEMORY AND I/O INTERFACE  
FEATURES  
SDRAM Interface  
The ADSP-21161N adds the following architectural features to  
the ADSP-2116x family core.  
The SDRAM interface enables the ADSP-21161N to transfer  
data to and from synchronous DRAM (SDRAM) at the core  
clock frequency or at one-half the core clock frequency. The  
synchronous approach, coupled with the core clock frequency,  
supports data transfer at a high throughput—up to 440M  
bytes/s for 32-bit transfers and up to 660M bytes/s for 48-bit  
transfers.  
Dual-Ported On-Chip Memory  
The ADSP-21161N contains one megabit of on-chip SRAM,  
organized as two blocks of 0.5M bits (Figure 3). Each block can  
be configured for different combinations of code and data stor-  
age. Each memory block is dual-ported for single-cycle,  
The SDRAM interface provides a glueless interface with stan-  
dard SDRAMs—16Mb, 64Mb, 128Mb, and 256Mb— and  
includes options to support additional buffers between the  
ADSP-21161N and SDRAM. The SDRAM interface is  
extremely flexible and provides capability for connecting  
SDRAMs to any one of the ADSP-21161N’s four external mem-  
ory banks, with up to all four banks mapped to SDRAM.  
independent accesses by the core processor and I/O processor.  
The dual-ported memory in combination with three separate  
on-chip buses allow two data transfers from the core and one  
from the I/O processor, in a single cycle. On the ADSP-21161N,  
the memory can be configured as a maximum of 32K words of  
32-bit data, 64K words of 16-bit data, 21K words of 48-bit  
instructions (or 40-bit data), or combinations of different word  
sizes up to one megabit. All of the memory can be accessed as  
16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point  
storage format is supported that effectively doubles the amount  
of data that may be stored on-chip. Conversion between the  
32-bit floating-point and 16-bit floating-point formats is done  
in a single instruction. While each memory block can store  
combinations of code and data, accesses are most efficient when  
one block stores data using the DM bus for transfers, and the  
other block stores instructions and data using the PM bus for  
transfers. Using the DM bus and PM bus, with one dedicated to  
Systems with several SDRAM devices connected in parallel may  
require buffering to meet overall system timing requirements.  
The ADSP-21161N supports pipelining of the address and con-  
trol signals to enable such buffering between itself and multiple  
SDRAM devices.  
Target Board JTAG Emulator Connector  
Analog Devices DSP Tools product line of JTAG emulators uses  
the IEEE 1149.1 JTAG test access port of the ADSP-21161N  
processor to monitor and control the target board processor  
during emulation. Analog Devices DSP Tools product line of  
Rev. C  
|
Page 5 of 60  
|
January 2013  
ADSP-21161N  
ADDRESS  
ADDRESS  
0x0020 0000  
0x0000 0000 0x0001 FFFF  
IOP REGISTERS  
0x0002 0000 0x0002 1FFF (BLK 0)  
0x0002 8000 0x0002 9FFF (BLK 1)  
LONG WORD ADDRESSING  
INTERNAL  
MEMORY  
SPACE  
MS0  
0x0004 0000 0x0004 3FFF (BLK 0)  
0x0005 0000 0x0005 3FFF (BLK 1)  
BANK 0  
NORMAL WORD ADDRESSING  
0x00FF FFFF (NON-SDRAM)  
0x03FF FFFF (SDRAM)  
0x0008 0000 0X0008 7FFF (BLK 0)  
0x000A 0000 0x000A 7FFF (BLK 1)  
SHORT WORD ADDRESSING  
0x0400 0000  
IOP REGISTERS OF ADSP-21161N  
0x0010 0000  
0x0012 0000  
0x0014 0000  
0x0011 FFFF  
0x0013 FFFF  
0x0015 FFFF  
WITH ID = 001  
IOP REGISTERS OF ADSP-21161N  
MS1  
WITH ID = 010  
BANK 1  
IOP REGISTERS OF ADSP-21161N  
0x04FF FFFF (NON-SDRAM)  
0x07FF FFFF (SDRAM)  
WITH ID = 011  
MULTIPROCESSOR  
MEMORY  
IOP REGISTERS OF ADSP-21161N  
0x0016 0000  
0x0017 FFFF  
0x0019 FFFF  
WITH ID = 100  
0x0800 0000  
SPACE  
IOP REGISTERS OF ADSP-21161N  
0x0018 0000  
WITH ID = 101  
MS2  
BANK 2  
IOP REGISTERS OF ADSP-21161N  
0x001A 0000  
0x001C 0000  
0x001B FFFF  
0x08FF FFFF (NON-SDRAM)  
0x0BFF FFFF (SDRAM)  
WITH ID = 110  
RESERVED  
0x0C00 0000  
0x001F FFFF  
MS3  
BANK  
3
EXTERNAL MEMORY SPACE  
0x0CFF FFFF (NON-SDRAM)  
0x0FFF FFFF (SDRAM)  
NOTE: BANK SIZES ARE FIXED  
Figure 3. Memory Map  
JTAG emulators provides emulation at full processor speed,  
allowing inspection and modification of memory, registers, and  
processor stacks. The processor’s JTAG interface ensures that  
the emulator will not affect target system loading or timing.  
core is simultaneously executing its program instructions. DMA  
transfers can occur between the ADSP-21161N’s internal mem-  
ory and external memory, external peripherals, or a host  
processor. DMA transfers can also occur between the ADSP-  
21161N’s internal memory and its serial ports, link ports, or the  
SPI-compatible (Serial Peripheral Interface) port. External bus  
packing and unpacking of 32-, 48-, or 64-bit words in internal  
memory is performed during DMA transfers from either 8-,  
16-, or 32-bit wide external memory. Fourteen channels of  
DMA are available on the ADSP-21161N—two are shared  
between the SPI interface and the link ports, eight via the serial  
ports, and four via the processor’s external port (for host pro-  
cessor, other ADSP-21161Ns, memory, or I/O transfers).  
Programs can be downloaded to the ADSP-21161N using DMA  
transfers. Asynchronous off-chip peripherals can control two  
DMA channels using DMA Request/Grant lines (DMAR2–1,  
DMAG2–1). Other DMA features include interrupt generation  
upon completion of DMA transfers, and DMA chaining for  
automatic linked DMA transfers.  
For complete information on SHARC Analog Devices DSP  
Tools product line of JTAG emulator operation, see the appro-  
priate Emulator Hardware User’s Guide. For detailed infor-  
mation on the interfacing of Analog Devices JTAG emulators  
with Analog Devices DSP products with JTAG emulation ports,  
please refer to Engineer to Engineer Note EE-68: Analog Devices  
JTAG Emulation Technical Reference. Both of these documents  
can be found on the Analog Devices website.  
DMA Controller  
The ADSP-21161N’s on-chip DMA controller enables zero-  
overhead data transfers without processor intervention. The  
DMA controller operates independently and invisibly to the  
processor core, allowing DMA operations to occur while the  
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ADSP-21161N  
its own double-buffered input and output registers.  
Clock/acknowledge handshaking controls link port transfers.  
Transfers are programmable as either transmit or receive.  
DATA47–16  
DATA15–0  
47  
40 39  
32 31  
24 23  
16 15  
L1DATA7–0  
DATA15-8  
8
7
0
L0DATA7–0  
DATA70  
PROM  
BO O T  
Serial Ports  
The ADSP-21161N features four synchronous serial ports that  
provide an inexpensive interface to a wide variety of digital and  
mixed-signal peripheral devices. Each serial port is made up of  
two data lines, a clock and frame sync. The data lines can be  
programmed to either transmit or receive.  
8-BIT PACKED DMA DATA  
8-BIT PACKED INSTRUCTION  
EXECUTION  
16-BIT PACKED DMA DATA  
16-BIT PACKED INSTRUC-  
TION EXECUTION  
FLOAT OR FIXED, D31D0,  
32-BIT PACKED  
32-BIT PACKED INSTRUC-  
TION  
The serial ports operate at up to half the clock rate of the core,  
providing each with a maximum data rate of 55M bit/s. The  
serial data pins are programmable as either a transmitter or  
receiver, providing greater flexibility for serial communications.  
Serial port data can be automatically transferred to and from  
on-chip memory via a dedicated DMA. Each of the serial ports  
features a Time Division Multiplex (TDM) multichannel mode,  
where two serial ports are TDM transmitters and two serial  
ports are TDM receivers (SPORT0 Rx paired with SPORT2 Tx,  
SPORT1 Rx paired with SPORT3 Tx). Each of the serial ports  
also support the I2S protocol (an industry standard interface  
commonly used by audio codecs, ADCs and DACs), with two  
data pins, allowing four I2S channels (using two I2S stereo  
devices) per serial port, with a maximum of up to 16 I2S chan-  
nels. The serial ports permit little-endian or big-endian  
transmission formats and word lengths selectable from 3 bits to  
32 bits. For I2S mode, data-word lengths are selectable between  
8 bits and 32 bits. Serial ports offer selectable synchronization  
and transmit modes as well as optional μ-law or A-law com-  
panding. Serial port clocks and frame syncs can be internally or  
externally generated.  
48-BIT INSTRUCTION FETCH  
(NO PACKING)  
NOTE:  
EXTRA DA TA LINES DATA15–0 ARE ONLY ACCESSIBLE IF LINK PORTS  
ARE DISABLED. ENABLE THESE ADDITIONAL DATA LINKS BY SELECT-  
ING IPACK1–0 = 01 IN SYSCON.  
Figure 4. External Data Alignment Options  
Multiprocessing  
The ADSP-21161N offers powerful features tailored to  
multiprocessing DSP systems. The external port and link ports  
provide integrated glueless multiprocessing support.  
The external port supports a unified address space (see Figure 3)  
that enables direct interprocessor accesses of each ADSP-  
21161N’s internal memory-mapped (I/O processor) registers.  
All other internal memory can be indirectly accessed via DMA  
transfers initiated via the programming of the IOP DMA  
parameter and control registers. Distributed bus arbitration  
logic is included on-chip for simple, glueless connection of sys-  
tems containing up to six ADSP-21161Ns and a host processor  
(Figure 5). Master processor change over incurs only one cycle  
of overhead. Bus arbitration is selectable as either fixed or rotat-  
ing priority. Bus lock enables indivisible read-modify-write  
sequences for semaphores. A vector interrupt is provided for  
interprocessor commands. Using an instruction rate of  
110 MHz, maximum throughput for interprocessor data trans-  
fer is 440M bytes/s over the external port.  
Serial Peripheral (Compatible) Interface  
Serial Peripheral Interface (SPI) is an industry standard syn-  
chronous serial link, enabling the ADSP-21161N SPI-  
compatible port to communicate with other SPI-compatible  
devices. SPI is a 4-wire interface consisting of two data pins, one  
device select pin, and one clock pin. It is a full-duplex synchro-  
nous serial interface, supporting both master and slave modes.  
The SPI port can operate in a multimaster environment by  
interfacing with up to four other SPI-compatible devices, either  
acting as a master or slave device. The ADSP-21161N SPI-com-  
patible peripheral implementation also features programmable  
baud rate and clock phase/polarities. The ADSP-21161N SPI-  
compatible port uses open drain drivers to support a multimas-  
ter configuration and to avoid data contention.  
Two link ports provide a second method of multiprocessing  
communications. Each link port can support communications  
to another ADSP-21161N. The ADSP-21161N, running at  
110 MHz, has a maximum throughput for interprocessor com-  
munications over the links of 220M bytes/s. The link ports and  
cluster multiprocessing can be used concurrently or  
independently.  
Host Processor Interface  
Link Ports  
The ADSP-21161N host interface enables easy connection to  
standard 8-bit, 16-bit, or 32-bit microprocessor buses with little  
additional hardware required. The host interface is accessed  
through the ADSP-21161N’s external port. Four channels of  
DMA are available for the host interface; code and data transfers  
are accomplished with low software overhead. The host proces-  
sor requests the ADSP-21161N’s external bus with the host bus  
request (HBR), host bus grant (HBG), and chip select (CS) sig-  
nals. The host can directly read and write the internal IOP  
registers of the ADSP-21161N, and can access the DMA channel  
The ADSP-21161N features two 8-bit link ports that provide  
additional I/O capabilities. With the capability of running at  
110 MHz, each link port can support 110M bytes/s. Link port  
I/O is especially useful for point-to-point interprocessor com-  
munication in multiprocessing systems. The link ports can  
operate independently and simultaneously, with a maximum  
data throughput of 220M bytes/s. Link port data is packed into  
48- or 32-bit words and can be directly read by the core proces-  
sor or DMA-transferred to on-chip memory. Each link port has  
Rev. C  
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ADSP-21161N  
CLOCK  
RESET  
ADSP-21161N #4  
ADSP-21161N #3  
ADDR23-0  
CLKIN  
DATA47-16  
RESET  
3
ID2-0  
CONTROL  
ADSP-21161N #2  
CLKIN  
ADDR23-0  
DATA47-16  
RESET  
2
ID2-0  
CONTROL  
ADDR  
DATA  
BOOT  
EPROM  
(OPTIONAL)  
ADSP-21161N #1  
CS  
BMS  
ADDR23-0  
ADDR  
DATA  
CLKIN  
GLOBAL  
MEMORY  
AND  
DATA47-16  
RD  
RESET  
OE  
PERIPHERALS  
(OPTIONAL)  
1
ID2-0  
WR  
ACK  
WE  
ACK  
CS  
MS3-0  
SBTS  
CS  
HOST  
HBR  
HBG  
REDY  
PROCESSOR  
INTERFACE  
(OPTIONAL)  
ADDR  
DATA  
BR6-2  
BR1  
RAS  
CAS  
RAS  
CAS  
DQM  
SDWE  
DQM  
WE  
SDCLK1-0  
CLK  
SDCKE  
CKE  
SDRAM  
(OPTIONAL)  
SDA10  
A10  
CS  
ADDR  
DATA  
Figure 5. Shared Memory Multiprocessing System  
setup and message registers. DMA setup via a host would allow  
it to access any internal memory address via DMA transfers.  
Vector interrupt support provides efficient execution of host  
commands.  
The host processor interface can be used in either multiproces-  
sor or single processor SHARC systems. For multiprocessor  
systems, host access to the SHARC requires address pins  
ADDR17, ADDR18, ADDR19, and ADDR20 to be driven low.  
It is not enough to tie these pins to ground through a resistor  
Rev. C  
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ADSP-21161N  
(for example 10k ohm). These pins must be driven low with a  
strong enough drive strength (10–50 ohms) to overcome the  
SHARC keeper latches present on these pins. If the drive  
strength provided is not strong enough, data access failures can  
occur.  
10  
0.1F  
AVDD  
VDDINT  
0.01F  
AGND  
For single processor SHARC systems using this host access fea-  
ture, address pins ADDR17, ADDR18, ADDR19, and ADDR20  
may be tied low (for example through a 10k ohm resistor),  
driven low by a buffer/driver, or left floating. Any of these  
options is sufficient.  
Figure 6. Analog Power (AVDD) Filter Circuit  
DEVELOPMENT TOOLS  
Analog Devices supports its processors with a complete line of  
software and hardware development tools, including integrated  
development environments (which include CrossCore® Embed-  
ded Studio and/or VisualDSP++®), evaluation products,  
emulators, and a wide variety of software add-ins.  
General-Purpose I/O Ports  
The ADSP-21161N also contains 12 programmable, general  
purpose I/O pins that can function as either input or output. As  
output, these pins can signal peripheral devices; as input, these  
pins can provide the test for conditional branching.  
Integrated Development Environments (IDEs)  
For C/C++ software writing and editing, code generation, and  
debug support, Analog Devices offers two IDEs.  
Program Booting  
The newest IDE, CrossCore Embedded Studio, is based on the  
The internal memory of the ADSP-21161N can be booted at  
system power-up from either an 8-bit EPROM, a host processor,  
the SPI interface, or through one of the link ports. Selection of  
the boot source is controlled by the Boot Memory Select (BMS),  
EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins.  
8-, 16-, or 32-bit host processors can also be used for booting.  
TM  
Eclipse framework. Supporting most Analog Devices proces-  
sor families, it is the IDE of choice for future processors,  
including multicore devices. CrossCore Embedded Studio  
seamlessly integrates available software add-ins to support real  
time operating systems, file systems, TCP/IP stacks, USB stacks,  
algorithmic software modules, and evaluation hardware board  
support packages. For more information visit  
Phase-Locked Loop and Crystal Double Enable  
www.analog.com/cces.  
The ADSP-21161N uses an on-chip phase-locked loop (PLL) to  
generate the internal clock for the core. The CLK_CFG1–0 pins  
are used to select ratios of 2:1, 3:1, and 4:1. In addition to the  
PLL ratios, the CLKDBL pin can be used for more clock ratio  
options. The (1/2CLKIN) rate set by the CLKDBL  
pin determines the rate of the PLL input clock and the rate at  
which the external port operates. With the combination of  
CLK_CFG1–0 and CLKDBL, ratios of 2:1, 3:1, 4:1, 6:1, and 8:1  
between the core and CLKIN are supported. See also Figure 8  
on Page 20.  
The other Analog Devices IDE, VisualDSP++, supports proces-  
sor families introduced prior to the release of CrossCore  
Embedded Studio. This IDE includes the Analog Devices VDK  
real time operating system and an open source TCP/IP stack.  
For more information visit www.analog.com/visualdsp. Note  
that VisualDSP++ will not support future Analog Devices  
processors.  
EZ-KIT Lite Evaluation Board  
For processor evaluation, Analog Devices provides wide range  
of EZ-KIT Lite® evaluation boards. Including the processor and  
key peripherals, the evaluation board also supports on-chip  
emulation capabilities and other evaluation and development  
features. Also available are various EZ-Extenders®, which are  
daughter cards delivering additional specialized functionality,  
including audio and video processing. For more information  
visit www.analog.com and search on “ezkit” or “ezextender”.  
Power Supplies  
The ADSP-21161N has separate power supply connections for  
the analog (AVDD/AGND), internal (VDDINT), and external  
(VDDEXT) power supplies. The internal and analog supplies must  
meet the 1.8 V requirement. The external supply must meet the  
3.3 V requirement. All external supply pins must be connected  
to the same supply.  
Note that the analog supply (AVDD) powers the ADSP-21161N’s  
clock generator PLL. To produce a stable clock, provide an  
external circuit to filter the power input to the AVDD pin. Place  
the filter as close as possible to the pin. The AVDD filter circuit  
shown in Figure 6 must be added for each ADSP-21161N in the  
multiprocessor system. To prevent noise coupling, use a wide  
trace for the analog ground (AGND) signal and install a decou-  
pling capacitor as close as possible to the pin.  
EZ-KIT Lite Evaluation Kits  
For a cost-effective way to learn more about developing with  
Analog Devices processors, Analog Devices offer a range of EZ-  
KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT  
Lite evaluation board, directions for downloading an evaluation  
version of the available IDE(s), a USB cable, and a power supply.  
The USB controller on the EZ-KIT Lite board connects to the  
USB port of the user’s PC, enabling the chosen IDE evaluation  
suite to emulate the on-board processor in-circuit. This permits  
the customer to download, execute, and debug programs for the  
EZ-KIT Lite system. It also supports in-circuit programming of  
the on-board Flash device to store user-specific boot code,  
enabling standalone operation. With the full version of Cross-  
Rev. C  
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ADSP-21161N  
Core Embedded Studio or VisualDSP++ installed (sold  
separately), engineers can develop software for supported EZ-  
KITs or any custom system utilizing supported Analog Devices  
processors.  
For details on target board design issues including mechanical  
layout, single processor connections, signal buffering, signal ter-  
mination, and emulator pod logic, see the EE-68: Analog Devices  
JTAG Emulation Technical Reference on the Analog Devices  
website (www.analog.com)—use site search on “EE-68.” This  
document is updated regularly to keep pace with improvements  
to emulator support.  
Software Add-Ins for CrossCore Embedded Studio  
Analog Devices offers software add-ins which seamlessly inte-  
grate with CrossCore Embedded Studio to extend its capabilities  
and reduce development time. Add-ins include board support  
packages for evaluation hardware, various middleware pack-  
ages, and algorithmic modules. Documentation, help,  
configuration dialogs, and coding examples present in these  
add-ins are viewable through the CrossCore Embedded Studio  
IDE once the add-in is installed.  
ADDITIONAL INFORMATION  
This data sheet provides a general overview of the  
ADSP-21161N architecture and functionality. For detailed  
information on the ADSP-2116x Family core architecture and  
instruction set, refer to the ADSP-21161 SHARC DSP Hardware  
Reference and the ADSP-21160 SHARC DSP Instruction Set  
Reference.  
Board Support Packages for Evaluation Hardware  
RELATED SIGNAL CHAINS  
Software support for the EZ-KIT Lite evaluation boards and EZ-  
Extender daughter cards is provided by software add-ins called  
Board Support Packages (BSPs). The BSPs contain the required  
drivers, pertinent release notes, and select example code for the  
given evaluation hardware. A download link for a specific BSP is  
located on the web page for the associated EZ-KIT or EZ-  
Extender product. The link is found in the Product Download  
area of the product web page.  
A signal chain is a series of signal-conditioning electronic com-  
ponents that receive input (data acquired from sampling either  
real-time phenomena or from stored data) in tandem, with the  
output of one portion of the chain supplying input to the next.  
Signal chains are often used in signal processing applications to  
gather and process data or to apply system controls based on  
analysis of real-time phenomena. For more information about  
this term and related topics, see the “signal chain” entry in  
Wikipedia or the Glossary of EE Terms on the Analog Devices  
website.  
Middleware Packages  
Analog Devices separately offers middleware add-ins such as  
real time operating systems, file systems, USB stacks, and  
TCP/IP stacks. For more information see the following web  
pages:  
Analog Devices eases signal processing system development by  
providing signal processing components that are designed to  
work together well. A tool for viewing relationships between  
specific applications and related components is available on the  
www.analog.com website.  
www.analog.com/ucos3  
www.analog.com/ucfs  
www.analog.com/ucusbd  
www.analog.com/lwip  
The Application Signal Chains page in the Circuits from the  
TM  
Lab site (http://www.analog.com/signal chains) provides:  
• Graphical circuit block diagram presentation of signal  
chains for a variety of circuit types and applications  
Algorithmic Modules  
To speed development, Analog Devices offers add-ins that per-  
form popular audio and video processing algorithms. These are  
available for use with both CrossCore Embedded Studio and  
VisualDSP++. For more information visit www.analog.com and  
search on “Blackfin software modules” or “SHARC software  
modules”.  
• Drill down links for components in each chain to selection  
guides and application information  
• Reference designs applying best practice design techniques  
Designing an Emulator-Compatible DSP Board (Target)  
For embedded system test and debug, Analog Devices provides  
a family of emulators. On each JTAG DSP, Analog Devices sup-  
plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit  
emulation is facilitated by use of this JTAG interface. The emu-  
lator accesses the processor’s internal features via the  
processor’s TAP, allowing the developer to load code, set break-  
points, and view variables, memory, and registers. The  
processor must be halted to send data and commands, but once  
an operation is completed by the emulator, the DSP system is set  
to run at full speed with no impact on system timing. The emu-  
lators require the target board to include a header that supports  
connection of the DSP’s JTAG port to the emulator.  
Rev. C  
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ADSP-21161N  
PIN FUNCTION DESCRIPTIONS  
ADSP-21161N pin definitions are listed below. Inputs identified  
as synchronous (S) must meet timing requirements with respect  
to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-  
tified as asynchronous (A) can be asserted asynchronously to  
CLKIN (or to TCK for TRST). Tie or pull unused inputs to  
The following symbols appear in the Type column of Table 2:  
A = Asynchronous, G = Ground, I = Input, O = Output,  
P = Power Supply, S = Synchronous, (A/D) = Active Drive,  
(O/D) = Open Drain, and T = Three-State (when SBTS is  
asserted or when the ADSP-21161N is a bus slave).  
VDDEXT or GND, except for the following:  
Unlike previous SHARC processors, the ADSP-21161N con-  
tains internal series resistance equivalent to 50 on all  
input/output drivers except the CLKIN and XTAL pins.  
Therefore, for traces longer than six inches, external series resis-  
tors on control, data, clock, or frame sync pins are not required  
to dampen reflections from transmission line effects for point-  
to-point connections. However, for more complex networks  
such as a star configuration, series termination is still  
recommended.  
• ADDR23–0, DATA47–0, BRST, CLKOUT (Note: These  
pins have a logic-level hold circuit enabled on the  
ADSP-21161N DSP with ID2–0 = 00x.)  
• PA, ACK, RD, WR, DMARx, DMAGx, (ID2–0 = 00x)  
(Note: These pins have a pull-up enabled on the  
ADSP-21161N DSP with ID2–0 = 00x.)  
• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note: See  
Link Port Buffer Control Register Bit definitions in the  
ADSP-21161N SHARC DSP Hardware Reference.)  
• DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU,  
TMS,TRST, TDI (Note: These pins have a pull-up.)  
Table 2. Pin Function Descriptions  
Pin  
Type  
Function  
ADDR23–0  
I/O/T  
External Bus Address. The ADSP-21161N outputs addresses for external memory and peripherals on these  
pins. In a multiprocessor system the bus master outputs addresses for read/writes of the IOP registers of other  
ADSP-21161Ns while all other internal memory resources can be accessed indirectly via DMA control (that  
is, accessing IOP DMA parameter registers). The ADSP-21161N inputs addresses when a host processor or  
multiprocessing bus master is reading or writing its IOP registers. A keeper latch on the DSP’s ADDR23-0 pins  
maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N with  
ID2–0=00x.  
DATA47–16  
I/O/T  
External Bus Data. The ADSP-21161N inputs and outputs data and instructions on these pins. Pull-up  
resistors on unused data pins are not necessary. A keeper latch on the DSP’s DATA47–16 pins maintains the  
input at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2–0=00x.  
Note: DATA15–8 pins (multiplexed with L1DAT7–0) can also be used to extend the data bus if the link ports are  
disabled and will not be used. In addition, DATA7–0 pins (multiplexed with L0DAT7–0) can also be used to extend  
the data bus if the link ports are not used. This enables execution of 48-bit instructions from external SBSRAM  
(system clock speed-external port), SRAM (system clock speed-external port) and SDRAM (core clock or one-half  
the core clock speed). The IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1–0=0x1)  
to enable this full instruction Width/No-packing Mode of operation.  
MS3–0  
I/O/T  
Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of  
external memory. Memory bank sizes are fixed to 16 M words for non-SDRAM and 64M words for SDRAM.  
The MS3–0 outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs  
transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert with the  
other address lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted. In a  
multiprocessor system, the MSx signals are tracked by slave SHARCs.  
RD  
I/O/T  
I/O/T  
Memory Read Strobe. RD is asserted whenever ADSP-21161N reads a word from external memory or from  
the IOP registers of other ADSP-21161Ns. External devices, including other ADSP-21161Ns, must assert RD  
for reading from a word of the ADSP-21161N IOP register memory. In a multiprocessing system, RD is driven  
by the bus master. RD has a 20 kinternal pull-up resistor that is enabled for DSPs with ID2–0=00x.  
Memory Write Low Strobe. WR is asserted when ADSP-21161N writes a word to external memory or IOP  
registers of other ADSP-21161Ns. External devices must assert WR for writing to ADSP-21161N IOP registers.  
In a multiprocessing system, the bus master drives WR. WRhas a 20 kinternal pull-up resistor that is enabled  
for DSPs with ID2–0=00x.  
WR  
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ADSP-21161N  
Table 2. Pin Function Descriptions (Continued)  
Pin  
Type  
Function  
BRST  
I/O/T  
SequentialBurstAccess. BRSTisassertedbyADSP-21161Ntoindicatethatdataassociatedwithconsecutive  
addresses is being read or written. A slave device samples the initial address and increments an internal  
address counter after each transfer. The incremented address is not pipelined on the bus. A master ADSP-  
21161N in a multiprocessor environment can read slave external port buffers (EPBx) using the burst protocol.  
BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that, except for  
the last data request cycle (denoted by RD or WR asserted and BRST negated). A keeper latch on the DSP’s  
BRST pin maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N  
with ID2–0=00x.  
ACK  
I/O/S  
I/S  
Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to an external memory  
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an  
external memory access. The ADSP-21161N deasserts ACK as an output to add wait states to a synchronous  
access of its IOP registers. ACK has a 20 kinternal pull-up resistor that is enabled during reset or on DSPs  
with ID2–0=00x.  
SBTS  
Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus address,  
data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21161N attempts to  
access external memory while SBTS is asserted, the processor will halt and the memory access will not be  
completed until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21161N  
deadlock.  
CAS  
I/O/T  
I/O/T  
I/O/T  
O/T  
SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10,  
defines the operation for the SDRAM to perform.  
RAS  
SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines  
the operation for the SDRAM to perform.  
SDWE  
DQM  
SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes SDA10, defines the  
operation for the SDRAM to perform.  
SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a precharge command  
and during SDRAM power-up initialization.  
SDCLK0  
SDCLK1  
I/O/S/T  
O/S/T  
SDRAM Clock Output 0. Clock for SDRAM devices.  
SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices,  
handles the increased clock load requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or  
both SDCLKx pins can be three-stated.  
SDCKE  
SDA10  
IRQ2–0  
FLAG11–0  
TIMEXP  
HBR  
I/O/T  
O/T  
I/A  
SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet supplied with the  
SDRAM device.  
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-SDRAM accesses or host  
accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.  
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edge-triggered  
or level-sensitive.  
I/O/A  
O
Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested as a  
condition. As an output, it can be used to signal external peripherals.  
Timer Expired. Asserted for four core clock cycles when the timer is enabled and TCOUNT decrements to  
zero.  
I/A  
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21161N’s external  
bus. When HBR is asserted in a multiprocessing system, the ADSP-21161N that is bus master will relinquish  
the bus and assert HBG. To relinquish the bus, the ADSP-21161N places the address, data, select, and strobe  
lines in a high impedance state. HBR has priority over all ADSP-21161N bus requests (BR6–1) in a multipro-  
cessing system.  
HBG  
CS  
I/O  
I/A  
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of  
the external bus. HBG is asserted (held low) by the ADSP-21161N until HBR is released. In a multiprocessing  
system, HBG is output by the ADSP-21161N bus master and is monitored by all others.  
After HBR is asserted, and before HBG is given, HBG will float for 1 tCK (1 CLKIN cycle). To avoid erroneous  
grants, HBG should be pulled up with a 20 kto 50 kexternal resistor.  
Chip Select. Asserted by host processor to select the ADSP-21161N.  
Rev. C  
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Page 12 of 60  
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January 2013  
ADSP-21161N  
Table 2. Pin Function Descriptions (Continued)  
Pin  
Type  
Function  
REDY  
O (O/D)  
Host Bus Acknowledge. The ADSP-21161N deasserts REDY (low) to add wait states to a host access of its  
IOP registers when CS and HBR inputs are asserted.  
DMAR1  
DMAR2  
DMAG1  
I/A  
I/A  
O/T  
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services. DMAR1 has  
a 20 kinternal pull-up resistor that is enabled for DSPs with ID2–0=00x.  
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has  
a 20 kinternal pull-up resistor that is enabled for DSPs with ID2–0=00x.  
DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21161N to indicate that the requested DMA starts on the  
next cycle. Driven by bus master only. DMAG1 has a 20 kinternal pull-up resistor that is enabled for DSPs  
with ID2–0=00x.  
DMAG2  
BR6–1  
O/T  
DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21161N to indicate that the requested DMA starts on the  
next cycle. Driven by bus master only. DMAG2 has a 20 kinternal pull-up resistor that is enabled for DSPs  
with ID2–0=00x.  
I/O/S  
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21161Ns to arbitrate for bus mastership. An  
ADSP-21161N only drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all  
others. In a multiprocessor system with less than six ADSP-21161Ns, the unused BRx pins should be pulled  
high; the processor's own BRx line must not be pulled high or low because it is an output.  
BMSTR  
ID2–0  
O
I
Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21161N is current bus master  
of the shared external bus. The ADSP-21161N drives BMSTR high only while it is the bus master. In a single-  
processor system (ID=000), the processor drives this pin high. This pin is used for debugging purposes.  
Multiprocessing ID. Determines which multiprocessing bus request (BR6–BR1) is used by ADSP-21161N.  
ID=001 corresponds to BR1, ID=010 corresponds to BR2, and so on. Use ID=000 or ID=001 in single-  
processorsystems. Theselinesareasystemconfigurationselectionthatshouldbehardwiredoronlychanged  
at reset.  
RPBA  
PA  
I/S  
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus  
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration  
selection that must be set to the same value on every ADSP-21161N. If the value of RPBA is changed during  
system operation, it must be changed in the same CLKIN cycle on every ADSP-21161N.  
I/O/T  
Priority Access. Asserting its PA pin enables an ADSP-21161N bus slave to interrupt background DMA  
transfers and gain access to the external bus. PA is connected to all ADSP-21161Ns in the system. If access  
priority is not required in a system, the PA pin should be left unconnected. PA has a 20 kinternal pull-up  
resistor that is enabled for DSPs with ID2–0=00x.  
DxA  
DxB  
I/O  
I/O  
Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has an internal pull-up resistor.  
Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to  
receive serial data.  
Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has an internal pull-up resistor.  
Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to  
receive serial data.  
SCLKx  
FSx  
I/O  
I/O  
Transmit/Receive Serial Clock (Serial Ports 0, 1, 2, 3). Each SCLK pin has an internal pull-up resistor. This  
signal can be either internally or externally generated.  
Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates shifting of serial data.  
This signal is either generated internally or externally. It can be active high or low or an early or a late frame  
sync, in reference to the shifting of serial data.  
SPICLK  
I/O  
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is  
transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit trans-  
mitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word.  
Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift  
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge  
of the clock and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data  
are programmable into the SPICTL control register and define the transfer format. SPICLK has a 50 kinternal  
pull-up resistor.  
Rev. C  
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Page 13 of 60  
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January 2013  
ADSP-21161N  
Table 2. Pin Function Descriptions (Continued)  
Pin  
Type  
Function  
SPIDS  
I
SerialPeripheral InterfaceSlaveDeviceSelect. Anactivelowsignalusedto enableslavedevices. Thisinput  
signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster  
mode SPIDS signal can be asserted to a master device to signal that an error has occurred, as some other  
deviceisalsotrying to bethe masterdevice. If assertedlow when thedeviceisin mastermode, it isconsidered  
a multimaster error. For a single-master, multiple-slave configuration where FLAG3–0 are used, this pin must  
be tied or pulled high to VDDEXT on the master device. For ADSP-21161N to ADSP-21161N SPI interaction, any  
of the master ADSP-21161N’s FLAG3–0 pins can be used to drive the SPIDS signal on the ADSP-21161N SPI  
slave device.  
MOSI  
MISO  
I/O (o/d)  
I/O (o/d)  
SPI Master Out Slave. If the ADSP-21161N is configured as a master, the MOSI pin becomes a data transmit  
(output) pin, transmitting output data. If the ADSP-21161N is configured as a slave, the MOSI pin becomes a  
data receive (input) pin, receiving input data. In an ADSP-21161N SPI interconnection, the data is shifted out  
from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has an internal  
pull-up resistor.  
SPI Master In Slave Out. If the ADSP-21161N is configured as a master, the MISO pin becomes a data receive  
(input) pin, receiving input data. If the ADSP-21161N is configured as a slave, the MISO pin becomes a data  
transmit (output) pin, transmitting output data. In an ADSP-21161N SPI interconnection, the data is shifted  
out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has an  
internal pull-up resistor. MISO can be configured as o/d by setting the OPD bit in the SPICTL register.  
Note: Only one slave is allowed to transmit data at any given time.  
LxDAT7–0  
I/O  
Link Port Data (Link Ports 0–1).  
[DATA15–0]  
[I/O/T]  
For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when used as a data  
pin; or a 20 kinternal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.  
For silicon revisions 0.3, 1.0, and 1.1 each LxDAT pin has a 50 kinternal pull-down resistor that is enabled  
or disabled by the LxPDRDE bit of the LCTL register.  
Note: L1DAT7–0 are multiplexed with the DATA15–8 pins L0DAT7–0 are multiplexed with the DATA7–0 pins. If link  
ports are disabled and are not used, these pins can be used as additional data lines for executing instructions at  
up to the full clock rate from external memory. See DATA47–16 for more information.  
LxCLK  
LxACK  
EBOOT  
LBOOT  
BMS  
I/O  
Link Port Clock (Link Ports 0–1). Each LxCLK pin has an internal pull-down 50 kresistor that is enabled or  
disabled by the LxPDRDE bit of the LCTL register.  
I/O  
Link Port Acknowledge (Link Ports 0–1). Each LxACK pin has an internal pull-down 50 kresistor that is  
enabled or disabled by the LxPDRDE bit of the LCTL register.  
I
EPROM Boot Select. For a description of how this pin operates, see the table in the BMS pin description. This  
signal is a system configuration selection that should be hardwired.  
I
Link Boot. For a description of how this pin operates, see the table in the BMS pin description. This signal is  
a system configuration selection that should be hardwired.  
I/O/T  
Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins (see Table 4).  
This input is a system configuration selection that should be hardwired. For Host and PROM boot, DMA  
channel 10 (EPB0) is used. For Link boot and SPI boot, DMA channel 8 is used.  
Three-state only in EPROM boot mode (when BMS is an output).  
CLKIN  
I
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21161N clock input. It configures the ADSP-  
21161N to use either its internal clock generator or an external clock source. Connecting the necessary  
components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN  
while leaving XTAL unconnected configures the ADSP-21161N to use the external clock source such as an  
external clock oscillator.The ADSP-21161N external port cycles at the frequency of CLKIN. The instruction  
cycle rate is a multiple of the CLKIN frequency; it is programmable at power-up via the CLK_CFG1–0 pins.  
CLKIN may not be halted, changed, or operated below the specified frequency.  
XTAL  
O
I
Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the ADSP-21161N’s internal clock  
oscillator or to disable it to use an external clock source. See CLKIN.  
CLK_CFG1-0  
Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate is equal to n PLLICLK where  
n is user selectable to 2, 3, or 4, using the CLK_CFG1–0 inputs. These pins can also be used in combination  
with the CLKDBL pin to generate additional core clock rates of 6 CLKIN and 8 CLKIN (see the Clock Rate  
Ratios table in the CLKDBL description).  
Rev. C  
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Page 14 of 60  
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January 2013  
ADSP-21161N  
Table 2. Pin Function Descriptions (Continued)  
Pin  
Type  
Function  
CLKDBL  
I
Crystal Double Mode Enable. This pin is used to enable the 2clock double circuitry, where CLKOUT can  
be configured as either 1or 2the rate of CLKIN. This CLKIN double circuit is primarily intended to be used  
for an external crystal in conjunction with the internal clock generator and the XTAL pin. The internal clock  
generator when used in conjunction with the XTAL pin and an external crystal is designed to support up to  
a maximum of 27.5 MHz external crystal frequency. CLKDBL can be used in XTAL mode to generate a 55 MHz  
input into the PLL. The 2clock mode is enabled (during RESET low) by tying CLKDBL to GND, otherwise it is  
connected to VDDEXT for 1clock mode. For example, this enables the use of a 27.5 MHz crystal to enable 110  
MHz core clock rates and a 55 MHz CLKOUT operation when CLK_CFG0=0, CLK_CFG1=0 and CLKDBL=0.  
This pin can also be used to generate different clock rate ratios for external clock oscillators as well. The  
possible clock rate ratio options (up to 110 MHz) for either CLKIN (external clock oscillator) or XTAL (crystal  
input) are shown in Table 3 on Page 16. An 8:1 ratio enables the use of a 12.5 MHz crystal to generate a 100  
MHzcore(instructionclock)rateanda25MHzCLKOUT(externalport)clockrate. Seealso Figure 8onPage 20.  
Note: When using an external crystal, the maximum crystal frequency cannot exceed 27.5 MHz. For all other  
external clock sources, the maximum CLKIN frequency is 55 MHz.  
CLKOUT  
O/T  
Local Clock Out. CLKOUT is 1or 2and is driven at either 1or 2the frequency of CLKIN frequency by the  
current bus master. The frequency is determined by the CLKDBL pin. This output is three-stated when the  
ADSP-21161N is not the bus master or when the host controls the bus (HBG asserted). A keeper latch on the  
DSP’s CLKOUT pin maintains the output at the level it was last driven. This latch is only enabled on the ADSP-  
21161N with ID2–0=00x.  
If CLKDBL enabled, CLKOUT=2 CLKIN  
If CLKDBL disabled, CLKOUT=1 CLKIN  
Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1 CLKIN or 2 CLKIN.  
Do not use CLKOUT in multiprocessing systems. Use CLKIN instead.  
RESET  
I/A  
O
Processor Reset. Resets the ADSP-21161N to a known state and begins execution at the program memory  
location specified by the hardware reset vector address. The RESET input must be asserted (low) at power-up.  
RSTOUT1  
Reset Out. When RSTOUT is asserted (low), this pin indicates that the core blocks are in reset. It is deasserted  
4080 cycles after RESET is deasserted indicating that the PLL is stable and locked.  
TCK  
TMS  
TDI  
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan.  
I/S  
I/S  
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kinternal pull-up resistor.  
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kinternal pull-up  
resistor.  
TDO  
TRST  
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.  
I/A  
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held  
low for proper operation of the ADSP-21161N. TRST has a 20 kinternal pull-up resistor.  
EMU  
O (O/D)  
Emulation Status. Must be connected to the ADSP-21161N Analog Devices DSP Tools product line of JTAG  
emulators target board connector only. EMU has a 50 kinternal pull-up resistor.  
VDDINT  
VDDEXT  
AVDD  
P
P
P
Core Power Supply. Nominally +1.8 V dc and supplies the DSP’s core processor (14 pins).  
I/O Power Supply. Nominally +3.3 V dc. (13 pins).  
Analog Power Supply. Nominally +1.8 V dc and supplies the DSP’s internal PLL (clock generator). This pin  
has the same specifications as VDDINT, except that added filtering circuitry is required. For more information,  
see Power Supplies on Page 9.  
AGND  
GND  
NC  
G
G
Analog Power Supply Return.  
Power Supply Return. (26 pins).  
Do Not Connect. Reserved pins that must be left open and unconnected. (4 pins)  
1 RSTOUT exists only for silicon revisions 1.2 and greater.  
Rev. C  
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Page 15 of 60  
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January 2013  
 
ADSP-21161N  
Table 3. Clock Rate Ratios  
CLKDBL  
CLK_CFG1  
CLK_CFG0  
Core:CLKIN  
CLKIN:CLKOUT  
1
1
1
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
2:1  
3:1  
4:1  
4:1  
6:1  
8:1  
1:1  
1  
1  
1:2  
1:2  
1:2  
BOOT MODES  
Table 4. Boot Mode Selection  
EBOOT  
LBOOT  
BMS  
Booting Mode  
1
0
0
0
0
1
0
0
1
1
0
1
Output  
1 (Input)  
0 (Input)  
1 (Input)  
0 (Input)  
x (Input)  
EPROM (Connect BMS to EPROM chip select.)  
Host Processor  
Serial Boot via SPI  
Link Port  
No Booting. Processor executes from external memory.  
Reserved  
Rev. C  
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Page 16 of 60  
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January 2013  
ADSP-21161N  
SPECIFICATIONS  
OPERATING CONDITIONS  
100 MHz  
Max  
110 MHz  
Parameter1 Description  
Test Conditions  
Min  
Min  
Max  
Unit  
VDDINT  
AVDD  
VDDEXT  
VIH  
Internal (Core) Supply Voltage  
1.71  
1.71  
3.13  
2.0  
1.89  
1.89  
3.47  
1.71  
1.71  
3.13  
2.0  
1.89  
V
Analog (PLL) Supply Voltage  
External (I/O) Supply Voltage  
High Level Input Voltage2  
Low Level Input Voltage2  
1.89  
V
3.47  
V
@ VDDEXT = Max  
@ VDDEXT = Min  
VDDEXT +0.5  
VDDEXT +0.5  
+0.8  
V
VIL  
–0.5  
–40  
+0.8  
–0.5  
–40  
V
TCASE  
Case Operating Temperature3  
+105  
+125  
C  
1 Specifications subject to change without notice.  
2 Applies to input and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, DMAR1, DMAR2, BR6–1, ID2–0,  
RPBA, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE,  
CLK_CFGx, CLKDBL, CLKIN, RESET, TRST, TCK, TMS, TDI.  
3 See Thermal Characteristics on Page 55 for information on thermal specifications.  
Rev. C  
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Page 17 of 60  
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January 2013  
 
 
ADSP-21161N  
ELECTRICAL CHARACTERISTICS  
Parameter Description  
Test Conditions  
Min  
Max  
Unit  
VOH  
VOL  
IIH  
IIL  
IIHC  
IILC  
IIKH  
IIKL  
IIKH-OD  
IIKL-OD  
IILPU  
IOZH  
IOZL  
IOZLPU1  
IOZLPU2  
IOZHPD1  
IOZHPD2  
IDD-INPEAK  
High Level Output Voltage1  
@ VDDEXT = Min, IOH = –2.0 mA2  
@ VDDEXT = Min, IOL = 4.0 mA2  
@ VDDEXT = Max, VIN = VDDEXT Max  
@ VDDEXT = Max, VIN = 0 V  
@ VDDEXT = Max, VIN = VDDEXT Max  
@ VDDEXT = Max, VIN = 0 V  
@ VDDEXT = Max, VIN = 2.0 V  
@ VDDEXT = Max, VIN = 0.8 V  
@ VDDEXT = Max  
2.4  
V
V
Low Level Output Voltage1  
0.4  
10  
10  
35  
35  
High Level Input Current3, 4  
Low Level Input Current3  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
mA  
CLKIN High Level Input Current5  
CLKIN Low Level Input Current5  
Keeper High Load Current6  
–250  
50  
–300  
300  
–100  
200  
Keeper Low Load Current6  
Keeper High Overdrive Current6, 7, 8  
Keeper Low Overdrive Current6, 7, 8  
Low Level Input Current Pull-Up4  
Three-State Leakage Current9, 10, 11  
Three-State Leakage Current9, 12, 13  
Three-State Leakage Current Pull-Up110  
Three-State Leakage Current Pull-Up211  
Three-State Leakage Current Pull-Down112  
Three-State Leakage Current Pull-Down213  
Supply Current (Internal)14, 15  
@ VDDEXT = Max  
@ VDDEXT = Max, VIN = 0 V  
@ VDDEXT = Max, VIN = VDDEXT Max  
@ VDDEXT = Max, VIN = 0 V  
@ VDDEXT = Max, VIN = 0 V  
@ VDDEXT = Max, VIN = 0 V  
@ VDDEXT = Max, VIN = VDDEXT Max  
@ VDDEXT = Max, VIN = VDDEXT Max  
tCCLK = 9.0 ns, VDDINT = Max  
350  
10  
10  
500  
350  
350  
500  
965  
900  
t
CCLK = 10.0 ns, VDDINT = Max  
tCCLK = 9.0 ns, VDDINT = Max  
CCLK = 10.0 ns, VDDINT = Max  
tCCLK = 9.0 ns, VDDINT = Max  
CCLK = 10.0 ns, VDDINT = Max  
tCCLK = 9.0 ns, VDDINT = Max  
CCLK = 10.0 ns, VDDINT = Max  
IDD-INHIGH  
IDD-INLOW  
IDD-IDLE  
Supply Current (Internal)15, 16  
Supply Current (Internal)15, 17  
Supply Current (Idle)15, 18  
700  
650  
mA  
mA  
mA  
t
535  
500  
t
425  
400  
t
AIDD  
CIN  
Supply Current (Analog)19  
Input Capacitance20, 21  
@ AVDD = Max  
fIN = 1 MHz, TCASE = 25°C, VIN = 1.8 V  
10  
4.7  
mA  
pF  
1
Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,  
BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL,  
TDO, CLKOUT, TIMEXP, RSTOUT.  
2 See Output Drive Currents on Page 54 for typical drive current capabilities.  
3 Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE,  
SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN.  
4 Applies to input pins with 20 kinternal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.  
5 Applies to CLKIN only.  
6 Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.  
7 Current required to switch from kept high to low or from kept low to high.  
8 Characterized, but not tested.  
9 Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10,  
BRST.  
10Applies to three-statable pins with 20 kpull-ups: RD, WR, DMAG1, DMAG2, PA.  
11Applies to three-statable pins with 50 kinternal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI.  
12Applies to three-statable pins with 50 kinternal pull-downs: LxDAT7–0 (below Revision1.2), LxCLK, LxACK. Use IOZHPD2 for Rev. 1.2 and higher.  
13Applies to three-statable pins with 20 kinternal pull-downs: LxDAT7-0 (Revision 1.2 and higher).  
14The test program used to measure IDDINPEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power  
measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 20.  
15Current numbers are for VDDINT and AVDD supplies combined.  
16  
I
I
is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page 20.  
is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 20.  
DDINHIGH  
17  
DDINLOW  
18Idle denotes ADSP-21161N state during execution of IDLE instruction. For more information, see Power Dissipation on Page 20.  
19Characterized, but not tested.  
20Applies to all signal pins.  
21Guaranteed, but not tested.  
Rev. C  
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Page 18 of 60  
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January 2013  
 
ADSP-21161N  
PACKAGE INFORMATION  
ESD CAUTION  
The information presented in Figure 7 provides details about  
how to read the package brand and relate it to specific product  
features.  
ESD (electrostatic discharge) sensitive device.  
Charged devices and circuit boards can discharge  
without detection. Although this product features  
patented or proprietary protection circuitry, damage  
may occur on devices subjected to high energy ESD.  
Therefore, proper ESD precautions should be taken to  
avoid performance degradation or loss of functionality.  
a
ADSP-21161N  
tppZ-cc  
vvvvvv.x n.n  
TIMING SPECIFICATIONS  
#yyww country_of_origin  
The ADSP-21161N’s internal clock switches at higher frequen-  
cies than the system input clock (CLKIN). To generate the  
internal clock, the DSP uses an internal phase-locked loop  
(PLL). This PLL-based clocking minimizes the skew between  
the system clock (CLKIN) signal and the DSP’s internal clock  
(the clock source for the external port logic and I/O pads).  
S
Figure 7. Typical Package Brand  
Table 5. Package Brand Information  
The ADSP-21161N’s internal clock (a multiple of CLKIN) pro-  
vides the clock signal for timing internal memory, processor  
core, link ports, serial ports, and external port (as required for  
read/write strobes in asynchronous access mode). During reset,  
program the ratio between the DSP’s internal clock frequency  
and external (CLKIN) clock frequency with the CLK_CFG1–0  
and CLKDBL pins. Even though the internal clock is the clock  
source for the external port, it behaves as described in the Clock  
Rate Ratio chart in Table 3 on Page 16. To determine switching  
frequencies for the serial and link ports, divide down the inter-  
nal clock, using the programmable divider control of each port  
(DIVx for the serial ports and LxCLKD for the link ports).  
Brand Key  
Field Description  
Model Number  
ADSP-21161N  
t
Temperature Range  
Package Type  
pp  
z
RoHS Compliance Option  
Assembly Lot Code  
Silicon Revision  
vvvvv.x  
n.n  
#
RoHS Compliance Designation  
Date Code  
yyww  
Note the following definitions of various clock periods that are a  
function of CLKIN and the appropriate ratio control (Table 7).  
ABSOLUTE MAXIMUM RATINGS  
Stresses greater than those listed in Table 6 may cause perma-  
nent damage to the device. These are stress ratings only;  
functional operation of the device at these or any other condi-  
tions greater than those indicated in the operational sections of  
this specification is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device  
reliability.  
Figure 8 enables Core-to-CLKIN ratios of 2:1, 3:1, 4:1, 6:1, and  
8:1 with external oscillator or crystal. It also shows support for  
CLKOUT-to-CLKIN ratios of 1:1 and 2:1.  
Use the exact timing information given. Do not attempt to  
derive parameters from the addition or subtraction of others.  
While addition or subtraction would yield meaningful results  
for an individual device, the values given in this data sheet  
reflect statistical variations and worst cases. Consequently, it is  
not meaningful to add parameters to derive longer times.  
Table 6. Absolute Maximum Ratings  
Parameter  
Rating  
See Figure 37 on Page 54 under Test Conditions for voltage ref-  
erence levels.  
Internal (Core) Supply Voltage (VDDINT  
)
–0.3 V to +2.2 V  
–0.3 V to +2.2 V  
–0.3 V to +4.6 V  
–0.5 V to VDDEXT + 0.5 V  
–0.5 V to VDDEXT + 0.5 V  
200 pF  
Analog (PLL) Supply Voltage (AVDD  
)
Switching characteristics specify how the processor changes its  
signals. Circuitry external to the processor must be designed for  
compatibility with these signal characteristics. Switching char-  
acteristics describe what the processor will do in a given circum-  
stance. Use switching characteristics to ensure that any timing  
requirement of a device connected to the processor (such as  
memory) is satisfied.  
External (I/O) Supply Voltage (VDDEXT  
)
Input Voltage  
Output Voltage Swing  
Load Capacitance  
Storage Temperature Range  
–65C to +150C  
Timing requirements apply to signals that are controlled by cir-  
cuitry external to the processor, such as the data input for a read  
operation. Timing requirements guarantee that the processor  
operates correctly with other devices.  
Rev. C  
|
Page 19 of 60  
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January 2013  
ADSP-21161N  
CORE  
I/O PROCESSOR  
SYNCHRONOUS EP  
ASYNCHRONOUS EP  
HARDWARE  
INTERRUPT  
I/O FLAG  
MULTIPROCESSING  
SBSRAM  
HOST  
SRAM  
TIMER  
LINK PORTS  
x1, x1/2, x1/3, x1/4  
SDRAM  
x1, x1/2  
CLKIN  
(CRYSTAL OSCILLATOR  
4.2–55 MHz)  
SERIAL PORTS  
x1/2 MAX  
CLOCK DOUBLER  
RATIOS  
x2, x3, x4  
x1, x2  
XTAL  
(QUARTZ CRYSTAL  
27.5 MHz MAX)  
PLL  
SPI  
x1/8 MAX  
CLKOUT  
CLK_CFG1–0  
CLKDBL  
Figure 8. Core Clock and System Clock Relationship to CLKIN  
Table 7. CLKOUT and CCLK Clock Generation Operation  
Timing Requirements  
Description1  
Calculation  
CLKIN  
CLKOUT  
PLLICLK  
CCLK  
tCK  
Input Clock  
1/tCK  
External Port System Clock  
PLL Input Clock  
1/tCKOP  
1/tPLLIN  
Core Clock  
1/tCCLK  
CLKIN Clock Period  
(Processor) Core Clock Period  
Link Port Clock Period  
Serial Port Clock Period  
SDRAM Clock Period  
SPI Clock Period  
1/CLKIN  
1/CCLK  
tCCLK  
tLCLK  
(tCCLK) LR  
(tCCLK) SR  
(tCCLK) SDCKR  
(tCCLK) SPIR  
tSCLK  
tSDK  
tSPICLK  
1 where:  
LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD)  
SR = serial port-to-core clock ratio (wide range, determined by CLKDIV)  
SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register)  
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register)  
LCLK = Link Port Clock  
SCLK = Serial Port Clock  
SDK = SDRAM Clock  
SPICLK = SPI Clock  
POWER DISSIPATION  
Total power dissipation has two components: one due to inter-  
nal circuitry and one due to the switching of external output  
drivers.  
Internal power dissipation depends on the instruction execution  
sequence and the data operands involved. Using the current  
specifications (IDDINPEAK, IDDINHIGH, IDDINLOW, IDDIDLE) from the  
Electrical Characteristics on Page 18 and the current-versus-  
operation information in Table 8, the programmer can estimate  
the ADSP-21161N’s internal power supply (VDDINT) input cur-  
rent for a specific application, according to the following  
formula:  
% Peak IDD  
-
INPEAK  
% High IDD  
-
INHIGH  
% Low IDD  
-
INLOW  
+ % Peak IDD  
-
IDLE  
= IDDINT  
Rev. C  
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Page 20 of 60  
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January 2013  
 
ADSP-21161N  
Table 8. Operation Types Versus Input Current  
Operation  
Peak Activity1 (IDDINPEAK  
Multifunction  
Cache  
)
High Activity1 (IDDINHIGH  
Multifunction  
)
Low Activity1 (IDDINLOW  
)
Instruction Type  
Single Function  
Instruction Fetch  
Core Memory Access2  
Internal Memory DMA  
External Memory DMA  
Internal Memory  
Internal Memory  
2 per tCK cycle (DM64 and PM64)  
1 per 2 tCCLK cycles  
1 per tCK cycle (DM64)  
1 per 2 tCCLK cycles  
None  
N/A  
1 per external port cycle (32)  
Worst case  
1 per external port cycle (32)  
Random  
N/A  
Data bit pattern for core  
memory access and DMA  
N/A  
1 The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.  
2 These assume a 2:1 core clock ratio. For more information on ratios and clocks (tCK and tCCLK), see the timing ratio definitions on Page 19.  
The external component of total power dissipation is caused by  
the switching of output pins. Its magnitude depends on:  
• The bus cycle time is 55 MHz  
• The external SDRAM clock rate is 110 MHz  
• Ignoring SDRAM refresh cycles  
• The number of output pins that switch during each cycle  
(O)  
• Addresses are incremental and on the same page  
• The maximum frequency at which they can switch (f)  
• Their load capacitance (C)  
The PEXT equation is calculated for each class of pins that can  
drive, as shown in Table 9.  
• Their voltage swing (VDD  
)
A typical power consumption can now be calculated for these  
conditions by adding a typical internal power dissipation:  
and is calculated by:  
2
P
= O C V  
f  
P
= P  
+ P  
+ P  
EXT  
DD  
TOTAL  
EXT  
INT  
PLL  
The load capacitance should include the processor package  
capacitance (CIN). The switching frequency includes driving the  
Where:  
P
P
EXT is from Table 9.  
INT is IDDINT × 1.8 V, using the calculation IDDINT listed in Power  
load high and then back low. At a maximum rate of 1/tCK  
,
address and data pins can drive high and low, while writing to a  
SDRAM memory.  
Dissipation on Page 20.  
P
PLL is AIDD × 1.8 V, using the value for AIDD listed in the Electri-  
Example: Estimate PEXT with the following assumptions:  
cal Characteristics on Page 18.  
• A system with one bank of external memory (32 bit)  
Note that the conditions causing a worst-case PEXT are different  
from those causing a worst-case PINT. Maximum PINT cannot  
occur while 100% of the output pins are switching from all ones  
to all zeros. Note also that it is not common for an application to  
have 100% or even 50% of the outputs switching  
simultaneously.  
• Two 1M 
؋
 16 SDRAM chips are used, each with a load of  
10 pF (ignoring trace capacitance)  
• External Data Memory writes can occur every cycle at a  
rate of 1/tCK with 50% of the pins switching  
Table 9. External Power Calculations—110 MHz Instruction Rate  
2
Pin Type  
Address  
MSx  
Number of Pins  
% Switching  
؋
 C  
؋
 f  
؋
 VDD  
10.9 V  
10.9 V  
10.9 V  
10.9 V  
10.9 V  
= PEXT  
11  
4
20  
0
24.7 pF  
24.7 pF  
24.7 pF  
14.7 pF  
24.7 pF  
55 MHz  
N/A  
= 0.033 W  
= 0.000 W  
= 0.000 W  
= 0.141 W  
= 0.030 W  
EXT = 0.204 W  
SDWE  
1
0
N/A  
Data  
32  
1
50  
100  
55 MHz  
110 MHz  
SDCLK0  
P
Rev. C  
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Page 21 of 60  
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January 2013  
 
ADSP-21161N  
protection circuitry. With this technique, if the 1.8 V rail rises  
ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail  
along with the 1.8 V rail.  
Power-Up Sequencing — Silicon Revision 1.2 and Greater  
The timing requirements for DSP startup are given in Table 10.  
During the power-up sequence of the DSP, differences in the  
ramp-up rates and activation time between the two supplies can  
cause current to flow in the I/O ESD protection circuitry. To  
prevent damage to the ESD diode protection circuitry, Analog  
Devices recommends including a bootstrap Schottky diode.  
DC INPUT  
SOURCE  
3.3V I/O  
VOLTAGE  
VDDEXT  
REGULATOR  
ADSP-21161N  
The bootstrap Schottky diode is connected between the 1.8 V  
and 3.3 V power supplies as shown in Figure 9. It protects the  
ADSP-21161N from partially powering the 3.3 V supply.  
Including a Schottky diode will shorten the delay between  
the supply ramps and thus prevent damage to the ESD diode  
1.8V CORE  
VOLTAGE  
REGULATOR  
VDDINT  
Figure 9. Dual Voltage Schottky Diode  
Table 10. Power-Up Sequencing Silicon Revision 1.2 and Greater (DSP Startup)  
Parameter  
Min  
Max  
Unit  
Timing Requirements  
tRSTVDD  
tIVDDEVDD  
tCLKVDD  
tCLKRST  
tPLLRST  
tWRST  
RESET Low Before VDDINT/VDDEXT on  
VDDINT on Before VDDEXT  
CLKIN Valid After VDDINT/VDDEXT Valid1  
CLKIN Valid Before RESET Deasserted2  
PLL Control Setup Before RESET Deasserted3  
Subsequent RESET Low Pulsewidth4  
0
ns  
ms  
ms  
μs  
μs  
ns  
–50  
0
+200  
200  
10  
20  
4tCK  
Switching Requirements  
3, 5  
tCORERST DSP core reset deasserted after RESET deasserted  
4080tCK  
1 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds  
depending on the design of the power supply subsystem.  
2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for start-up time.  
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.  
3 Based on CLKIN cycles.  
4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and  
propagate default states at all I/O pins.  
5 The 4080 cycle count depends on tSRST specification in Table 12. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in  
4081 cycles maximum.  
RESET  
tRSTVDD  
VDDINT  
tIVDDEVDD  
VDDEXT  
tCLKRST  
tCLKVDD  
CLKIN  
CLKDBL  
CLK_CFG1-0  
tPLLRST  
tCORERST  
RSTOUT  
Figure 10. Power-Up Sequencing for Silicon Revision 1.2 and Greater (DSP Startup)  
Rev. C  
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Page 22 of 60  
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January 2013  
 
ADSP-21161N  
Clock Input  
In systems that use multiprocessing or SBSRAM, CLKDBL can-  
not be enabled nor can the systems use an external crystal as the  
CLKIN source.  
Do not use CLKOUT as the clock source for the SBSRAM  
device. Using an external crystal in conjunction with CLKDBL  
to generate a CLKOUT frequency is not supported. Negative  
hold times can result from the potential skew between CLKIN  
and CLKOUT.  
Table 11. Clock Input  
100 MHz  
110 MHz  
Unit  
Parameter  
Min  
Max  
Min  
Max  
Timing Requirements  
tCK  
CLKIN Period1  
20  
238  
119  
119  
3
18  
7
238  
119  
119  
3
ns  
ns  
ns  
ns  
ns  
tCKL  
tCKH  
tCKRF  
tCCLK  
CLKIN Width Low1  
CLKIN Width High1  
CLKIN Rise/Fall (0.4 V–2.0 V)  
CCLK Period  
7.5  
7.5  
7
10  
30  
9
30  
Switching Characteristics  
tDCKOO CLKOUT Delay After CLKIN  
0
2
0
2
ns  
ns  
ns  
ns  
tCKOP  
CLKOUT Period  
tCK –1  
tCK+1  
tCK –1  
tCK+1  
tCKWH CLKOUT Width High  
tCKWL CLKOUT Width Low  
tCKOP/2–2  
tCKOP/2–2  
tCKOP/2+2  
tCKOP/2+2  
tCKOP/2–2  
tCKOP/2–2  
tCKOP/2+2  
tCKOP/2+2  
1 CLKIN is dependent on the configuration of the CLKCFGx and CLKDBL pins to achieve desired tCCLK  
.
tCK  
CLKIN  
tCKH  
tCKL  
1
1
tCKOP  
tDCKOO  
1
1
tCKWH  
tCKWL  
CLKOUT  
2
tDCKOO  
2
2
tCKOP  
tDCKOO  
2
2
tCKWL  
tCKWH  
CLKOUT  
NOTES:  
1. WHEN CLKDBL IS DISABLED, ANY SPECIFICATION TO CLKIN  
APPLIES TO THE RISING EDGE, ONLY.  
2. WHEN CLKDBL IS ENABLED, ANY SPECIFICATION TO CLKIN  
APPLIES TO THE RISING OR FALLING EDGE.  
Figure 11. Clock Input  
Rev. C  
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Page 23 of 60  
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January 2013  
ADSP-21161N  
Clock Signals  
The ADSP-21161N can use an external clock or a crystal. See  
CLKIN pin description. The programmer can configure the  
ADSP-21161N to use its internal clock generator by connecting  
the necessary components to CLKIN and XTAL. Figure 12  
shows the component connections used for a crystal operating  
in fundamental mode.  
CLKIN  
XTAL  
X1  
C2  
27pF  
C1  
27pF  
SUGGESTED COMPONENTS FOR 100MHz OPERATION:  
ECLIPTEK EC2SM-25.000M (SURFACE MOUNT PACKAGE)  
ECLIPTEK EC-25.000M (THROUGH-HOLE PACKAGE)  
C1 = 27pF  
C2 = 27pF  
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.  
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. THIS 25MHz  
CRYSTAL GENERATES A 100MHz CCLK AND A 50MHz EP CLOCK  
WITH CLKDBL ENABLED AND A 2:1 PLL MULTIPLY RATIO.  
Figure 12. 100 MHz Operation (Fundamental Mode Crystal)  
Reset  
Table 12. Reset  
Parameter  
Min  
Max  
Unit  
Timing Requirements  
tWRST  
tSRST  
RESET Pulsewidth Low1  
RESET Setup Before CLKIN High2  
4tCK  
8.5  
ns  
ns  
1 Applies after the power-up sequence is complete.  
2 Only required if multiple ADSP-21161Ns mustcome out of reset synchronousto CLKIN with program counters (PC) equal. Not required for multipleADSP-21161Ns  
communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.  
CLKIN  
tSRST  
tWRST  
RESET  
Figure 13. Reset  
Rev. C  
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Page 24 of 60  
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January 2013  
 
ADSP-21161N  
Interrupts  
Table 13. Interrupts  
Parameter  
Min  
Max  
Unit  
Timing Requirements  
tSIR  
tHIR  
tIPW  
IRQ2–0 Setup Before CLKIN1  
IRQ2–0 Hold After CLKIN1  
IRQ2–0 Pulsewidth2  
6
ns  
ns  
ns  
0
tCKOP + 2  
1 Only required for IRQx recognition in the following cycle.  
2 Applies only if tSIR and tHIR requirements are not met.  
CLKIN  
tHIR  
tSIR  
IRQ2–0  
tIPW  
Figure 14. Interrupts  
Timer  
Table 14. Timer  
Parameter  
Min  
Max  
Unit  
Switching Characteristic  
tDTEX  
CCLK to TIMEXP  
1
7
ns  
CCLK  
tDTEX  
tDTEX  
TIMEXP  
Figure 15. Timer  
Rev. C  
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January 2013  
 
ADSP-21161N  
Flags  
Table 15. Flags  
100 MHz  
Max  
110 MHz  
Max  
Parameter  
Min  
Min  
Unit  
Timing Requirement  
tSFI  
FLAG11–0IN Setup Before CLKIN1  
FLAG11–0IN Hold After CLKIN1  
FLAG11–0IN Delay After RD/WR Low1  
FLAG11–0IN Hold After RD/WR Deasserted1  
4
1
4
1
ns  
ns  
ns  
ns  
tHFI  
tDWRFI  
tHFIWR  
12  
9
9
9
5
0
0
Switching Characteristics  
tDFO  
FLAG11–0OUT Delay After CLKIN  
ns  
ns  
ns  
ns  
tHFO  
FLAG11–0OUT Hold After CLKIN  
CLKIN to FLAG11–0OUT Enable  
CLKIN to FLAG11–0OUT Disable  
1
1
1
1
tDFOE  
tDFOD  
5
1 Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.  
CLKIN  
tDFO  
tDFO  
tDFOD  
tDFOE  
tHFO  
FLAG11–0  
CLKIN  
OUT  
FLAG OUTPUT  
tSFI  
tHFI  
FLAG11–0  
IN  
tDWRFI  
tHFIWR  
⑁ ⌹  
⌹⌬,  
FLAG INPUT  
Figure 16. Flags  
Rev. C  
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Page 26 of 60  
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January 2013  
 
ADSP-21161N  
Table 16. These specifications apply when the ADSP-21161N is  
the bus master accessing external memory space in asynchro-  
nous access mode.  
Memory Read — Bus Master  
Use these specifications for asynchronous interfacing to memo-  
ries (and memory-mapped peripherals) without reference to  
CLKIN except for ACK pin requirements listed in footnote 4 of  
Table 16. Memory Read — Bus Master  
100 MHz  
110 MHz  
Parameter  
Min  
Max  
Min  
Max  
Unit  
Timing Requirements  
tDAD  
Address, Selects Delay to  
tCKOP 0.25tCCLK8.5+W  
0.75tCKOP –11+W  
tCKOP 0.25tCCLK6.75+W ns  
Data Valid1, 2, 3  
tDRLD  
tHDA  
RD Low to Data Valid1,3  
0.75tCKOP –11+W  
ns  
ns  
Data Hold from Address, 0  
Selects4  
0
tSDS  
Data Setup to RD High  
Data Hold from RD High4  
8
1
8
1
ns  
ns  
ns  
tHDRH  
tDAAK  
ACK Delay from Address,  
Selects2, 5  
ACK Delay from RD Low5  
ACK Setup to CLKIN5  
ACK Hold After CLKIN  
tCKOP 0.5tCCLK–12+W  
tCKOP0.75tCCLK–11+W  
tCKOP 0.5tCCLK–12+W  
tDSAK  
tSAKC  
tHAKC  
tCKOP0.75tCCLK–11+W ns  
0.5tCCLK+3  
1
0.5tCCLK+3  
1
ns  
ns  
Switching Characteristics  
tDRHA Address Selects Hold  
0.25tCCLK–1+H  
0.25tCCLK 3  
0.25tCCLK–1+H  
0.25tCCLK 3  
ns  
ns  
After RD High  
tDARL  
Address Selects to RD  
Low2  
tRW  
RD Pulsewidth  
tCKOP–0.5tCCLK 1+W  
0.5tCCLK –1+HI  
tCKOP–0.5tCCLK 1+W  
0.5tCCLK 1+HI  
ns  
ns  
tRWR  
RD High to WR, RD,  
DMAGx Low  
W = (number of wait states specified in WAIT register) × tCKOP  
.
HI = tCKOP (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).  
H = tCKOP (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).  
1 Data Delay/Setup: User must meet tDAD, tDRLD, or tSDS.  
2 The falling edge of MSx, BMS is referenced.  
3 The maximum limits of timing requirement values for tDAD and tDRLD parameters are applicable for the case where ACK is always high.  
4 Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Example System Hold Time Calculation on Page 54 for the calculation of hold times given capacitive  
and dc loads.  
5 For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,  
ACK must be driven low (deasserted) by tDAAK, tDSAK, or tSAKC. For the second and subsequent cycles of an asynchronous external memory access, the tSAKC and tHAKC must be  
met for both assertion and deassertion of ACK signal.  
Rev. C  
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Page 27 of 60  
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January 2013  
 
ADSP-21161N  
tHDA  
ADDRESS  
MSx, BMS  
tDRHA  
tDARL  
tRW  
RD  
tSDS  
tDRLD  
tDAD  
tHDRH  
DATA  
tDSAK  
tDAAK  
tRWR  
ACK  
tHAKC  
tSAKC  
CLKIN  
WR, DMAG  
Figure 17. Memory Read — Bus Master  
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ADSP-21161N  
Table 17. These specifications apply when the ADSP-21161N is  
the bus master accessing external memory space in asynchro-  
nous access mode.  
Memory Write — Bus Master  
Use these specifications for asynchronous interfacing to memo-  
ries (and memory-mapped peripherals) without reference to  
CLKIN except for ACK pin requirements listed in footnote 1 of  
Table 17. Memory Write — Bus Master  
Parameter  
Min  
Max  
Unit  
Timing Requirements  
tDAAK  
tDSAK  
tSAKC  
tHAKC  
ACK Delay from Address, Selects1, 2  
ACK Delay from WR Low1  
ACK Setup to CLKIN1  
tCKOP–0.5tCCLK–12+W  
tCKOP–0.75tCCLK–11+W  
ns  
ns  
ns  
ns  
0.5tCCLK +3  
1
ACK Hold After CLKIN1  
Switching Characteristics  
tDAWH  
tDAWL  
tWW  
Address, Selects to WR Deasserted2  
Address, Selects to WR Low2  
tCKOP – 0.25tCCLK 3+W  
0.25tCCLK – 3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WR Pulsewidth  
tCKOP – 0.5tCCLK 1+W  
tCKOP 0.25tCCLK – 13.5+W  
0.25tCCLK 1+H  
tDDWH  
tDWHA  
tDWHD  
tDATRWH  
tWWR  
Data Setup Before WR High  
Address Hold After WR Deasserted  
Data Hold After WR Deasserted  
Data Disable After WR Deasserted3  
WR High to WR, RD, DMAGx Low  
Data Disable Before WR or RD Low  
WR Low to Data Enabled  
0.25tCCLK 1+H  
0.25tCCLK 2+H  
0.25tCCLK+2.5+H  
0.5tCCLK – 1.25+HI  
0.25tCCLK 3+I  
tDDWR  
tWDE  
–0.25tCCLK – 1  
W = (number of wait states specified in WAIT register) × tCKOP  
.
H = tCKOP (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).  
HI = tCKOP (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).  
I = tCKOP (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).  
1 For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,  
ACK must be driven low (deasserted) by tDAAK, tDSAK, or tSAKC. For the second and subsequent cycles of an asynchronous external memory access, the tSAKC and tHAKC must be  
met for both assertion and deassertion of ACK signal.  
2 The falling edge of MSx, BMS is referenced.  
3 See Example System Hold Time Calculation on Page 54 for calculation of hold times given capacitive and dc loads.  
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ADSP-21161N  
ADDRESS  
MSx, BMS  
tDAWH  
tDWHA  
tDAWL  
tWW  
WR  
tWWR  
tDATRWH  
tWDE  
tDDWH  
tDDWR  
DATA  
ACK  
tDSAK  
tDWHD  
tDAAK  
tHAKC  
tSAKC  
CLKIN  
RD, DMAG  
Figure 18. Memory Write — Bus Master  
Rev. C  
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ADSP-21161N  
must meet the slave's timing requirements for synchronous  
read/writes (see Synchronous Read/Write — Bus Slave on  
Page 32). The slave ADSP-21161N must also meet these (bus  
master) timing requirements for data and acknowledge setup  
and hold times.  
Synchronous Read/Write — Bus Master  
Use these specifications for interfacing to external memory sys-  
tems that require CLKIN, relative to timing or for accessing a  
slave ADSP-21161N (in multiprocessor memory space). When  
accessing a slave ADSP-21161N, these switching characteristics  
Table 18. Synchronous Read/Write — Bus Master  
Parameter  
Min  
Max  
Unit  
Timing Requirements  
tSSDATI  
tHSDATI  
tSACKC  
tHACKC  
Data Setup Before CLKIN  
Data Hold After CLKIN  
ACK Setup Before CLKIN  
ACK Hold After CLKIN  
5.5  
ns  
ns  
ns  
ns  
1
0.5tCCLK+3  
1
Switching Characteristics  
tDADDO  
tHADDO  
tDRDO  
Address, MSx, BMS, BRST, Delay After CLKIN  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address, MSx, BMS, BRST, Hold After CLKIN  
RD High Delay After CLKIN  
WR High Delay After CLKIN  
RD/WR Low Delay After CLKIN  
Data Delay After CLKIN  
1.5  
0.25tCCLK–1  
0.25tCCLK–1  
0.25tCCLK–1  
0.25tCCLK+9  
0.25tCCLK+9  
0.25tCCLK+9  
12.5  
tDWRO  
tDRWL  
tDDATO  
tHDATO  
Data Hold After CLKIN  
1.5  
CLKIN  
tHADDO  
tDADDO  
ADDRESS  
MSx, BRST  
tSACKC  
tHACKC  
ACK  
(IN)  
READ CYCLE  
tDRWL  
tDRDO  
RD  
tSSDATI  
tHSDATI  
DATA  
(IN)  
WRITE CYCLE  
tDRWL  
tDWRO  
WR  
tDDATO  
tHDATO  
DATA (OUT)  
Figure 19. Synchronous Read/Write — Bus Master  
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ADSP-21161N  
Synchronous Read/Write — Bus Slave  
Use these specifications for ADSP-21161N bus master accesses  
of a slave’s IOP registers in multiprocessor memory space. The  
bus master must meet these (bus slave) timing requirements.  
Table 19. Synchronous Read/Write — Bus Slave  
Parameter  
Min  
Max  
Unit  
Timing Requirements  
tSADDI  
tHADDI  
tSRWI  
Address, BRST Setup Before CLKIN  
Address, BRST Hold After CLKIN  
RD/WR Setup Before CLKIN  
RD/WR Hold After CLKIN  
5
ns  
ns  
ns  
ns  
ns  
ns  
1
5
tHRWI  
1
tSSDATI  
tHSDATI  
Data Setup Before CLKIN  
5.5  
1
Data Hold After CLKIN  
Switching Characteristics  
tDDATO  
tHDATO  
tDACKC  
tHACKO  
Data Delay After CLKIN  
12.5  
10  
ns  
ns  
ns  
ns  
Data Hold After CLKIN  
ACK Delay After CLKIN  
ACK Hold After CLKIN  
1.5  
1.5  
CLKIN  
tSADDI  
tHADDI  
ADDRESS  
tHACKO  
tDACKC  
ACK  
READ ACCESS  
tSRWI  
tHRWI  
RD  
tDDATO  
tHDATO  
DATA  
(OUT)  
WRITE ACCESS  
tHRWI  
tSRWI  
WR  
tSSDATI  
tHSDATI  
DATA  
(IN)  
Figure 20. Synchronous Read/Write — Bus Slave  
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ADSP-21161N  
Host Bus Request  
Use these specifications for asynchronous host bus requests of  
an ADSP-21161N (HBR, HBG).  
Table 20. Host Bus Request  
100 MHz  
Max  
110 MHz  
Parameter  
Min  
Min  
Max  
Unit  
Timing Requirements  
tHBGRCSV  
tSHBRI  
HBG Low to RD/WR/CS Valid  
HBR Setup Before CLKIN1  
HBR Hold After CLKIN1  
HBG Setup Before CLKIN  
HBG Hold After CLKIN  
19  
19  
ns  
ns  
ns  
ns  
ns  
6
1
6
1
6
1
6
1
tHHBRI  
tSHBGI  
tHHBGI  
Switching Characteristics  
tDHBGO  
tHHBGO  
tDRDYCS  
tTRDYHG  
tARDYTR  
HBG Delay After CLKIN  
7
7
ns  
ns  
ns  
ns  
ns  
HBG Hold After CLKIN  
1.5  
1.5  
REDY (O/D) or (A/D) Low from CS and HBR Low2  
REDY (O/D) Disable or REDY (A/D) High from HBG2  
REDY (A/D) Disable from CS or HBR High2  
10  
11  
10  
11  
tCKOP + 14  
tCKOP + 12  
1 Only required for recognition in the current cycle.  
2 (O/D) = open drain, (A/D) = active drive.  
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ADSP-21161N  
CLKIN  
tSHBRI  
tHHBRI  
HBR  
tDHBG O  
tHHBGO  
HBG (OUT)  
tSHBGI  
tHHBGI  
HBG  
(IN)  
HBR  
CS  
tDRDY CS  
tTRDYHG  
RE DY  
(O/D)  
tARDYTR  
RE DY  
(A/D)  
tHBGRCS V  
HBG (OUT)  
RD  
WR  
CS  
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE  
Figure 21. Host Bus Request  
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ADSP-21161N  
Multiprocessor Bus Request  
Use these specifications for passing of bus mastership between  
multiprocessing ADSP-21161Ns (BRx).  
Table 21. Multiprocessor Bus Request  
Parameter  
Min  
Max  
Unit  
Timing Requirements  
tSBRI  
BRx Setup Before CLKIN High  
BRx Hold After CLKIN High  
PA Setup Before CLKIN High  
PA Hold After CLKIN High  
9
ns  
ns  
ns  
ns  
ns  
ns  
tHBRI  
0.5  
9
tSPAI  
tHPAI  
1
tSRPBAI  
tHRPBAI  
RPBA Setup Before CLKIN High  
RPBA Hold After CLKIN High  
6
2
Switching Characteristics  
tDBRO  
tHBRO  
tDPASO  
tTRPAS  
tDPAMO  
tPATR  
BRx Delay After CLKIN High  
8
8
ns  
ns  
ns  
ns  
BRx Hold After CLKIN High  
1.0  
PA Delay After CLKIN High, Slave  
PA Disable After CLKIN High, Slave  
PA Delay After CLKIN High, Master  
PA Disable Before CLKIN High, Master  
1.5  
0.25tCCLK+9  
ns  
ns  
0.25tCCLK–5  
CLKIN  
tDBRO  
tHBRO  
BRx (OUT)  
tDP A SO  
tTRPAS  
PA (OUT)  
(SLAV E)  
tDPAMO  
tPAT R  
PA (OUT)  
(MASTER)  
tSBRI  
tHBRI  
BRx (IN)  
tS PAI  
tHPAI  
PA (IN)  
(O/D)  
tS RPBAI  
tHR P BAI  
RP BA  
O/D = OPEN DRAIN  
Figure 22. Multiprocessor Bus Request  
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ADSP-21161N  
for this timing. Although the DSP will recognize HBR asserted  
before reset, a HBG will not be returned by the DSP until after  
reset is deasserted and the DSP completes bus synchronization.  
Note: Host internal memory access is not supported.  
Asynchronous Read/Write — Host to ADSP-21161N  
Use these specifications for asynchronous host processor  
accesses of an ADSP-21161N, after the host has asserted CS and  
HBR (low). After HBG is returned by the ADSP-21161N, the  
host can drive the RD and WR pins to access the  
ADSP-21161N’s IOP registers. HBR and HBG are assumed low  
Table 22. Read Cycle  
Parameter  
Min  
Max  
Unit  
Timing Requirements  
tSADRDL  
tHADRDH  
tWRWH  
Address Setup and CS Low Before RD Low  
Address Hold and CS Hold Low After RD  
RD/WR High Width  
0
ns  
ns  
ns  
ns  
ns  
2
3.5  
0
tDRDHRDY  
tDRDHRDY  
RD High Delay After REDY (O/D) Disable  
RD High Delay After REDY (A/D) Disable  
0
Switching Characteristics  
tSDATRDY  
tDRDYRDL  
tRDYPRD  
tHDARWH  
Data Valid Before REDY Disable from Low  
2
ns  
ns  
ns  
ns  
REDY (O/D) or (A/D) Low Delay After RD Low  
REDY (O/D) or (A/D) Low Pulsewidth for Read  
Data Disable After RD High  
10  
6
1.5tCCLK  
2
Table 23. Write Cycle  
Parameter  
Min  
Max  
Unit  
Timing Requirements  
tSCSWRL  
tHCSWRH  
tSADWRH  
tHADWRH  
tWWRL  
CS Low Setup Before WR Low  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CS Low Hold After WR High  
Address Setup Before WR High  
Address Hold After WR High  
WR Low Width  
0
6
2
tCCLK  
3.5  
0
tWRWH  
RD/WR High Width  
tDWRHRDY  
tSDATWH  
tHDATWH  
WR High Delay After REDY (O/D) or (A/D) Disable  
Data Setup Before WR High  
Data Hold After WR High  
5
4
Switching Characteristics  
tDRDYWRL  
REDY (O/D) or (A/D) Low Delay After WR/CS Low1  
tRDYPWR  
REDY (O/D) or (A/D) Low Pulsewidth for Write1  
11  
ns  
ns  
12  
1 Only when slave write FIFO is full.  
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ADSP-21161N  
READ CYCLE  
ADDRESS/CS  
tSADRDL  
tHADRDH  
tWRWH  
RD  
tHDARW H  
DATA (OUT)  
tSDAT RDY  
tDRDYRDL  
tDRDHRDY  
tRDYPRD  
REDY (O/D)  
REDY (A/D)  
WRITE CYCLE  
ADDRESS  
tSADW RH  
tHADW RH  
tSCSWRL  
tHCSWRH  
CS  
tWWRL  
tW RW H  
WR  
tSDATWH  
tHDATWH  
DATA (IN)  
tDRDYWRL  
tRDYPW R  
tDWRHRDY  
REDY (O/D)  
REDY (A/D)  
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE  
Figure 23. Asynchronous Read/Write — Host to ADSP-21161N  
Rev. C  
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ADSP-21161N  
During reset, the DSP will not respond to SBTS, HBR, and MMS  
accesses. Although the DSP will recognize HBR asserted before  
reset, a HBG will not be returned by the DSP until after reset is  
deasserted and the DSP completes bus synchronization.  
Three-State Timing — Bus Master, Bus Slave  
These specifications show how the memory interface is disabled  
(stops driving) or enabled (resumes driving) relative to CLKIN  
and the SBTS pin. This timing is applicable to bus master transi-  
tion cycles (BTC) and host transition cycles (HTC) as well as the  
SBTS pin.  
Table 24. Three-State Timing — Bus Master, Bus Slave  
Parameter  
Min  
Max  
Unit  
Timing Requirements  
tSTSCK  
tHTSCK  
SBTS Setup Before CLKIN  
SBTS Hold After CLKIN  
6
2
ns  
ns  
Switching Characteristics  
tMIENA Address/Select Enable After CLKIN High  
tMIENS  
tMIENHG  
tMITRA  
1.5  
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Strobes Enable After CLKIN High1  
HBG Enable After CLKIN  
–1.5  
+9  
1.5  
9
Address/Select Disable After CLKIN High  
Strobes Disable After CLKIN High  
HBG Disable After CLKIN2  
0.5tCKOP–20  
tCKOP0.25tCCLK–17  
0.5tCKOP+NtCCLK–20  
1.5  
0.5tCKOP–15  
tMITRS  
tCKOP0.25tCCLK–12.5  
0.5tCKOP+NtCCLK–15  
10  
tMITRHG  
tDATEN  
tDATTR  
tACKEN  
tACKTR  
tCDCEN  
tCDCTR  
tATRHBG  
tSTRHBG  
tBTRHBG  
tMENHBG  
Data Enable After CLKIN3  
Data Disable After CLKIN3  
1.5  
6
ACK Enable After CLKIN High  
ACK Disable After CLKIN High  
CLKOUT Enable After CLKIN2  
1.5  
9
0.2  
5
0.5tCKOP+NtCCLK  
tCKOP–5  
0.5tCKOP+NtCCLK+5  
tCKOP  
CLKOUT Disable After CLKIN  
Address/Select Disable Before HBG Low4  
RD/WR/DMAGx Disable Before HBG Low4  
BMS Disable Before HBG Low4  
Memory Interface Enable After HBG High4  
1.5tCKOP–6  
tCKOP+0.25tCCLK–4  
0.5tCKOP–4  
tCKOP–5  
1.5tCKOP+2  
tCKOP+0.25tCCLK+3  
0.5tCKOP+2  
tCKOP+5  
1 Strobes = RD, WR, DMAGx.  
2 Where N = 0.5, 1.0, 1.5 for 1:2, 1:3, and 1:4, respectively.  
3 In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.  
4 Memory Interface = Address, RD, WR, MSx, DMAGx, and BMS (in EPROM boot mode). BMS is only an output in EPROM boot mode.  
Rev. C  
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ADSP-21161N  
CLKIN  
tSTSCK  
tHTSCK  
SBTS  
tMIENA, tMIENS, tMIENHG  
tMITRA, tMITRS, tMITRHG  
MEMORY  
INTERFACE  
tDATEN  
tDATTR  
DATA  
ACK  
tACKEN  
tACKTR  
CLKIN  
tCDCEN  
tCDCTR  
CLKOUT  
HBG  
tMENHBG  
tATRHBG, tSTRHBG, tBTRHBG  
MEMORY  
INTERFACE  
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, DMAGx, BMS (IN EPROM MODE)  
Figure 24. Three-State Timing — Bus Master, Bus Slave  
Rev. C  
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ADSP-21161N  
DMAG signals. For Paced Master mode, the data transfer is  
controlled by ADDR23–0, RD, WR, MS3–0, and ACK (not  
DMAG). For Paced Master mode, the Memory Read-Bus Mas-  
ter, Memory Write-Bus Master, and Synchronous Read/Write-  
Bus Master timing specifications for ADDR23–0, RD, WR,  
MS3–0, DATA47–16, and ACK also apply.  
DMA Handshake  
These specifications describe the three DMA handshake modes.  
In all three modes DMAR is used to initiate transfers. For hand-  
shake mode, DMAG controls the latching or enabling of data  
externally. For external handshake mode, the data transfer is  
controlled by the ADDR23–0, RD, WR, MS3–0, ACK, and  
Table 25.