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产品型号ADUM1200BRZ的概述

芯片ADUM1200BRZ的概述 ADUM1200BRZ是一款由Analog Devices公司推出的双通道数字隔离器。该芯片采用了高度集成的设计,专为在工业、医疗及其他要求高电压隔离和数据完整性的应用中工作而开发。ADUM1200的工作原理基于ADuM系列的iCoupler技术,这种技术通过电光耦合或电容耦合实现数字信号的隔离。 ADUM1200BRZ的主要特点包括低功耗、高速信号传输和高耐压隔离等。该芯片不仅可应用于需要高电压隔离的通信系统,还被广泛应用于工控、数据采集、医疗设备等领域。通过实现数字信号与电源之间的有效隔离,ADUM1200为系统提供了额外的安全性与稳定性,有效降低了信号传输过程中的干扰和损坏风险。 芯片ADUM1200BRZ的详细参数 ADUM1200BRZ的规格参数如下: 1. 工作电压范围:3.0V至5.5V。 2. 数据传输速率:最高可达2.5 Mbps。 ...

产品型号ADUM1200BRZ的Datasheet PDF文件预览

Dual-Channel Digital Isolators  
ADuM1200/ADuM1201  
GENERAL DESCRIPTION  
FEATURES  
Narrow body SOIC 8-lead package  
Low power operation  
5 V operation  
The ADuM120x are dual-channel digital isolators based on  
Analog Devices’ iCoupler® technology. Combining high speed  
CMOS and monolithic transformer technology, these isolation  
components provide outstanding performance characteristics  
superior to alternatives such as optocoupler devices.  
1.1 mA per channel maximum @ 0 Mbps to 2 Mbps  
3.7 mA per channel maximum @ 10 Mbps  
8.2 mA per channel maximum @ 25 Mbps  
3 V operation  
0.8 mA per channel maximum @ 0 Mbps to 2 Mbps  
2.2 mA per channel maximum @ 10 Mbps  
4.8 mA per channel maximum @ 25 Mbps  
Bidirectional communication  
By avoiding the use of LEDs and photodiodes, iCoupler devices  
remove the design difficulties commonly associated with  
optocouplers. The typical optocoupler concerns regarding  
uncertain current transfer ratios, nonlinear transfer functions,  
and temperature and lifetime effects are eliminated with the  
simple iCoupler digital interfaces and stable performance  
characteristics. The need for external drivers and other discrete  
components is eliminated with these iCoupler products.  
Furthermore, iCoupler devices consume one-tenth to one-sixth  
the power of optocouplers at comparable signal data rates.  
3 V/5 V level translation  
High temperature operation: 105°C  
High data rate: dc to 25 Mbps (NRZ)  
Precise timing characteristics  
3 ns maximum pulse-width distortion  
3 ns maximum channel-to-channel matching  
High common-mode transient immunity: > 25 kV/µs  
Safety and regulatory approvals  
UL recognition  
2500 V rms for 1 minute per UL 1577  
CSA component acceptance notice #5A  
VDE certificate of conformity  
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01  
DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000  
VIORM = 560 V peak  
The ADuM120x isolators provide two independent isolation  
channels in a variety of channel configurations and data rates  
(see the Ordering Guide). Both parts operate with the supply  
voltage on either side ranging from 2.7 V to 5.5 V, providing  
compatibility with lower voltage systems as well as enabling a  
voltage translation functionality across the isolation barrier. In  
addition, the ADuM120x provide low pulse-width distortion  
(< 3 ns for CR grade) and tight channel-to-channel matching  
(< 3 ns for CR grade). Unlike other optocoupler alternatives, the  
ADuM120x isolators have a patented refresh feature that  
ensures dc correctness in the absence of input logic transitions  
and during power-up/power-down conditions.  
APPLICATIONS  
Size-critical multichannel isolation  
SPI® interface/data converter isolation  
RS-232/RS-422/RS-485 transceiver isolation  
Digital field bus isolation  
FUNCTIONAL BLOCK DIAGRAMS  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
V
V
V
V
V
V
DD1  
DD2  
OA  
DD1  
DD2  
IA  
ENCODE  
ENCODE  
DECODE  
DECODE  
DECODE  
ENCODE  
ENCODE  
DECODE  
V
V
V
OA  
IA  
V
IB  
OB  
IB  
OB  
GND  
GND  
GND  
GND  
2
1
2
1
Figure 1. ADuM1200 Functional Block Diagram  
Figure 2. ADuM1201 Functional Block Diagram  
Rev. B  
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Specifications subject to change without notice. No license is granted by implication  
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© 2004 Analog Devices, Inc. All rights reserved.  
ADuM1200/ADuM1201  
TABLE OF CONTENTS  
Specifications..................................................................................... 3  
ESD Caution................................................................................ 12  
Pin Configurations and Function Descriptions......................... 13  
Typical Performance Characteristics ........................................... 14  
Application Information................................................................ 15  
PC Board Layout ........................................................................ 15  
Propagation Delay-Related Parameters................................... 15  
DC Correctness and Magnetic Field Immunity........................... 15  
Power Consumption .................................................................. 16  
Outline Dimensions....................................................................... 17  
Ordering Guide .......................................................................... 17  
Electrical Characteristics—5 V Operation................................ 3  
Electrical Characteristics—3 V Operation................................ 5  
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V  
Operation....................................................................................... 7  
Package Characteristics ............................................................. 10  
Regulatory Information............................................................. 10  
Insulation and Safety-Related Specifications.......................... 10  
DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation  
Characteristics ............................................................................ 11  
Recommended Operating Conditions .................................... 11  
Absolute Maximum Ratings.......................................................... 12  
REVISION HISTORY  
9/04—Data Sheet Changed from Rev. A to Rev. B  
Changes to Table 5.......................................................................... 10  
6/04—Data Sheet Changed from Rev. 0 to Rev. A  
Changes to Format .............................................................Universal  
Changes to General Description .................................................... 1  
Changes to Electrical Characteristics—5 V Operation ............... 3  
Changes to Electrical Characteristics—3 V Operation ............... 5  
Changes to Electrical Characteristics—Mixed 5 V/3 V or  
3 V/5 V Operation ............................................................................ 7  
4/04—Revision 0: Initial Version  
Rev. B | Page 2 of 20  
ADuM1200/ADuM1201  
SPECIFICATIONS  
ELECTRICAL CHARACTERISTICS—5 V OPERATION  
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the  
entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.  
Table 1.  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
Test Conditions  
DC SPECIFICATIONS  
Input Supply Current, per Channel, Quiescent IDDI (Q)  
0.50  
0.19  
0.60  
0.25  
mA  
mA  
Output Supply Current, per Channel, Quiescent  
ADuM1200, Total Supply Current, Two Channels1  
DC to 2 Mbps  
IDDO (Q)  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (Q)  
IDD2 (Q)  
1.1  
0.5  
1.4  
0.8  
mA  
mA  
DC to 1 MHz logic signal freq.  
DC to 1 MHz logic signal freq.  
10 Mbps (BR and CR Grades Only)  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (10)  
IDD2 (10)  
4.3  
1.3  
5.5  
2.0  
mA  
mA  
5 MHz logic signal freq.  
5 MHz logic signal freq.  
25 Mbps (CR Grade Only)  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (25)  
IDD2 (25)  
10  
2.8  
13  
3.4  
mA  
mA  
12.5 MHz logic signal freq.  
12.5 MHz logic signal freq.  
ADuM1201, Total Supply Current, Two Channels1  
DC to 2 Mbps  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (Q)  
IDD2 (Q)  
0.8  
0.8  
1.1  
1.1  
mA  
mA  
DC to 1 MHz logic signal freq.  
DC to 1 MHz logic signal freq.  
10 Mbps (BR and CR Grades Only)  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (10)  
IDD2 (10)  
2.8  
2.8  
3.5  
3.5  
mA  
mA  
5 MHz logic signal freq.  
5 MHz logic signal freq.  
25 Mbps (CR Grade Only)  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (25)  
IDD2 (25)  
6.3  
6.3  
8.0  
8.0  
mA  
mA  
12.5 MHz logic signal freq.  
12.5 MHz logic signal freq.  
For All Models  
Input Currents  
Logic High Input Threshold  
Logic Low Input Threshold  
IIA, IIB  
VIH  
VIL  
−10  
0.7 VDD1, VDD2  
+0.01 +10  
µA  
V
V
0 ≤ VIA, VIB ≤ VDD1 or VDD2  
0.3 VDD1,  
VDD2  
Logic High Output Voltages  
VOAH  
VOBH  
VDD1  
DD2 − 0.1  
VDD1  
VDD2 − 0.5  
,
5.0  
4.8  
V
V
IOx = −20 µA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
V
,
Logic Low Output Voltages  
VOAL  
VOBL  
0.0  
0.04  
0.2  
0.1  
0.1  
0.4  
V
V
V
IOx = 20 µA, VIx = VIxL  
IOx = 400 µA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
SWITCHING SPECIFICATIONS  
ADuM120xAR  
Minimum Pulse Width2  
Maximum Data Rate3  
PW  
1000  
ns  
Mbps  
ns  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
1
Propagation Delay4  
tPHL, tPLH 50  
PWD  
tPSK  
tPSKCD/OD  
tR/tF  
150  
40  
100  
50  
4
Pulse-Width Distortion, |tPLH − tPHL  
|
Propagation Delay Skew5  
Channel-to-Channel Matching6  
ns  
ns  
Output Rise/Fall Time (10% to 90%)  
10  
Rev. B | Page 3 of 20  
 
ADuM1200/ADuM1201  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
Test Conditions  
ADuM120xBR  
Minimum Pulse Width2  
Maximum Data Rate3  
Propagation Delay4  
Pulse-Width Distortion, |tPLH − tPHL  
Change Versus Temperature  
Propagation Delay Skew5  
PW  
100  
ns  
Mbps  
ns  
ns  
ps/°C  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
10  
tPHL, tPLH 20  
PWD  
50  
3
4
|
5
tPSK  
tPSKCD  
15  
3
Channel-to-Channel Matching,  
Codirectional Channels6  
ns  
Channel-to-Channel Matching,  
tPSKOD  
tR/tF  
15  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Opposing Directional Channels6  
Output Rise/Fall Time (10% to 90%)  
ADuM120xCR  
2.5  
Minimum Pulse Width2  
PW  
20  
50  
40  
ns  
Mbps  
ns  
ns  
ps/°C  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Maximum Data Rate3  
25  
tPHL, tPLH 20  
PWD  
Propagation Delay4  
45  
3
4
Pulse-Width Distortion, |tPLH – tPHL  
Change Versus Temperature  
Propagation Delay Skew5  
Channel-to-Channel Matching,  
Codirectional Channels6  
|
5
tPSK  
tPSKCD  
15  
3
ns  
Channel-to-Channel Matching,  
tPSKOD  
tR/tF  
15  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Opposing Directional Channels6  
Output Rise/Fall Time (10% to 90%)  
For All Models  
2.5  
Common-Mode Transient Immunity  
at Logic High Output7  
Common-Mode Transient Immunity  
at Logic Low Output7  
|CMH|  
|CML|  
25  
25  
35  
35  
kV/µs  
kV/µs  
VIx = VDD1, VDD2, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, VCM = 1000 V,  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.2  
0.19  
0.05  
Mbps  
mA/Mbps  
mA/Mbps  
Input Dynamic Supply Current, per Channel8  
IDDI (D)  
Output Dynamic Supply Current, per Channel8 IDDO (D)  
1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load  
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See  
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11  
for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.  
2 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.  
3 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.  
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is  
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.  
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output  
load within the recommended operating conditions.  
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of  
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with  
inputs on opposing sides of the isolation barrier.  
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate  
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient  
magnitude is the range over which the common mode is slewed.  
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for  
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply  
current for a given data rate.  
Rev. B | Page 4 of 20  
 
 
 
 
ADuM1200/ADuM1201  
ELECTRICAL CHARACTERISTICS—3 V OPERATION  
All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V. All min/max specifications apply over the  
entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.  
Table 2.  
Parameter  
Symbol Min  
Typ Max  
Unit  
Test Conditions  
DC SPECIFICATIONS  
Input Supply Current, per Channel, Quiescent IDDI (Q)  
0.26 0.35  
0.11 0.20  
mA  
mA  
Output Supply Current, per Channel, Quiescent  
ADuM1200, Total Supply Current, Two Channels1  
DC to 2 Mbps  
IDDO (Q)  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (Q)  
IDD2 (Q)  
0.6  
0.2  
1.0  
0.6  
mA  
mA  
DC to 1 MHz logic signal freq.  
DC to 1 MHz logic signal freq.  
10 Mbps (BR and CR Grades Only)  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (10)  
IDD2 (10)  
2.2  
0.7  
3.4  
1.1  
mA  
mA  
5 MHz logic signal freq.  
5 MHz logic signal freq.  
25 Mbps (CR Grade Only)  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (25)  
IDD2 (25)  
5.2  
1.5  
7.7  
2.0  
mA  
mA  
12.5 MHz logic signal freq.  
12.5 MHz logic signal freq.  
ADuM1201, Total Supply Current, Two Channels1  
DC to 2 Mbps  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (Q)  
IDD2 (Q)  
0.4  
0.4  
0.8  
0.8  
mA  
mA  
DC to 1 MHz logic signal freq.  
DC to 1 MHz logic signal freq.  
10 Mbps (BR and CR Grades Only)  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (10)  
IDD2 (10)  
1.5  
1.5  
2.2  
2.2  
mA  
mA  
5 MHz logic signal freq.  
5 MHz logic signal freq.  
25 Mbps (CR Grade Only)  
VDD1 Supply Current  
VDD2 Supply Current  
IDD1 (25)  
IDD2 (25)  
3.4  
3.4  
4.8  
4.8  
mA  
mA  
12.5 MHz logic signal freq.  
12.5 MHz logic signal freq.  
For All Models  
Input Currents  
IIA, IIB  
VIH  
VIL  
−10  
0.7 VDD1, VDD2  
0.01 10  
0.3 VDD1, VDD2  
µA  
V
0 ≤ VIA, VIB, ≤ VDD1 or VDD2  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
VOAH  
VDD1  
VDD2 − 0.1  
VDD1  
,
3.0  
2.8  
0.0  
V
V
IOx = −20 µA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
VOBH  
,
V
DD2 − 0.5  
Logic Low Output Voltages  
VOAL  
VOBL  
0.1  
V
V
V
IOx = 20 µA, VIx = VIxL  
IOx = 400 µA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
0.04 0.1  
0.2  
0.4  
SWITCHING SPECIFICATIONS  
ADuM120xAR  
Minimum Pulse Width2  
Maximum Data Rate3  
PW  
1000  
ns  
Mbps  
ns  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
1
Propagation Delay4  
tPHL, tPLH 50  
PWD  
tPSK  
tPSKCD/OD  
tR/tF  
150  
40  
100  
50  
4
Pulse-Width Distortion, |tPLH − tPHL  
|
Propagation Delay Skew5  
Channel-to-Channel Matching6  
ns  
ns  
Output Rise/Fall Time (10% to 90%)  
10  
Rev. B | Page 5 of 20  
 
ADuM1200/ADuM1201  
Parameter  
Symbol Min  
Typ Max  
Unit  
Test Conditions  
ADuM120xBR  
Minimum Pulse Width2  
Maximum Data Rate3  
Propagation Delay4  
Pulse-Width Distortion, |tPLH −tPHL  
Change Versus Temperature  
Propagation Delay Skew5  
PW  
100  
ns  
Mbps  
ns  
ns  
ps/°C  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
10  
tPHL, tPLH 20  
PWD  
60  
3
4
|
5
tPSK  
tPSKCD  
22  
3
Channel-to-Channel Matching,  
Codirectional Channels6  
ns  
Channel-to-Channel Matching,  
tPSKOD  
tR/tF  
22  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Opposing Directional Channels6  
Output Rise/Fall Time (10% to 90%)  
ADuM120xCR  
3.0  
Minimum Pulse Width2  
PW  
20  
50  
40  
ns  
Mbps  
ns  
ns  
ps/°C  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Maximum Data Rate3  
25  
tPHL, tPLH 20  
PWD  
Propagation Delay4  
55  
3
4
Pulse-Width Distortion, |tPLH − tPHL  
Change Versus Temperature  
Propagation Delay Skew5  
Channel-to-Channel Matching,  
Codirectional Channels6  
|
5
tPSK  
tPSKCD  
16  
3
ns  
Channel-to-Channel Matching,  
tPSKOD  
tR/tF  
16  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Opposing Directional Channels6  
Output Rise/Fall Time (10% to 90%)  
For All Models  
3.0  
Common Mode Transient Immunity  
at Logic High Output7  
Common Mode Transient Immunity  
at Logic Low Output7  
|CMH|  
|CML|  
25  
25  
35  
35  
kV/µs  
kV/µs  
VIx = VDD1, VDD2, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, VCM = 1000 V,  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.1  
0.10  
0.03  
Mbps  
mA/Mbps  
mA/Mbps  
Input Dynamic Supply Current, per Channel8  
IDDI (D)  
Output Dynamic Supply Current, per Channel8 IDDO (D)  
1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load  
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See  
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11  
for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.  
2 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.  
3 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.  
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is  
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.  
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output  
load within the recommended operating conditions.  
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of  
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with  
inputs on opposing sides of the isolation barrier.  
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate  
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient  
magnitude is the range over which the common mode is slewed.  
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for  
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply  
current for a given data rate.  
Rev. B | Page 6 of 20  
 
 
 
 
ADuM1200/ADuM1201  
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION  
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤  
VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the entire recommended operating range, unless otherwise noted.  
All typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V.  
Table 3.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
DC SPECIFICATIONS  
Input Supply Current, per Channel, Quiescent IDDI (Q)  
5 V/3 V Operation  
3 V/5 V Operation  
Output Supply Current, per Channel, Quiescent IDDO (Q)  
5 V/3 V Operation  
mA  
mA  
mA  
mA  
mA  
mA  
0.50  
0.26  
0.6  
0.35  
0.11  
0.19  
0.20  
0.25  
3 V/5 V Operation  
ADuM1200, Total Supply Current, Two Channels1  
DC to 2 Mbps  
VDD1 Supply Current  
5 V/3 V Operation  
3 V/5 V Operation  
IDD1 (Q)  
1.1  
0.6  
1.4  
1.0  
mA  
mA  
DCto1MHzlogicsignalfreq.  
DCto1MHzlogicsignalfreq.  
VDD2 Supply Current  
5 V/3 V Operation  
3 V/5 V Operation  
IDD2 (Q)  
0.2  
0.5  
0.6  
0.8  
mA  
mA  
DCto1MHzlogicsignalfreq.  
DCto1MHzlogicsignalfreq.  
10 Mbps (BR and CR Grades Only)  
VDD1 Supply Current  
5 V/3 V Operation  
IDD1 (10)  
4.3  
2.2  
5.5  
3.4  
mA  
mA  
5 MHz logic signal freq.  
5 MHz logic signal freq.  
3 V/5 V Operation  
VDD2 Supply Current  
5 V/3 V Operation  
3 V/5 V Operation  
IDD2 (10)  
0.7  
1.3  
1.1  
2.0  
mA  
mA  
5 MHz logic signal freq.  
5 MHz logic signal freq.  
25 Mbps (CR Grade Only)  
VDD1 Supply Current  
5 V/3 V Operation  
IDD1 (25)  
10  
5.2  
13  
7.7  
mA  
mA  
12.5 MHz logic signal freq.  
12.5 MHz logic signal freq.  
3 V/5 V Operation  
VDD2 Supply Current  
5 V/3 V Operation  
3 V/5 V Operation  
IDD2 (25)  
1.5  
2.8  
2.0  
3.4  
mA  
mA  
12.5 MHz logic signal freq.  
12.5 MHz logic signal freq.  
ADuM1201, Total Supply Current, Two Channels1  
DC to 2 Mbps  
VDD1 Supply Current  
5 V/3 V Operation  
3 V/5 V Operation  
IDD1 (Q)  
0.8  
0.4  
1.1  
0.8  
mA  
mA  
DCto1MHzlogicsignalfreq.  
DCto1MHzlogicsignalfreq.  
VDD2 Supply Current  
5 V/3 V Operation  
3 V/5 V Operation  
IDD2 (Q)  
0.4  
0.8  
0.8  
1.1  
mA  
mA  
DCto1MHzlogicsignalfreq.  
DCto1MHzlogicsignalfreq.  
10 Mbps (BR and CR Grades Only)  
VDD1 Supply Current  
5 V/3 V Operation  
IDD1 (10)  
2.8  
1.5  
3.5  
2.2  
mA  
mA  
5 MHz logic signal freq.  
5 MHz logic signal freq.  
3 V/5 V Operation  
VDD2 Supply Current  
5 V/3 V Operation  
3 V/5 V Operation  
IDD2 (10)  
1.5  
2.8  
2.2  
3.5  
mA  
mA  
5 MHz logic signal freq.  
5 MHz logic signal freq.  
Rev. B | Page 7 of 20  
 
ADuM1200/ADuM1201  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
25 Mbps (CR Grade Only)  
VDD1 Supply Current  
5 V/3 V Operation  
IDD1 (25)  
6.3  
3.4  
8.0  
4.8  
mA  
mA  
12.5 MHz logic signal freq.  
12.5 MHz logic signal freq.  
3 V/5 V Operation  
VDD2 Supply Current  
5 V/3 V Operation  
3 V/5 V Operation  
IDD2 (25)  
3.4  
6.3  
4.8  
8.0  
mA  
mA  
12.5 MHz logic signal freq.  
12.5 MHz logic signal freq.  
For All Models  
Input Currents  
IIA, IIB  
VIH  
VIL  
−10  
0.7 VDD1, VDD2  
0.01  
10  
µA  
V
V
V
V
0 ≤ VIA, VIB ≤ VDD1 or VDD2  
Logic High Input Threshold  
Logic Low Input Threshold  
5 V/3 V Operation  
3 V/5 V Operation  
Logic High Output Voltages  
0.3 VDD1, VDD2  
0.8  
0.4  
VOAH  
VOBH  
,
VDD1  
VDD2 − 0.1  
VDD1  
DD2 − 0.5  
,
VDD1  
,
V
IOx = −20 µA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
VDD2  
,
VDD1  
,
V
V
VDD2 − 0.2  
Logic Low Output Voltages  
VOAL, VOBL  
0.0  
0.04  
0.2  
0.1  
0.1  
0.4  
V
V
V
IOx = 20 µA, VIx = VIxL  
IOx = 400 µA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
SWITCHING SPECIFICATIONS  
ADuM120xAR  
Minimum Pulse Width2  
Maximum Data Rate3  
PW  
1000  
ns  
Mbps  
ns  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
1
50  
Propagation Delay4  
tPHL, tPLH  
PWD  
tPSK  
tPSKCD/OD  
tR/tF  
150  
40  
50  
4
Pulse-Width Distortion, |tPLH − tPHL  
Propagation Delay Skew5  
Channel-to-Channel Matching6  
Output Rise/Fall Time (10% to 90%)  
ADuM120xBR  
|
50  
ns  
ns  
10  
Minimum Pulse Width2  
Maximum Data Rate3  
PW  
100  
ns  
Mbps  
ns  
ns  
ps/°C  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
10  
15  
Propagation Delay4  
tPHL, tPLH  
PWD  
55  
3
4
Pulse-Width Distortion, |tPLH − tPHL  
Change Versus Temperature  
Propagation Delay Skew5  
Channel-to-Channel Matching,  
Codirectional Channels6  
|
5
tPSK  
tPSKCD  
22  
3
ns  
Channel-to-Channel Matching,  
tPSKOD  
tR/tf  
22  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Opposing Directional Channels6  
Output Rise/Fall Time (10% to 90%)  
5 V/3 V Operation  
3.0  
2.5  
ns  
ns  
3 V/5 V Operation  
Rev. B | Page 8 of 20  
ADuM1200/ADuM1201  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
ADuM120xCR  
Minimum Pulse Width2  
PW  
20  
50  
40  
ns  
Mbps  
ns  
ns  
ps/°C  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Maximum Data Rate3  
25  
20  
Propagation Delay4  
tPHL, tPLH  
PWD  
50  
3
4
Pulse-Width Distortion, |tPLH – tPHL  
Change Versus Temperature  
Propagation Delay Skew5  
Channel-to-Channel Matching,  
Codirectional Channels6  
|
5
tPSK  
tPSKCD  
15  
3
ns  
Channel-to-Channel Matching,  
tPSKOD  
tR/tf  
15  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Opposing Directional Channels6  
Output Rise/Fall Time (10% to 90%)  
5 V/3 V Operation  
3.0  
2.5  
ns  
ns  
3 V/5 V Operation  
For All Models  
Common-Mode Transient Immunity  
at Logic High Output7  
Common-Mode Transient Immunity  
at Logic Low Output7  
|CMH|  
|CML|  
fr  
25  
25  
35  
35  
kV/µs  
kV/µs  
VIx = VDD1, VDD2, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, VCM = 1000 V,  
transient magnitude = 800 V  
Refresh Rate  
5 V/3 V Operation  
3 V/5 V Operation  
1.2  
1.1  
Mbps  
Mbps  
Input Dynamic Supply Current, per Channel8 IDDI (D)  
5 V/3 V Operation  
3 V/5 V Operation  
Output Dynamic Supply Current, per Channel8 IDDI (D)  
0.19  
0.10  
mA/Mbps  
mA/Mbps  
5 V/3 V Operation  
3 V/5 V Operation  
0.03  
0.05  
mA/Mbps  
mA/Mbps  
1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load  
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See  
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11  
for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.  
2 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.  
3 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.  
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is  
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.  
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output  
load within the recommended operating conditions.  
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of  
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with  
inputs on opposing sides of the isolation barrier.  
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate  
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient  
magnitude is the range over which the common mode is slewed.  
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for  
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply  
current for a given data rate.  
Rev. B | Page 9 of 20  
 
 
 
 
ADuM1200/ADuM1201  
PACKAGE CHARACTERISTICS  
Table 4.  
Parameter  
Symbol  
RI-O  
CI-O  
Min  
Typ  
1012  
1.0  
Max  
Unit  
pF  
Test Conditions  
Resistance (Input-Output)1  
Capacitance (Input-Output)1  
Input Capacitance  
f = 1 MHz  
CI  
4.0  
pF  
IC Junction-to-Case Thermal Resistance, Side 1  
θJCI  
46  
°C/W  
Thermocouple located at center of  
package underside  
IC Junction-to-Case Thermal Resistance, Side 2  
θJCO  
41  
°C/W  
1 The device is considered a 2-terminal device; Pins 1, 2, 3, and 4 are shorted together, and Pins 5, 6, 7, and 8 are shorted together.  
REGULATORY INFORMATION  
The ADuM1200/ADuM1201 have been approved by the following organizations:  
Table 5.  
UL  
CSA  
VDE  
Recognized under 1577 Component  
Recognition Program1  
Approved under CSA Component  
Acceptance Notice #5A  
Certified according to  
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-012  
2500 V rms isolation voltage  
Basic insulation, 560 V peak  
Complies with DIN EN 60747-5-2 (VDE 0884  
Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12;  
EN 60950: 2000, Reinforced insulation, 560 V peak  
File 2471900-4880-0001  
File E214100  
File 205078  
1 In accordance with UL1577, each ADuM120x is proof-tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA).  
2 In accordance with DIN EN 60747-5-2, each ADuM120x is proof-tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection  
limit = 5 pC).  
INSULATION AND SAFETY-RELATED SPECIFICATIONS  
Table 6.  
Parameter  
Symbol Value  
Unit  
V rms  
mm  
Conditions  
Rated Dielectric Insulation Voltage  
Minimum External Air Gap (Clearance)  
2500  
1 minute duration  
Measured from input terminals to output terminals, shortest  
distance through air  
L(I01)  
4.90 min  
Minimum External Tracking (Creepage) L(I02)  
4.01 min  
0.017 min  
>175  
mm  
mm  
V
Measured from input terminals to output terminals, shortest  
distance path along body  
Insulation distance through insulation  
Minimum Internal Gap (Internal  
Clearance)  
Tracking Resistance (Comparative  
Tracking Index)  
CTI  
DIN IEC 112/VDE 0303 Part 1  
Isolation Group  
IIIa  
Material Group (DIN VDE 0110, 1/89, Table 1)  
Rev. B | Page 10 of 20  
 
 
 
 
ADuM1200/ADuM1201  
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS  
Table 7.  
Description  
Symbol Characteristic Unit  
Installation Classification per DIN VDE 0110  
For Rated Mains Voltage ≤ 150 V rms  
For Rated Mains Voltage ≤ 300 V rms  
For Rated Mains Voltage ≤ 400 V rms  
Climatic Classification  
Pollution Degree (DIN VDE 0110, Table 1)  
Maximum Working Insulation Voltage  
Input to Output Test Voltage, Method b1  
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC  
Input to Output Test Voltage, Method a  
After Environmental Tests Subgroup 1  
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC  
After Input and/or Safety Test Subgroup 2/3  
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC  
Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec)  
I−IV  
I−III  
I−II  
40/105/21  
2
VIORM  
VPR  
560  
1050  
V peak  
V peak  
VPR  
896  
672  
V peak  
V peak  
VTR  
4000  
Safety-Limiting Values (maximum value allowed in the event of a failure; also see the thermal  
derating curve, Figure 3)  
Case Temperature  
Side 1 Current  
Side 2 Current  
TS  
IS1  
IS2  
RS  
150  
160  
170  
>109  
°C  
mA  
mA  
Insulation Resistance at TS, VIO = 500 V  
Note that the “*” marking on the package denotes DIN EN 60747-5-2 approval for a 560 V peak working voltage.  
This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.  
200  
RECOMMENDED OPERATING CONDITIONS  
180  
160  
Table 8.  
Parameter  
140  
Symbol  
Min Max Unit  
SIDE #2  
SIDE #1  
120  
100  
80  
60  
40  
20  
0
Operating Temperature  
Supply Voltages1  
Input Signal Rise and Fall Times  
TA  
−40 +105 °C  
VDD1, VDD2 2.7  
5.5  
1.0  
V
ms  
1 All voltages are relative to their respective ground. See the DC Correctness and  
Magnetic Field Immunity section for information on immunity to external  
magnetic fields.  
0
50  
100  
CASE TEMPERATURE (°C)  
150  
200  
Figure 3. Thermal Derating Curve, Dependence of Safety-  
Limiting Values on Case Temperature, per DIN EN 60747-5-2  
Rev. B | Page 11 of 20  
 
 
 
ADuM1200/ADuM1201  
ABSOLUTE MAXIMUM RATINGS  
Ambient temperature = 25°C, unless otherwise noted.  
Table 9.  
Parameter  
Symbol  
Min  
−55  
−40  
−0.5  
−0.5  
−0.5  
−35  
−100  
Max  
Unit  
°C  
°C  
V
V
Storage Temperature  
Ambient Operating Temperature  
Supply Voltages1  
Input Voltage,1, 2  
Output Voltage1, 2  
Average Output Current, per Pin3  
Common-Mode Transients4  
TST  
TA  
VDD1, VDD2  
VIA, VIB  
VOA, VOB  
IO  
150  
105  
7.0  
VDDI + 0.5  
VDDO + 0.5  
35  
V
mA  
kV/µs  
+100  
1 All voltages are relative to their respective ground.  
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively.  
3 See Figure 3 for maximum rated current values for various temperatures.  
4 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or  
permanent damage.  
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;  
Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is  
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.  
ESD CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on  
the human body and test equipment and can discharge without detection. Although this product features  
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy  
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance  
degradation or loss of functionality.  
Table 10. ADuM1200 Truth Table (Positive Logic)  
VIA Input VIB Input VDD1 State  
VDD2 State  
Powered  
Powered  
Powered  
Powered  
VOA Output  
VOB Output  
Notes  
H
L
H
L
H
L
L
H
X
Powered  
Powered  
Powered  
Powered  
H
L
H
L
H
L
L
H
H
X
Unpowered Powered  
H
Outputs return to the input state within 1 µs  
of VDDI power restoration.  
X
X
Powered Unpowered  
Indeterminate  
Indeterminate  
Outputs return to the input state within 1 µs  
of VDDO power restoration.  
Table 11. ADuM1201 Truth Table (Positive Logic)  
VIA Input VIB Input VDD1 State  
VDD2 State  
Powered  
Powered  
Powered  
Powered  
VOA Output  
VOB Output  
Notes  
H
L
H
L
H
L
L
H
X
Powered  
Powered  
Powered  
Powered  
H
L
H
L
H
L
L
H
H
X
Unpowered Powered  
Indeterminate  
Outputs return to the input state within 1 µs  
of VDD1 power restoration.  
X
X
Powered Unpowered  
H
Indeterminate  
Outputs return to the input state within 1 µs  
of VDDO power restoration.  
Rev. B | Page 12 of 20  
 
 
 
 
 
 
ADuM1200/ADuM1201  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
V
1
2
3
4
8
7
6
5
V
V
V
V
1
2
3
4
8
7
6
5
V
V
V
DD1  
DD2  
DD1  
DD2  
ADuM1200  
TOP VIEW  
(Not to Scale)  
ADuM1201  
TOP VIEW  
(Not to Scale)  
V
V
OA  
IA  
OA  
IA  
V
V
IB  
OB  
IB  
GND  
OB  
GND  
GND  
GND  
2
1
2
1
Figure 4. ADuM1200 Pin Configuration  
Figure 5. ADuM1201 Pin Configuration  
Table 12. ADuM1200 Pin Function Descriptions  
Table 13. ADuM1201 Pin Function Descriptions  
Pin  
No.  
Pin  
No.  
Mnemonic Function  
Mnemonic Function  
1
VDD1  
Supply Voltage for Isolator Side 1,  
1
VDD1  
Supply Voltage for Isolator Side 1,  
2.7 V to 5.5 V.  
Logic Input A.  
Logic Input B.  
Ground 1. Ground reference for isolator  
Side 1.  
2.7 V to 5.5 V.  
Logic Output A.  
Logic Input B.  
Ground 1. Ground reference for Isolator  
Side 1.  
2
3
4
VIA  
VIB  
GND1  
2
3
4
VOA  
VIB  
GND1  
5
GND2  
Ground 2. Ground reference for isolator  
Side 2.  
5
GND2  
Ground 2. Ground reference for Isolator  
Side 2.  
6
7
8
VOB  
VOA  
VDD2  
Logic Output B.  
Logic Output A.  
Supply Voltage for Isolator Side 2,  
2.7 V to 5.5 V.  
6
7
8
VOB  
VIA  
VDD2  
Logic Output B.  
Logic Input A.  
Supply Voltage for Isolator Side 2,  
2.7 V to 5.5 V.  
Rev. B | Page 13 of 20  
 
ADuM1200/ADuM1201  
TYPICAL PERFORMANCE CHARACTERISTICS  
10  
20  
15  
10  
5
8
6
4
5V  
3V  
5V  
3V  
2
0
0
0
10  
20  
30  
0
10  
20  
30  
DATA RATE (Mbps)  
DATA RATE (Mbps)  
Figure 6. Typical Input Supply Current per Channel vs. Data Rate  
for 5 V and 3 V Operation  
Figure 9. Typical ADuM1200 VDD1 Supply Current vs. Data Rate  
for 5 V and 3 V Operation  
4
4
3
2
3
2
5V  
5V  
3V  
1
1
0
3V  
0
0
10  
20  
30  
0
10  
20  
30  
DATA RATE (Mbps)  
DATA RATE (Mbps)  
Figure 7. Typical Output Supply Current per Channel vs. Data Rate  
for 5 V and 3 V Operation (No Output Load)  
Figure 10. Typical ADuM1200 VDD2 Supply Current vs. Data Rate  
for 5 V and 3 V Operation  
4
10  
8
3
6
5V  
5V  
2
4
3V  
3V  
1
2
0
0
0
10  
20  
30  
0
10  
20  
30  
DATA RATE (Mbps)  
DATA RATE (Mbps)  
Figure 8. Typical Output Supply Current per Channel vs. Data Rate  
for 5 V and 3 V Operation (15 pF Output Load)  
Figure 11. Typical ADuM1201 VDD1 or VDD2 Supply Current vs. Data Rate  
for 5 V and 3 V Operation  
Rev. B | Page 14 of 20  
 
 
 
 
 
 
ADuM1200/ADuM1201  
APPLICATION INFORMATION  
The pulses at the transformer output have an amplitude greater  
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,  
therefore establishing a 0.5 V margin in which induced voltages  
can be tolerated. The voltage induced across the receiving coil is  
given by  
PC BOARD LAYOUT  
The ADuM120x digital isolators require no external interface  
circuitry for the logic interfaces. Power supply bypassing is  
strongly recommended at the input and output supply pins. The  
capacitor value should be between 0.01 µF and 0.1 µF. The total  
lead length between both ends of the capacitor and the input  
power supply pin should not exceed 20 mm.  
V = (/dt) Πr2 ;n =1,2,...N  
n
where:  
PROPAGATION DELAY-RELATED PARAMETERS  
Propagation delay is a parameter that describes the time it takes  
a logic signal to propagate through a component. The  
propagation delay to a logic low output may differ from the  
propagation delay to a logic high.  
β is the magnetic flux density (gauss).  
N is the number of turns in the receiving coil.  
rn is the radius of the nth turn in the receiving coil (cm).  
Given the geometry of the receiving coil in the ADuM120x and  
an imposed requirement that the induced voltage be at most  
50% of the 0.5 V margin at the decoder, a maximum allowable  
magnetic field is calculated, as shown in Figure 13.  
INPUT (V  
)
50%  
IX  
tPLH  
tPHL  
OUTPUT (V  
)
50%  
OX  
100  
Figure 12. Propagation Delay Parameters  
10  
Pulse-width distortion is the maximum difference between  
these two propagation delay values and is an indication of how  
accurately the input signals timing is preserved.  
1
Channel-to-channel matching refers to the maximum amount  
that the propagation delay differs between channels within a  
single ADuM120x component.  
0.1  
0.01  
0.001  
Propagation delay skew refers to the maximum amount that the  
propagation delay differs between multiple ADuM120x  
components operating under the same conditions.  
1k  
10k  
100k  
1M  
10M  
100M  
MAGNETIC FIELD FREQUENCY (Hz)  
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY  
Figure 13. Maximum Allowable External Magnetic Flux Density  
Positive and negative logic transitions at the isolator input cause  
narrow (~1 ns) pulses to be sent to the decoder via the  
transformer. The decoder is bistable and is therefore either set  
or reset by the pulses, indicating input logic transitions. In the  
absence of logic transitions of more than 2 µs at the input, a  
periodic set of refresh pulses indicative of the correct input state  
are sent to ensure dc correctness at the output. If the decoder  
receives no internal pulses for more than about 5 µs, the input  
side is assumed to be unpowered or nonfunctional, in which  
case the isolator output is forced to a default state (see Table 8)  
by the watchdog timer circuit.  
For example, at a magnetic field frequency of 1 MHz, the  
maximum allowable magnetic field of 0.2 kgauss induces a  
voltage of 0.25 V at the receiving coil. This is about 50% of the  
sensing threshold and does not cause a faulty output transition.  
Similarly, if such an event were to occur during a transmitted  
pulse (and had the worst-case polarity), it would reduce the  
received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V  
sensing threshold of the decoder.  
The preceding magnetic flux density values correspond to  
specific current magnitudes at given distances away from the  
ADuM120x transformers. Figure 14 expresses these allowable  
current magnitudes as a function of frequency for selected  
distances. As seen, the ADuM120x are extremely immune and  
can be affected only by extremely large currents operated at  
high frequency and very close to the component. For the 1 MHz  
example, one would have to place a 0.5 kA current 5 mm away  
from the ADuM120x to affect the component’s operation.  
The ADuM120x are extremely immune to external magnetic  
fields. The limitation on the ADuM120xs magnetic field  
immunity is set by the condition in which induced voltage in  
the transformer’s receiving coil is sufficiently large to either  
falsely set or reset the decoder. The following analysis defines  
the conditions under which this may occur. The 3 V operating  
condition of the ADuM120x is examined because it represents  
the most susceptible mode of operation.  
Rev. B | Page 15 of 20  
 
 
ADuM1200/ADuM1201  
1000  
POWER CONSUMPTION  
DISTANCE = 1m  
The supply current at a given channel of the ADuM120x  
isolator is a function of the supply voltage, the channel’s data  
rate, and the channels output load.  
100  
10  
For each input channel, the supply current is given by  
DISTANCE = 100mm  
1
I
DDI = IDDI (Q)  
IDDI = IDDI (D) × (2f – fr) + IDDI (Q)  
for each output channel, the supply current is given by  
IDDO = IDDO (Q) f ≤ 0.5fr  
f ≤ 0.5fr  
DISTANCE = 5mm  
f > 0.5fr  
0.1  
0.01  
1k  
10k  
100k  
1M  
10M  
100M  
MAGNETIC FIELD FREQUENCY (Hz)  
I
DDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f – fr) + IDDO (Q)  
f > 0.5fr  
Figure 14. Maximum Allowable Current for Various  
Current-to-ADuM120x Spacings  
where:  
Note that at combinations of strong magnetic fields and high  
frequencies, any loops formed by printed circuit board traces  
could induce sufficiently large error voltages to trigger the  
threshold of succeeding circuitry. Care should be taken in the  
layout of such traces to avoid this possibility.  
I
DDI (D), IDDO (D) are the input and output dynamic supply currents  
per channel (mA/Mbps).  
CL is the output load capacitance (pF).  
V
DDO is the output supply voltage (V).  
f is the input logic signal frequency (MHz, half of the input data  
rate, NRZ signaling).  
fr is the input stage refresh rate (Mbps).  
I
DDI (Q), IDDO (Q) are the specified input and output quiescent  
supply currents (mA).  
To calculate the total IDD1 and IDD2 supply current, the supply  
currents for each input and output channel corresponding to  
IDD1 and IDD2 are calculated and totaled. Figure 6 and Figure 7  
provide per-channel supply currents as a function of data rate  
for an unloaded output condition. Figure 8 provides per-  
channel supply current as a function of data rate for a 15 pF  
output condition. Figure 9 through Figure 11 provide total IDD1  
and IDD2 supply current as a function of data rate for  
ADuM1200 and ADuM1201 channel configurations.  
Rev. B | Page 16 of 20  
 
ADuM1200/ADuM1201  
OUTLINE DIMENSIONS  
5.00 (0.1968)  
4.80 (0.1890)  
8
1
5
4
6.20 (0.2440)  
5.80 (0.2284)  
4.00 (0.1574)  
3.80 (0.1497)  
1.27 (0.0500)  
BSC  
0.50 (0.0196)  
0.25 (0.0099)  
× 45°  
1.75 (0.0688)  
1.35 (0.0532)  
0.25 (0.0098)  
0.10 (0.0040)  
8°  
0.51 (0.0201)  
0.31 (0.0122)  
0° 1.27 (0.0500)  
COPLANARITY  
0.10  
0.25 (0.0098)  
0.17 (0.0067)  
SEATING  
PLANE  
0.40 (0.0157)  
COMPLIANT TO JEDEC STANDARDS MS-012AA  
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN  
Figure 15. 8-Lead Standard Small Outline Package [SOIC]  
Narrow Body (R-8)  
Dimensions shown in millimeters (inches)  
ORDERING GUIDE  
Maximum  
Number  
of Inputs,  
VDD1 Side  
Number  
of Inputs,  
VDD2 Side  
Maximum  
Data Rate  
(Mbps)  
Maximum  
Propagation  
Delay, 5 V (ns)  
Pulse-Width  
Distortion  
(ns)  
Temperature  
Range (°C)  
Package  
Option1  
Model  
ADuM1200AR  
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
100  
100  
100  
100  
50  
50  
50  
50  
40  
40  
40  
40  
3
3
3
3
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
R-8  
ADuM1200AR-RL7  
ADuM1200ARZ2  
ADuM1200ARZ-RL72  
ADuM1200BR  
ADuM1200BR-RL7  
ADuM1200BRZ2  
ADuM1200BRZ-RL72  
ADuM1200CR  
ADuM1200CR-RL7  
ADuM1200CRZ2  
ADuM1200CRZ-RL72  
ADuM1201AR  
ADuM1201AR-RL7  
ADuM1201ARZ2  
ADuM1201ARZ-RL72  
ADuM1201BR  
ADuM1201BR-RL7  
ADuM1201BRZ2  
ADuM1201BRZ-RL72  
ADuM1201CR  
ADuM1201CR-RL7  
ADuM1201CRZ2  
ADuM1201CRZ-RL72  
10  
10  
10  
10  
25  
25  
25  
25  
1
45  
45  
45  
45  
3
3
3
3
100  
100  
100  
100  
50  
50  
50  
50  
40  
40  
40  
40  
3
3
3
3
1
1
1
10  
10  
10  
10  
25  
25  
25  
25  
45  
45  
45  
45  
3
3
3
3
1 R-8 = 8-lead narrow body SOIC.  
2 Z = Pb-free part.  
Rev. B | Page 17 of 20  
 
 
 
 
ADuM1200/ADuM1201  
NOTES  
Rev. B | Page 18 of 20  
ADuM1200/ADuM1201  
NOTES  
Rev. B | Page 19 of 20  
ADuM1200/ADuM1201  
NOTES  
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D04642–0–9/04(B)  
Rev. B | Page 20 of 20  
配单直通车
ADUM1200BRZ产品参数
型号:ADUM1200BRZ
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
零件包装代码:SOIC
包装说明:SOP,
针数:8
Reach Compliance Code:unknown
风险等级:5.05
Is Samacsys:N
模拟集成电路 - 其他类型:ANALOG CIRCUIT
JESD-30 代码:R-PDSO-G8
JESD-609代码:e3
长度:4.9 mm
湿度敏感等级:1
功能数量:1
端子数量:8
最高工作温度:105 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260
座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:MATTE TIN
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:40
宽度:3.9 mm
Base Number Matches:1
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