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Quad-Channel Digital Isolators

ADuM1400/ADuM1401/ADuM1402

GENERAL DESCRIPTION

FEATURES

Low power operation

5 V operation

The ADuM140x are 4-channel digital isolators based on Analog

Devices’ iCoupler® technology. Combining high speed CMOS

and monolithic air core transformer technology, these isolation

components provide outstanding performance characteristics

superior to alternatives such as optocoupler devices.

1.0 mA per channel max @ 0 Mbps to 2 Mbps

3.5 mA per channel max @ 10 Mbps

31 mA per channel max @ 90 Mbps

3 V operation

0.7 mA per channel max @ 0 Mbps to 2 Mbps

2.1 mA per channel max @ 10 Mbps

20 mA per channel max @ 90 Mbps

Bidirectional communication

By avoiding the use of LEDs and photodiodes, iCoupler devices

remove the design difficulties commonly associated with

optocouplers. The typical optocoupler concerns regarding

uncertain current transfer ratios, nonlinear transfer functions,

and temperature and lifetime effects are eliminated with the

simple iCoupler digital interfaces and stable performance

characteristics. The need for external drivers and other discretes

is eliminated with these iCoupler products. Furthermore,

iCoupler devices consumes one-tenth to one-sixth the power of

optocouplers at comparable signal data rates.

3 V/5 V level translation

High temperature operation: 105°C

High data rate: dc to 90 Mbps (NRZ)

Precise timing characteristics

2 ns max pulse-width distortion

2 ns max channel-to-channel matching

High common-mode transient immunity: >25 kV/μs

Output enable function

The ADuM140x isolators provide four independent isolation

channels in a variety of channel configurations and data rates

(see the Ordering Guide). All models operate with the supply

voltage on either side ranging from 2.7 V to 5.5 V, providing

compatibility with lower voltage systems as well as enabling a

voltage translation functionality across the isolation barrier. In

addition, the ADuM140x provides low pulse-width distortion

(<2 ns for CRW grade) and tight channel-to-channel matching

(<2 ns for CRW grade). Unlike other optocoupler alternatives,

the ADuM140x isolators have a patented refresh feature that

ensures dc correctness in the absence of input logic transitions

and during power-up/power-down conditions.

Wide body 16-lead SOIC package, Pb-free models available

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA component acceptance notice #5A

VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000

V_IORM= 560 V peak

APPLICATIONS

General-purpose multichannel isolation

SPI® interface/data converter isolation

RS-232/RS-422/RS-485 transceiver

Industrial field bus isolation

FUNCTIONAL BLOCK DIAGRAMS

1

2

3

4

5

6

7

8

16

1

2

3

16

15

14

1

2

3

4

5

6

7

8

16

V

DD1

DD2

DD1

DD2

DD1

DD2

GND

15 GND

GND

2

GND

15 GND

2

1

IA

IB

IC

2

1

IA

IB

IC

1

IA

IB

ENCODE

DECODE

14

ENCODE

DECODE

ENCODE

DECODE

ENCODE

14

13

12

11

10

9

V

OA

OB

OC

OD

E2

OA

OB

OC

ID

OA

OB

IC

13

12

11

10

9

4

5

6

7

8

13

12

11

10

9

V

OC

OD

V

OD

ID

NC

GND

ID

V

E1

E2

E1

E2

GND

2

GND

2

GND

2

1

Figure 1. ADuM1400 Functional Block Diagram

Figure 2. ADuM1401 Functional Block Diagram

Figure 3. ADuM1402 Functional Block Diagram

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

ADuM1400/ADuM1401/ADuM1402

TABLE OF CONTENTS

Specifications..................................................................................... 3

ESD Caution................................................................................ 14

Pin Configurations and Pin Function Descriptions.................. 15

Typical Performance Characteristics ........................................... 17

Application Information................................................................ 19

PC Board Layout ........................................................................ 19

Propagation Delay-Related Parameters................................... 19

DC Correctness and Magnetic Field Immunity........................... 19

Power Consumption .................................................................. 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3 V Operation................................ 6

Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V

Operation....................................................................................... 8

Package Characteristics ............................................................. 12

Regulatory Information............................................................. 12

Insulation and Safety-Related Specifications.......................... 12

DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics ............................................................................ 13

Recommended Operating Conditions .................................... 13

Absolute Maximum Ratings.......................................................... 14

REVISION HISTORY

6/04—Data Sheet Changed from Rev. A to Rev. B.

Changes to Format .............................................................Universal

Changes to Features.......................................................................... 1

Changes to Electrical Characteristics—5 V Operation ............... 3

Changes to Electrical Characteristics—3 V Operation ............... 5

Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation ............................................................................ 7

Changes to DIN EN 60747-5-2 (VDE 0884 Part 2)

Insulation Characteristics Title..................................................... 11

Changes to the Ordering Guide.................................................... 19

5/04—Data Sheet Changed from Rev. 0 to Rev. A.

Updated Format..................................................................Universal

Changes to the Features................................................................... 1

Changes to Table 7 and Table 8..................................................... 14

Changes to Table 9.......................................................................... 15

Changes to the DC Correctness and Magnetic Field Immunity

Section.............................................................................................. 20

Changes to the Power Consumption Section ............................. 21

Changes to the Ordering Guide.................................................... 22

9/03—Revision 0: Initial Version.

Rev. B | Page 2 of 24

ADuM1400/ADuM1401/ADuM1402

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION¹

4.5 V ≤ V_DD1≤ 5.5 V, 4.5 V ≤ V_DD2≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless other-

wise noted; all typical specifications are at T_A= 25°C, V_DD1= V_DD2= 5 V.

Table 1.

Parameter

Symbol

Min

Typ Max Unit

Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent

Output Supply Current, per Channel, Quiescent

ADuM1400, Total Supply Current, Four Channels²

DC to 2 Mbps

I_{DDI (Q)}

I_{DDO (Q)}

0.50 0.53 mA

0.19 0.21 mA

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

2.2

0.9

2.8

1.4

mA

DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (10)}

I_{DD2 (10)}

8.6

2.6

10.6 mA

3.5 mA

5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (90)}

I_{DD2 (90)}

76

21

100 mA

45 MHz logic signal freq.

25

mA

ADuM1401, Total Supply Current, Four Channels²

DC to 2 Mbps

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

1.8

1.2

2.4

1.8

mA

DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (10)}

I_{DD2 (10)}

7.1

4.1

9.0

5.0

mA

5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (90)}

I_{DD2 (90)}

62

35

82

43

mA

45 MHz logic signal freq.

ADuM1402, Total Supply Current, Four Channels²

DC to 2 Mbps

V_DD1or V_DD2Supply Current

10 Mbps (BRW and CRW Grades Only)

V_DD1or V_DD2Supply Current

90 Mbps (CRW Grade Only)

V_DD1or V_DD2Supply Current

For All Models

I_{DD1 (Q)}, I_{DD2 (Q)}

I_{DD1 (10)}, I_{DD2 (10)}

I_{DD1 (90)}, I_{DD2 (90)}

1.5

5.6

49

2.1

7.0

62

mA

DC to 1 MHz logic signal freq.

5 MHz logic signal freq.

45 MHz logic signal freq.

Input Currents

I_IA, I_IB, I_IC,

I_ID, I_E1, I_E2

V_IH, V_EH

V_IL, V_EL

V_OAH, V_OBH

V_OCH, V_ODH

–10

2.0

+0.01 +10 µA

V

0 ≤ V_IA, V_IB, V_IC, V_ID≤ V_DD1or V_DD2

0 ≤ V_E1, V_E2≤ V_DD1or V_DD2

,

Logic High Input Threshold

Logic Low Input Threshold

Logic High Output Voltages

0.8

V

,

V_DD1

V_DD2– 0.1

V_DD1

V_DD2– 0.4

,

5.0

4.8

0.0

0.04 0.1

0.2 0.4

I_Ox= –20 µA, V_Ix= V_IxH

I_Ox= –4 mA, V_Ix= V_IxH

,

V

Logic Low Output Voltages

V_OAL, V_OBL

,

0.1

V

I_Ox= 20 µA, V_Ix= V_IxL

I_Ox= 400 µA, V_Ix= V_IxL

I_Ox= 4 mA, V_Ix= V_IxL

V

_OCL, V_ODL

Rev. B | Page 3 of 24

ADuM1400/ADuM1401/ADuM1402

Parameter

Symbol

Min

Typ Max Unit

Test Conditions

SWITCHING SPECIFICATIONS

ADuM140xARW

Minimum Pulse Width³

Maximum Data Rate⁴

PW

1000 ns

Mbps

100 ns

C_L= 15 pF, CMOS signal levels

1

50

Propagation Delay⁵

t_PHL, t_PLH

PWD

t_PSK

65

5

Pulse-Width Distortion, |t_PLH– t_PHL

Propagation Delay Skew⁶

Channel-to-Channel Matching⁷

ADuM140xBRW

|

40

50

ns

t_PSKCD/OD

Minimum Pulse Width³

PW

100 ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

Maximum Data Rate⁴

10

20

Propagation Delay⁵

t_PHL, t_PLH

PWD

32

5

50

3

5

Pulse-Width Distortion, |t_PLH– t_PHL

Change vs. Temperature

Propagation Delay Skew⁶

Channel-to-Channel Matching,

Codirectional Channels⁷

|

ns

ps/°C

ns

t_PSK

t_PSKCD

15

3

Channel-to-Channel Matching,

t_PSKOD

6

ns

C_L= 15 pF, CMOS signal levels

Opposing-Directional Channels⁷

ADuM140xCRW

Minimum Pulse Width³

Maximum Data Rate⁴

PW

8.3

120

27

0.5

3

11.1 ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

90

18

Propagation Delay⁵

t_PHL, t_PLH

PWD

32

2

5

Pulse-Width Distortion, |t_PLH– t_PHL

Change vs. Temperature

Propagation Delay Skew⁶

Channel-to-Channel Matching,

Codirectional Channels⁷

|

ns

ps/°C

ns

t_PSK

t_PSKCD

10

2

Channel-to-Channel Matching,

t_PSKOD

5

ns

C_L= 15 pF, CMOS signal levels

Opposing-Directional Channels⁷

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance)

Output Enable Propagation Delay

(High Impedance to High/Low)

Output Rise/Fall Time (10% to 90%)

Common-Mode Transient Immunity

at Logic High Output⁸

t

_PHZ, t_PLH

6

8

ns

C_L= 15 pF, CMOS signal levels

V_Ix= V_DD1/V_DD2, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

t_PZH, t_PZL

t_R/t_F

|CM_H|

2.5

35

ns

kV/µs

25

Common-Mode Transient Immunity

at Logic Low Output⁸

|CM_L|

35

kV/µs

transient magnitude = 800 V

Refresh Rate

f_r

1.2

Mbps

Input Dynamic Supply Current, per Channel⁹

Output Dynamic Supply Current, per Channel⁹

I_{DDI (D)}

I_{DDO (D)}

0.19

0.05

mA/Mbps

See Notes on next page.

Rev. B | Page 4 of 24

ADuM1400/ADuM1401/ADuM1402

¹All voltages are relative to their respective ground.

²The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on

Page 20. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11

through Figure 14 for total I_DD1and I_DD2supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

³The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

⁴The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

⁵t_PHLpropagation delay is measured from the 50% level of the falling edge of the V_Ixsignal to the 50% level of the falling edge of the V_Oxsignal. t_PLHpropagation delay is

measured from the 50% level of the rising edge of the V_Ixsignal to the 50% level of the rising edge of the V_Oxsignal.

⁶t_PSKis the magnitude of the worst-case difference in t_PHLor t_PLHthat is measured between units at the same operating temperature, supply voltages, and output load

within the recommended operating conditions.

⁷Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with

inputs on opposing sides of the isolation barrier.

⁸CM_His the maximum common-mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V_DD2. CM_Lis the maximum common-mode voltage slew rate

that can be sustained while maintaining V_O< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

magnitude is the range over which the common mode is slewed.

⁹Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 20 for guidance on calculating the per-channel sup-

ply current for a given data rate.

Rev. B | Page 5 of 24

ADuM1400/ADuM1401/ADuM1402

ELECTRICAL CHARACTERISTICS—3 V OPERATION¹

2.7 V ≤ V_DD1≤ 3.6 V, 2.7 V ≤ V_DD2≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless other-

wise noted; all typical specifications are at T_A= 25°C, V_DD1= V_DD2= 3.0 V.

Table 2.

Parameter

Symbol

Min

Typ Max Unit

Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent

Output Supply Current, per Channel, Quiescent

ADuM1400, Total Supply Current, Four Channels²

DC to 2 Mbps

I_{DDI (Q)}

I_{DDO (Q)}

0.26 0.31 mA

0.11 0.14 mA

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

1.2

0.5

1.9 mA

0.9 mA

DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (10)}

I_{DD2 (10)}

4.5

1.4

6.5 mA

2.0 mA

5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (90)}

I_{DD2 (90)}

42

11

65

15

mA

45 MHz logic signal freq.

ADuM1401, Total Supply Current, Four Channels²

DC to 2 Mbps

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

1.0

0.7

1.6 mA

1.2 mA

DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (10)}

I_{DD2 (10)}

3.7

2.2

5.4 mA

3.0 mA

5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (90)}

I_{DD2 (90)}

34

19

52

27

mA

45 MHz logic signal freq.

ADuM1402, Total Supply Current, Four Channels²

DC to 2 Mbps

V_DD1or V_DD2Supply Current

10 Mbps (BRW and CRW Grades Only)

V_DD1or V_DD2Supply Current

90 Mbps (CRW Grade Only)

V_DD1or V_DD2Supply Current

For All Models

I_{DD1 (Q)}, I_{DD2 (Q)}

I_{DD1 (10)}, I_{DD2 (10)}

I_{DD1 (90)}, I_{DD2 (90)}

0.9

3.0

27

1.5 mA

4.2 mA

DC to 1 MHz logic signal freq.

5 MHz logic signal freq.

39

mA

45 MHz logic signal freq.

Input Currents

I_IA, I_IB, I_IC,

I_ID, I_E1, I_E2

V_IH, V_EH

V_IL, V_EL

V_OAH, V_OBH

V_OCH, V_ODH

–10

1.6

+0.01 +10 µA

V

0 ≤ V_IA, V_IB, V_IC, V_ID≤ V_DD1or

V

_DD2, 0 ≤ V_E1,V_E2≤ V_DD1or V_DD2

Logic High Input Threshold

Logic Low Input Threshold

Logic High Output Voltages

0.4

V

,

V_DD1, V_DD2– 0.1 3.0

V_DD1, V_DD2– 0.4 2.8

0.0

I_Ox= –20 µA, V_Ix= V_IxH

I_Ox= –4 mA, V_Ix= V_IxH

I_Ox= 20 µA, V_Ix= V_IxL

I_Ox= 400 µA, V_Ix= V_IxL

I_Ox= 4 mA, V_Ix= V_IxL

Logic Low Output Voltages

V_OAL, V_OBL

V_OCL, V_ODL

,

0.1

0.04 0.1

0.2

0.4

SWITCHING SPECIFICATIONS

ADuM140xARW

Minimum Pulse Width³

Maximum Data Rate⁴

PW

1000 ns

Mbps

100 ns

C_L= 15 pF, CMOS signal levels

1

50

Propagation Delay⁵

t_PHL, t_PLH

PWD

t_PSK

75

5

Pulse-Width Distortion, |t_PLH– t_PHL

|

40

50

ns

Propagation Delay Skew⁶

Channel-to-Channel Matching⁷

t_PSKCD/OD

Rev. B | Page 6 of 24

ADuM1400/ADuM1401/ADuM1402

Parameter

Symbol

Min

Typ Max Unit

Test Conditions

ADuM140xBRW

Minimum Pulse Width³

PW

100 ns

Mbps

C_L= 15 pF, CMOS signal levels

Maximum Data Rate⁴

10

20

Propagation Delay⁵

t_PHL, t_PLH

PWD

38

5

50

3

ns

5

Pulse-Width Distortion, |t_PLH– t_PHL

Change vs. Temperature

Propagation Delay Skew⁶

Channel-to-Channel Matching,

Codirectional Channels⁷

|

ps/°C

ns

t_PSK

t_PSKCD

22

3

Channel-to-Channel Matching,

t_PSKOD

6

ns

C_L= 15 pF, CMOS signal levels

Opposing-Directional Channels⁷

ADuM140xCRW

Minimum Pulse Width³

Maximum Data Rate⁴

PW

8.3

120

34

0.5

3

11.1 ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

90

20

Propagation Delay⁵

t_PHL, t_PLH

PWD

45

2

5

Pulse-Width Distortion, |t_PLH– t_PHL

Change vs. Temperature

Propagation Delay Skew⁶

Channel-to-Channel Matching,

Codirectional Channels⁷

|

ns

ps/°C

ns

t_PSK

t_PSKCD

16

2

Channel-to-Channel Matching,

t_PSKOD

5

ns

C_L= 15 pF, CMOS signal levels

Opposing-Directional Channels⁷

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance)

Output Enable Propagation Delay

(High Impedance to High/Low)

t_PHZ, t_PLH

t_PZH, t_PZL

6

8

ns

C_L= 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%)

t_R/t_F

3

ns

Common-Mode Transient Immunity

at Logic High Output⁸

Common-Mode Transient Immunity

at Logic Low Output⁸

|CM_H|

25

35

kV/µs

V_Ix= V_DD1/V_DD2, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

|CM_L|

35

kV/µs

transient magnitude = 800 V

Refresh Rate

f_r

1.1

Mbps

Input Dynamic Supply Current, per Channel⁹I_{DDI (D)}

Output Dynamic Supply Current, per Channel⁹I_{DDO (D)}

0.10

0.03