ADUM1411ARWZ全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

Quad-Channel Digital Isolators

ADuM1410/ADuM1411/ADuM1412

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

Low power operation

5 V operation

1

2

3

16

15

14

V

DD1

DD2

ADuM1410

GND

1

2

1.3 mA per channel max @ 0 Mbps to 2 Mbps

4.0 mA per channel max @ 10 Mbps

3 V operation

0.8 mA per channel max @ 0 Mbps to 2 Mbps

1.8 mA per channel max @ 10 Mbps

Bidirectional communication

3 V/5 V level translation

High temperature operation: 105°C

Up to 10 Mbps data rate (NRZ)

Programmable default output state

High common-mode transient immunity: >25 kV/μs

16-lead, Pb-free, SOIC wide body package

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA component acceptance notice #5A

VDE certificate of conformity (pending)

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000

V

ENCODE

DECODE

V

IA

OA

OB

OC

OD

4

5

13

12

IB

V

IC

6

7

8

11

10

9

V

ID

DISABLE

GND

CTRL

GND

1

2

Figure 1. ADuM1410 Functional Block Diagram

1

2

3

16

15

14

V

DD1

DD2

ADuM1411

GND

1

2

V

ENCODE

DECODE

ENCODE

V

IA

OA

OB

OC

ID

4

5

13

12

IB

V

IC

6

7

8

11

10

9

V

OD

CTRL

GND

CTRL

2

1

GND

1

2

Figure 2. ADuM1411 Functional Block Diagram

V

_IORM= 560 V peak

1

2

3

16

15

14

V

DD2

DD1

ADuM1412

APPLICATIONS

GND

V

GND

1

2

ENCODE

DECODE

ENCODE

V

General-purpose multichannel isolation

SPI® interface/data converter isolation

RS-232/RS-422/RS-485 transceiver

Industrial field bus isolation

IA

IB

OA

V

4

5

13

12

V

OB

V

OC

IC

ID

6

7

8

11

10

9

OD

CTRL

GND

CTRL

2

1

GND

1

2

Figure 3. ADuM1412 Functional Block Diagram

GENERAL DESCRIPTION

Furthermore, iCoupler devices consume one-tenth to one-sixth

The ADuM141x¹are four-channel digital isolators based on

Analog Devices, Inc. iCoupler® technology. Combining high

speed CMOS and monolithic air core transformer technologies,

these isolation components provide outstanding performance

characteristics superior to alternatives such as optocoupler devices.

the power of optocouplers at comparable signal data rates.

The ADuM141x isolators provide four independent isolation

channels in a variety of channel configurations and data rates

(see the Ordering Guide) up to 10 Mbps. All models operate

with the supply voltage on either side ranging from 2.7 V to 5.5 V,

providing compatibility with lower voltage systems as well as

enabling voltage translation functionality across the isolation

barrier. All products also have a default output control pin. This

allows the user to define the logic state the outputs are to adopt

in the absence of the input power. Unlike other optocoupler

alternatives, the ADuM141x isolators have a patented refresh

feature that ensures dc correctness in the absence of input logic

transitions and during power-up/power-down conditions.

By avoiding the use of LEDs and photodiodes, iCoupler devices

remove the design difficulties commonly associated with opto-

couplers. The usual concerns that arise with optocouplers, such

as uncertain current transfer ratios, nonlinear transfer functions,

and temperature and lifetime effects are eliminated with the

simple iCoupler digital interfaces and stable performance charac-

teristics. The need for external drivers and other discrete

components is eliminated with these iCoupler products.

¹Protected by U.S. Patents 5,952,849, 6,873,065 and 7,075,329. Other patents pending.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADuM1410/ADuM1411/ADuM1412

TABLE OF CONTENTS

Features .............................................................................................. 1

Absolute Maximum Ratings ......................................................... 12

Recommended Operating Conditions .................................... 12

ESD Caution................................................................................ 12

Pin Configurations and Function Descriptions......................... 13

Typical Performance Characteristics ........................................... 16

Application Information................................................................ 18

PC Board Layout ........................................................................ 18

Propagation Delay-Related Parameters................................... 18

DC Correctness and Magnetic Field Immunity........................... 18

Power Consumption .................................................................. 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3 V Operation................................ 5

Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V

Operation....................................................................................... 7

Package Characteristics ............................................................. 10

Regulatory Information............................................................. 10

Insulation and Safety-Related Specifications.......................... 10

DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics ............................................................................ 11

REVISION HISTORY

10/06—Rev. D to Rev. E

Added ADuM1411 and ADuM1412................................Universal

Deleted ADuM1310 ...........................................................Universal

Changes to Features.......................................................................... 1

Changes to Specifications Section.................................................. 3

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide .......................................................... 20

3/06—Rev. C to Rev. D

Added Note 1 and Changes to Figure 2......................................... 1

Changes to Absolute Maximum Ratings..................................... 11

11/05—Rev. SpB to Rev. C: Initial Version

Rev. E | Page 2 of 20

ADuM1410/ADuM1411/ADuM1412

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

4.5 V ≤ V_DD1≤ 5.5 V, 4.5 V ≤ V_DD2≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless

otherwise noted; all typical specifications are at T_A= 25°C, V_DD1= V_DD2= 5 V. ¹

Table 1.

Parameter

Symbol

Min

Typ

Max Unit

Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel,

Quiescent

Output Supply Current per Channel,

Quiescent

I_{DDI (Q)}

0.50

0.38

0.73

0.53

mA

I_{DDO (Q)}

ADuM1410, Total Supply Current, Four

Channels²

DC to 2 Mbps

V_DD1Supply Current

V_DD2Supply Current

10 Mbps (BRW Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

2.4

1.2

3.2

1.6

mA

DC to 1 MHz logic signal frequency

I_{DD1 (10)}

I_{DD2 (10)}

8.8

2.8

12

4.0

mA

5 MHz logic signal frequency

ADuM1411, Total Supply Current, Four

Channels²

DC to 2 Mbps

V_DD1Supply Current

V_DD2Supply Current

10 Mbps (BRW Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

2.2

1.8

2.8

2.4

mA

DC to 1 MHz logic signal frequency

I_{DD1 (10)}

I_{DD2 (10)}

5.4

3.8

7.6

5.3

mA

5 MHz logic signal frequency

ADuM1412, Total Supply Current, Four

Channels²

DC to 2 Mbps

V_DD1or V_DD2Supply Current

10 Mbps (BRW Grade Only)

V_DD1or V_DD2Supply Current

For All Models

I_{DD1 (Q)}, I_{DD2 (Q)}

I_{DD1 (10)}, I_{DD2 (10)}

I_IA, I_IB, I_IC,

2.0

4.6

2.6

6.5

mA

μA

DC to 1 MHz logic signal frequency

5 MHz logic signal frequency

Input Currents

−10

2.0

+0.01 +10

0 ≤ V_IA,V_IB, V_IC,V_ID≤ V_DD1or V_DD2,

I_ID, I_CTRL1

,

0 ≤ V_CTRL1,V_CTRL2≤ V_DD1or V_DD2

,

I

_CTRL2, I_DISABLE

V_DISABLE≤ V_DD1

Logic High Input Threshold

Logic Low Input Threshold

Logic High Output Voltages

V_IH

V_IL

V

0.8

V_OAH, V_OBH

,

V_DD1, V_DD2− 0.1 5.0

V_DD1, V_DD2− 0.4 4.8

0.0

I_Ox= −20 μA, V_Ix= V_IxH

I_Ox= −4 mA, V_Ix= V_IxH

I_Ox= 20 μA, V_Ix= V_IxL

I_Ox= 400 μA, V_Ix= V_IxL

I_Ox= 4 mA, V_Ix= V_IxL

V_OCH, V_ODH

Logic Low Output Voltages

V_OAL, V_OBL

,

0.1

0.4

V_OCL, V_ODL

0.04

0.2

SWITCHING SPECIFICATIONS

ADuM1411ARW and ADuM1412ARW

Minimum Pulse Width³

PW

1000 ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

Maximum Data Rate⁴

1

20

Propagation Delay⁵

Pulse Width Distortion, |t_PLH− t_PHL

Propagation Delay Skew⁶

t_PHL, t_PLH

PWD

t_PSK

65

100

40

5

|

ns

50

Channel-to-Channel Matching⁷

t_PSKCD/OD

Rev. E | Page 3 of 20

ADuM1410/ADuM1411/ADuM1412

Parameter

Symbol

Min

Typ

Max Unit

Test Conditions

ADuM141xBRW

Minimum Pulse Width³

PW

100

ns

Mbps

ns

ps/°C

ns

C_L= 15 pF, CMOS signal levels

Maximum Data Rate⁴

10

20

Propagation Delay⁵

t_PHL, t_PLH

PWD

30

5

50

5

Pulse Width Distortion, |t_PLH− t_PHL

Change vs. Temperature

Propagation Delay Skew⁶

Channel-to-Channel Matching,

Codirectional Channels⁷

|

t_PSK

t_PSKCD

30

5

ns

Channel-to-Channel Matching,

t_PSKOD

6

ns

C_L= 15 pF, CMOS signal levels

Opposing-Directional Channels⁷

For All Models

Output Rise/Fall Time (10% to 90%)

Common-Mode Transient Immunity |CM_H|

at Logic High Output⁸

Common-Mode Transient Immunity |CM_L|

at Logic Low Output⁸

t_R/t_F

2.5

35

ns

kV/μs

C_L= 15 pF, CMOS signal levels

V_Ix= V_DD1/V_DD2, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

transient magnitude = 800 V

25

35

kV/μs

Refresh Rate

Input Enable Time⁹

Input Disable Time⁹

Input Dynamic Supply Current per

Channel¹⁰

Output Dynamic Supply Current per I_{DDO (D)}

Channel¹⁰

f_r

1.2

Mbps

μs

t_ENABLE

t_DISABLE

I_{DDI (D)}

2.0

5.0

V_IA, V_IB, V_IC, V_ID, = 0 or V_DD1

0.12

0.04

mA/Mbps

¹All voltages are relative to their respective ground.

²The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.

See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through

Figure 15 for total V_DD1and V_DD2supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.

³The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

⁴The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

⁵t_PHLpropagation delay is measured from the 50% level of the falling edge of the V_Ixsignal to the 50% level of the falling edge of the V_Oxsignal. t_PLHpropagation delay is

measured from the 50% level of the rising edge of the V_Ixsignal to the 50% level of the rising edge of the V_Oxsignal.

⁶t_PSKis the magnitude of the worst-case difference in t_PHLor t_PLHthat is measured between units at the same operating temperature, supply voltages, and output load

within the recommended operating conditions.

⁷Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with

inputs on opposing sides of the isolation barrier.

⁸CM_His the maximum common-mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V_DD2. CM_Lis the maximum common-mode voltage slew rate

that can be sustained while maintaining V_O< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

magnitude is the range over which the common mode is slewed.

⁹Input enable time is the duration from when V_DISABLEis set low until the output states are guaranteed to match the input states in the absence of any input data logic

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the

much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V_DISABLEis set high

until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (See Table 10).

¹⁰Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current

for a given data rate.

Rev. E | Page 4 of 20

ADuM1410/ADuM1411/ADuM1412

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V_DD1≤ 3.6 V, 2.7 V ≤ V_DD2≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless

otherwise noted; all typical specifications are at T_A= 25°C, V_DD1= V_DD2= 3.0 V. ¹

Table 2.

Parameter

Symbol

Min

Typ Max Unit

Test Conditions

DC SPECIFICATIONS

Input Supply Current per Channel, Quiescent

I_{DDI (Q)}

0.25 0.38 mA

0.19 0.33 mA

Output Supply Current per Channel, Quiescent I_{DDO (Q)}

ADuM1410, Total Supply Current, Four Channels²

DC to 2 Mbps

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

1.2

0.8

1.6 mA

1.0 mA

DC to 1 MHz logic signal frequency

10 Mbps (BRW Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (10)}

I_{DD2 (10)}

4.5

1.4

6.5 mA

1.8 mA

5 MHz logic signal frequency

ADuM1411, Total Supply Current, Four Channels²

DC to 2 Mbps

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

1.0

0.9

1.9 mA

1.7 mA

DC to 1 MHz logic signal frequency

10 Mbps (BRW Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (10)}

I_{DD2 (10)}

3.1

2.1

4.5 mA

3.0 mA

5 MHz logic signal frequency

ADuM1412, Total Supply Current, Four Channels²

DC to 2 Mbps

V_DD1or V_DD2Supply Current

10 Mbps (BRW Grade Only)

V_DD1or V_DD2Supply Current

For All Models

I_{DD1 (Q)}, I_{DD2 (Q)}

I_{DD1 (10)}, I_{DD2 (10)}

I_IA, I_IB, I_IC,

1.0

2.6

1.8 mA

3.8 mA

DC to 1 MHz logic signal frequency

5 MHz logic signal frequency

Input Currents

−10

1.6

+0.01 +10 μA

0 ≤ V_IA,V_IB, V_IC,V_ID≤ V_DD1or V_DD2,

I_ID, I_CTRL1

,

0 ≤ V_CTRL1,V_CTRL2≤ V_DD1or V_DD2

,

I_CTRL2, I_DISABLE

V_IH

V_IL

V_DISABLE≤ V_DD1

Logic High Input Threshold

Logic Low Input Threshold

Logic High Output Voltages

V

0.4

0.1

V

V_OAH, V_OBH

,

V_DD1, V_DD2− 0.1 3.0

V_DD1, V_DD2− 0.4 2.8

0.0

I_Ox= −20 μA, V_Ix= V_IxH

I_Ox= −4 mA, V_Ix= V_IxH

I_Ox= 20 μA, V_Ix= V_IxL

I_Ox= 400 μA, V_Ix= V_IxL

I_Ox= 4 mA, V_Ix= V_IxL

V_OCH, V_ODH

Logic Low Output Voltages

V_OAL, V_OBL

,

V_OCL, V_ODL

0.04 0.1

0.2

0.4

SWITCHING SPECIFICATIONS

ADuM1411ARW and ADuM1412ARW

Minimum Pulse Width³

PW

1000 ns

Mbps

100 ns

C_L= 15 pF, CMOS signal levels

Maximum Data Rate⁴

1

20

Propagation Delay⁵

t_PHL, t_PLH

PWD

t_PSK

75

5

Pulse Width Distortion, |t_PLH− t_PHL

Propagation Delay Skew⁶

Channel-to-Channel Matching⁷

ADuM141xBRW

|

40

50

ns

t_PSKCD/OD

Minimum Pulse Width³

Maximum Data Rate⁴

Propagation Delay⁵

PW

100 ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

10

20

t_PHL, t_PLH

40

60

Rev. E | Page 5 of 20

ADuM1410/ADuM1411/ADuM1412

Parameter

Pulse Width Distortion, |t_PLH− t_PHL

Symbol

Min

Typ Max Unit

Test Conditions

5

|

PWD

5

ns

C_L= 15 pF, CMOS signal levels

Change vs. Temperature

Propagation Delay Skew⁶

Channel-to-Channel Matching,

Codirectional Channels⁷

5

ps/°C

ns

t_PSK

t_PSKCD

30

5

Channel-to-Channel Matching,

t_PSKOD

6

ns

C_L= 15 pF, CMOS signal levels

Opposing-Directional Channels⁷

For All Models

Output Rise/Fall Time (10% to 90%)

Common-Mode Transient Immunity

at Logic High Output⁸

Common-Mode Transient Immunity

at Logic Low Output⁸

t_R/t_F

|CM_H|

2.5

35

ns

kV/μs

C_L= 15 pF, CMOS signal levels

V_Ix= V_DD1/V_DD2, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

transient magnitude = 800 V

25

|CM_L|

35

kV/μs

Refresh Rate

Input Enable Time⁹

Input Disable Time⁹

1.1

2.0

5.0

Mbps

μs

t_ENABLE

t_DISABLE

V_IA, V_IB, V_IC, V_ID= 0 or V_DD1

Input Dynamic Supply Current per Channel¹⁰I_{DDI (D)}

Output Dynamic Supply Current per Channel¹⁰I_{DDO (D)}

0.07

0.02