ADUM3201ARZ-RL7中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

Dual-Channel, Digital Isolators,

Enhanced System-Level ESD Reliability

ADuM3200/ADuM3201

GENERAL DESCRIPTION

FEATURES

Enhanced system-level ESD performance per IEC 61000-4-x

Narrow body, 8-lead SOIC, Pb-free package

Low power operation

The ADuM320x¹are dual-channel, digital isolators based on

Analog Devices’ iCoupler® technology. Combining high speed

CMOS and monolithic transformer technology, these isolation

components provide outstanding performance characteristics

superior to alternatives such as optocoupler devices.

5 V operation

1.6 mA per channel maximum @ 0 Mbps to 2 Mbps

3.7 mA per channel maximum @ 10 Mbps

7.5 mA per channel maximum @ 25 Mbps

3 V operation

1.4 mA per channel maximum @ 0 Mbps to 2 Mbps

2.4 mA per channel maximum @ 10 Mbps

4.6 mA per channel maximum @ 25 Mbps

Bidirectional communication

By avoiding the use of LEDs and photodiodes, iCoupler devices

remove the design difficulties commonly associated with

optocouplers. The typical optocoupler concerns regarding

uncertain current transfer ratios, nonlinear transfer functions,

and temperature and lifetime effects are eliminated with the

simple iCoupler digital interfaces and stable performance

characteristics. The need for external drivers and other discrete

components is eliminated with these iCoupler products.

Furthermore, iCoupler devices consume one-tenth to one-sixth

the power of optocouplers at comparable signal data rates.

3 V/5 V level translation

High temperature operation: 105°C

High data rate: dc to 25 Mbps (NRZ)

Precise timing characteristics

3 ns maximum pulse-width distortion

3 ns maximum channel-to-channel matching

High common-mode transient immunity: >25 kV/μs

Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A

VDE Certificate of Conformity

The ADuM320x isolators provide two independent isolation

channels in a variety of channel configurations and data rates

(see the Ordering Guide). Both parts operate with the supply

voltage on either side ranging from 2.7 V to 5.5 V, providing

compatibility with lower voltage systems as well as enabling a

voltage translation functionality across the isolation barrier. The

ADuM320x isolators have a patented refresh feature that ensures

dc correctness in the absence of input logic transitions and

during power-up/power-down conditions.

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000

V_IORM= 560 V peak

In comparison to the ADuM120x isolators, the ADuM320x

isolators contain various circuit and layout changes to provide

increased capability relative to system-level IEC 61000-4-x

testing (ESD, burst, surge). The precise capability in these tests

for either the ADuM120x or ADuM320x products is strongly

determined by the design and layout of the user’s board or

module. For more information, see Application Note AN-793,

ESD/Latch-Up Considerations with iCoupler Isolation Products.

APPLICATIONS

Size-critical multichannel isolation

SPI® interface/data converter isolation

RS-232/RS-422/RS-485 transceiver isolation

Digital field bus isolation

¹Protected by U.S. Patents 5,952,849; 6,873,065; and other pending patents.

FUNCTIONAL BLOCK DIAGRAMS

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

V

DD1

DD2

OA

OB

DD1

DD2

IA

ENCODE

DECODE

ENCODE

DECODE

V

OA

IA

V

IB

OB

GND

2

1

2

1

Figure 1. ADuM3200 Functional Block Diagram

Figure 2. ADuM3201 Functional Block Diagram

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADuM3200/ADuM3201

TABLE OF CONTENTS

Features .............................................................................................. 1

Recommended Operating Conditions .................................... 11

Absolute Maximum Ratings ......................................................... 12

ESD Caution................................................................................ 12

Pin Configurations and Function Descriptions......................... 13

Typical Performance Characteristics ........................................... 14

Application Information................................................................ 15

PC Board Layout ........................................................................ 15

System-Level ESD Considerations and Enhancements ........ 15

Propagation Delay-Related Parameters................................... 15

DC Correctness and Magnetic Field Immunity........................... 15

Power Consumption .................................................................. 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Operation................................ 3

Electrical Characteristics—3 V Operation................................ 5

Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V

Operation....................................................................................... 7

Package Characteristics ............................................................. 10

Regulatory Information............................................................. 10

Insulation and Safety-Related Specifications.......................... 10

DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics ............................................................................ 11

REVISION HISTORY

7/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADuM3200/ADuM3201

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All voltages are relative to their respective ground. 4.5 V ≤ V_DD1≤ 5.5 V, 4.5 V ≤ V_DD2≤ 5.5 V. All minimum/maximum specifications

apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 5 V.

Table 1.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent

Output Supply Current, per Channel, Quiescent

ADuM3200, Total Supply Current, Two Channels¹

DC to 2 Mbps

I_{DDI (Q)}

I_{DDO (Q)}

0.4

0.5

0.8

0.6

mA

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

1.3

1.0

1.7

1.6

mA

DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (10)}

I_{DD2 (10)}

3.5

1.7

4.6

2.8

mA

5 MHz logic signal freq.

25 Mbps (CR Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (25)}

I_{DD2 (25)}

7.7

3.1

10.0

3.9

mA

12.5 MHz logic signal freq.

ADuM3201, Total Supply Current, Two Channels¹

DC to 2 Mbps

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

1.1

1.3

1.5

1.8

mA

DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (10)}

I_{DD2 (10)}

2.6

3.1

3.4

4.0

mA

5 MHz logic signal freq.

25 Mbps (CR Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (25)}

I_{DD2 (25)}

5.3

6.4

6.8

8.3

mA

12.5 MHz logic signal freq.

For All Models

Input Currents

Logic High Input Threshold

I_IA, I_IB

V_IH

−10

0.7 V_DD1

+0.01 +10

μA

V

0 ≤ V_IA, V_IB≤ V_DD1or V_DD2

,

V_DD2

Logic Low Input Threshold

Logic High Output Voltages

V_IL

0.3 V_DD1,

V_DD2

V

V_OAH

V_OBH

V_DD1

V_DD2− 0.1

V_DD1

,

5.0

4.8

I_Ox= −20 μA, V_Ix= V_IxH

I_Ox= −4 mA, V_Ix= V_IxH

,

V

_DD2− 0.5

Logic Low Output Voltages

V_OAL

V_OBL

0.0

0.04

0.2

0.1

0.4

V

I_Ox= 20 μA, V_Ix= V_IxL

I_Ox= 400 μA, V_Ix= V_IxL

I_Ox= 4 mA, V_Ix= V_IxL

SWITCHING SPECIFICATIONS

ADuM320xAR

Minimum Pulse Width²

Maximum Data Rate³

PW

1000

ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

1

20

Propagation Delay⁴

t_PHL, t_PLH

PWD

t_PSK

t_PSKCD/OD

t_R/t_F

150

40

100

50

4

Pulse-Width Distortion, |t_PLH− t_PHL

|

Propagation Delay Skew⁵

Channel-to-Channel Matching⁶

ns

Output Rise/Fall Time (10% to 90%)

10

Rev. 0 | Page 3 of 20

ADuM3200/ADuM3201

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions

ADuM320xBR

Minimum Pulse Width²

Maximum Data Rate³

Propagation Delay⁴

Pulse-Width Distortion, |t_PLH− t_PHL

Change vs. Temperature

Propagation Delay Skew⁵

PW

100

ns

Mbps

ns

ps/°C

ns

C_L= 15 pF, CMOS signal levels

10

20

t_PHL, t_PLH

PWD

50

3

4

|

5

t_PSK

t_PSKCD

15

3

Channel-to-Channel Matching,

Codirectional Channels⁶

ns

Channel-to-Channel Matching,

t_PSKOD

t_R/t_F

15

ns

C_L= 15 pF, CMOS signal levels

Opposing Directional Channels⁶

Output Rise/Fall Time (10% to 90%)

ADuM320xCR

2.5

Minimum Pulse Width²

PW

20

50

40

ns

Mbps

ns

ps/°C

ns

C_L= 15 pF, CMOS signal levels

Maximum Data Rate³

25

20

Propagation Delay⁴

t_PHL, t_PLH

PWD

45

3

4

Pulse-Width Distortion, |t_PLH– t_PHL

Change vs. Temperature

Propagation Delay Skew⁵

Channel-to-Channel Matching,

Codirectional Channels⁶

|

5

t_PSK

t_PSKCD

15

3

ns

Channel-to-Channel Matching,

t_PSKOD

t_R/t_F

15

ns

C_L= 15 pF, CMOS signal levels

Opposing Directional Channels⁶

Output Rise/Fall Time (10% to 90%)

For All Models

2.5

Common-Mode Transient Immunity

at Logic High Output⁷

Common-Mode Transient Immunity

at Logic Low Output⁷

|CM_H|

|CM_L|

25

35

kV/μs

V_Ix= V_DD1, V_DD2, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

transient magnitude = 800 V

Refresh Rate

f_r

1.2

Mbps

Input Dynamic Supply Current, per Channel⁸

Output Dynamic Supply Current, per Channel⁸

I_{DDI (D)}

I_{DDO (D)}

0.19

0.05

mA/Mbps

¹The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See

Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11

for total I_DD1and I_DD2supply currents as a function of data rate for ADuM3200 and ADuM3201 channel configurations.

²The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

³The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

⁴t_PHLpropagation delay is measured from the 50% level of the falling edge of the V_Ixsignal to the 50% level of the falling edge of the V_Oxsignal. t_PLHpropagation delay is

measured from the 50% level of the rising edge of the V_Ixsignal to the 50% level of the rising edge of the V_Oxsignal.

⁵t_PSKis the magnitude of the worst-case difference in t_PHLand/or t_PLHthat is measured between units at the same operating temperature, supply voltages, and output

load within the recommended operating conditions.

⁶Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with

inputs on opposing sides of the isolation barrier.

⁷CM_His the maximum common-mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V_DD2. CM_Lis the maximum common-mode voltage slew rate

that can be sustained while maintaining V_O< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

magnitude is the range over which the common mode is slewed.

⁸Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for

information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply

current for a given data rate.

Rev. 0 | Page 4 of 20

ADuM3200/ADuM3201

ELECTRICAL CHARACTERISTICS—3 V OPERATION

All voltages are relative to their respective ground. 2.7 V ≤ V_DD1≤ 3.6 V, 2.7 V ≤ V_DD2≤ 3.6 V. All minimum/maximum specifications

apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T_A= 25°C,

V_DD1= V_DD2= 3.0 V.

Table 2.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I_{DDI (Q)}

0.3

0.5

mA

Output Supply Current, per Channel, Quiescent

ADuM3200, Total Supply Current, Two Channels¹

DC to 2 Mbps

I_{DDO (Q)}

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

0.8

0.7

1.3

1.0

mA

DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (10)}

I_{DD2 (10)}

2.0

1.1

3.2

1.7

mA

5 MHz logic signal freq.

25 Mbps (CR Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (25)}

I_{DD2 (25)}

4.3

1.8

6.4

2.4

mA

12.5 MHz logic signal freq.

ADuM3201,Total Supply Current,Two Channels¹

DC to 2 Mbps

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (Q)}

I_{DD2 (Q)}

0.7

0.8

1.3

1.6

mA

DC to 1 MHz logic signal freq.

10 Mbps (BR and CR Grades Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (10)}

I_{DD2 (10)}

1.5

1.9

2.1

2.4

mA

5 MHz logic signal freq.

25 Mbps (CR Grade Only)

V_DD1Supply Current

V_DD2Supply Current

I_{DD1 (25)}

I_{DD2 (25)}

3.0

3.6

4.2

5.1

mA

12.5 MHz logic signal freq.

For All Models

Input Currents

Logic High Input Threshold

I_IA, I_IB

V_IH

−10

0.7 V_DD1,

V_DD2

+0.01 +10

μA

V

0 ≤ V_IA, V_IB, ≤ V_DD1or V_DD2

Logic Low Input Threshold

Logic High Output Voltages

V_IL

0.3 V_DD1

V_DD2

,

V

V_OAH

V_OBH

V_DD1

V_DD2− 0.1

V_DD1

V_DD2− 0.5

,

3.0

2.8

I_Ox= −20 μA, V_Ix= V_IxH

I_Ox= −4 mA, V_Ix= V_IxH

,

Logic Low Output Voltages

V_OAL

V_OBL

0.0

0.04

0.2

0.1

0.4

V

I_Ox= 20 μA, V_Ix= V_IxL

I_Ox= 400 μA, V_Ix= V_IxL

I_Ox= 4 mA, V_Ix= V_IxL

SWITCHING SPECIFICATIONS

ADuM320xAR

Minimum Pulse Width²

Maximum Data Rate³

PW

1000

ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

1

Propagation Delay⁴

t_PHL, t_PLH20

PWD

t_PSK

t_PSKCD/OD

t_R/t_F

150

40

100

50

4

Pulse-Width Distortion, |t_PLH− t_PHL

|

Propagation Delay Skew⁵

Channel-to-Channel Matching⁶

ns

Output Rise/Fall Time (10% to 90%)

10

Rev. 0 | Page 5 of 20

ADuM3200/ADuM3201

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions

ADuM320xBR

Minimum Pulse Width²

Maximum Data Rate³

Propagation Delay⁴

Pulse-Width Distortion, |t_PLH−t_PHL

Change vs. Temperature

Propagation Delay Skew⁵

PW

100

ns

Mbps

ns

ps/°C

ns

C_L= 15 pF, CMOS signal levels

10

t_PHL, t_PLH20

PWD

60

3

4

|

5

t_PSK

t_PSKCD

22

3

Channel-to-Channel Matching,

Codirectional Channels⁶

ns

Channel-to-Channel Matching,

t_PSKOD

t_R/t_F

22

ns

C_L= 15 pF, CMOS signal levels

Opposing Directional Channels⁶

Output Rise/Fall Time (10% to 90%)

ADuM320xCR

3.0

Minimum Pulse Width²

PW

20

50

40

ns

Mbps

ns

ps/°C

ns

C_L= 15 pF, CMOS signal levels

Maximum Data Rate³

25

t_PHL, t_PLH20

PWD

Propagation Delay⁴

55

3

4

Pulse-Width Distortion, |t_PLH− t_PHL

Change vs. Temperature

Propagation Delay Skew⁵

Channel-to-Channel Matching,

Codirectional Channels⁶

|

5

t_PSK

t_PSKCD

16

3

ns

Channel-to-Channel Matching,

t_PSKOD

t_R/t_F

16

ns

C_L= 15 pF, CMOS signal levels

Opposing Directional Channels⁶

Output Rise/Fall Time (10% to 90%)

For All Models

3.0

Common Mode Transient Immunity

at Logic High Output⁷

Common Mode Transient Immunity

at Logic Low Output⁷

|CM_H|

|CM_L|

25

35

kV/μs

V_Ix= V_DD1, V_DD2, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

transient magnitude = 800 V

Refresh Rate

f_r

1.1

0.10

0.03

Mbps

mA/Mbps

Input Dynamic Supply Current, per Channel⁸

I_{DDI (D)}

Output Dynamic Supply Current, per Channel⁸I_{DDO (D)}

¹The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See

Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11

for total I_DD1and I_DD2supply currents as a function of data rate for ADuM3200 and ADuM3201 channel configurations.

²The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

³The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

⁴t_PHLpropagation delay is measured from the 50% level of the falling edge of the V_Ixsignal to the 50% level of the falling edge of the V_Oxsignal. t_PLHpropagation delay is

measured from the 50% level of the rising edge of the V_Ixsignal to the 50% level of the rising edge of the V_Oxsignal.

⁵t_PSKis the magnitude of the worst-case difference in t_PHLand/or t_PLHthat is measured between units at the same operating temperature, supply voltages, and output

load within the recommended operating conditions.

⁶Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with

inputs on opposing sides of the isolation barrier.

⁷CM_His the maximum common-mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V_DD2. CM_Lis the maximum common-mode voltage slew rate

that can be sustained while maintaining V_O< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

magnitude is the range over which the common mode is slewed.

⁸Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for

information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply

current for a given data rate.

Rev. 0 | Page 6 of 20

ADuM3200/ADuM3201

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION

All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V_DD1≤ 5.5 V, 2.7 V ≤ V_DD2≤ 3.6 V. 3 V/5 V operation:

2.7 V ≤ V_DD1≤ 3.6 V, 4.5 V ≤ V_DD2≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,

unless otherwise noted. All typical specifications are at T_A= 25°C; V_DD1= 3.0 V, V_DD2= 5.0 V; or V_DD1= 5.0 V, V_DD2= 3.0 V.

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent

5 V/3 V Operation

I_{DDI (Q)}

0.4

0.3

0.8

0.5

mA

3 V/5 V Operation

Output Supply Current, per Channel, Quiescent

5 V/3 V Operation

3 V/5 V Operation

ADuM3200, Total Supply Current, Two Channels¹

I_{DDO (Q)}

0.3

0.5

0.6

mA

DC to 2 Mbps

V_DD1Supply Current

5 V/3 V Operation

3 V/5 V Operation

I_{DD1 (Q)}

1.3

0.8

1.7

1.3

mA

DCto1MHzlogicsignalfreq.

V_DD2Supply Current

5 V/3 V Operation

3 V/5 V Operation

I_{DD2 (Q)}

0.7

1.0

1.6

mA

DCto1MHzlogicsignalfreq.

10 Mbps (BR and CR Grades Only)

V_DD1Supply Current

5 V/3 V Operation

I_{DD1 (10)}

3.5

2.0

4.6

3.2

mA

5 MHz logic signal freq.

3 V/5 V Operation

V_DD2Supply Current

5 V/3 V Operation

3 V/5 V Operation

I_{DD2 (10)}

1.1

1.7

2.8

mA

5 MHz logic signal freq.

25 Mbps (CR Grade Only)

V_DD1Supply Current

5 V/3 V Operation

I_{DD1 (25)}

7.7

4.3

10.0

6.4

mA

12.5 MHz logic signal freq.

3 V/5 V Operation

V_DD2Supply Current

5 V/3 V Operation

3 V/5 V Operation

I_{DD2 (25)}

1.8

3.1

2.4

3.9

mA

12.5 MHz logic signal freq.

ADuM3201, Total Supply Current, Two Channels¹

DC to 2 Mbps

V_DD1Supply Current

5 V/3 V Operation

3 V/5 V Operation

I_{DD1 (Q)}

1.1

0.7

1.5

1.3

mA

DCto1MHzlogicsignalfreq.

V_DD2Supply Current

5 V/3 V Operation

3 V/5 V Operation

I_{DD2 (Q)}

0.8

1.3

1.6

1.8

mA

DCto1MHzlogicsignalfreq.

10 Mbps (BR and CR Grades Only)

V_DD1Supply Current

5 V/3 V Operation

I_{DD1 (10)}

2.6

1.5

3.4

2.1

mA

5 MHz logic signal freq.

3 V/5 V Operation

V_DD2Supply Current

5 V/3 V Operation

3 V/5 V Operation

I_{DD2 (10)}

1.9

3.1

2.4

4.0

mA

5 MHz logic signal freq.

Rev. 0 | Page 7 of 20

ADuM3200/ADuM3201

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

25 Mbps (CR Grade Only)

V_DD1Supply Current

5 V/3 V Operation

3 V/5 V Operation

V_DD2Supply Current

5 V/3 V Operation

3 V/5 V Operation

For All Models

I_{DD1 (25)}

5.3

3.0

6.8

4.2

mA

12.5 MHz logic signal freq.

I_{DD2 (25)}

3.6

6.4

5.1

8.3

mA

12.5 MHz logic signal freq.

Input Currents

Logic High Input Threshold

I_IA, I_IB

V_IH

−10

0.7 V_DD1

+0.01

+10

μA

V

0 ≤ V_IA, V_IB≤ V_DD1or V_DD2

,

V_DD2

Logic Low Input Threshold

V_IL

0.3 V_DD1

,

V

V_DD2

5 V/3 V Operation

3 V/5 V Operation

Logic High Output Voltages

0.8

0.4

V

V_OAH, V_OBHV_DD1

V_DD2− 0.1 V_DD2

V_DD1V_DD1

,

V_DD1

,

I_Ox= −20 μA, V_Ix= V_IxH

I_Ox= −4 mA, V_Ix= V_IxH

,

V

V_DD2− 0.5

V_DD2− 0.2

Logic Low Output Voltages

V_OAL, V_OBL

0.0

0.04

0.2

0.1

0.4

V

I_Ox= 20 μA, V_Ix= V_IxL

I_Ox= 400 μA, V_Ix= V_IxL

I_Ox= 4 mA, V_Ix= V_IxL

SWITCHING SPECIFICATIONS

ADuM320xAR

Minimum Pulse Width²

Maximum Data Rate³

PW

1000

ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

1

15

Propagation Delay⁴

t_PHL, t_PLH

PWD

t_PSK

t_PSKCD/OD

t_R/t_F

150

40

50

4

Pulse-Width Distortion, |t_PLH− t_PHL

Propagation Delay Skew⁵

Channel-to-Channel Matching⁶

Output Rise/Fall Time (10% to 90%)

ADuM320xBR

|

50

ns

10

Minimum Pulse Width²

Maximum Data Rate³

PW

100

ns

Mbps

ns

ps/°C

ns

C_L= 15 pF, CMOS signal levels

10

15

Propagation Delay⁴

t_PHL, t_PLH

PWD

55

3

4

Pulse-Width Distortion, |t_PLH− t_PHL

Change vs. Temperature

Propagation Delay Skew⁵

Channel-to-Channel Matching,

Codirectional Channels⁶

|

5

t_PSK

t_PSKCD

22

3

ns

Channel-to-Channel Matching,

t_PSKOD

t_R/t_f

22

ns

C_L= 15 pF, CMOS signal levels

Opposing Directional Channels⁶

Output Rise/Fall Time (10% to 90%)

5 V/3 V Operation

3.0

2.5

ns

C_L= 15 pF, CMOS signal levels

3 V/5 V Operation

Rev. 0 | Page 8 of 20

ADuM3200/ADuM3201

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

ADuM320xCR

Minimum Pulse Width²

PW

20

50

40

ns

Mbps

ns

ps/°C

ns

C_L= 15 pF, CMOS signal levels

Maximum Data Rate³

25

20

Propagation Delay⁴

t_PHL, t_PLH

PWD

50

3

4

Pulse-Width Distortion, |t_PLH– t_PHL

Change vs. Temperature

Propagation Delay Skew⁵

Channel-to-Channel Matching,

Codirectional Channels⁶

|

5

t_PSK

t_PSKCD

15

3

ns

Channel-to-Channel Matching,

t_PSKOD

t_R/t_f

15

ns

C_L= 15 pF, CMOS signal levels

Opposing Directional Channels⁶

Output Rise/Fall Time (10% to 90%)

5 V/3 V Operation

3.0

2.5

ns

C_L= 15 pF, CMOS signal levels

3 V/5 V Operation

For All Models

Common-Mode Transient Immunity

at Logic High Output⁷

Common-Mode Transient Immunity

at Logic Low Output⁷

|CM_H|

|CM_L|

f_r

25

35

kV/μs

V_Ix= V_DD1, V_DD2, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V_CM= 1000 V,

transient magnitude = 800 V

Refresh Rate

5 V/3 V Operation

3 V/5 V Operation

1.2

1.1

Mbps

Input Dynamic Supply Current,

per Channel⁸

I_{DDI (D)}

5 V/3 V Operation

3 V/5 V Operation

0.19

0.10

mA/Mbps

Output Dynamic Supply Current,