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产品型号ADXL346_1的Datasheet PDF文件预览

3-Axis, ± ± g/± ꢀ g/± ꢁ g/± ꢂ1 g  
Ultralow Power Digital Accelerometer  
ADXL3ꢀ1  
FEATURES  
GENERAL DESCRIPTION  
Ultralow power: as low as 23 μA in measurement mode and  
0.2 μA in standby mode at VS = 2.6 V (typical)  
Power consumption scales automatically with bandwidth  
User-selectable resolution  
The ADXL346 is a small, thin, ultralow power, 3-axis accelerometer  
with high resolution (13-bit) measurement at up to 16 g. Digital  
output data is formatted as 16-bit twos complement and is acces-  
sible through either an SPI (3- or 4-wire) or I2C® digital interface.  
Fixed 10-bit resolution  
The ADXL346 is well suited for mobile device applications. It  
measures the static acceleration of gravity in tilt-sensing appli-  
cations, as well as dynamic acceleration resulting from motion  
or shock. Its high resolution (4 mg/LSB) enables measurement  
of inclination changes of less than 1.0°.  
Full resolution, where resolution increases with g range,  
up to 13-bit resolution at 16 g (maintaining 4 mg/LSB  
scale factor in all g ranges)  
Patent pending, embedded memory management system  
with FIFO technology minimizes host processor load  
Single-tap/double-tap detection  
Several special sensing functions are provided. Activity and  
inactivity sensing detect the presence or lack of motion by  
comparing the acceleration on any axis with user-set thresholds.  
Tap sensing detects single and double taps in any direction. Free-  
fall sensing detects if the device is falling. Orientation detection  
is capable of concurrent four- and six-position sensing and a  
user-selectable interrupt on orientation change for 2D or 3D  
applications. These functions can be mapped individually to  
either of two interrupt output pins. An integrated, patent pending  
memory management system with 32-level first in, first out (FIFO)  
buffer can be used to store data to minimize host processor activity  
and lower overall system power consumption.  
Activity/inactivity monitoring  
Free-fall detection  
Concurrent four- and six-position orientation detection  
Supply and I/O voltage range: 1.7 V to 2.75 V  
SPI (3- and 4-wire) and I2C digital interfaces  
Flexible interrupt modes mappable to either interrupt pin  
Measurement ranges selectable via serial command  
Bandwidth selectable via serial command  
Wide temperature range (−40°C to +85°C)  
10,000 g shock survival  
Pb free/RoHS compliant  
Small and thin: 3 mm × 3 mm × 0.95 mm LGA package  
Low power modes enable intelligent motion-based power  
management with threshold sensing and active acceleration  
measurement at extremely low power dissipation.  
APPLICATIONS  
Handsets  
The ADXL346 is supplied in a small, thin, 3 mm × 3 mm ×  
0.95 mm, 16-lead, plastic package.  
Medical instrumentation  
Gaming and pointing devices  
Industrial instrumentation  
Personal navigation devices  
Hard disk drive (HDD) protection  
FUNCTIONAL BLOCK DIAGRAM  
V
V
DD I/O  
S
ADXL346  
POWER  
MANAGEMENT  
INT1  
INT2  
CONTROL  
AND  
INTERRUPT  
LOGIC  
SENSE  
ELECTRONICS  
ADC  
DIGITAL  
FILTER  
3-AXIS  
SENSOR  
SDA/SDI/SDIO  
32-LEVEL  
FIFO  
SERIAL I/O  
SDO/ALT  
ADDRESS  
SCL/SCLK  
GND  
CS  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2010 Analog Devices, Inc. All rights reserved.  
 
ADXL3ꢀ1  
TABLE OF CONTENTS  
Register Definitions ................................................................... 23  
Applications Information.............................................................. 29  
Power Supply Decoupling ......................................................... 29  
Mechanical Considerations for Mounting.............................. 29  
Tap Detection.............................................................................. 29  
Improved Tap Detection............................................................ 30  
Tap Sign ....................................................................................... 30  
Threshold .................................................................................... 31  
Link Mode................................................................................... 31  
Sleep Mode vs. Low Power Mode............................................. 31  
Offset Calibration....................................................................... 31  
Using Self-Test ............................................................................ 32  
Orientation Sensing ................................................................... 32  
Data Formatting of Upper Data Rates..................................... 34  
Noise Performance..................................................................... 35  
Operation at Voltages Other Than 2.6 V ................................ 35  
Offset Performance at Lowest Data Rates............................... 36  
Axes of Acceleration Sensitivity ............................................... 37  
Layout and Design Recommendations ................................... 38  
Outline Dimensions....................................................................... 39  
Ordering Guide .......................................................................... 39  
Features .............................................................................................. 1  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Absolute Maximum Ratings............................................................ 5  
Thermal Resistance ...................................................................... 5  
Package Information.................................................................... 5  
ESD Caution.................................................................................. 5  
Pin Configuration and Function Descriptions............................. 6  
Typical Performance Characteristics ............................................. 7  
Theory of Operation ...................................................................... 12  
Power Sequencing ...................................................................... 12  
Power Savings ............................................................................. 13  
Serial Communications ................................................................. 14  
SPI................................................................................................. 14  
I2C................................................................................................. 17  
Interrupts..................................................................................... 19  
FIFO ............................................................................................. 20  
Self-Test........................................................................................ 21  
Register Map.................................................................................... 22  
REVISION HISTORY  
5/10—Revision 0: Initial Version  
Rev. 0 | Page 2 of 40  
 
ADXL3ꢀ1  
SPECIFICATIONS  
TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V, acceleration = 0 g, CS = 10 μF tantalum, CI/O = 0.1 μF, ODR = 800 Hz, unless otherwise noted.  
Table 1. Specifications  
Parameter  
Test Conditions  
Each axis  
User selectable  
Percentage of full scale  
Min1  
Typ 2  
2ꢀ ꢁꢀ 8ꢀ 16  
0.ꢂ  
0.1  
1
Max1  
Unit  
SENSOR INPUT  
Measurement Range  
Nonlinearity  
Inter-Axis Alignment Error  
Cross-Axis Sensitivity3  
OUTPUT RESOLUTION  
All g Ranges  
g
%
Degrees  
%
Each axis  
10-bit resolution  
Full resolution  
Full resolution  
Full resolution  
10  
Bits  
Bits  
Bits  
Bits  
Bits  
2 g Range  
g Range  
8 g Range  
16 g Range  
10  
11  
12  
13  
Full resolution  
SENSITIVITY  
Each axis  
Sensitivity at XOUTꢀ YOUTꢀ ZOUT  
All g rangesꢀ full resolution  
2 gꢀ 10-bit resolution  
gꢀ 10-bit resolution  
8 g, 10-bit resolution  
16 g, 10-bit resolution  
All g ranges  
All g rangesꢀ full resolution  
2 gꢀ 10-bit resolution  
g, 10-bit resolution  
8 g, 10-bit resolution  
16 g, 10-bit resolution  
230  
230  
11ꢂ  
ꢂ7  
2ꢂ6  
2ꢂ6  
128  
6ꢁ  
32  
1.0  
3.9  
3.9  
7.8  
1ꢂ.6  
31.2  
282  
282  
1ꢁ1  
71  
LSB/g  
LSB/g  
LSB/g  
LSB/g  
LSB/g  
%
mg/LSB  
mg/LSB  
mg/LSB  
mg/LSB  
mg/LSB  
%/°C  
29  
3ꢂ  
Sensitivity Deviation from Ideal  
Scale Factor at XOUTꢀ YOUTꢀ ZOUT  
3.ꢂ  
3.ꢂ  
7.1  
1ꢁ.1  
28.6  
ꢁ.3  
ꢁ.3  
8.7  
17.ꢂ  
3ꢁ.ꢂ  
Sensitivity Change Due to Temperature  
0 g OFFSET  
0.02  
Each axis  
0 g Output for XOUTꢀ YOUTꢀ ZOUT  
0 g Output Deviation from Ideal  
0 g Offset vs. Temperature for X-ꢀ Y-Axes  
0 g Offset vs. Temperature for Z-Axis  
NOISE  
−1ꢂ0  
0
+1ꢂ0  
mg  
mg  
mg/°C  
mg/°C  
3ꢂ  
0.7  
1.3  
X-ꢀ Y-Axes  
ODR = 100 Hz for 2 gꢀ 10-bit  
resolution or all g rangesꢀ full  
resolution  
ODR = 100 Hz for 2 gꢀ 10-bit  
resolution or all g rangesꢀ full  
resolution  
1.1  
1.ꢂ  
LSB rms  
LSB rms  
Z-Axis  
OUTPUT DATA RATE AND BANDWIDTH  
Output Data Rate (ODR)ꢀ ꢂꢀ 6  
SELF-TEST7  
User selectable  
0.10  
3200  
Hz  
Output Change in X-Axis  
Output Change in Y-Axis  
Output Change in Z-Axis  
POWER SUPPLY  
0.27  
−1.ꢂꢂ  
0.ꢁ0  
1.ꢂꢂ  
−0.27  
1.9ꢂ  
g
g
g
Operating Voltage Range (VS)  
Interface Voltage Range (VDD I/O  
Measurement Mode Supply Current  
1.7  
1.7  
2.6  
1.8  
1ꢁ0  
30  
0.2  
1.ꢁ  
2.7ꢂ  
VS  
V
V
μA  
μA  
μA  
ms  
)
ODR ≥ 100 Hz  
ODR < 10 Hz  
Standby Mode Supply Current  
Turn-On and Wake-Up Time8  
ODR = 3200 Hz  
Rev. 0 | Page 3 of 40  
 
 
ADXL3ꢀ1  
Parameter  
Test Conditions  
Min1  
Typ 2  
Max1  
Unit  
°C  
TEMPERATURE  
Operating Temperature Range  
WEIGHT  
−ꢁ0  
+8ꢂ  
Device Weight  
18  
mg  
1 All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed.  
2 The typical specifications shown are for at least 68% of the population of parts and are based on the worst case of mean 1 ꢃ except for 0 g output and sensitivityꢀ  
which represents the target value. For 0 g offset and sensitivityꢀ the deviation from the ideal describes the worst case of mean 1 ꢃ.  
3 Cross-axis sensitivity is defined as coupling between any two axes.  
Bandwidth is the −3 dB frequency and is half the output data rate bandwidth = ODR/2.  
The output format for the 3200 Hz and 1600 Hz ODRs is different from the output format for the remaining ODRs. This difference is described in the Data Formatting of  
Upper Data Rates section.  
6 Output data rates below 6.2ꢂ Hz exhibit additional offset shift with increased temperatureꢀ depending on selected output data rate. Refer to the Offset Performance at  
Lowest Data Rates section for details.  
7 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT registerꢀ Address 0x31) minus the output (g) when the SELF_TEST bit = 0.  
Due to device filteringꢀ the output reaches its final value after ꢁ × τ when enabling or disabling self-testꢀ where τ = 1/(data rate). The part must be in normal power  
operation (LOW_POWER bit = 0 in the BW_RATE registerꢀ Address 0x2C) for self-test to operate correctly.  
8 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rateꢀ the turn-on and wake-up times are each approximately 11.1 ms. For  
other data ratesꢀ the turn-on and wake-up times are each approximately τ + 1.1 in millisecondsꢀ where τ = 1/(data rate).  
Rev. 0 | Page ꢁ of ꢁ0  
 
ADXL3ꢀ1  
ABSOLUTE MAXIMUM RATINGS  
PACKAGE INFORMATION  
Table 2.  
The information in Figure 2 and Table 4 provide details about  
the package branding for ADXL346. For a complete listing of  
product availability, see the Ordering Guide section.  
Parameter  
Acceleration  
Any Axisꢀ Unpowered  
Any Axisꢀ Powered  
VS  
Rating  
10ꢀ000 g  
10ꢀ000 g  
−0.3 V to +3.0 V  
−0.3 V to +3.0 V  
−0.3 V to VDD I/O + 0.3 V or  
3.0 Vꢀ whichever is less  
VDD I/O  
Digital Pins  
Y2Z  
All Other Pins  
Output Short-Circuit Duration  
(Any Pin to Ground)  
−0.3 V to +3.0 V  
Indefinite  
vvvv  
Temperature Range  
Powered  
Storage  
Figure 2. Product Information on Package (Top View)  
−ꢁ0°C to +10ꢂ°C  
−ꢁ0°C to +10ꢂ°C  
Table 4. Package Branding Information  
Branding Key  
Field Description  
Y2Z  
vvvv  
Part identifier for ADXL3ꢁ6  
Factory lot code  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
ESD CAUTION  
THERMAL RESISTANCE  
Table 3. Package Characteristics  
Package Type  
θJA  
θJC  
Device Weight  
16-Terminal LGA  
1ꢂ0°C/W  
8ꢂ°C/W  
18 mg  
Rev. 0 | Page ꢂ of 40  
 
 
 
ADXL3ꢀ1  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
16  
15  
14  
1
2
3
4
5
13  
12  
11  
10  
9
V
GND  
GND  
INT1  
NC  
DD I/O  
NC  
ADXL346  
+X  
NC  
SCL/SCLK  
NC  
+Y  
+Z  
INT2  
6
7
8
NC = NO INTERNAL  
CONNECTION  
TOP VIEW  
(Not to Scale)  
Figure 3. Pin Configuration (Top View)  
Table 5. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
2
VDD I/O  
NC  
Digital Interface Supply Voltage.  
Not Internally Connected.  
3
NC  
Not Internally Connected.  
SCL/SCLK  
NC  
Serial Communications Clock.  
Not Internally Connected.  
6
7
8
SDA/SDI/SDIO  
SDO/ALT ADDRESS  
CS  
Serial Data (I2C)/Serial Data Input (SPI ꢁ-Wire)/Serial Data Input and Output (SPI 3-Wire).  
Serial Data Output (SPI ꢁ-Wire)/Alternate I2C Address Select (I2C).  
Chip Select.  
9
INT2  
NC  
INT1  
GND  
GND  
VS  
Interrupt 2 Output.  
Not Internally Connected.  
Interrupt 1 Output.  
Must be connected to ground.  
Must be connected to ground.  
Supply Voltage.  
Reserved. This pin must be connected to VS.  
Must be connected to ground.  
10  
11  
12  
13  
1ꢁ  
1ꢂ  
16  
RESERVED  
GND  
Rev. 0 | Page 6 of 40  
 
ADXL3ꢀ1  
TYPICAL PERFORMANCE CHARACTERISTICS  
30  
30  
25  
20  
15  
10  
5
25  
20  
15  
10  
5
0
–150  
0
–150  
–100  
–50  
0
50  
100  
150  
–100  
–50  
0
50  
100  
150  
ZERO g OFFSET (mg)  
ZERO g OFFSET (mg)  
Figure 4. X-Axis Zero g Offset at 25°C, VS = 2.6 V  
Figure 7. X-Axis Zero g Offset at 25°C, VS = 1.8 V  
30  
30  
25  
20  
15  
10  
5
25  
20  
15  
10  
5
0
–150  
0
–150  
–100  
–50  
0
50  
100  
150  
–100  
–50  
0
50  
100  
150  
ZERO g OFFSET (mg)  
ZERO g OFFSET (mg)  
Figure 5. Y-Axis Zero g Offset at 25°C, VS = 2.6 V  
Figure 8. Y-Axis Zero g Offset at 25°C, VS = 1.8 V  
30  
25  
20  
15  
10  
5
30  
25  
20  
15  
10  
5
0
–150  
0
–150  
–100  
–50  
0
50  
100  
150  
–100  
–50  
0
50  
100  
150  
ZERO g OFFSET (mg)  
ZERO g OFFSET (mg)  
Figure 6. Z-Axis Zero g Offset at 25°C, VS = 2.6 V  
Figure 9. Z-Axis Zero g Offset at 25°C, VS = 1.8 V  
Rev. 0 | Page 7 of 40  
 
ADXL3ꢀ1  
250  
200  
150  
100  
50  
60  
50  
40  
30  
20  
10  
0
–50  
–100  
–150  
–200  
–250  
0
–3  
–2  
–1  
0
1
–40  
–20  
0
20  
40  
60  
80  
100  
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/°C)  
TEMPERATURE (°C)  
Figure 10. X-Axis Zero g Offset Temperature Coefficient, VS = 2.6 V  
Figure 13. X-Axis Zero g Offset vs. Temperature—  
Eight Parts Soldered to PCB, VS = 2.6 V  
60  
50  
40  
30  
20  
10  
0
250  
200  
150  
100  
50  
0
–50  
–100  
–150  
–200  
–250  
–3  
–2  
–1  
0
1
–40  
–20  
0
20  
40  
60  
80  
100  
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/°C)  
TEMPERATURE (°C)  
Figure 11. Y-Axis Zero g Offset Temperature Coefficient, VS = 2.6 V  
Figure 14. Y-Axis Zero g Offset vs. Temperature—  
Eight Parts Soldered to PCB, VS = 2.6 V  
60  
50  
40  
30  
20  
10  
0
250  
200  
150  
100  
50  
0
–50  
–100  
–150  
–200  
–250  
–3  
–2  
–1  
0
1
–40  
–20  
0
20  
40  
60  
80  
100  
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/°C)  
TEMPERATURE (°C)  
Figure 12. Z-Axis Zero g Offset Temperature Coefficient, VS = 2.6 V  
Figure 15. Z-Axis Zero g Offset vs. Temperature—  
Eight Parts Soldered to PCB, VS = 2.6 V  
Rev. 0 | Page 8 of 40  
ADXL3ꢀ1  
60  
50  
40  
30  
20  
10  
0
60  
50  
40  
30  
20  
10  
0
230  
240  
250  
260  
270  
280  
230  
240  
250  
260  
270  
280  
SENSITIVITY (LSB/g)  
SENSITIVITY (LSB/g)  
Figure 16. X-Axis Sensitivity at 25°C, VS = 2.6 V, Full Resolution  
Figure 19. X-Axis Sensitivity at 25°C, VS = 1.8 V, Full Resolution  
60  
50  
40  
30  
20  
10  
0
60  
50  
40  
30  
20  
10  
0
230  
240  
250  
260  
270  
280  
230  
240  
250  
260  
270  
280  
SENSITIVITY (LSB/g)  
SENSITIVITY (LSB/g)  
Figure 17. Y-Axis Sensitivity at 25°C, VS = 2.6 V, Full Resolution  
Figure 20. Y-Axis Sensitivity at 25°C, VS = 1.8 V, Full Resolution  
60  
50  
40  
30  
20  
10  
0
60  
50  
40  
30  
20  
10  
0
230  
240  
250  
260  
270  
280  
230  
240  
250  
260  
270  
280  
SENSITIVITY (LSB/g)  
SENSITIVITY (LSB/g)  
Figure 18. Z-Axis Sensitivity at 25°C, VS = 2.6 V, Full Resolution  
Figure 21. Z-Axis Sensitivity at 25°C, VS = 1.8 V, Full Resolution  
Rev. 0 | Page 9 of 40  
ADXL3ꢀ1  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
280  
275  
270  
265  
260  
255  
250  
245  
240  
235  
230  
0
–40  
–20  
0
20  
40  
60  
80  
100  
–0.10  
–0.05  
0
0.05  
0.10  
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)  
TEMPERATURE (°C)  
Figure 22. X-Axis Sensitivity Temperature Coefficient, VS = 2.6 V  
Figure 25. X-Axis Sensitivity vs. Temperature—  
Eight Parts Soldered to PCB, VS = 2.6 V, Full Resolution  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
280  
275  
270  
265  
260  
255  
250  
245  
240  
235  
230  
–40  
–20  
0
20  
40  
60  
80  
100  
–0.10  
–0.05  
0
0.05  
0.10  
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)  
TEMPERATURE (°C)  
Figure 23. Y-Axis Sensitivity Temperature Coefficient, VS = 2.6 V  
Figure 26. Y-Axis Sensitivity vs. Temperature—  
Eight Parts Soldered to PCB, VS = 2.6 V, Full Resolution  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
280  
275  
270  
265  
260  
255  
250  
245  
240  
235  
230  
–0.10  
–0.05  
0
0.05  
0.10  
–40  
–20  
0
20  
40  
60  
80  
100  
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)  
TEMPERATURE (°C)  
Figure 24. Z-Axis Sensitivity Temperature Coefficient, VS = 2.6 V  
Figure 27. Z-Axis Sensitivity vs. Temperature—  
Eight Parts Soldered to PCB, VS = 2.6 V, Full Resolution  
Rev. 0 | Page 10 of 40  
ADXL3ꢀ1  
40  
35  
30  
25  
20  
15  
10  
5
40  
35  
30  
25  
20  
15  
10  
5
0
0
90  
100  
110  
120  
130  
140  
150  
160  
170  
180  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
OUTPUT CURRENT (µA)  
SELF-TEST SHIFT (g)  
Figure 28. X-Axis Self-Test Response at 25°C, VS = 2.6 V  
Figure 31. Supply Current at 25°C, 100 Hz Output Data Rate, VS = 2.6 V  
40  
35  
30  
25  
20  
15  
10  
5
160  
140  
120  
100  
80  
60  
40  
20  
0
0
–1.0  
–0.9  
–0.8  
–0.7  
–0.6  
–0.5  
3.13 6.25 12.50 25  
50 100 200 400 800 1600 3200  
SELF-TEST SHIFT (g)  
OUTPUT DATA RATE (Hz)  
Figure 29. Y-Axis Self-Test Response at 25°C, VS = 2.6 V  
Figure 32. Supply Current vs. Output Data Rate at 25°C—10 Parts, VS = 2.6 V  
40  
35  
30  
25  
20  
15  
10  
5
150  
140  
130  
120  
110  
100  
90  
0
1.0  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
1.8  
2.0  
2.2  
2.4  
2.6  
2.8  
SELF-TEST SHIFT (g)  
SUPPLY VOLTAGE, V (V)  
S
Figure 30. Z-Axis Self-Test Response at 25°C, VS = 2.6 V  
Figure 33. Supply Current vs. Supply Voltage at 25°C  
Rev. 0 | Page 11 of 40  
 
ADXL3ꢀ1  
THEORY OF OPERATION  
The ADXL346 is a complete 3-axis acceleration measurement  
system with a selectable measurement range of 2 g, 4 g, 8 g,  
or 16 g. It measures both dynamic acceleration resulting from  
motion or shock and static acceleration, such as gravity, which  
allows the device to be used as a tilt sensor.  
POWER SEQUENCING  
Power can be applied to VS or VDD I/O in any sequence without  
damaging the ADXL346. All possible power-on modes are  
summarized in Table 6. The interface voltage level is set with  
the interface supply voltage, VDD I/O, which must be present to  
ensure that the ADXL346 does not create a conflict on the  
communication bus. For single-supply operation, VDD I/O can be  
the same as the main supply, VS. In a dual-supply application,  
however, VDD I/O can differ from VS to accommodate the desired  
The sensor is a polysilicon surface-micromachined structure  
built on top of a silicon wafer. Polysilicon springs suspend the  
structure over the surface of the wafer and provide a resistance  
against forces due to applied acceleration.  
interface voltage, as long as VS is greater than or equal to VDD I/O  
.
Deflection of the structure is measured using differential capacitors  
that consist of independent fixed plates and plates attached to the  
moving mass. Acceleration deflects the proof mass and unbalances  
the differential capacitor, resulting in a sensor output with an  
amplitude proportional to acceleration. Phase-sensitive de-  
modulation is used to determine the magnitude and polarity  
of the acceleration.  
After VS is applied, the device enters standby mode, where power  
consumption is minimized and the device waits for VDD I/O to be  
applied and for the command to enter measurement mode to be  
received. (This command can be initiated by setting the measure  
bit (Bit D3) in the POWER_CTL register (Address 0x2D).) In  
addition, any register can be written to or read from to configure  
the part while the device is in standby mode. It is recommended  
to configure the device in standby mode and then to enable  
measurement mode. Clearing the measure bit returns the  
device to the standby mode.  
Table 6. Power Sequencing  
Condition  
VS  
VDD I/O  
Description  
Power Off  
Off  
Off  
The device is completely offꢀ but there is a potential for a communication  
bus conflict.  
Bus Disabled  
Bus Enabled  
On  
Off  
The device is on in standby modeꢀ but communication is unavailable and will  
create a conflict on the communication bus. The duration of this state should  
be minimized during power-up to prevent a conflict.  
No functions are availableꢀ but the device will not create a conflict on the  
communication bus.  
At power-upꢀ the device is in standby modeꢀ awaiting a command to enter  
measurement modeꢀ and all sensor functions are off. After the device is  
instructed to enter measurement modeꢀ all sensor functions are available.  
Off  
On  
On  
On  
Standby or  
Measurement Mode  
Rev. 0 | Page 12 of 40  
 
 
ADXL3ꢀ1  
POWER SAVINGS  
Power Modes  
Table 8. Typical Current Consumption vs. Data Rate, Low  
Power Mode (TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V)  
Output Data  
The ADXL346 automatically modulates its power consumption  
in proportion to its output data rate, as outlined in Table 7. If  
additional power savings is desired, a lower power mode is  
available. In this mode, the internal sampling rate is reduced,  
allowing for power savings in the 12.5 Hz to 400 Hz data rate  
range at the expense of slightly greater noise. To enter low  
power mode, set the LOW_POWER bit (Bit D4) in the BW_RATE  
register (Address 0x2C). The current consumption in low power  
mode is shown in Table 8 for cases where there is an advantage  
to using low power mode. Use of low power mode for a data  
rate not shown in Table 8 does not provide any advantage over  
the same data rate in normal power mode. Therefore, it is  
recommended that only data rates listed in Table 8 be used in  
low power mode. The current consumption values shown in  
Table 7 and Table 8 are for a VS of 2.6 V.  
Rate (Hz)  
Bandwidth (Hz)  
Rate Code  
IDD (μA)  
ꢁ00  
200  
100  
ꢂ0  
2ꢂ  
12.ꢂ  
200  
100  
ꢂ0  
2ꢂ  
12.ꢂ  
6.2ꢂ  
1100  
1011  
1010  
1001  
1000  
0111  
90  
ꢂꢂ  
ꢁ0  
31  
27  
23  
Autosleep Mode  
Additional power can be saved if the ADXL346 automatically  
switches to sleep mode during periods of inactivity. To enable  
this feature, set the THRESH_INACT register (Address 0x25)  
and the TIME_INACT register (Address 0x26) each to a value  
that signifies inactivity (the appropriate value depends on the  
application), and then set the AUTO_SLEEP bit (Bit D4) and the  
link bit (Bit D5) in the POWER_CTL register (Address 0x2D).  
Current consumption at the sub-8 Hz data rates used in this  
mode is typically 23 ꢀA for a VS of 2.6 V.  
Table 7. Typical Current Consumption vs. Data Rate  
(TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V)  
Output Data  
Rate (Hz)  
3200  
1600  
800  
Bandwidth (Hz)  
Rate Code  
1111  
1110  
1101  
1100  
1011  
1010  
1001  
1000  
0111  
0110  
0101  
0100  
0011  
0010  
0001  
0000  
IDD (μA)  
1ꢁ0  
90  
Standby Mode  
1600  
800  
ꢁ00  
200  
100  
ꢂ0  
For even lower power operation, standby mode can be used.  
In standby mode, current consumption is reduced to 0.2 ꢀA  
(typical). In this mode, no measurements are made. Standby mode  
is entered by clearing the measure bit (Bit D3) in the  
POWER_CTL register (Address 0x2D). Placing the device into  
standby mode preserves the contents of FIFO.  
1ꢁ0  
1ꢁ0  
1ꢁ0  
1ꢁ0  
90  
ꢁ00  
200  
100  
ꢂ0  
2ꢂ  
2ꢂ  
12.ꢂ  
6.2ꢂ  
3.13  
1.ꢂ6  
0.78  
0.39  
0.20  
0.10  
0.0ꢂ  
ꢂꢂ  
ꢁ0  
31  
27  
23  
23  
23  
23  
12.ꢂ  
6.2ꢂ  
3.13  
1.ꢂ6  
0.78  
0.39  
0.20  
0.10  
23  
Rev. 0 | Page 13 of 40  
 
 
 
 
ADXL3ꢀ1  
SERIAL COMMUNICATIONS  
I2C and SPI digital communications are available. In both cases,  
CS  
is the serial port enable line and is controlled by the SPI master.  
2
CS  
the ADXL346 operates as a slave. I C mode is enabled if the pin  
This line must go low at the start of a transmission and high at  
the end of a transmission, as shown in Figure 36. SCLK is the  
serial port clock and is supplied by the SPI master. SCLK should  
idle high during a period of no transmission. SDI and SDO are  
the serial data input and output, respectively. Data is updated  
on the falling edge of SCLK and should be sampled on the  
rising edge of SCLK.  
CS  
is tied high to VDD I/O. The  
pin should always be tied high to  
VDD I/O or be driven by an external controller because there is no  
CS  
default mode if the  
pin is left unconnected. Therefore, not  
taking these precautions may result in an inability to communicate  
CS  
with the part. In SPI mode, the  
pin is controlled by the bus  
master. In both SPI and I2C modes of operation, data transmitted  
from the ADXL346 to the master device should be ignored during  
writes to the ADXL346.  
To read or write multiple bytes in a single transmission, the  
W
multiple-byte bit, located after the R/ bit in the first byte transfer  
(MB in Figure 36 to Figure 38), must be set. After the register  
addressing and the first byte of data, each subsequent set of  
clock pulses (eight clock pulses) causes the ADXL346 to point  
to the next register for a read or write. This shifting continues  
SPI  
For SPI, either 3- or 4-wire configuration is possible, as shown in  
the connection diagrams in Figure 34 and Figure 35. Clearing the  
SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31)  
selects 4-wire mode, whereas setting the SPI bit selects 3-wire  
mode. The maximum SPI clock speed is 5 MHz with 100 pF  
maximum loading, and the timing scheme follows clock polarity  
(CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to  
the ADXL346 before the clock polarity and phase of the host  
CS  
until the clock pulses cease and is deasserted. To perform reads  
CS  
or writes on different, nonsequential registers,  
must be  
deasserted between transmissions and the new register must be  
addressed separately.  
The timing diagram for 3-wire SPI reads or writes is shown in  
Figure 38. The 4-wire equivalents for SPI writes and reads are  
shown in Figure 36 and Figure 37, respectively. For correct  
operation of the part, the logic thresholds and timing parameters  
in Table 9 and Table 10 must be met at all times.  
CS  
processor are configured, the  
before changing the clock polarity and phase. When using 3-wire  
SPI, it is recommended that the SDO pin either be pulled up to  
pin should be brought high  
VDD I/O or be pulled down to GND via a 10 kΩ resistor.  
Use of the 3200 Hz and 1600 Hz output data rates is recom-  
mended only with SPI communication rates greater than or  
equal to 2 MHz. The 800 Hz output data rate is recommended  
only for communication speeds greater than or equal to 400 kHz,  
and the remaining data rates scale proportionally. For example,  
the minimum recommended communication speed for a 200 Hz  
output data rate is 100 kHz. Operation at an output data rate  
above the recommended maximum may result in undesirable  
effects on the acceleration data, including missing samples or  
additional noise.  
ADXL346  
PROCESSOR  
CS  
SDIO  
SDO  
D OUT  
D IN/OUT  
SCLK  
D OUT  
Figure 34. 3-Wire SPI Connection Diagram  
ADXL346  
PROCESSOR  
CS  
SDI  
D OUT  
D OUT  
D IN  
SDO  
SCLK  
D OUT  
Figure 35. 4-Wire SPI Connection Diagram  
Rev. 0 | Page 1ꢁ of ꢁ0  
 
 
 
ADXL3ꢀ1  
CS  
tM  
tS  
tSCLK  
tQUIET  
tCS,DIS  
tDELAY  
SCLK  
SDI  
tSETUP  
tHOLD  
MB  
W
A5  
A0  
D7  
D0  
tSDO  
tDIS  
ADDRESS BITS  
X
DATA BITS  
X
SDO  
X
X
X
X
tR,  
tF  
Figure 36. SPI 4-Wire Write  
CS  
SCLK  
SDI  
tSCLK  
tM  
tS  
tCS,DIS  
tQUIET  
tDELAY  
tHOLD  
tSETUP  
R
MB  
A5  
A0  
X
X
tSDO  
tDIS  
ADDRESS BITS  
X
X
X
X
D7  
D0  
SDO  
tR,  
tF  
DATA BITS  
Figure 37. SPI 4-Wire Read  
CS  
SCLK  
SDIO  
tDELAY  
tM  
tS  
tSCLK  
tQUIET  
tCS,DIS  
tSETUP  
tSDO  
tHOLD  
MB  
tR, tF  
A0  
R/W  
A5  
D7  
D0  
ADDRESS BITS  
DATA BITS  
SDO  
NOTES  
1. tSDO IS ONLY PRESENT DURING READS.  
Figure 38. SPI 3-Wire Read/Write  
Rev. 0 | Page 1ꢂ of 40  
 
 
 
ADXL3ꢀ1  
Table 9. SPI Digital Input/Output  
Limit1  
Max  
Parameter  
Test Conditions  
Min  
Unit  
Digital Input  
Low Level Input Voltage (VIL)  
High Level Input Voltage (VIH)  
Low Level Input Current (IIL)  
High Level Input Current (IIH)  
Digital Output  
0.3 × VDD I/O  
0.1  
V
V
μA  
μA  
0.7 × VDD I/O  
−0.1  
VIN = VDD I/O  
VIN = 0 V  
Low Level Output Voltage (VOL  
High Level Output Voltage (VOH  
Low Level Output Current (IOL  
)
IOL = 10 mA  
IOH = −ꢁ mA  
VOL = VOLꢀ max  
VOH = VOHꢀ min  
0.2 × VDD I/O  
V
V
mA  
mA  
pF  
)
0.8 × VDD I/O  
10  
)
High Level Output Current (IOH  
)
−ꢁ  
8
Pin Capacitance  
fIN = 1 MHzꢀ VIN = 2.6 V  
1 Limits are based on characterization results; not production tested.  
Table 10. SPI Timing (TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V)1  
Limit2, 3  
Parameter  
fSCLK  
tSCLK  
tDELAY  
tQUIET  
Min  
Max  
Unit  
MHz  
ns  
Description  
SPI clock frequency  
1/(SPI clock frequency) mark-space ratio for the SCLK input is ꢁ0/60 to 60/ꢁ0  
CS falling edge to SCLK falling edge  
200  
ns  
ns  
SCLK rising edge to CS rising edge  
tDIS  
10  
ns  
CS rising edge to SDO disabled  
tCS  
ꢀDIS  
1ꢂ0  
ns  
CS deassertion between SPI communications  
tS  
tM  
tSETUP  
tHOLD  
tSDO  
0.3 × tSCLK  
0.3 × tSCLK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCLK low pulse width (space)  
SCLK high pulse width (mark)  
SDI valid before SCLK rising edge  
SDI valid after SCLK rising edge  
SCLK falling edge to SDO/SDIO output transition  
SDO/SDIO output low to output high transition  
SDO/SDIO output high to output low transition  
ꢁ0  
20  
20  
tR  
tF  
1
CS  
The ꢀ SCLKꢀ SDIꢀ and SDO pins are not internally pulled up or down; they must be driven for proper operation.  
2 Limits are based on characterization results; not production tested.  
3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9.  
Output rise and fall times are measured with a capacitive load of 1ꢂ0 pF.  
Rev. 0 | Page 16 of 40  
 
 
ADXL3ꢀ1  
I2C  
Due to communication speed limitations, the maximum output  
data rate when using 400 kHz I2C is 800 Hz and scales linearly with  
a change in the I2C communication speed. For example, using I2C  
at 100 kHz would limit the maximum ODR to 200 Hz. Operation  
at an output data rate above the recommended maximum may  
result in an undesirable effect on the acceleration data, including  
missing samples or additional noise.  
tied high to VDD I/O, the ADXL346 is in I2C mode,  
CS  
With  
requiring a simple 2-wire connection as shown in Figure 39.  
The ADXL346 conforms to the UM10204 I2C-Bus Specification  
and User Manual, Rev. 03—19 June 2007, available from NXP  
Semiconductor. It supports standard (100 kHz) and fast (400 kHz)  
data transfer modes if the bus parameters given in Table 11 and  
Table 12 are met. Single- or multiple-byte reads/writes are sup-  
ported, as shown in Figure 40. With the ALT ADDRESS pin (Pin 7)  
high, the 7-bit I2C address for the device is 0x1D, followed by the  
V
DD I/O  
R
R
P
ADXL346  
PROCESSOR  
P
W
R/ bit. This translates to 0x3A for a write and 0x3B for a read.  
CS  
2
W
An alternate I C address of 0x53 (followed by the R/ bit) can  
be chosen by grounding the ALT ADDRESS pin. This translates  
to 0xA6 for a write and 0xA7 for a read.  
SDA  
ALT ADDRESS  
SCL  
D IN/OUT  
D OUT  
There are no internal pull-up or pull-down resistors for any  
Figure 39. I2C Connection Diagram (Address 0x53)  
unused pins; therefore, there is no known state or default state  
CS  
If other devices are connected to the same I2C bus, the nominal  
operating voltage level of these other devices cannot exceed VDD I/O  
by more than 0.3 V. External pull-up resistors, RP, are necessary for  
proper I2C operation. Refer to the UM10204 I2C-Bus Specification  
and User Manual, Rev. 03—19 June 2007, when selecting pull-up  
resistor values to ensure proper operation.  
for the  
or ALT ADDRESS pin if left floating or unconnected.  
CS  
It is required that the  
pin be connected to VDD I/O and that  
the ALT ADDRESS pin be connected to either VDD I/O or GND  
when using I2C.  
Table 11. I2C Digital Input/Output  
Limit1  
Parameter  
Test Conditions  
Min  
Max  
Unit  
Digital Input  
Low Level Input Voltage (VIL)  
High Level Input Voltage (VIH)  
Low Level Input Current (IIL)  
High Level Input Current (IIH)  
Digital Output  
0.3 × VDD I/O  
0.1  
V
V
μA  
μA  
0.7 × VDD I/O  
−0.1  
VIN = VDD I/O  
VIN = 0 V  
Low Level Output Voltage (VOL  
)
VDD I/O < 2 Vꢀ IOL = 3 mA  
0.2 × VDD I/O  
ꢁ00  
V
V
DD I/O ≥ 2 Vꢀ IOL = 3 mA  
VOL = VOLꢀ max  
IN = 1 MHzꢀ VIN = 2.6 V  
mV  
mA  
pF  
Low Level Output Current (IOL  
)
3
Pin Capacitance  
f
8
1 Limits are based on characterization results; not production tested.  
SINGLE-BYTE WRITE  
MASTER START  
SLAVE  
SLAVE ADDRESS + WRITE  
REGISTER ADDRESS  
REGISTER ADDRESS  
REGISTER ADDRESS  
REGISTER ADDRESS  
DATA  
DATA  
STOP  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
MULTIPLE-BYTE WRITE  
MASTER START  
SLAVE  
SLAVE ADDRESS + WRITE  
DATA  
STOP  
ACK  
ACK  
SINGLE-BYTE READ  
MASTER START  
SLAVE  
SLAVE ADDRESS + WRITE  
SLAVE ADDRESS + WRITE  
START1  
START1  
SLAVE ADDRESS + READ  
SLAVE ADDRESS + READ  
NACK  
STOP  
ACK  
ACK  
DATA  
DATA  
MULTIPLE-BYTE READ  
MASTER START  
SLAVE  
ACK  
NACK  
STOP  
DATA  
1
THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.  
NOTES  
1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.  
Figure 40. I2C Device Addressing  
Rev. 0 | Page 17 of 40  
 
 
 
 
ADXL3ꢀ1  
Table 12. I2C Timing (TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V)  
Limit1, 2  
Parameter  
Min  
Max  
Unit  
kHz  
μs  
μs  
μs  
μs  
ns  
μs  
Description  
fSCL  
t1  
t2  
t3  
tꢁ  
ꢁ00  
SCL clock frequency  
SCL cycle time  
tHIGHꢀ SCL high time  
tLOWꢀ SCL low time  
tHDꢀ STAꢀ start/repeated start condition hold time  
tSUꢀ DATꢀ data setup time  
tHDꢀ DATꢀ data hold time  
2.ꢂ  
0.6  
1.3  
0.6  
100  
0
tꢂ  
t6  
3ꢀ ꢁꢀ ꢂꢀ 6  
0.9  
t7  
t8  
t9  
t10  
0.6  
0.6  
1.3  
μs  
μs  
μs  
ns  
ns  
ns  
ns  
ns  
tSUꢀ STAꢀ setup time for repeated start  
tSUꢀ STOꢀ stop condition setup time  
tBUFꢀ bus-free time between a stop condition and a start condition  
tRꢀ rise time of both SCL and SDA when receiving  
tRꢀ rise time of both SCL and SDA when receiving or transmitting  
tFꢀ fall time of SDA when receiving  
tFꢀ fall time of both SCL and SDA when transmitting  
tFꢀ fall time of both SCL and SDA when transmitting or receiving  
Capacitive load for each bus line  
300  
0
t11  
2ꢂ0  
300  
7
20 + 0.1 CB  
7
CB  
ꢁ00  
pF  
1 Limits are based on characterization resultsꢀ with fSCL = ꢁ00 kHz and a 3 mA sink current; not production tested.  
2 All values referred to the VIH and the VIL levels given in Table 11.  
3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.  
A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIHꢀmin of the SCL signal) to bridge the undefined region of  
the falling edge of SCL.  
The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal.  
6 The maximum value for t6 is a function of the clock low time (t3)ꢀ the clock rise time (t10)ꢀ and the minimum data setup time (tꢂ(min)). This value is calculated as t6(max) = t3 − t10 − tꢂ(min)  
.
7 CB is the total capacitance of one bus line in picofarads.  
SDA  
t3  
t4  
t9  
t10  
t11  
SCL  
t2  
t7  
t1  
t8  
t4  
t6  
t5  
START  
CONDITION  
REPEATED  
START  
CONDITION  
STOP  
CONDITION  
Figure 41. I2C Timing Diagram  
Rev. 0 | Page 18 of 40  
 
ADXL3ꢀ1  
DOUBLE_TAP Bit  
INTERRUPTS  
The DOUBLE_TAP bit is set when two acceleration events  
that are greater than the value in the THRESH_TAP register  
(Address 0x1D) occur for less time than is specified in the DUR  
register (Address 0x21). The second tap starts after the time  
specified by the latent register (Address 0x22) but within the  
time specified in the window register (Address 0x23). See the Tap  
Detection section for more details.  
The ADXL346 provides two output pins for driving interrupts:  
INT1 and INT2. Both interrupt pins are push-pull, low impedance  
pins with the output specifications listed in Table 13. The default  
configuration of the interrupt pins is active high. This can be  
changed to active low by setting the INT_INVERT bit (Bit D5)  
in the DATA_FORMAT (Address 0x31) register. All functions  
can be used simultaneously, with the only limiting feature being  
that some functions may need to share interrupt pins.  
Activity Bit  
The activity bit is set when acceleration greater than the value stored  
in the THRESH_ACT register (Address 0x24) is experienced on  
any participating axis, as set by the ACT_INACT_CTL register  
(Address 0x27).  
Interrupts are enabled by setting the appropriate bit in the  
INT_ENABLE register (Address 0x2E) and are mapped to either  
the INT1 or INT2 pin based on the contents of the INT_MAP  
register (Address 0x2F). When initially configuring the interrupt  
pins, it is recommended that the functions and interrupt mapping  
be done before enabling the interrupts. When changing the con-  
figuration of an interrupt, it is recommended that the interrupt be  
disabled first, by clearing the bit corresponding to that function in  
the INT_ENABLE register, and then the function be reconfigured  
before enabling the interrupt again. Configuration of the functions  
while the interrupts are disabled helps to prevent the accidental  
generation of an interrupt before it is desired.  
Inactivity Bit  
The inactivity bit is set when acceleration of less than the  
value stored in the THRESH_INACT register (Address 0x25) is  
experienced for more time than is specified in the TIME_INACT  
register (Address 0x26) on all participating axes, as set by the  
ACT_INACT_CTL register (Address 0x27). The maximum value  
for TIME_INACT is 255 sec.  
FREE_FALL Bit  
The interrupt functions are latched and cleared by either reading  
the DATAX, DATAY, and DATAZ registers (Address 0x32 to  
Address 0x37) until the interrupt condition is no longer valid  
for the data-related interrupts or by reading the INT_SOURCE  
register (Address 0x30) for the remaining interrupts. This section  
describes the interrupts that can be set in the INT_ENABLE  
register and monitored in the INT_SOURCE register.  
The FREE_FALL bit is set when acceleration of less than the  
value stored in the THRESH_FF register (Address 0x28) is  
experienced for more time than is specified in the TIME_FF  
register (Address 0x29) on all axes (logical AND). The FREE_FALL  
interrupt differs from the inactivity interrupt as follows: all axes  
always participate and are logically ANDed, the timer period is  
much smaller (1.28 sec maximum), and the mode of operation is  
always dc-coupled.  
DATA_READY Bit  
The DATA_READY bit is set when new data is available and is  
cleared when no new data is available.  
Watermark Bit  
The watermark bit is set when the number of samples in FIFO  
equals the value stored in the samples bits (Register FIFO_CTL,  
Address 0x38). The watermark bit is cleared automatically when  
FIFO is read, and the content returns to a value below the value  
stored in the samples bits.  
SINGLE_TAP Bit  
The SINGLE_TAP bit is set when a single acceleration event  
that is greater than the value in the THRESH_TAP register  
(Address 0x1D) occurs for less time than is specified in  
the DUR register (Address 0x21).  
Table 13. Interrupt Pin Digital Output  
Limit1  
Parameter  
Test Conditions  
Min  
Max  
Unit  
Digital Output  
Low Level Output Voltage (VOL  
)
IOL = 300 μA  
0.2 × VDD I/O  
V
High Level Output Voltage (VOH  
Low Level Output Current (IOL  
)
IOH = −1ꢂ0 μA  
VOL = VOLꢀ max  
VOH = VOHꢀ min  
0.8 × VDD I/O  
300  
V
)
μA  
μA  
pF  
High Level Output Current (IOH  
)
−1ꢂ0  
8
Pin Capacitance  
fIN = 1 MHzꢀ VIN = 2.6 V  
Rise/Fall Time  
Rise Time (tR)2  
Fall Time (tF)3  
CLOAD = 1ꢂ0 pF  
CLOAD = 1ꢂ0 pF  
210  
1ꢂ0  
ns  
ns  
1 Limits are based on characterization results; not production tested.  
2 Rise time is measured as the transition time from VOLꢀ max to VOHꢀ min of the interrupt pin.  
3 Fall time is measured as the transition time from VOHꢀ min to VOLꢀ max of the interrupt pin.  
Rev. 0 | Page 19 of 40  
 
 
ADXL3ꢀ1  
Stream Mode  
Overrun Bit  
In stream mode, data from measurements of the x-, y-, and z-  
axes are stored in FIFO. When the number of samples in FIFO  
equals the level specified in the samples bits of the FIFO_CTL  
register (Address 0x38), the watermark interrupt is set. FIFO  
continues accumulating samples and holds the latest 32 samples  
from measurements of the x-, y-, and z-axes, discarding older  
data as new data arrives. The watermark interrupt continues  
occurring until the number of samples in FIFO is less than the  
value stored in the samples bits of the FIFO_CTL register.  
The overrun bit is set when new data replaces unread data. The  
precise operation of the overrun function depends on the FIFO  
mode. In bypass mode, the overrun bit is set when new data  
replaces unread data in the DATAX, DATAY, and DATAZ registers  
(Address 0x32 to Address 0x37). In all other modes, the overrun  
bit is set when FIFO is filled. The overrun bit is automatically  
cleared when the contents of FIFO are read.  
Orientation Bit  
The orientation bit is set when the orientation of the accelerometer  
changes from a valid orientation to a different valid orientation.  
An interrupt is not generated, however, if the orientation of the  
accelerometer changes from a valid orientation to an invalid  
orientation, or from a valid orientation to an invalid orientation  
and then back to the same valid orientation. An invalid orientation  
is defined as an orientation within the dead zone, or the region of  
hysteresis. This region helps to prevent rapid orientation change  
due to noise when the accelerometer orientation is close to the  
boundary between two valid orientations.  
Trigger Mode  
In trigger mode, FIFO accumulates samples, holding the latest  
32 samples from measurements of the x-, y-, and z-axes. After  
a trigger event occurs and an interrupt is sent to the INT1 or  
INT2 pin (determined by the trigger bit in the FIFO_CTL register),  
FIFO keeps the last n samples (where n is the value specified by  
the samples bits in the FIFO_CTL register) and then operates in  
FIFO mode, collecting new samples only when FIFO is not full.  
A delay of at least 5 μs should be present between the trigger event  
occurring and the start of reading data from the FIFO to allow  
the FIFO to discard and retain the necessary samples. Additional  
trigger events cannot be recognized until the trigger mode is  
reset. To reset the trigger mode, set the device to bypass mode  
and then set the device back to trigger mode. Note that the FIFO  
data should be read first because placing the device into bypass  
mode clears FIFO.  
The orientations that are valid for the interrupt depend on which  
mode, 2D or 3D, is linked to the orientation interrupt. The mode is  
selected with the INT_3D bit (Bit D3) in the ORIENT_CONF  
register (Address 0x3B). See the Register 0x3B—ORIENT_CONF  
(Read/Write) section for more details on how to enable the  
orientation interrupt.  
FIFO  
Retrieving Data from FIFO  
The ADXL346 contains patent pending technology for an  
embedded memory management system with 32-level FIFO  
that can be used to minimize host processor burden. This buffer  
has four modes: bypass, FIFO, stream, and trigger (see Table 22).  
Each mode is selected by the settings of the FIFO_MODE bits  
(Bits[D7:D6]) in the FIFO_CTL register (Address 0x38).  
The FIFO data is read through the DATAX, DATAY, and DATAZ  
registers (Address 0x32 to Address 0x37). When the FIFO is in  
FIFO, stream, or trigger mode, reads to the DATAX, DATAY,  
and DATAZ registers read data stored in the FIFO. Each time  
data is read from the FIFO, the oldest x-, y-, and z-axes data are  
placed into the DATAX, DATAY, and DATAZ registers.  
Bypass Mode  
If a single-byte read operation is performed, the remaining bytes of  
data for the current FIFO sample are lost. Therefore, all axes of  
interest should be read in a burst (or multiple-byte) read operation.  
To ensure that the FIFO has completely popped (that is, that new  
data has completely moved into the DATAX, DATAY, and DATAZ  
registers), there must be at least 5 μs between the end of reading  
the data registers and the start of a new read of the FIFO or a  
read of the FIFO_STATUS register (Address 0x39). The end of  
reading a data register is signified by the transition of data from  
In bypass mode, FIFO is not operational and, therefore,  
remains empty.  
FIFO Mode  
In FIFO mode, data from measurements of the x-, y-, and z-axes  
are stored in FIFO. When the number of samples in FIFO  
equals the level specified in the samples bits of the FIFO_CTL  
register (Address 0x38), the watermark interrupt is set. FIFO  
continues accumulating samples until it is full (32 samples from  
measurements of the x-, y-, and z-axes) and then stops collecting  
data. After FIFO stops collecting data, the device continues to  
operate; therefore, features such as tap detection can be used  
after FIFO is full. The watermark interrupt continues to occur  
until the number of samples in FIFO is less than the value  
stored in the samples bits of the FIFO_CTL register.  
CS  
Register 0x37 to Register 0x38 or by the  
pin going high.  
For SPI operation at 1.6 MHz or less, the register addressing  
portion of the transmission is a sufficient delay to ensure that  
the FIFO has completely popped. For SPI operation greater than  
CS  
1.6 MHz, it is necessary to deassert the  
pin to ensure a total  
delay of 5 μs; otherwise, the delay will not be sufficient. The total  
delay necessary for 5 MHz operation is at most 3.4 μs. This is  
not a concern when using I2C mode because the communication  
rate is low enough to ensure a sufficient delay between FIFO reads.  
Rev. 0 | Page 20 of 40  
 
 
ADXL3ꢀ1  
SELF-TEST  
Table 14. Self-Test Output Scale Factors for Different Supply  
Voltages, VS  
The ADXL346 incorporates a self-test feature that effectively  
tests its mechanical and electronic systems simultaneously.  
When the self-test function is enabled (via the SELF_TEST bit  
(Bit D7 in the DATA_FORMAT register, Address 0x31), an  
electrostatic force is exerted on the mechanical sensor. This  
electrostatic force moves the mechanical sensing element in the  
same manner as acceleration would, and it is additive to the  
acceleration experienced by the device. This added electrostatic  
force results in an output change in the x-, y-, and z-axes. Because  
Supply Voltage, VS X-, Y-Axes  
Z-Axis  
0.38  
0.ꢁ7  
0.ꢂ8  
1.00  
1.11  
1.70 V  
1.80 V  
2.00 V  
2.60 V  
2.7ꢂ V  
0.ꢁ3  
0.ꢁ8  
0.ꢂ9  
1.00  
1.13  
Table 15. Self-Test Output in LSB for 2 g, 10-Bit or Full  
Resolution (TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V)  
2
the electrostatic force is proportional to VS , the output change  
varies with VS. This effect is shown in Figure 42.  
Axis  
Min  
Max  
ꢁ00  
−70  
ꢂ00  
Unit  
LSB  
LSB  
LSB  
X
Y
Z
70  
−ꢁ00  
100  
The scale factors listed in Table 14 can be used to adjust the  
expected self-test output limits for different supply voltages, VS.  
The self-test feature of the ADXL346 also exhibits a bimodal  
behavior. However, the limits listed in Table 1 and Table 15 to  
Table 18 are valid for both potential self-test values due to bi-  
modality. Use of the self-test feature at data rates less than 100 Hz  
or at 1600 Hz may yield values outside these limits. Therefore,  
the part must be in normal power operation (LOW_POWER  
bit = 0 in the BW_RATE register, Address 0x2C) and be placed  
into a data rate of 100 Hz through 800 Hz or 3200 Hz for the  
self-test function to operate correctly.  
Table 16. Self-Test Output in LSB for 4 g, 10-Bit Resolution  
(TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V)  
Axis  
Min  
Max  
200  
−3ꢂ  
2ꢂ0  
Unit  
LSB  
LSB  
LSB  
X
Y
Z
3ꢂ  
−200  
ꢂ0  
Table 17. Self-Test Output in LSB for 8 g, 10-Bit Resolution  
(TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V)  
3
X-AXIS SELF-TEST HIGH LIMIT  
Axis  
Min  
Max  
100  
−17  
12ꢂ  
Unit  
LSB  
LSB  
LSB  
Y-AXIS SELF-TEST HIGH LIMIT  
Z-AXIS SELF-TEST HIGH LIMIT  
X-AXIS SELF-TEST LOW LIMIT  
Y-AXIS SELF-TEST LOW LIMIT  
Z-AXIS SELF-TEST LOW LIMIT  
2
X
Y
Z
17  
−100  
2ꢂ  
1
0
Table 18. Self-Test Output in LSB for 16 g, 10-Bit Resolution  
(TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V)  
Axis  
Min  
Max  
Unit  
LSB  
LSB  
LSB  
–1  
–2  
–3  
X
Y
Z
8
−ꢂ0  
12  
ꢂ0  
−8  
63  
1.6  
1.8  
2.0  
2.2  
2.4  
2.6  
2.8  
SUPPLY VOLTAGE, V (V)  
S
Figure 42. Self-Test Output Change Limits vs. Supply Voltage  
Rev. 0 | Page 21 of 40  
 
 
 
 
 
 
 
ADXL3ꢀ1  
REGISTER MAP  
Table 19. Register Map  
Address  
Hex  
Dec  
0
Name  
Type  
Reset Value Description  
0x00  
0x01 to 0x1C  
0x1D  
0x1E  
0x1F  
0x20  
0x21  
0x22  
0x23  
0x2ꢁ  
0x2ꢂ  
0x26  
0x27  
0x28  
0x29  
0x2A  
0x2B  
0x2C  
0x2D  
0x2E  
0x2F  
0x30  
0x31  
0x32  
0x33  
0x3ꢁ  
0x3ꢂ  
0x36  
0x37  
0x38  
0x39  
0x3A  
0x3B  
0x3C  
DEVID  
R
11100110  
Device ID.  
1 to 28  
29  
30  
31  
32  
33  
3ꢁ  
3ꢂ  
36  
37  
38  
39  
ꢁ0  
ꢁ1  
ꢁ2  
ꢁ3  
ꢁꢁ  
ꢁꢂ  
ꢁ6  
ꢁ7  
ꢁ8  
ꢁ9  
ꢂ0  
ꢂ1  
ꢂ2  
ꢂ3  
ꢂꢁ  
ꢂꢂ  
ꢂ6  
ꢂ7  
ꢂ8  
ꢂ9  
60  
Reserved  
THRESH_TAP  
OFSX  
Reserved. Do not access.  
Tap threshold.  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
R/W  
R/W  
R/W  
R/W  
R
R/W  
R
R
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00001010  
00000000  
00000000  
00000000  
00000010  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00000000  
00100101  
00000000  
X-axis offset.  
OFSY  
Y-axis offset.  
OFSZ  
Z-axis offset.  
DUR  
Tap duration.  
Latent  
Tap latency.  
Window  
Tap window.  
THRESH_ACT  
THRESH_INACT  
TIME_INACT  
ACT_INACT_CTL  
THRESH_FF  
TIME_FF  
Activity threshold.  
Inactivity threshold.  
Inactivity time.  
Axis enable control for activity and inactivity detection.  
Free-fall threshold.  
Free-fall time.  
TAP_AXES  
ACT_TAP_STATUS  
BW_RATE  
POWER_CTL  
INT_ENABLE  
INT_MAP  
INT_SOURCE  
DATA_FORMAT  
DATAX0  
DATAX1  
DATAY0  
DATAY1  
DATAZ0  
Axis control for single tap/double tap.  
Source of single tap/double tap.  
Data rate and power mode control.  
Power-saving features control.  
Interrupt enable control.  
Interrupt mapping control.  
Source of interrupts.  
Data format control.  
X-Axis Data 0.  
X-Axis Data 1.  
Y-Axis Data 0.  
Y-Axis Data 1.  
Z-Axis Data 0.  
R
R
R
R
R/W  
R
R
R/W  
R
DATAZ1  
Z-Axis Data 1.  
FIFO control.  
FIFO_CTL  
FIFO_STATUS  
TAP_SIGN  
ORIENT_CONF  
Orient  
FIFO status.  
Sign and source for single tap/double tap.  
Orientation configuration.  
Orientation status.  
Rev. 0 | Page 22 of 40  
 
ADXL3ꢀ1  
Register 0x24—THRESH_ACT (Read/Write)  
REGISTER DEFINITIONS  
The THRESH_ACT register is eight bits and holds the threshold  
value for detecting activity. The data format is unsigned, so the  
magnitude of the activity event is compared with the value in  
the THRESH_ACT register. The scale factor is 62.5 mg/LSB.  
A value of 0 may result in undesirable behavior if the activity  
interrupt is enabled.  
Register 0x00—DEVID (Read Only)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
1
1
1
0
0
1
1
0
The DEVID register holds a fixed device ID code of 0xE6  
(346 octal).  
Register 0x1D—THRESH_TAP (Read/Write)  
Register 0x25—THRESH_INACT (Read/Write)  
The THRESH_TAP register is eight bits and holds the threshold  
value for tap interrupts. The data format is unsigned, so the  
magnitude of the tap event is compared with the value in  
THRESH_TAP for normal tap detection. For information on  
improved tap detection, refer to the Improved Tap Detection  
section. The scale factor is 62.5 mg/LSB (that is, 0xFF = +16 g).  
A value of 0 may result in undesirable behavior if single-tap/  
double-tap interrupts are enabled.  
The THRESH_INACT register is eight bits and holds the threshold  
value for detecting inactivity. The data format is unsigned, so  
the magnitude of the inactivity event is compared with the value  
in the THRESH_INACT register. The scale factor is 62.5 mg/LSB.  
A value of 0 may result in undesirable behavior if the inactivity  
interrupt is enabled.  
Register 0x26—TIME_INACT (Read/Write)  
The TIME_INACT register is eight bits and contains an unsigned  
time value representing the amount of time that acceleration  
must be less than the value in the THRESH_INACT register for  
inactivity to be declared. The scale factor is 1 sec/LSB. Unlike  
the other interrupt functions, which use unfiltered data (see the  
Threshold section), the inactivity function uses filtered output  
data. At least one output sample must be generated for the  
inactivity interrupt to be triggered. This results in the function  
appearing unresponsive if the TIME_INACT register is set to a  
value less than the time constant of the output data rate. A value  
of 0 results in an interrupt when the output data is less than the  
value in the THRESH_INACT register.  
Register 0x1E, Register 0x1F, Register 0x20—OFSX,  
OFSY, OFSZ (Read/Write)  
The OFSX, OFSY, and OFSZ registers are each eight bits and  
offer user-set offset adjustments in twos complement format  
with a scale factor of 15.6 mg/LSB (that is, 0x7F = 2 g). The  
values stored in the offset registers are automatically added to  
the acceleration data, and the resulting value is stored in the  
output data registers. For additional information regarding  
offset calibration and the use of the offset registers, refer to the  
Offset Calibration section.  
Register 0x21—DUR (Read/Write)  
The DUR register is eight bits and contains an unsigned time  
value representing the maximum time that an event must be  
above the THRESH_TAP threshold to qualify as a tap event. For  
information on improved tap detection, refer to the Improved Tap  
Detection section. The scale factor is 625 ꢀs/LSB. A value of 0  
disables the single-tap/double-tap functions.  
Register 0x27—ACT_INACT_CTL (Read/Write)  
D7  
D6  
D5  
D4  
ACT ac/dc  
D3  
ACT_X enable  
ACT_Y enable  
ACT_Z enable  
D2  
D1  
D0  
INACT ac/dc INACT_X enable INACT_Y enable INACT_Z enable  
ACT AC/DC and INACT AC/DC Bits  
Register 0x22—Latent (Read/Write)  
A setting of 0 selects dc-coupled operation, and a setting of 1  
enables ac-coupled operation. In dc-coupled operation, the  
current acceleration magnitude is compared directly with  
THRESH_ACT and THRESH_INACT to determine whether  
activity or inactivity is detected.  
The latent register is eight bits and contains an unsigned time  
value representing the wait time from the detection of a tap  
event to the start of the time window (defined by the window  
register) during which a possible second tap event can be detected.  
For information on improved tap detection, refer to the Improved  
Tap Detection section. The scale factor is 1.25 ms/LSB. A value of 0  
disables the double-tap function.  
In ac-coupled operation for activity detection, the acceleration  
value at the start of activity detection is taken as a reference  
value. New samples of acceleration are then compared to this  
reference value, and if the magnitude of the difference exceeds  
the THRESH_ACT value, the device triggers an activity interrupt.  
Register 0x23—Window (Read/Write)  
The window register is eight bits and contains an unsigned time  
value representing the amount of time after the expiration of the  
latency time (determined by the latent register) during which a  
second valid tap can begin. For information on improved tap  
detection, refer to the Improved Tap Detection section. The scale  
factor is 1.25 ms/LSB. A value of 0 disables the double-tap  
function.  
Similarly, in ac-coupled operation for inactivity detection, a  
reference value is used for comparison and is updated whenever  
the device exceeds the inactivity threshold. After the reference  
value is selected, the device compares the magnitude of the  
difference between the reference value and the current acceleration  
with THRESH_INACT. If the difference is less than the value in  
THRESH_INACT for the time in TIME_INACT, the device is  
considered inactive and the inactivity interrupt is triggered.  
Rev. 0 | Page 23 of 40  
 
ADXL3ꢀ1  
Register 0x2B—ACT_TAP_STATUS (Read Only)  
ACT_x Enable Bits and INACT_x Enable Bits  
D7 D6  
ACT_X ACT_Y ACT_Z Asleep TAP_X TAP_Y TAP_Z  
source source source source source source  
D5  
D4  
D3  
D2  
D1  
D0  
A setting of 1 enables x-, y-, or z-axis participation in detecting  
activity or inactivity. A setting of 0 excludes the selected axis from  
participation. If all axes are excluded, the function is disabled.  
For activity detection, all participating axes are logically ORed,  
causing the activity function to trigger when any of the partici-  
pating axes exceeds the threshold. For inactivity detection, all  
participating axes are logically ANDed, causing the inactivity  
function to trigger only if all participating axes are below the  
threshold for the specified period of time.  
0
ACT_x Source and TAP_x Source Bits  
These bits indicate the first axis involved in a tap or activity  
event. A setting of 1 corresponds to involvement in the event,  
and a setting of 0 corresponds to no involvement. When new  
data is available, these bits are not cleared but are overwritten by  
the new data. The ACT_TAP_STATUS register should be read  
before clearing the interrupt. Disabling an axis from participation  
clears the corresponding source bit when the next activity or  
single-tap/double-tap event occurs.  
Register 0x28—THRESH_FF (Read/Write)  
The THRESH_FF register is eight bits and holds the threshold  
value, in unsigned format, for free-fall detection. The acceleration  
on all axes is compared with the value in THRESH_FF to deter-  
mine if a free-fall event occurred. The scale factor is 62.5 mg/LSB.  
Note that a value of 0 mg may result in undesirable behavior if  
the free-fall interrupt is enabled. Values between 300 mg and  
600 mg (0x05 to 0x09) are recommended.  
Asleep Bit  
A setting of 1 in the asleep bit indicates that the part is asleep,  
and a setting of 0 indicates that the part is not asleep. This bit  
toggles only if the device is configured for autosleep. See the  
Register 0x2D—POWER_CTL (Read/Write) section for more  
information on autosleep mode.  
Register 0x29—TIME_FF (Read/Write)  
The TIME_FF register is eight bits and stores an unsigned time  
value representing the minimum time that the value of all axes  
must be less than THRESH_FF to generate a free-fall interrupt.  
The scale factor is 5 ms/LSB. A value of 0 may result in undesirable  
behavior if the free-fall interrupt is enabled. Values between 100 ms  
and 350 ms (0x14 to 0x46) are recommended.  
Register 0x2C—BW_RATE (Read/Write)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Rate  
D0  
0
0
0
LOW_POWER  
LOW_POWER Bit  
A setting of 0 in the LOW_POWER bit selects normal operation,  
and a setting of 1 selects reduced power operation, which is  
associated with somewhat higher noise (see the Power Modes  
section for details).  
Register 0x2A—TAP_AXES (Read/Write)  
D7  
D6  
D5  
D4  
Improved Suppress TAP_X TAP_Y  
tap  
D3  
D2  
D1  
D0  
0
0
0
TAP_Z  
enable enable enable  
Rate Bits  
Improved Tap Bit  
These bits select the device bandwidth and output data rate (see  
Table 7 and Table 8 for details). The default value is 0x0A, which  
translates to a 100 Hz output data rate. An output data rate should  
be selected that is appropriate for the communication protocol and  
frequency selected. Selecting too high of an output data rate with a  
low communication speed results in samples being discarded.  
The improved tap bit is used to enable improved tap detection.  
This mode of operation improves tap detection by performing  
an ac-coupled differential comparison of the output acceleration  
data. The improved tap detection is performed on the same output  
data available in the DATAX, DATAY, and DATAZ registers. Due  
to the dependency on the output data rate and the ac-coupled  
differential measurement, the threshold and timing values for  
single taps and double taps must be adjusted for improved tap  
detection. For further explanation of improved tap detection, see  
the Improved Tap Detection section. Improved tap is enabled  
by setting the improved tap bit to a value of 1 and is disabled  
by clearing the bit to a value of 0.  
Register 0x2D—POWER_CTL (Read/Write)  
D7 D6 D5  
D4  
D3  
D2  
D1 D0  
0
0
Link AUTO_SLEEP Measure Sleep Wakeup  
Link Bit  
A setting of 1 in the link bit with both the activity and inactivity  
functions enabled delays the start of the activity function until  
inactivity is detected. After activity is detected, inactivity detection  
begins, preventing the detection of activity. This bit serially links  
the activity and inactivity functions. When this bit is set to 0,  
the inactivity and activity functions are concurrent. Additional  
information can be found in the Link Mode section.  
Suppress Bit  
Setting the suppress bit suppresses double-tap detection if  
acceleration greater than the value in THRESH_TAP is present  
between taps. See the Tap Detection section for more details.  
TAP_x Enable Bits  
A setting of 1 in the TAP_X enable, TAP_Y enable, or TAP_Z  
enable bit enables x-, y-, or z-axis participation in tap detection.  
A setting of 0 excludes the selected axis from participation in  
tap detection.  
Rev. 0 | Page 2ꢁ of ꢁ0  
 
 
ADXL3ꢀ1  
When clearing the link bit, it is recommended that the part be  
placed into standby mode and then set back to measurement  
mode with a subsequent write. This is done to ensure that the  
device is properly biased if sleep mode is manually disabled;  
otherwise, the first few samples of data after the link bit is cleared  
may have additional noise, especially if the device was asleep  
when the bit was cleared.  
Wakeup Bits  
These bits control the frequency of readings in sleep mode as  
described in Table 20.  
Table 20. Frequency of Readings in Sleep Mode  
Setting  
D1  
0
0
1
1
D0  
0
1
0
1
Frequency (Hz)  
8
2
1
AUTO_SLEEP Bit  
If the link bit is set, a setting of 1 in the AUTO_SLEEP bit enables  
the autosleep functionality. In this mode, the ADXL346 auto-  
matically switches to sleep mode if the inactivity function is  
enabled and inactivity is detected (that is, when acceleration is  
below the THRESH_INACT value for at least the time indicated  
by TIME_INACT). If activity is also enabled, the ADXL346  
automatically wakes up from sleep after detecting activity and  
returns to operation at the output data rate set in the BW_RATE  
register. A setting of 0 in the AUTO_SLEEP bit disables automatic  
switching to sleep mode. See the description of the sleep bit in this  
section for more information on sleep mode.  
Register 0x2E—INT_ENABLE (Read/Write)  
D7  
DATA_READY  
D3  
Inactivity  
D6  
D5  
D4  
Activity  
D0  
Overrun/  
orientation  
SINGLE_TAP  
D2  
FREE_FALL  
DOUBLE_TAP  
D1  
Watermark  
Setting bits in this register to a value of 1 enables their respective  
functions to generate interrupts, whereas a value of 0 prevents  
the functions from generating interrupts. The DATA_READY,  
watermark, and overrun/orientation bits enable only the interrupt  
output; the functions are always enabled. It is recommended that  
interrupts be configured before enabling their outputs.  
If the link bit is not set, the AUTO_SLEEP feature is disabled,  
and setting the AUTO_SLEEP bit does not have any impact on  
device operation. Refer to the Link Bit section or the Link Mode  
section for more information about using the link feature.  
When clearing the AUTO_SLEEP bit, it is recommended that the  
part be placed into standby mode and then set back to measure-  
ment mode with a subsequent write. This is done to ensure that  
the device is properly biased if sleep mode is manually disabled;  
otherwise, the first few samples of data after the AUTO_SLEEP  
bit is cleared may have additional noise, especially if the device  
was asleep when the bit was cleared.  
Register 0x2F—INT_MAP (Read/Write)  
D7  
DATA_READY  
D3  
Inactivity  
D6  
D5  
D4  
Activity  
D0  
Overrun/  
orientation  
SINGLE_TAP  
D2  
FREE_FALL  
DOUBLE_TAP  
D1  
Watermark  
Measure Bit  
Bits set to 0 in this register send their respective interrupts to the  
INT1 pin, whereas bits set to 1 send their respective interrupts to  
the INT2 pin. All selected interrupts for a given pin are ORed.  
A setting of 0 in the measure bit places the part into standby mode,  
and a setting of 1 places the part into measurement mode. The  
ADXL346 powers up in standby mode with minimum power  
consumption.  
Register 0x30—INT_SOURCE (Read Only)  
D7  
D6  
D5  
D4  
DATA_READY  
D3  
Inactivity  
SINGLE_TAP  
D2  
FREE_FALL  
DOUBLE_TAP  
D1  
Watermark  
Activity  
D0  
Overrun/  
Sleep Bit  
A setting of 0 in the sleep bit puts the part into the normal mode  
of operation, and a setting of 1 places the part into sleep mode.  
Sleep mode suppresses DATA_READY, stops transmission of data  
to FIFO, and switches the sampling rate to one specified by the  
wakeup bits. In sleep mode, only the activity function can be used.  
While the DATA_READY interrupt is suppressed, the output  
data registers are still updated at the sampling rate set by the  
wakeup bits.  
orientation  
Bits set to 1 in this register indicate that their respective functions  
have triggered an event, whereas bits set to 0 indicate that the  
corresponding events have not occurred. The DATA_READY,  
watermark, and overrun/orientation bits are always set if the  
corresponding events occur, regardless of the INT_ENABLE  
register settings, and are cleared by reading data from the  
DATAX, DATAY, and DATAZ registers. The DATA_READY and  
watermark bits may require multiple reads, as indicated in the  
FIFO mode descriptions in the FIFO section. Other bits, and the  
corresponding interrupts, including orientation if enabled, are  
cleared by reading the INT_SOURCE register.  
When clearing the sleep bit, it is recommended that the part be  
placed into standby mode and then set back to measurement  
mode with a subsequent write. This is done to ensure that the  
device is properly biased if sleep mode is manually disabled;  
otherwise, the first few samples of data after the sleep bit is  
cleared may have additional noise, especially if the device was  
asleep when the bit was cleared.  
Rev. 0 | Page 2ꢂ of 40  
 
ADXL3ꢀ1  
Register 0x31—DATA_FORMAT (Read/Write)  
and DATAx1 as the most significant byte, where x represents X,  
Y, or Z. The DATA_FORMAT register (Address 0x31) controls  
the format of the data. It is recommended that a multiple-byte  
read of all registers be performed to prevent a change in data  
between reads of sequential registers.  
D7  
D6 D5  
D4 D3  
D2  
D1 D0  
SELF_TEST SPI INT_INVERT  
0
FULL_RES Justify  
Range  
The DATA_FORMAT register controls the presentation of data  
to Register 0x32 through Register 0x37. All data, except that for  
the 16 g range, must be clipped to avoid rollover.  
Register 0x38—FIFO_CTL (Read/Write)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
SELF_TEST Bit  
FIFO_MODE Trigger  
Samples  
A setting of 1 in the SELF_TEST bit applies a self-test force to  
the sensor, causing a shift in the output data. A value of 0 disables  
the self-test force.  
FIFO_MODE Bits  
These bits set the FIFO mode, as described in Table 22.  
SPI Bit  
Table 22. FIFO Modes  
A value of 1 in the SPI bit sets the device to 3-wire SPI mode,  
and a value of 0 sets the device to 4-wire SPI mode.  
Setting  
D7  
0
D6  
0
Mode  
Bypass  
FIFO  
Function  
FIFO is bypassed.  
INT_INVERT Bit  
0
1
FIFO collects up to 32 values and then  
stops collecting dataꢀ collecting new  
data only when FIFO is not full.  
A value of 0 in the INT_INVERT bit sets the interrupts to active  
high, and a value of 1 sets the interrupts to active low.  
1
1
0
1
Stream  
Trigger  
FIFO holds the last 32 data values.  
When FIFO is fullꢀ the oldest data is  
overwritten with newer data.  
When triggered by the trigger bitꢀ  
FIFO holds the last data samples  
before the trigger event and then  
continues to collect data until FIFO is  
full. New data is collected only when  
FIFO is not full.  
FULL_RES Bit  
When this bit is set to a value of 1, the device is in full resolution  
mode, where the output resolution increases with the g range  
set by the range bits to maintain a 4 mg/LSB scale factor. When  
the FULL_RES bit is set to 0, the device is in 10-bit mode, and  
the range bits determine the maximum g range and scale factor.  
Justify Bit  
A setting of 1 in the justify bit selects left-justified (MSB) mode,  
and a setting of 0 selects right-justified mode with sign extension.  
Trigger Bit  
A value of 0 in the trigger bit links the trigger event of trigger mode  
to INT1, and a value of 1 links the trigger event to INT2.  
Range Bits  
These bits set the g range as described in Table 21.  
Samples Bits  
The function of these bits depends on the FIFO mode selected (see  
Table 23). Entering a value of 0 in the samples bits immediately sets  
the watermark bit in the INT_SOURCE register (Address 0x30),  
regardless of which FIFO mode is selected. Undesirable operation  
may occur if a value of 0 is used for the samples bits when trigger  
mode is used.  
Table 21. g Range Setting  
Setting  
D1  
0
D0  
0
g Range  
2 g  
0
1
g  
1
0
8 g  
1
1
16 g  
Table 23. Samples Bits Functions  
FIFO Mode Samples Bits Function  
Register 0x32 to Register 0x37—DATAX0, DATAX1,  
DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)  
Bypass  
FIFO  
None.  
Specifies how many FIFO entries are needed to  
trigger a watermark interrupt.  
These six bytes (Register 0x32 to Register 0x37) are eight bits  
each and hold the output data for each axis. Register 0x32 and  
Register 0x33 hold the output data for the x-axis, Register 0x34 and  
Register 0x35 hold the output data for the y-axis, and Register 0x36  
and Register 0x37 hold the output data for the z-axis. The output  
data is twos complement, with DATAx0 as the least significant byte  
Stream  
Trigger  
Specifies how many FIFO entries are needed to  
trigger a watermark interrupt.  
Specifies how many FIFO samples are retained in  
the FIFO buffer before a trigger event.  
Rev. 0 | Page 26 of 40  
 
 
 
ADXL3ꢀ1  
Register 0x39—FIFO_STATUS (Read Only)  
An orientation interrupt is generated whenever the orientation  
status for the mode selected by the INT_3D bit changes in the  
orient register (Address 0x3C). The orientation interrupt is  
cleared by reading the INT_SOURCE register. Clearing the  
INT_ORIENT bit, or the orientation bit in the INT_ENABLE  
register (Address 0x2E), disables and clears the interrupt.  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
FIFO_TRIG  
0
Entries  
FIFO_TRIG Bit  
A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,  
and a 0 means that a FIFO trigger event has not occurred.  
Writing to the BW_RATE register (Address 0x2C) or placing  
the part into standby mode resets the orientation feature, clearing  
the orientation filter and the interrupt. However, resetting the  
orientation feature also resets the orientation status in the orient  
register (Address 0x3C) and, therefore, causes an interrupt to be  
generated when the next output sample is available if the present  
orientation is not the default orientation. A value of 0 for the  
INT_ORIENT bit disables generation of the orientation interrupt  
and permits the use of the overrun function.  
Entries Bits  
These bits report how many data values are stored in FIFO.  
Access to collect the data from FIFO is provided through the  
DATAX, DATAY, and DATAZ registers. FIFO reads must be  
done in burst or multiple-byte mode because each FIFO level is  
cleared after any read (single- or multiple-byte) of FIFO. FIFO  
stores a maximum of 32 entries, which equates to a maximum  
of 33 entries available at any given time because an additional  
entry is available at the output filter of the device.  
Dead Zone Bits  
Register 0x3A—TAP_SIGN (Read Only)  
These bits determine the region between two adjacent orientations,  
where the orientation is considered invalid and is not updated. A  
value of 0 may result in undesirable behavior when the orientation  
is close to the bisector between two adjacent regions. The dead zone  
angle is determined by these bits, as described in Table 24. See the  
Orientation Sensing section for more details.  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
XSIGN YSIGN ZSIGN  
0
XTAP YTAP ZTAP  
xSIGN Bits  
These bits indicate the sign of the first axis involved in a tap  
event. A setting of 1 corresponds to acceleration in the negative  
direction, and a setting of 0 corresponds to acceleration in the  
positive direction. These bits update only when a new single-  
tap/double-tap event is detected, and only the axes enabled in the  
TAP_AXES register (Address 0x2A) are updated. The TAP_SIGN  
register should be read before clearing the interrupt. See the Tap  
Sign section for more details.  
Table 24. Dead Zone and Divisor Codes  
Dead Zone Angle Divisor  
Decimal  
Binary  
000  
001  
010  
011  
100  
101  
110  
111  
(Degrees)  
Bandwidth (Hz)  
0
1
2
3
6
7
ꢂ.1  
ODR/9  
10.2  
ODR/22  
1ꢂ.2  
ODR/ꢂ0  
20.ꢁ  
ODR/100  
ODR/200  
ODR/ꢁ00  
ODR/800  
ODR/1600  
xTAP Bits  
2ꢂ.ꢂ  
These bits indicate the first axis involved in a tap event. A  
setting of 1 corresponds to involvement in the event, and a  
setting of 0 corresponds to no involvement. When new data is  
available, these bits are not cleared but are overwritten by the  
new data. The TAP_SIGN register should be read before clearing  
the interrupt. Disabling an axis from participation clears the  
corresponding source bit when the next single-tap/double-tap  
event occurs.  
30.8  
36.1  
ꢁ1.ꢁ  
INT_3D Bit  
If the orientation interrupt is enabled, the INT_3D bit determines  
whether 2D or 3D orientation detection generates an interrupt.  
A value of 0 generates an interrupt only if the 2D orientation  
changes from a valid 2D orientation to a different valid 2D  
orientation. A value of 1 generates an interrupt only if the 3D  
orientation changes from a valid 3D orientation to a different  
valid 3D orientation.  
Register 0x3B—ORIENT_CONF (Read/Write)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
INT_  
ORIENT  
Dead zone  
INT_  
3D  
Divisor  
INT_ORIENT Bit  
Divisor Bits  
Setting the INT_ORIENT bit enables the orientation interrupt.  
A value of 1 overrides the overrun function of the device and  
replaces overrun in the INT_MAP (Address 0x2F), INT_ENABLE  
(Address 0x2E), and INT_SOURCE (Address 0x30) registers with  
the orientation function. After setting the INT_ORIENT bit, the  
orientation bits in the INT_MAP and INT_ENABLE registers must  
be configured to map the orientation interrupt to INT1 or INT2  
and to enable generation of the interrupt to the pin.  
These bits set the bandwidth of the filter used to low-pass filter the  
measured acceleration for stable orientation sensing. The divisor  
bandwidth is determined by these bits, as detailed in Table 24,  
where ODR is the output data rate set in the BW_RATE register  
(Address 0x2C). See the Orientation Sensing section for more  
details.  
Rev. 0 | Page 27 of 40  
 
 
ADXL3ꢀ1  
Register 0x3C—Orient (Read Only)  
Writing to the BW_RATE register (Address 0x2C) or placing  
the part into standby mode resets the orientation feature, clearing  
the orientation filter and the orientation status. An orientation  
interrupt (if enabled) results from these actions if the orientation  
during the next output sample is different from the default  
value (+X for 2D orientation detection and undefined for 3D  
orientation).  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
V2  
2D_ORIENT  
V3  
3D_ORIENT  
Vx Bits  
These bits show the validity of the 2D (V2) and 3D (V3) orienta-  
tions. A value of 1 corresponds to the orientation being valid. A  
value of 0 means that the orientation is invalid because the current  
orientation is in the dead zone.  
Table 25. 2D Orientation Codes  
Decimal  
Binary Orientation  
Dominant Axis  
xD_ORIENT Bits  
0
1
2
3
00  
01  
10  
11  
Portrait positive  
+X  
−X  
+Y  
−Y  
These bits represent the current 2D (2D_ORIENT) and 3D  
(3D_ORIENT) orientations of the accelerometer. If the orien-  
tation interrupt is enabled, this register is read to determine the  
orientation of the device when the interrupt occurs. Because this  
register updates with each new sample of acceleration data, it  
should be read at the time of the orientation interrupt to ensure  
that the orientation change that caused the interrupt has been  
identified. Orientation values are shown in Table 25 and Table 26.  
See the Orientation Sensing section for more details.  
Portrait negative  
Landscape positive  
Landscape negative  
Table 26. 3D Orientation Codes  
Decimal  
Binary Orientation  
Dominant Axis  
3
2
1
6
011  
100  
010  
101  
001  
110  
Front  
Back  
Left  
+X  
−X  
+Y  
−Y  
+Z  
−Z  
Right  
Top  
Bottom  
Rev. 0 | Page 28 of 40  
 
 
ADXL3ꢀ1  
APPLICATIONS INFORMATION  
POWER SUPPLY DECOUPLING  
TAP DETECTION  
The tap interrupt function is capable of detecting either single  
or double taps. The following parameters are shown in Figure 45  
for a valid single-tap event and a valid double-tap event:  
A 1 μF tantalum capacitor (CS) at VS and a 0.1 μF ceramic capacitor  
(CI/O) at VDD I/O placed close to the ADXL346 supply pins is  
recommended to adequately decouple the accelerometer from  
noise on the power supply. If additional decoupling is necessary,  
a resistor or ferrite bead, no larger than 100 Ω, in series with VS  
may be helpful. Additionally, increasing the bypass capacitance  
on VS to a 10 μF tantalum capacitor in parallel with a 0.1 μF  
ceramic capacitor may also improve noise.  
The tap detection threshold is defined by the THRESH_TAP  
register (Address 0x1D).  
The maximum tap duration time is defined by the DUR  
register (Address 0x21).  
The tap latency time is defined by the latent register  
(Address 0x22) and is the waiting period from the end of  
the first tap until the start of the time window when a  
second tap can be detected, which is determined by the  
value in the window register (Address 0x23).  
Care should be taken to ensure that the connection from the  
ADXL346 ground to the power supply ground has low impedance  
because noise transmitted through ground has an effect similar  
to noise transmitted through VS. It is recommended that VS and  
VDD I/O be separate supplies to minimize digital clock noise on  
the VS supply. If this is not possible, additional filtering of the  
supplies as previously mentioned may be necessary.  
The interval after the latency time (set by the latent register) is  
defined by the window register. Although a second tap must  
begin after the latency time has expired, it need not finish  
before the end of the time defined by the window register.  
V
V
S
DD I/O  
C
C
I/O  
S
FIRST TAP  
SECOND TAP  
V
V
S
DD I/O  
ADXL346  
SDA/SDI/SDIO  
THRESHOLD  
(THRESH_TAP)  
3-WIRE OR  
4-WIRE SPI  
OR I C  
SDO/ALT ADDRESS  
SCL/SCLK  
INT1  
INT2  
INTERRUPT  
CONTROL  
2
INTERFACE  
CS  
GND  
TIME LIMIT FOR  
TAPS (DUR)  
Figure 43. Applications Diagram  
TIME WINDOW FOR  
SECOND TAP (WINDOW)  
LATENCY  
TIME  
(LATENT)  
MECHANICAL CONSIDERATIONS FOR MOUNTING  
The ADXL346 should be mounted on the PCB in a location  
close to a hard mounting point of the PCB to the case. Mounting  
the ADXL346 at an unsupported PCB location, as shown in  
Figure 44, may result in large, apparent measurement errors due  
to undampened PCB vibration. Locating the accelerometer near  
a hard mounting point ensures that any PCB vibration at the  
accelerometer is above the accelerometers mechanical sensor  
resonant frequency and, therefore, effectively invisible to the  
accelerometer. Multiple mounting points, close to the sensor,  
and/or a thicker PCB also help to reduce the effect of system  
resonance on the performance of the sensor.  
SINGLE-TAP  
INTERRUPT  
DOUBLE-TAP  
INTERRUPT  
Figure 45. Tap Interrupt Function with Valid Single and Double Taps  
If only the single-tap function is in use, the single-tap interrupt  
is triggered when the acceleration goes below the threshold, as  
long as DUR has not been exceeded. If both single and double-  
tap functions are in use, the single-tap interrupt is triggered  
when the double-tap event has been either validated or  
invalidated.  
Several events can occur to invalidate the second tap of a  
double-tap event. First, if the suppress bit in the TAP_AXES  
register (Address 0x2A) is set, any acceleration spike above the  
threshold during the latency time (set by the latent register)  
invalidates the double-tap detection, as shown in Figure 46.  
ACCELEROMETERS  
PCB  
MOUNTING POINTS  
Figure 44. Incorrectly Placed Accelerometers  
Rev. 0 | Page 29 of 40  
 
 
 
 
ADXL3ꢀ1  
INVALIDATES DOUBLE TAP IF  
SUPRESS BIT IS SET  
DUR, latent, window, and THRESH_TAP registers is required.  
In general, a good starting point is to set the DUR register to a  
value greater than 0x10 (10 ms), the latent register to a value greater  
than 0x10 (20 ms), the window register to a value greater than  
0x40 (80 ms), and the THRESH_TAP register to a value greater  
than 0x30 (3 g). Setting a very low value in the latent, window, or  
THRESH_TAP register may result in an unpredictable response  
due to the accelerometer picking up echoes of the tap inputs.  
TIME LIMIT  
FOR TAPS  
(DUR)  
LATENCY  
TIME (LATENT)  
TIME WINDOW FOR SECOND  
TAP (WINDOW)  
After a tap interrupt has been received, the first axis to exceed  
the THRESH_TAP level is reported in the ACT_TAP_STATUS  
register (Address 0x2B). This register is never cleared but is  
overwritten with new data.  
Figure 46. Double-Tap Event Invalid Due to High g Event  
When the Suppress Bit Is Set  
A double-tap event can also be invalidated if acceleration above  
the threshold is detected at the start of the time window for the  
second tap (set by the window register (Address 0x23)). This results  
in an invalid double tap at the start of this window, as shown in  
Figure 47. Additionally, a double-tap event can be invalidated if  
an acceleration exceeds the time limit for taps (set by the DUR  
register (Address 0x21)), resulting in an invalid double tap at  
the end of the DUR time limit for the second tap event, also  
shown in Figure 47.  
IMPROVED TAP DETECTION  
Improved tap detection is enabled by setting the improved tap  
bit of the TAP_AXES register (Address 0x2A). When improved  
tap detection is enabled, the filtered output data corresponding to  
the output data rate set in the BW_RATE register (Address 0x2C)  
is processed to determine if a tap event occurred. In addition, an  
ac-coupled differential measurement is used. This results in the  
timing values and threshold values for improved tap detection  
being different from those used for normal tap detection.  
INVALIDATES DOUBLE TAP  
AT START OF WINDOW  
When improved tap detection is used, new values must be  
determined based on test results. In general, no timing values  
(in the DUR, latent, or window registers) should be set that are  
less than the time step resolution set by the output data rate.  
The threshold value for improved tap detection can typically be  
set much lower than the threshold for normal tap detection.  
The value used depends on the value in the BW_RATE register  
and should be determined through system testing. Refer to the  
Threshold section for more details.  
TIME LIMIT  
FOR TAPS  
(DUR)  
TIME LIMIT  
FOR TAPS  
(DUR)  
LATENCY  
TIME  
(LATENT)  
TIME WINDOW FOR  
SECOND TAP (WINDOW)  
TAP SIGN  
TIME LIMIT  
A negative sign is produced by experiencing a negative accel-  
eration, which corresponds to tapping on the positive face of the  
device for the desired axis. The positive face of the device is the  
face such that movement in that direction is positive acceleration.  
For example, tapping on the face that corresponds to the +X  
direction, labeled as front in Figure 48, results in a negative sign  
for the x-axis. Tapping on the face labeled as left in Figure 48  
results in a negative sign for the y-axis, and tapping on the face  
labeled top results in a negative sign for the z-axis. Conversely,  
tapping on the back, right, or bottom sides results in positive  
signs for the corresponding axes.  
FOR TAPS  
(DUR)  
INVALIDATES  
DOUBLE TAP AT  
END OF DUR  
Figure 47. Tap Interrupt Function with Invalid Double Taps  
Single taps, double taps, or both can be detected by setting the  
respective bits in the INT_ENABLE register (Address 0x2E).  
Control over participation of each of the three axes in single-tap/  
double-tap detection is exerted by setting the appropriate bits in  
the TAP_AXES register (Address 0x2A). For the double-tap  
function to operate, both the latent and window registers must  
be set to a nonzero value.  
+z  
TOP  
(+Z)  
+y  
LEFT  
(+Y)  
Every mechanical system has somewhat different single-tap/  
double-tap responses based on the mechanical characteristics of  
the system. Therefore, some experimentation with values for the  
FRONT  
(+X)  
+x  
Figure 48. 3D Orientation with Coordinate System  
Rev. 0 | Page 30 of 40  
 
 
 
 
 
 
ADXL3ꢀ1  
and application of any compounds on or over the component. If  
calibration is deemed necessary, it is recommended that calibration  
be performed after system assembly to compensate for these effects.  
THRESHOLD  
The lower output data rates are achieved by decimating a  
common sampling frequency inside the device. The activity,  
free-fall, and single-tap/double-tap detection functions without  
improved tap enabled are performed using undecimated data.  
As the bandwidth of the output data varies with the data rate  
and is lower than the bandwidth of the undecimated data, the  
high frequency and high g data that is used to determine activity,  
free-fall, and single-tap/double-tap events may not be present if  
the output of the accelerometer is examined. This may result in  
functions triggering when acceleration data does not appear to  
meet the conditions set by the user for the corresponding function.  
A simple method of calibration is to measure the offset while  
assuming that the sensitivity of the ADXL346 is as specified in  
Table 1. The offset can then be automatically accounted for by  
using the built-in offset registers (Register 0x1E, Register 0x1F, and  
Register 0x20). This results in the data acquired from the DATAX,  
DATAY, and DATAZ registers (Address 0x32 to Address 0x37)  
already compensating for any offset.  
In a no-turn or single-point calibration scheme, the part is oriented  
such that one axis, typically the z-axis, is in the 1 g field of gravity  
and the remaining axes, typically the x- and y-axes, are in a 0 g  
field. The output is then measured by taking the average of a  
series of samples. The number of samples averaged is a choice of  
the system designer, but a recommended starting point is 0.1 sec  
worth of data for data rates of 100 Hz or greater. This corresponds  
to 10 samples at the 100 Hz data rate. For data rates of less than  
100 Hz, it is recommended that at least 10 samples be averaged  
together. These values are stored as X0g, Y0g, and Z+1g for the 0 g  
measurements on the x- and y-axes and the 1 g measurement  
on the z-axis, respectively.  
LINK MODE  
The function of the link bit is to reduce the number of activity  
interrupts that the processor must service by setting the device  
to look for activity only after inactivity. For proper operation of  
this feature, the processor must still respond to the activity and  
inactivity interrupts by reading the INT_SOURCE register  
(Address 0x30) and, therefore, clearing the interrupts. If an activity  
interrupt is not cleared, the part cannot go into autosleep mode.  
The asleep bit in the ACT_TAP_STATUS register (Address 0x2B)  
indicates whether the part is asleep.  
The values measured for X0g and Y0g correspond to the offset of  
the x- and y-axes, and compensation is done by subtracting those  
values from the output of the accelerometer to obtain the actual  
acceleration:  
SLEEP MODE VS. LOW POWER MODE  
In applications where a low data rate and low power consumption  
are desired (at the expense of noise performance), it is recom-  
mended that low power mode be used. The use of low power  
mode preserves the functionality of the DATA_READY interrupt  
and the FIFO for postprocessing of the acceleration data. Sleep  
mode, while offering a low data rate and power consumption, is  
not intended for data acquisition.  
X
ACTUAL = XMEAS X0g  
ACTUAL = YMEAS Y0g  
Y
Because the z-axis measurement is done in a 1 g field, a no-turn or  
single-point calibration scheme assumes an ideal sensitivity, SZ,  
for the z-axis. This is subtracted from Z+1g to attain the z-axis  
offset, which is then subtracted from future measured values to  
obtain the actual value:  
However, when sleep mode is used in conjunction with the  
AUTO_SLEEP mode and the link mode, the part can automatically  
switch to a low power, low sampling rate mode when inactivity  
is detected. To prevent the generation of redundant inactivity  
interrupts, the inactivity interrupt is automatically disabled  
and activity is enabled. When the ADXL346 is in sleep mode, the  
host processor can also be placed into sleep mode or low power  
mode to save significant system power. Once activity is detected,  
the accelerometer automatically switches back to the original  
data rate of the application and provides an activity interrupt  
that can be used to wake up the host processor. Similar to when  
inactivity occurs, detection of activity events is disabled and  
inactivity is enabled.  
Z0g = Z1g SZ  
Z
ACTUAL = ZMEAS Z0g  
The ADXL346 can automatically compensate the output for offset  
by using the offset registers (Register 0x1E, Register 0x1F, and  
Register 0x20). These registers contain an 8-bit, twos complement  
value that is automatically added to all measured acceleration  
values, and the result is then placed into the DATAX, DATAY,  
and DATAZ registers. Because the value placed in an offset register  
is additive, a negative value is placed into the register to eliminate a  
positive offset and vice versa for a negative offset. The register  
has a scale factor of 15.6 mg/LSB and is independent of the  
selected g range.  
OFFSET CALIBRATION  
Accelerometers are mechanical structures containing elements  
that are free to move. These moving parts can be very sensitive  
to mechanical stresses, much more so than solid-state electronics.  
The 0 g bias or offset is an important accelerometer metric because  
it defines the baseline for measuring acceleration. Additional  
stresses can be applied during assembly of a system containing  
an accelerometer. These stresses can come from, but are not  
limited to, component soldering, board stress during mounting,  
As an example, assume that the ADXL346 is placed into full-  
resolution mode with a sensitivity of typically 256 LSB/g. The  
part is oriented such that the z-axis is in the field of gravity and  
the outputs of the x-, y-, and z-axes are measured as +10 LSB,  
−13 LSB, and +9 LSB, respectively. Using the previous equations,  
X0g is +10 LSB, Y0g is −13 LSB, and Z0g is +9 LSB. Each LSB of  
Rev. 0 | Page 31 of 40  
 
 
 
 
ADXL3ꢀ1  
output in full-resolution is 3.9 mg or one-quarter of an LSB of  
the offset register.  
recommended that at least 10 samples be averaged together. The  
averaged values should be stored and labeled appropriately as the  
self-test disabled data, that is, XST_OFF, YST_OFF, and ZST_OFF  
.
Because the offset register is additive, the 0 g values are negated  
and rounded to the nearest LSB of the offset register:  
Next, self-test should be enabled by setting Bit D7 of the  
DATA_FORMAT register (Address 0x31). The output needs some  
time (about four samples) to settle once self-test is enabled. After  
allowing the output to settle, several samples of acceleration data  
for the x-, y-, and z-axes should be taken again and averaged. It  
is recommended that the same number of samples be taken for  
this average as was previously taken. These averaged values should  
again be stored and labeled appropriately as the value with self-  
test enabled, that is, XST_ON, YST_ON, and ZST_ON. Self-test can then  
be disabled by clearing Bit D7 of the DATA_FORMAT register  
(Address 0x31).  
X
OFFSET = −Round(10/4) = −3 LSB  
OFFSET = −Round(−13/4) = 3 LSB  
Y
Z
OFFSET = −Round(9/4) = −2 LSB  
These values are programmed into the OFSX, OFSY, and OFXZ  
registers, respectively, as 0xFD, 0x03, and 0xFE. As with all  
registers in the ADXL346, the offset registers do not retain the  
value written into them when power is removed from the part.  
Power-cycling the ADXL346 returns the offset registers to their  
default value of 0x00.  
With the stored values for self-test enabled and disabled, the  
self-test change is as follows:  
Because the no-turn or single-point calibration method assumes an  
ideal sensitivity in the z-axis, any error in the sensitivity results in  
offset error. For instance, if the actual sensitivity was 250 LSB/g  
in the previous example, the offset would be 15 LSB, not 9 LSB.  
To help minimize this error, an additional measurement point  
can be used with the z-axis in a 0 g field, and the 0 g measurement  
can be used in the ZACTUAL equation.  
X
ST = XST_ON XST_OFF  
ST = YST_ON YST_OFF  
Y
Z
ST = ZST_ON ZST_OFF  
Because the measured output for each axis is expressed in LSBs,  
XST, YST, and ZST are also expressed in LSBs. These values can be  
converted to gs of acceleration by multiplying each value by the  
3.9 mg/LSB scale factor, if configured for full-resolution mode.  
Additionally, Table 15 through Table 18 correspond to the self-test  
range converted to LSBs and can be compared with the measured  
self-test change when operating at a VS of 2.6 V. For other voltages,  
the minimum and maximum self-test output values should be  
adjusted based on (multiplied by) the scale factors shown in  
Table 14. If the part was placed into 2 g, 10-bit or full-resolution  
mode, the values listed in Table 15 should be used. Although  
the fixed 10-bit mode or a range other than 16 g can be used, a  
different set of values, as indicated in Table 16 through Table 18,  
would need to be used. Using a range below 8 g may result in  
insufficient dynamic range and should be considered when  
selecting the range of operation for measuring self-test.  
USING SELF-TEST  
The self-test change is defined as the difference between the  
acceleration output of an axis with self-test enabled and the  
acceleration output of the same axis with self-test disabled (see  
Endnote 7 of Table 1). This definition assumes that the sensor  
does not move between these two measurements, because if the  
sensor moves, a non–self-test related shift corrupts the test.  
Proper configuration of the ADXL346 is also necessary for an  
accurate self-test measurement. The part should be set with a data  
rate greater than or equal to 100 Hz. This is done by ensuring that  
a value greater than or equal to 0x0A is written into the rate bits  
(Bit D3 through Bit D0) in the BW_RATE register (Address 0x2C).  
The part also must be placed into normal power operation by  
ensuring that the LOW_POWER bit (Bit D4) in the BW_RATE  
register is cleared (LOW_POWER bit = 0) for accurate self-test  
measurements. It is recommended that the part be set to full-  
resolution, 16 g mode to ensure that there is sufficient dynamic  
range for the entire self-test shift. This is done by setting the  
FULL_RES bit (Bit D3) and writing a value of 0x03 to the range  
bits (Bit D1 and Bit D0) of the DATA_FORMAT register  
(Address 0x31). This results in a high dynamic range for  
measurement and a 3.9 mg/LSB scale factor.  
If the self-test change is within the valid range, the test is considered  
successful. Generally, a part is considered to pass if the minimum  
magnitude of change is achieved. However, a part that changes  
by more than the maximum magnitude is not necessarily a failure.  
ORIENTATION SENSING  
The orientation function of the ADXL346 reports both 2D  
and 3D orientation concurrently through the orient register  
(Address 0x3C). The V2 and V3 bits (Bit D6 and Bit D3 in the  
orient register) report the validity of the 2D and 3D orientation  
codes. If V2 or V3 are set, their respective code is a valid  
orientation. If V2 or V3 are cleared, the orientation of the  
accelerometer is unknown, such as when the orientation is  
within the dead zone between valid regions.  
After the part is configured for accurate self-test measurement,  
several samples of acceleration data for the x-, y-, and z-axes  
should be retrieved from the sensor and averaged together. The  
number of samples averaged is a choice of the system designer,  
but a recommended starting point is 0.1 sec worth of data for  
data rates of 100 Hz or greater. This corresponds to 10 samples  
at the 100 Hz data rate. For data rates of less than 100 Hz, it is  
Rev. 0 | Page 32 of 40  
 
 
ADXL3ꢀ1  
PORTRAIT  
For 2D orientation sensing, the relation of the x- and y-axes to  
gravity is used to determine the accelerometer orientation (see  
Figure 49 and Table 25). Portrait positive corresponds to the x-axis  
being most closely aligned to the gravity vector and directed  
upwards, opposite the gravity vector. Portrait negative is the  
opposite of portrait positive, with the x-axis pointing downwards  
along the gravity vector. Landscape positive corresponds to the  
y-axis being most closely aligned with the gravity vector and  
directed upwards, away from the gravity vector. Landscape  
negative is the orientation opposite landscape positive. The  
dead zone regions are shown in the orientations for portrait  
positive (+X) and portrait negative (−X) of Figure 49. These  
regions also exist for landscape positive (+Y) and landscape  
negative (−Y), as shown in Figure 49.  
POSITIVE (00)  
NEGATIVE (01)  
DEADZONES  
+X  
+Y  
+Y  
+g  
+g  
+X  
LANDSCAPE  
POSITIVE (10)  
+Y  
NEGATIVE (11)  
+g  
+g  
+X  
+X  
In 3D orientation, the z-axis is also included. If the accelerometer is  
placed in a Cartesian coordinate system, as shown in Figure 48 of  
the Tap Sign section, the top of the device corresponds to the  
positive z-axis direction, the front of the device corresponds to  
the positive x-axis direction, and the right side of the device  
corresponds to the positive y-axis direction.  
+Y  
Figure 49. 2D Orientation with Corresponding Codes  
The width of the dead zone region between two orientation  
positions is determined by setting the value of the dead zone bits  
(Bits[D6:D4]) in the ORIENT_CONF register (Address 0x3B).  
The dead zone region size can be specified as per the values  
shown in Table 24. The dead zone angle represents the total  
angle where the orientation is considered invalid. Therefore, a  
dead zone of 15.4° corresponds to 7.7° in either direction away  
from the bisector of two bordering regions. An example with a  
dead zone region of 15.4° is shown in Figure 50. It should be  
noted that the values shown in Table 24 correspond to the  
typical dead zone angle when the gravity vector is completely  
contained in only two axes (xy, xz, or yz) and should be used  
only as a starting point. If the device is oriented such that the  
projection of gravity onto all three axes is nonzero, the effective  
sensitivity is reduced, causing an increase in the dead zone angle.  
Therefore, evaluation needs to be performed for specific appli-  
cation uses to determine the optimal setting for the dead zone.  
The states shown in Table 26 correspond to which side of the  
accelerometer is directed upwards, opposite the gravity vector.  
As shown in Figure 48, the accelerometer is oriented in the top  
state. If the device is flipped over such that the top of the device  
is facing down, toward gravity, the orientation is reported as the  
bottom state. If the device is adjusted such that the positive x-axis  
or positive y-axis direction is pointing upwards, away from the  
gravity vector, the accelerometer reports the orientation as front  
or left, respectively.  
The algorithm to detect orientation change is performed after  
filtering the output acceleration data to eliminate the effects of  
high frequency motion. This is performed by using a low-pass  
filter with a bandwidth set by the divisor bits (ORIENT_CONF  
register, Address 0x3B). The orientation filter uses the same  
output data available in the output data registers (Address 0x32  
to Address 0x37); therefore, the orient register (Address 0x3C)  
is updated at the same rate as the data rate that is set in the  
BW_RATE register (Address 0x2C). Because the output data  
is used, the bandwidth of the orientation filter depends on the  
value set in the BW_RATE register, and the divisor bandwidth  
values in Table 24 are referenced to the selected output data rate.  
PORTRAIT  
POSITIVE  
DEADZONE  
52.7°  
45°  
37.3°  
+X  
LANDSCAPE  
POSITIVE  
+g  
+Y  
To eliminate most human motion, such as walking or shaking, the  
value in the divisor bits (Bits[D2:D0]) of the ORIENT_CONF  
register (Address 0x3B) should be selected to effectively limit the  
orientation bandwidth to 1 Hz or 2 Hz. For example, with an  
output data rate of 100 Hz, a divisor selection of 3 (ODR/100)  
results in a 1 Hz bandwidth for orientation detection. For best  
results, it is recommended that an output data rate of ≥25 Hz in  
normal power mode and ≥200 Hz in low power operation be used.  
Figure 50. Orientation Showing a 15.4° Dead Zone Region  
By setting the INT_ORIENT bit (Bit D7) of the ORIENT_CONF  
register (Address 0x3B), an interrupt can be generated when the  
device is placed into a new valid orientation. Only one mode of  
orientation detection, 2D or 3D, can generate an interrupt at a  
time. The orientation detection mode is selected by setting or  
clearing the INT_3D bit (Bit D3) of the ORIENT_CONF register  
(Address 0x3B). For more details, refer to the Register 0x3B—  
ORIENT_CONF (Read/Write) section.  
Rev. 0 | Page 33 of 40  
 
 
ADXL3ꢀ1  
Writing to the BW_RATE register or placing the part into standby  
mode resets the orientation feature, clearing the orientation filter  
and the orientation status. These actions cause an orientation  
interrupt (if enabled), however, if the orientation during the  
next output sample is different from the default value (+X for  
2D orientation detection and undefined for 3D orientation).  
the LSB of the output data-word is Bit D6 of the DATAx0 register.  
In full-resolution operation when data is left justified, the location  
of the LSB changes according to the selected output range. For a  
range of 2 g, the LSB is Bit D6 of the DATAx0 register; for 4 g,  
Bit D5 of the DATAx0 register; for 8 g, Bit D4 of the DATAx0  
register; and for 16 g, Bit D3 of the DATAx0 register. This is  
shown in Figure 52.  
DATA FORMATTING OF UPPER DATA RATES  
The use of 3200 Hz and 1600 Hz output data rates for fixed 10-bit  
operation in the 4 g, 8 g, and 16 g output ranges provides an  
LSB that is valid and that changes according to the applied accel-  
eration. Therefore, in these modes of operation, Bit D0 is not  
always 0 when output data is right justified, and Bit D6 is not  
always 0 when output data is left justified. Operation at any data  
rate of 800 Hz or lower also provides a valid LSB in all ranges and  
modes that change according to the applied acceleration.  
Formatting of output data at the 3200 Hz and 1600 Hz output  
data rates changes depending on the mode of operation (full-  
resolution or fixed 10-bit) and the selected output range.  
When using the 3200 Hz or 1600 Hz output data rates in  
full-resolution or 2 g, 10-bit operation, the LSB of the output  
data-word is always 0. When data is right justified, this corresponds  
to Bit D0 of the DATAx0 register, as shown in Figure 51. When  
data is left justified and the part is operating in 2 g, 10-bit mode,  
DATAx1 REGISTER  
DATAx0 REGISTER  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
0
OUTPUT DATA-WORD FOR  
±16g, FULL-RESOLUTION MODE.  
OUTPUT DATA-WORD FOR THE ±2g,  
FULL-RESOLUTION AND ALL 10-BIT MODES.  
THE ±4g AND ±8g FULL-RESOLUTION MODES HAVE THE SAME LSB LOCATION AS THE±2g  
AND ±16g FULL-RESOLUTION MODES, BUT THE MSB LOCATION CHANGES TO BIT D2 AND  
BIT D3 OF THE DATAx1 REGISTER FOR ±4g AND ±8g, RESPECTIVELY.  
Figure 51. Data Formatting When Output Data Is Right Justified  
DATAx1 REGISTER  
DATAx0 REGISTER  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1  
D7 D6 D5 D4 D3 D2 D1 D0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
LSB FOR ±2g, FULL-RESOLUTION  
AND ALL 10-BIT MODES.  
MSB FOR ALL MODES  
OF OPERATION WHEN  
LEFT JUSTIFIED.  
LSB FOR ±4g, FULL-RESOLUTION MODE.  
LSB FOR ±8g, FULL-RESOLUTION MODE.  
LSB FOR ±16g, FULL-RESOLUTION MODE.  
FOR 3200Hz AND 1600Hz OUTPUT DATA RATES, THE LSB IN THESE MODES IS ALWAYS 0.  
ADDITIONALLY, ANY BITS TO THE RIGHT OF THE LSB ARE ALWAYS 0 WHEN THE OUTPUT  
DATA IS LEFT JUSTIFIED.  
Figure 52. Data Formatting When Output Data Is Left Justified  
Rev. 0 | Page 3ꢁ of 40  
 
 
 
ADXL3ꢀ1  
10k  
1k  
NOISE PERFORMANCE  
X-AXIS  
Y-AXIS  
Z-AXIS  
The specification of noise shown in Table 1 corresponds to the  
typical noise performance of the ADXL346 in normal power opera-  
tion with an output data rate of 100 Hz (LOW_POWER bit = 0,  
rate = 0x0A in the BW_RATE register, Address 0x2C). For normal  
power operation at data rates below 100 Hz, the noise of the  
ADXL346 is equivalent to the noise at 100 Hz ODR in LSBs. For  
data rates greater than 100 Hz, the noise increases approximately by  
a factor of √2 per doubling of the data rate. For example, at 400 Hz  
ODR, the noise on the x- and y-axes is typically less than 2 LSB  
rms, and the noise on the z-axis is typically less than 3 LSB rms.  
100  
10  
0.01  
0.1  
1
10  
100  
1k  
10k  
For low power operation (LOW_POWER bit = 1 in the BW_RATE  
register, Address 0x2C), the noise of the ADXL346 is constant  
for all valid data rates shown in Table 8. This value is typically  
less than 2.83 LSB rms for the x- and y-axes and typically less  
than 4.25 LSB rms for the z-axis.  
AVERAGING PERIOD, (s)  
Figure 54. Allan Deviation  
150  
X-AXIS  
Y-AXIS  
Z-AXIS  
140  
130  
120  
110  
100  
90  
The trend of noise performance for both normal power and low  
power modes of operation of the ADXL346 is shown in Figure 53.  
Figure 54 shows the typical Allan deviation for the ADXL346.  
The 1/f corner of the device, as shown in this figure, is very low,  
allowing absolute resolution of approximately 100 ꢀg (assuming  
that there is sufficient integration time). The figure also shows  
that the noise density is 420 ꢀg/√Hz for the x- and y-axes and  
530 ꢀg/√Hz for the z-axis.  
Figure 55 shows the typical noise performance trend of the  
ADXL346 over supply voltage. The performance is normalized  
to the tested and specified supply voltage, VS = 2.6 V. The x-axis  
offers the best noise performance over supply voltage, increasing by  
typically less than 25% from nominal at a supply voltage of 1.8 V.  
The performance of the y- and z-axes is comparable, with both  
axes increasing by typically less than 35% when operating with a  
supply voltage of 1.8 V. It should be noted, as shown in Figure 53,  
that the noise on the z-axis is typically higher than that on the  
y-axis; therefore, although the noise on the z- and y-axes change  
roughly the same in percentage over supply voltage, the magnitude  
of change on the z-axis is greater than the magnitude of change  
on the y-axis.  
1.6  
1.8  
2.0  
2.2  
2.4  
2.6  
2.8  
SUPPLY VOLTAGE, V (V)  
S
Figure 55. Normalized Noise vs. Supply Voltage  
OPERATION AT VOLTAGES OTHER THAN 2.6 V  
The ADXL346 is tested and specified at a supply voltage of  
VS = 2.6 V; however, it can be powered with a VS as high as 2.75 V  
or as low as 1.7 V. Some performance parameters change as the  
supply voltage changes, including the offset, sensitivity, noise,  
self-test, and supply current.  
Due to minuscule changes in the electrostatic forces as supply  
voltage is varied, the offset and sensitivity change slightly. When  
operating at a supply voltage of VS = 1.8 V, the offset of the x- and  
y-axes is typically 25 mg higher than at VS = 2.6 V operation. The  
z-axis is typically 20 mg lower when operating at a supply voltage  
of 1.8 V than when operating at VS = 2.6 V. Sensitivity on the  
x- and y-axes typically shifts from a nominal 256 LSB/g (full-  
resolution or 2 g, 10-bit operation) at VS = 2.6 V operation to  
250 LSB/g when operating with a supply voltage of 1.8 V. The z-axis  
sensitivity is unaffected by a change in supply voltage and is the  
same at VS = 1.8 V operation as it is at VS = 2.6 V operation. Simple  
linear interpolation can be used to determine typical shifts in  
offset and sensitivity at other supply voltages.  
7
X-AXIS, NORMAL POWER  
Y-AXIS, NORMAL POWER  
Z-AXIS, NORMAL POWER  
X-AXIS, LOW POWER  
6
5
Y-AXIS, LOW POWER  
Z-AXIS, LOW POWER  
4
3
2
1
0
3.13 6.25 12.50 25  
50 100 200 400 800 1600 3200  
OUTPUT DATA RATE (Hz)  
Figure 53. Noise vs. Output Data Rate for Normal and Low Power Modes,  
Full Resolution (256 LSB/g)  
Rev. 0 | Page 3ꢂ of 40  
 
 
 
 
 
ADXL3ꢀ1  
140  
120  
100  
80  
Changes in noise performance, self-test response, and supply  
current are discussed elsewhere throughout the data sheet. For  
more information about noise performance, review the Noise  
Performance section. The Self-Test section discusses both the  
operation of self-test over voltage (a square relationship with the  
supply voltage) and the conversion of the self-test response in  
gs to LSBs. Finally, Figure 33 shows the impact of supply voltage  
on typical current consumption at a 100 Hz output data rate,  
with all other output data rates following the same trend.  
0.10Hz  
0.20Hz  
0.39Hz  
0.78Hz  
1.56Hz  
3.13Hz  
6.25Hz  
60  
40  
OFFSET PERFORMANCE AT LOWEST DATA RATES  
20  
The ADXL346 offers several output data rates and bandwidths  
designed for a wide range of applications. However, at the lowest  
data rates, described as those data rates below 6.25 Hz, the offset  
performance over temperature can vary significantly from the  
remaining data rates. Figure 56, Figure 57, and Figure 58 show  
the typical offset performance of the ADXL346 over temperature  
for data rates of 6.25 Hz and lower. All plots are normalized to  
the offset at 100 Hz output data rate; therefore, a nonzero value  
corresponds to additional offset shift due to the temperature for  
that data rate.  
0
25  
35  
45  
55  
65  
75  
85  
TEMPERATURE (°C)  
Figure 56. Typical X-Axis Output vs. Temperature at Lower Data Rates,  
Normalized to 100 Hz Output Data Rate, VS = 2.6 V  
140  
120  
100  
80  
When using the lowest data rates, it is recommended that the  
operating temperature range of the device be limited to provide  
minimal offset shift across the operating temperature range.  
Due to variability between parts, it is also recommended that  
calibration over temperature be performed if any data rates  
below 6.25 Hz are in use.  
0.10Hz  
0.20Hz  
0.39Hz  
0.78Hz  
1.56Hz  
3.13Hz  
60  
40  
6.25Hz  
20  
0
25  
35  
45  
55  
65  
75  
85  
TEMPERATURE (°C)  
Figure 57. Typical Y-Axis Output vs. Temperature at Lower Data Rates,  
Normalized to 100 Hz Output Data Rate, VS = 2.6 V  
140  
120  
100  
80  
0.10Hz  
60  
0.20Hz  
0.39Hz  
0.78Hz  
1.56Hz  
3.13Hz  
6.25Hz  
40  
20  
0
–20  
25  
35  
45  
55  
65  
75  
85  
TEMPERATURE (°C)  
Figure 58. Typical Z-Axis Output vs. Temperature at Lower Data Rates,  
Normalized to 100 Hz Output Data Rate, VS = 2.6 V  
Rev. 0 | Page 36 of 40  
 
 
 
 
ADXL3ꢀ1  
AXES OF ACCELERATION SENSITIVITY  
A
Z
A
Y
A
X
Figure 59. Axes of Acceleration Sensitivity (Corresponding Output Increases When Accelerated Along the Sensitive Axis)  
X
Y
Z
= +1g  
= 0g  
= 0g  
OUT  
OUT  
OUT  
TOP  
GRAVITY  
X
Y
Z
= 0g  
= –1g  
= 0g  
X
Y
Z
= 0g  
= +1g  
= 0g  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
P
T O  
X
Y
Z
= 0g  
= 0g  
= +1g  
X
Y
Z
= 0g  
= 0g  
= –1g  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
X
Y
Z
= –1g  
= 0g  
= 0g  
OUT  
OUT  
OUT  
Figure 60. Output Response vs. Orientation to Gravity  
Rev. 0 | Page 37 of 40  
 
ADXL3ꢀ1  
LAYOUT AND DESIGN RECOMMENDATIONS  
Figure 61 shows the recommended printed wiring board land pattern. Figure 62 and Table 27 provide details about the recommended  
soldering profile.  
0.8000  
0.3000  
3.3500  
0.5000  
3.3500  
Figure 61. Recommended Printed Wiring Board Land Pattern  
(Dimensions shown in millimeters)  
CRITICAL ZONE  
tP  
T
TO T  
L
P
T
P
RAMP-UP  
T
L
tL  
T
SMAX  
T
SMIN  
tS  
RAMP-DOWN  
PREHEAT  
t
25°C TO PEAK  
TIME  
Figure 62. Recommended Soldering Profile  
Table 27. Recommended Soldering Profile1, 2  
Condition  
Pb-Free  
Profile Feature  
Sn63/Pb37  
Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP)  
Preheat  
3°C/sec max  
3°C/sec max  
Minimum Temperature (TSMIN  
)
100°C  
1ꢂ0°C  
Maximum Temperature (TSMAX  
Time from TSMIN to TSMAX (tS)  
SMAX to TL Ramp-Up Rate  
Liquid Temperature (TL)  
Time Maintained Above TL (tL)  
Peak Temperature (TP)  
Time of Actual TP − ꢂ°C (tP)  
Ramp-Down Rate  
Time 2ꢂ°C to Peak Temperature  
)
1ꢂ0°C  
200°C  
60 sec to 120 sec  
3°C/sec max  
183°C  
60 sec to 1ꢂ0 sec  
2ꢁ0 + 0/−ꢂ°C  
10 sec to 30 sec  
6°C/sec max  
6 minutes max  
60 sec to 180 sec  
3°C/sec max  
217°C  
60 sec to 1ꢂ0 sec  
260 + 0/−ꢂ°C  
20 sec to ꢁ0 sec  
6°C/sec max  
8 minutes max  
T
1 Based on JEDEC Standard J-STD-020D.1.  
2 For best resultsꢀ the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used.  
Rev. 0 | Page 38 of 40  
 
 
 
 
ADXL3ꢀ1  
OUTLINE DIMENSIONS  
3.10  
3.00 SQ  
2.90  
PIN 1  
CORNER  
0.350  
0.10  
0.50  
13  
9
1
5
14  
8
16  
6
BSC  
0.250  
0.50  
BOTTOM VIEW  
TOP VIEW  
END VIEW  
0.275  
1.00  
0.95  
0.85  
0.79  
0.74  
0.69  
SEATING  
PLANE  
Figure 63. 16-Terminal Land Grid Array [LGA]  
(CC-16-3)  
Solder Terminations Finish Is Au over Ni  
Dimensions shown in millimeters  
ORDERING GUIDE  
Measurement Specified  
Temperature  
Package  
Branding  
Code  
Model1  
Range (g)  
Voltage (V) Range  
Package Description  
Option  
CC-16-3  
CC-16-3  
CC-16-3  
ADXL3ꢁ6ACCZ  
2ꢀ ꢁꢀ 8ꢀ 16 2.6  
2ꢀ ꢁꢀ 8ꢀ 16 2.6  
2ꢀ ꢁꢀ 8ꢀ 16 2.6  
−ꢁ0°C to +8ꢂ°C 16-Terminal Land Grid Array [LGA]  
−ꢁ0°C to +8ꢂ°C 16-Terminal Land Grid Array [LGA]  
−ꢁ0°C to +8ꢂ°C 16-Terminal Land Grid Array [LGA]  
Evaluation Board  
Y2Z  
Y2Z  
Y2Z  
ADXL3ꢁ6ACCZ-RL  
ADXL3ꢁ6ACCZ-RL7  
EVAL-ADXL3ꢁ6Z  
EVAL-ADXL3ꢁ6Z-M  
Analog Devices Inertial Sensor Evaluation  
Systemꢀ Includes ADXL3ꢁ6 Satellite  
EVAL-ADXL3ꢁ6Z-S  
ADXL3ꢁ6 Satelliteꢀ Standalone  
1 Z = RoHS Compliant Part.  
Rev. 0 | Page 39 of 40  
 
 
ADXL3ꢀ1  
NOTES  
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).  
Analog Devices offers specific products designated for automotive applications; please consult your local Analog Devices sales representative for details. Standard products sold by  
Analog Devices are not designed, intended, or approved for use in life support, implantable medical devices, transportation, nuclear, safety, or other equipment where malfunction  
of the product can reasonably be expected to result in personal injury, death, severe property damage, or severe environmental harm. Buyer uses or sells standard products for use  
in the above critical applications at Buyer's own risk and Buyer agrees to defend, indemnify, and hold harmless Analog Devices from any and all damages, claims, suits, or expenses  
resulting from such unintended use.  
©2010 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D08167-0-5/10(0)  
Rev. 0 | Page ꢁ0 of ꢁ0  
配单直通车
ADXL362BCCZ-MI-RL产品参数
型号:ADXL362BCCZ-MI-RL
Brand Name:Analog Devices Inc
是否无铅: 含铅
是否Rohs认证: 符合
生命周期:Active
包装说明:TFLGA,
针数:16
制造商包装代码:CC-16-4
Reach Compliance Code:compliant
风险等级:5.58
模拟集成电路 - 其他类型:ANALOG CIRCUIT
JESD-30 代码:R-XBGA-N16
长度:3.25 mm
功能数量:1
端子数量:16
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:UNSPECIFIED
封装代码:TFLGA
封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
座面最大高度:1.14 mm
最大供电电压 (Vsup):3.5 V
最小供电电压 (Vsup):1.6 V
标称供电电压 (Vsup):2 V
表面贴装:YES
温度等级:INDUSTRIAL
端子形式:NO LEAD
端子节距:0.5 mm
端子位置:BOTTOM
宽度:3 mm
Base Number Matches:1
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