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产品型号AK8812的概述

芯片AK8812的概述 AK8812是一款高度集成的音频处理芯片,专为高保真音频应用设计,主要广泛应用于音频信号处理、智能音响、电视机、便携式音频设备等领域。凭借其卓越的音频性能和多功能特性,AK8812在市场上获得了显著的认可。 AK8812采用先进的音频编解码技术,支持多种音频格式的解码与处理,包括PCM、MP3等。此外,芯片内置高质量的音频转换器,能够实现高达24-bit的音频输入和输出,确保在音质方面的卓越表现。芯片还支持多种音频接口,包括I2S、PCM、SPDIF等,方便与其他组件进行连接与交互。 芯片AK8812的详细参数 AK8812的参数特性十分丰富,具体如下: - 音频位深: 24-bit - 采样率: 支持高达192kHz的采样率 - 动态范围: 大于100dB,确保音频信号传输的纯净度 - 总谐波失真: THD < 0.01%,提供极低的音频失真 - 供电电压: ...

产品型号AK8812的Datasheet PDF文件预览

ASAHIKASEI  
[AK8811/12]  
AK8811/12  
NTSC/PAL Digital Video Encoder  
GENERAL DESCRIPTION  
The AK8811 and AK8812 are low voltage, low power and small packaged Digital Video Encoder.  
They are suitable for a portable DVD or VCD player. They convert ITU-R.BT601/656 standard 8-  
bit parallel data into analog composite video, S-Video or analog component signals Y/Cb/Cr in  
NTSC and PAL formats.  
AK8812 and AK8811 support Macrovision Copy Protection Rev.7.1(only AK8812), Closed  
captioning and Video Blanking ID(CGMS). These functions are controlled by high-speed I2C Bus  
interface.  
FEATURES  
NTSC-M, PAL-B,D,G,H,I,M,N encoding.  
Simultaneous composite video signal and S-video signal outputs  
Y/Cb/Cr Component output (Based on EIAJ Guideline)  
CCIR-656 4:2:2 8-bit Parallel Input  
- EAV Decoding  
Master/Slave Operation  
- Digital Field Sync I/O  
- Digital Vertical/Horizontal Sync I/O  
Y filtering  
C filtering  
2 x over-sampling  
4 x over-sampling  
Single 27MHz Clock (The polarity could be inverted by SYSINV pin)  
Triple 10-bit DACs  
I2C Interface (400kHz)  
Closed Caption encoding (NTSC: line 21,284-SMPTE PAL: line 21,334-CCIR)  
Macrovision Copy Protection Rev. 7.1* (Only for AK8812)  
VBID, CGMS(EIAJ CPR-1024)  
On-chip Color bar generator  
Low Power Consumption  
3.3V only, CMOS Monolithic  
48pin LQFP Package  
* This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other intellectual  
rights. The use of Macrovision’s copy protection technology in the device must be authorized by Macrovision and  
is intended for home and other limited pay-per -view use only, unless otherwise authorized in written by  
Macrovision. Reverse engineering or disassembly is prohibited.  
Rev.1.1  
- 1 -  
2000/01  
ASAHI KASEI  
[AK8811/12]  
x2  
LPF-  
Luma  
DATA  
10-bit  
DAC  
COMPOSITE / U  
YCbCr (4:2:2)  
To  
D7 - D0  
YUV (4:4:4)  
x2  
LPF-  
Chroma-2  
10-bit  
DAC  
Y
LPF  
U,V  
Chroma-1  
MOD  
10-bit  
DAC  
CHROMA / V  
Video timing  
&
Sub Carrier  
Run in Clock  
FID/VSYNC  
HSYNC  
Base Wave  
Generator  
VREFIN  
VREFOUT  
VREF  
I2C  
SYSINV  
Interface  
SYSCLK  
/RESET  
IREF  
DVDD DVSS  
SELA  
AVDD AVSS  
SCL SDA  
Rev.1.1  
2
2000/01  
ASAHI KASEI  
48pin LQFP  
[AK8811/12]  
PIN LAYOUT  
48 47 46 45 44 43 42 41 40 39 38 37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
PD9  
1
2
3
4
5
6
7
8
9
PD4  
D7  
D6  
PD3  
PD2  
D5  
PD1  
D4  
PD0  
DVDD  
DVSS  
D3  
DVDD  
DVSS  
IREF  
D2  
VREFIN  
VREFOUT  
AVDD  
AVSS  
D1  
10  
11  
12  
D0  
TEST1  
13 14 15 16 17 18 19 20 21 22 23 24  
Rev.1.1  
3
2000/01  
ASAHI KASEI  
[AK8811/12]  
PIN/FUNCTION  
No.  
Pin Name  
I/O  
I
Description  
27MHz 8-Bit 4:2:2 multiplexed Y,Cb,Cr Data Input.  
For Rec.656 format, AK8811/12 decodes EAV.  
For non-Rec.656 format (without EAV), AK8811/12  
operates in Master or Slave mode.  
2-5,  
8-11  
D7 - D0  
I
I
27MHz Clock Input. The polarity could be inverted by  
SYSINV.  
41  
48  
SYSCLK  
SYSINV  
“L “ : data is latched with rising edge.  
“H” : data is latched with falling edge.  
I
After this pin becomes “L”, AK8811/12 starts the  
internal initializing sequence.  
18  
/RESET  
After initializing sequence, AK8811/12 is set NTSC  
mode, Rec.656 decoding mode. All DACs Off  
condition.  
I/O  
Either of FID or VSYNC selected by the register.  
Rec.656 decode mode :Output  
Master mode : Output  
FID  
45  
46  
/VSYNC  
Slave mode : Input  
FID shows that “L” is odd field and ”H” is even field.  
I/O  
Rec.656 decode mode : Output  
Master mode : Output  
Slave mode : Input  
HSYNC  
15  
16  
SCL  
SDA  
I
I/O  
I
Serial interface clock  
Serial interface data  
The slave address is set with this pin.  
“L”:40H “H”:42H  
14  
SELA  
O
Output of the Internal Vref. Terminate with 0.1uF or  
more capacitor.  
27  
28  
VREFOUT  
VREFIN  
I
Input of the Reference Voltage  
O
The currents flow this pin adjusts the full-scale  
output current of the DAC.  
29  
IREF  
O
24  
22  
COMPOSITE/U  
CHROMA/V  
Y
Output of Composite Video signal or component U  
Output of the C signal or component V  
Output of Luminance Signal.  
O
O
20  
21,26  
AVDD  
P
Analog +3.3V  
6,31,  
42,44  
DVDD  
AVSS  
P
Digital +3.3V  
G
Analog Ground  
19,23,25  
7,17,47,  
40,30  
DVSS  
G
I
Digital Ground  
TEST1  
TEST2  
12,13  
Test pin. Ground for normal operation  
1, 32-  
39,43  
I/O  
PD[9:0]  
Test pin. Open for normal operation  
Rev.1.1  
4
2000/01  
ASAHI KASEI  
[AK8811/12]  
ELECTRICAL CHARACTERISTICS  
Absolute Maximum Ratings  
Parameter  
Min  
-0.3  
Max  
4.6V  
Units  
Supply Voltage (VDD)  
DVDD, PVDD, AVDD  
Input Pin Voltage (Vin)  
V
-0.3  
VDD+0.3  
±10  
V
Input Pin Current (Iin)  
Analog Reference Current (IREF)  
Analog Output Current  
Power Dissipation  
-
-
-
mA  
mA  
mA  
mW  
°C  
0.21  
6.5  
1000  
125  
Storage Temperature  
-40  
(Note)When all Ground pins(DVSS, AVSS) are set to 0V.  
Recommended Operating Conditions  
Parameter  
Min  
3.0  
Typ.  
3.3  
Max  
3.6  
85  
Units  
V
Supply Voltage (VDD)  
Operating Temperature  
-40  
°C  
Rev.1.1  
5
2000/01  
ASAHI KASEI  
[AK8811/12]  
DC Characteristics  
Parameter  
[Power Supply:3.3V Temperature:25°C]  
Symbol  
Min  
Max  
Units  
Conditions  
Digital Input High Voltage  
Digital Input Low Voltage  
Digital Input leak Current  
Digital Output High Voltage  
Digital Output Low Voltage  
VIH1  
VIL1  
IL  
0.7VDD  
V
V
Note1)  
Note1)  
0.3VDD  
±10  
uA  
V
Note1)  
IOH =-1mA Note 2)  
IOL = 2mA Note 2)  
VOH  
VOL1  
2.4  
0.4  
20  
V
Digital  
Maximum  
Load  
pF  
Capacitance  
I2C Input High Voltage  
VIH2  
0.7VDD  
V
I2C(SDA,SCL)  
I2C Input Low Voltage  
I2C(SDA,SCL)  
VIL2  
0.3VDD  
0.4  
V
V
I2C(SDA) Output Voltage  
VOL2  
IOL = 3mA  
Note 1) D[9:0],FID/VSYNC, HSYNC, SYSCLK, /RESET pin  
Note 2) FID/VSYNC, HSYNC pin  
Note ) Connected Test Pin to Ground, SELA and SYSINV Pin are desired polarity.  
Analog Characteristics and Dissipation Current  
[Power Supply:3.3V Temperature:25°C]  
Parameter  
DAC Resolution  
Min  
1.21  
Typ  
10  
Max  
Units  
bit  
Conditions  
DAC Integral linearity error  
DAC Differential linearity error  
DAC Output Full Scale Voltage  
DAC Output offset Voltage  
Unbalances between DACs  
Isolation between DACs  
DAC Load Capacitance  
±0.6  
±0.4  
1.28  
± 2  
± 1  
1.38  
5.0  
±5  
LSB  
LSB  
V
Note1)  
Note2)  
mV  
%
±1  
Note3)  
50  
dB  
1MHz Full Scale  
Note4)  
30  
pF  
Internal Reference Voltage  
Internal Reference Drift  
DAC Current (Active mode)  
DAC Current (Sleep mode)  
Total Current  
1.17  
1.235  
50  
1.33  
V
ppm/°C  
mA  
uA  
15  
Note5)  
Note6)  
Note7)  
10  
50  
72  
mA  
Note 1) Under the condition of output load 390, IREF pin with 12k, using internal reference. The output full-scale  
current IOUT is calculated as Full scale output voltage (typ. 1.28V) /390=typ. 3.3mA.  
Note 2) DAC output when feeding code of 0 (Decimal).  
Note 3) Deviation between the DAC output when feeding 1V generating code of 800(Decimal).  
Note 4) The value is a design target. This value is not tested.  
Note 5) All DACs are operating.  
Note 6) All DACs are turned off with no system clock.  
Note 7) NTSC internal color bar with 3ch DACs operation and slave mode operation. DAC output pins is connected with  
only 390load.  
Rev.1.1  
6
2000/01  
ASAHI KASEI  
[AK8811/12]  
AC Characteristic  
1. SYSCLK  
Mid-points between  
VIH and VIL.  
fSYSCLK  
tCLKH  
tCLKL  
VIH  
VIL  
SYSCLK  
[ 3.3V Temperature 25°C ]  
Parameter  
Symbol  
Min.  
Typ.  
27  
Max  
Unit  
MHz  
nsec  
nsec  
SYSCLK  
fSYSCLK  
tCLKH  
SYSCLK Pulse width H  
SYSCLK Pulse width L  
15  
15  
tCLKL  
Rev.1.1  
7
2000/01  
ASAHI KASEI  
[AK8811/12]  
2. In case of SYSINV = L  
(2-1). Pixel Data Input  
Pixel Data Input Timing  
VIH  
VIL  
SYSCLK  
D7 - D0  
tDH  
tDS  
[ 3.3V Temperature 25°C ]  
Parameter  
Data Setup Time  
Data Hold Time  
Symbol  
tDS  
Min  
Typ  
Max  
Units  
nsec  
nsec  
5
8
tDH  
(2-2). Synchronizing Signal ( FID/VSYNC, HSYNC )  
(2-2-1) Input Synchronizing Signal Timing  
VIH  
VIL  
SYSCLK  
tDH  
tDS  
FID/VSYNC, HSYNC  
[ 3.3V Temperature 25°C ]  
Parameter  
Data Setup Time  
Data Hold Time  
Symbol  
Min  
5
Typ.  
Max  
Units  
nsec  
nsec  
tDS  
tDH  
8
Rev.1.1  
8
2000/01  
ASAHI KASEI  
[AK8811/12]  
(2-2-2) Output Synchronizing Signal Timing  
VIH  
SYSCLK  
tDEL  
FID/VSYNC, HSYNC  
[ 3.3V Temperature 25°C ]  
Parameter  
Symbol  
tDEL  
Min  
Typ.  
Max  
27  
Units  
nsec  
Delay from SYSCLK  
(2-3). Reset (Initialize)  
Reset Timing  
/RESET  
SYSCLK  
pRES  
[ 3.3V Temperature 25°C ]  
Parameter  
Symbol  
pRES  
Min  
10  
Typ.  
Max  
Units  
/RESET Pulse Width  
SYSCLK  
Rev.1.1  
9
2000/01  
ASAHI KASEI  
[AK8811/12]  
(3). In case of SYSINV = H  
(3-1). Pixel Data Input  
Pixel Data Input Timing  
VIH  
SYSCLK  
D7 - D0  
VIL  
tDS  
tDH  
[ 3.3V Temperature 25°C ]  
Parameter  
Data Setup Time  
Data Hold Time  
Symbol  
Min  
Typ  
Max  
Units  
nsec  
nsec  
tDS  
tDH  
5
8
(3-2). Synchronizing Signal ( FID/VSYNC, HSYNC )  
(3-2-1) Input Synchronizing Signal Timing  
VIH  
VIL  
SYSCLK  
tDH  
tDS  
FID/VSYNC, HSYNC  
[ 3.3V Temperature 25°C ]  
Parameter  
Symbol  
Min  
5
Typ.  
Max  
Units  
nsec  
nsec  
Data Setup Time  
Data Hold Time  
tDS  
tDH  
8
Rev.1.1  
10  
2000/01  
ASAHI KASEI  
[AK8811/12]  
(3-2-2) Output Synchronizing Signal Timing  
VIL  
SYSCLK  
tDEL  
FID/VSYNC, HSYNC  
[ 3.3V Temperature 25°C ]  
Parameter  
Symbol  
tDEL  
Min  
Typ.  
Max  
27  
Units  
nsec  
Delay from SYSCLK  
(3-3). Reset (Initialize)  
Reset Timing  
/RESET  
SYSCLK  
pRES  
[ 3.3V Temperature 25°C ]  
Parameter  
Symbol  
pRES  
Min  
10  
Typ.  
Max  
Units  
/RESET Pulse Width  
SYSCLK  
Rev.1.1  
11  
2000/01  
ASAHI KASEI  
[AK8811/12]  
(4). I2C Bus (SCL 400kHz cycle mode)  
(4-1) I/O Timing 1  
tBuf  
tF  
tHD:STA  
tR  
tSU:STO  
SDA  
SCL  
tF  
tR  
tSU:STA  
tLOW  
[ 3.3V Temperature 25°C ]  
Parameter  
Bus Free Time  
Symbol  
tBUF  
Min  
1.3  
0.6  
1.3  
Max  
Units  
usec  
usec  
usec  
nsec  
nsec  
usec  
usec  
Hold Time (Start Condition)  
Clock Pulse Low Time  
tHD:STA  
tLOW  
tR  
Bus Signal Rise Time  
300  
300  
Bus Signal Fall Time  
tF  
Setup Time(Start Condition)  
Setup Time(Stop Condition)  
tSU:STA  
tSU:STO  
0.6  
0.6  
All the figures shown above list are not restricted by AK8811/12 but are restricted by I2C Bus standard.  
Please see the I2C Bus standard for further details.  
(4-2) I/O Timing 2  
tHD:DAT  
SDA  
SCL  
tHIGH  
tSU:DAT  
[ 3.3V Temperature 25°C ]  
Parameter  
Symbol  
Min.  
100 (1)  
0.0  
Max.  
Unit.  
nsec  
usec  
usec  
Data Setup Time  
Data Hold Time  
tSU:DAT  
tHD:DAT  
tHIGH  
0.9 (2)  
Clock Pulse High Time  
0.6  
(1) In case of normal I2C bus mode tSU:DAT 250nsec  
(2) Using under minimum tLOW, this value must be satisfied.  
Rev.1.1  
12  
2000/01  
ASAHI KASEI  
[AK8811/12]  
FUNCTIONAL DESCRIPTION  
Reset  
When the reset pin [ /RESET ] set to “L”, AK8811/12 is in reset state. AK8811/12 starts in  
the internal initializing sequence at the trailing edge of the first SYSCLK after the reset pin is  
“L”. All internal registers are set to be default value by this initializing sequence. AK8811/12  
needs at least 10 clock counts of SYSCLK for this reset operation. After the reset operation,  
the video output pins are in high-impedance. AK8811/12 requires SYSCLK for the reset  
operation.  
Master-Clock  
AK8811/12 requires 27MHz clock at SYSCLK pin for operation. Video input data (ITU-R  
BT.656) is sampled at the trailing edge of this 27MHz. SYSINV decides the edge direction.  
SYSINV = L  
Data is sampled at rising edge of SYSCLK.  
SYSINV = H Data is sampled at falling edge of SYSCLK.  
Video Signal Interface  
AK8811/12 can interface with the video input data by the following 3 modes. The mode is  
set by the register [ Interface mode register(00H) ].  
1. ITU-R BT.656 Format  
AK8811/12 decodes EAV in stream data and manages an internal synchronization.  
In this case, AK8811/12 outputs FID (odd : “L” even : “H”)/ VSYNC and HSYNC.  
CCIR-bit of [ Interface mode register (00H) ] should be set “1” .  
2. ITU-R BT.656 like Format (4:2:2 Y/Cb/Cr)  
There are Master and Slave modes, for ITU-R BT.656 like Format which does not include  
EAV. In this mode, CCIR-bit of [ Interface mode register(00H) ] should be set “0” .  
<Master Mode>  
AK8811/12 provides FID/VSYNC and HSYNC to an external device according to the  
AK8811/12 internal timing counter. AK8811/12 starts to sample the input data at the  
fixed value on the internal pixel counter.  
In this mode, following setting should be done to [Interface mode register(00H)].  
CCIR-bit = 0  
MAS-bit = 1  
<Slave Mode>  
FID/VSYNC and HSYNC are supplied by an external device. AK8811/12 samples the  
data as same manner of Master mode.  
In this mode, following setting should be done to [Interface mode register(00H)].  
CCIR-bit = 0  
MAS-bit = 0  
Rev.1.1  
13  
2000/01  
ASAHI KASEI  
[AK8811/12]  
Video Signal Conversion  
Video reconstruction module converts the multiplexed data (ITU-R. BT601 Y/Cb/Cr) to the  
interlace format of NTSC-M, PAL-M, PAL-B,D,G,H,I,N and other formats (ex. NTSC-4.43 and  
PAL60). The video reconstruction format, the line number, the color encode way(NTSC or PAL)  
and the frequency of Color Sub-carrier is specified by [Video Process 1 register(01H)]. (cf. Burst  
Signal Table) The frequency and the phase of Color Sub-carrier are also adjustable by [Sub C.  
Freq. register(06H)] and [Sub C. Phase register(07H)]. The Sub-carrier has a free-running  
mode and a reset-mode. In the reset-mode, the Sub-carrier is reset automatically to the initial  
phase for every 4 fields (NTSC) or 8 fields (PAL).  
Component Video Output  
Video output mode is set by VS-bit of [ Video Process 3 register (03H) ].  
AK8811/12 can output not only the set of composite video signal and S-video signal but also can  
output component video signals(Y/Cb/Cr). The component video signals are complied with EIAJ  
guideline 1998/3.  
VS-bit = 0 : composite video signal and S-video signal output  
VS-bit = 1 : component video signal output  
Luminance Filter  
Luminance signal passes through the 2x Low Pass filter Fig.1 is the characteristic of  
Luminance Filter.  
Frequency [MHz]  
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0  
10  
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
Fig. 1 Luminance Filter  
Rev.1.1  
14  
2000/01  
ASAHI KASEI  
[AK8811/12]  
Chroma Filter  
Chroma signals (Cb,Cr) before Sub-carrier modulation pass through the 1.3 MHz Low pass  
filter shown in Fig.2. Chroma signal modulated by Sub-carrier passes through the filter  
shown in Fig.3.  
Frequency [MHz]  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5  
10  
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
Fig. 2 Chroma-1 LPF  
Frequency [MHz]  
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0  
10  
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
Fig. 3 Chroma-2 LPF  
Rev.1.1  
15  
2000/01  
ASAHI KASEI  
[AK8811/12]  
Color burst signal  
Color burst signal is generated by 24bits-length Digital Frequency Synthesizer. The Default  
frequency of the color burst is selected by [Video Process 1 Register(0x01)].  
Sub-carrier Freq. Video Process 1  
Standard  
[MHz]  
[VM1,VM0]  
[0,0]  
NTSC-M  
3.57954545  
PAL-M  
3.57561188  
4.43361875  
3.5820558  
4.43361875  
4.43361875  
4.43361875  
[0,1]  
PAL-B,D,G,H,I  
PAL-N(Arg.)  
PAL-N(non-Arg.)  
PAL60  
[1,1]  
[1,0]  
[1,1]  
[1,1]  
[1,1]  
NTSC-4.43  
Burst Signal Table  
Sub-carrier frequency 3.57561188MHz is allowed when PAL-M mode is selected.  
The burst frequency and initial phase resolution are as follows.  
Frequency resolution  
SCH Phase resolution  
0.8046Hz  
360°/256  
Video DAC  
AK8811/12 has the three current driven 10bits-DACs at 27MHz operation. The full scale  
voltage of DAC is determined by the current output from IREF pin. Typical output voltage is  
1.28Vo-p under the condition of VREFIN 1.235V, 12Kbetween IREF pin and Ground(AVSS)  
and DAC load resistance of 390. This full-scale voltage should be set in the range of 1.17V to  
1.33V by adjusting the resistor which terminates IREF pin. Each DAC output can be set to  
“active state” or to “inactive state” individually by [DAC Mode register(05H)]. When DAC is in  
“inactive state”, the output is Hi-impedance. When all DACs are set to “inactive state”, the  
analog part of AK8811/12 goes into sleep mode. In this case AK8811/12 stops outputing the  
reference voltage(VREF) output. When any DAC is switched over in “active state” from sleep  
mode, AK8811/12 starts outputing reference voltage. In this case AK8811/12 needs several  
milisecond for VREF wake-up time.  
Using internal VREF as the reference voltage, connect [VREF OUT] pin with [VREF IN] pin  
and [VREF OUT] pin is terminated with more than 0.1uF capacitor.  
Use external Reference Voltage  
In order to improve the accuracy of DAC output, external reference voltage may be used. In  
this case, VREFOUT pin still needs to be terminated with more than 0.1uF capacitor.  
Rev.1.1  
16  
2000/01  
ASAHI KASEI  
[AK8811/12]  
Copy Protection  
Macrovision Copy Protection Rev.7.1  
Information about the Macrovision encoding functions of the AK8812 is available to  
Macrovision licensees. Macrovision may be contacted at:  
Macrovision Corporation  
1341 Orleans Drive  
Sunnyvale, California 94089  
USA  
Attention: ACP-PPV Technical Support  
FAX: (408) 743 – 8610  
Rev.1.1  
17  
2000/01  
ASAHI KASEI  
[AK8811/12]  
Closed Caption and Extended Data  
AK8811/12 supports both Closed Captioning and Extended Data. They are controlled “ON”  
or ”OFF” respectively by [ Video Process 2 Register(02H) ]. Each data consists of 2 continuous  
bytes register( Closed Caption R (16H,17H) ), and it is recognized as the data is renewed when  
the second byte(17H register) is written in the register. After the data is renewed, AK8811/12  
encodes Closed Captioning and Extended Data at the designated line. If the data isn’t renewed,  
AK8811/12 outputs “ASCII-NULL” code. The data is supposed as Odd Parity and 7 bit US-  
ASCII code. Host should provide a parity bit.  
*In PAL encoding mode, AK8811/12 outputs them at the same timing and same pattern as NTSC.  
*The line where Closed Captioning data is encoded is as follows.  
525/60 System (SMPTE) 625/50 System (CCIR)  
Closed Caption  
Extended Data  
21 Line default  
284 Line default  
21 Line default  
334 Line default  
TWO 7-Bit+PARITY  
ASCII Characters  
(DATA)  
10.5±0.25uS  
12.91 uS  
P
A
R
I
T
Y
P
A
R
I
T
Y
S
T
A
50±2IRE  
7 Cycles of  
0.5035MHz  
(Clock RUN-IN)  
40IRE  
240±48nsec  
RISE/FALL TIMES  
(2T BAR SHAPING)  
10.003±0.25uS  
27.382 uS  
( 33.764 uS )  
61 uS  
Fig. 4 Closed Captioning Wave form  
Rev.1.1  
18  
2000/01  
ASAHI KASEI  
[AK8811/12]  
Video ID  
AK8811/12 supports Video ID (EIAJ standard, CPR-1204) encoding for the distinction of an  
aspect ratio, etc. Setting or Resetting the VBID-bit of [ Video Process 2 Register(02H) ], this  
function is switched On/Off. The data is set by using [ Video ID Data Register(1AH, 1BH) ].  
VBID Data Renewal Timing.  
VSYNC  
Set Control Register  
NEW DATA  
SI/SDA  
Data #1  
OLD DATA  
NEW DATA  
Fig. 5 VBID Data renewal Timing  
VBID Data Layout  
VBID is consists of 20 bits and its format is shown as follows.  
AK8811/12 generates CRC code automatically and appends it to the data. Initial value of  
the Polynomial is 1.  
bit 20  
bit 1  
DATA  
WORD 0  
2 bit  
WORD 1  
4 bit  
CRC  
6 bit  
WORD 2  
8 bit  
Fig. 6 VBID code assignment  
Rev.1.1  
19  
2000/01  
ASAHI KASEI  
[AK8811/12]  
VBID Waveform  
IRE  
100  
Ref.  
bit 1 bit 2 bit 3 •••• bit 20  
70 IRE ± 10 IRE  
0 IRE -5 IRE / +10 IRE  
0
2.235 usec ± 50ns  
-40  
11.2 usec ± 0.3 usec  
49.1 usec ± 0.44 usec  
Fig. 7 VBID Wave Form  
525/60 system  
70 IRE  
625/50 system  
490 mV  
Amplitude  
Encode Line  
20/283  
20/333  
VBID parameter table  
Rev.1.1  
20  
2000/01  
ASAHI KASEI  
[AK8811/12]  
AK8811/12 Interface Timing (Part 1) Master mode & ITU-R BT. 656 mode  
On ITU-R BT.656 decoding mode or master mode operation, AK8811/12 outputs HSYNC  
and FID or VSYNC (selected by register).  
When AK8811/12 receives ITU-R BT. 656 signal, AK8811/12 decodes [EAV] code in the data  
for synchronization then outputs the HSYNC. AK8811/12 outputs HSYNC at the rising edge  
of SYSCLK in the timing of the 32nd/24th(NTSC/PAL) data slot, which is counted from the  
[EAV] starting point as below. (See also AC Characteristics 2-2[Input Synchronizing Signal])  
On master mode operation, the front device connected with AK8811/12 (ex. MPEG Decoder)  
starts to set Cb on the 276th/288th(NTSC/PAL) slot, after starting to count HSYNC falling  
edge as 32nd/24th(NTSC/PAL) slot.  
FID/VSYNC is output synchronously with HSYNC at the timing of solid line as in Fig. 10  
Video Field.  
244T  
(264T)  
Cb  
Y
Cr  
Y
ITU-R. BT601(656)  
HSYNC  
27MHz SYSCLK  
NTSC(PAL)  
276  
(288)  
32  
(24)  
T=1/27MHz  
* Uncertainty of 1T occurs  
according to the Reset  
timing.  
Fig. 8 Interface Timing (ITU-R BT.656 or Master mode)  
Rev.1.1  
21  
2000/01  
ASAHI KASEI  
[AK8811/12]  
AK8811/12 Interface Timing (Part 2) Slave mode  
On slave mode operation, HSYNC and FID or VSYNC (Selected by register) are input to  
AK8811/12.  
AK8811/12 monitors the transition of HSYNC at the timing of the rising edge of SYSCLK.  
(Refer to AC Characteristic 2-1. [Input Synchronizing Signal]) After AK8811/12 recognizes  
HSYNC is Low-logic, AK8811/12 sets the slot number to the 32nd/24th(NTSC/PAL),  
internally, then AK8811/12 starts to sample the data as Cb on 276th/288th(NTSC/PAL) slot.  
Video field is recognized the transition timing between FID/VSYNC and HSYNC. (Fig.10.  
Video Field) As in the figure, there is a toreralnce of ±1/4H.  
244T  
(264T)  
Cb  
Y
Cr  
Y
ITU-R. BT601(656)  
HSYNC  
27MHz SYSCLK  
NTSC(PAL)  
276  
(288)  
32  
(24)  
T=1/27MHz  
* Uncertainty of 1T occurs  
according to the Reset  
timing.  
Fig. 9. Interfacing timing (Slave mode)  
1 H  
1/2 H  
1/2 H  
HSYNC  
1/2 H  
ODD Field  
Start  
FID/VSYNC  
1/2 H  
EVEN Field  
Start  
FID/VSYNC  
Fig. 10. Video Field  
22  
Rev.1.1  
2000/01  
ASAHI KASEI  
[AK8811/12]  
HSYNC FID/VSYNC Timing  
3
4
5
6
7
HSYNC  
FID  
EVEN  
ODD  
VSYNC  
266  
267  
268  
269  
270  
HSYNC  
FID  
ODD  
EVEN  
VSYNC  
Fig. 11. NTSC  
/ PAL/M  
625  
1
2
3
4
HSYNC  
FID  
ODD  
EVEN  
VSYNC  
313  
314  
315  
316  
317  
HSYNC  
FID  
ODD  
EVEN  
VSYNC  
Fig. 12 PAL  
Rev.1.1  
23  
2000/01  
ASAHI KASEI  
[AK8811/12]  
Color Bars  
AK8811/12 generates the Common Color Bar signal for NTSC and PAL internally. The  
generated Color Bar is “100% Amplitude, 100% Saturation”.  
Luminance  
White level  
Sync level  
Blank level  
Chrominace  
The following values are code for ITU-R. BT601  
WHITE  
128  
235  
128  
YELLOW  
16  
CYAN  
166  
170  
GREEN  
54  
145  
MAGENTA  
202  
RED  
90  
81  
BLUE  
240  
41  
BLACK  
128  
16  
128  
Cb  
Y
Cr  
210  
146  
106  
222  
16  
34  
240  
110  
Rev.1.1  
24  
2000/01  
ASAHI KASEI  
[AK8811/12]  
Component video output  
The levels of each Component video outputs are following. ( Color bar NTSC 100/0/100/0 )  
Magnitude is compliant to the guideline of EIAJ CPR-1024.  
White  
714mV  
(100 IRE)  
Yellow  
Cyan  
Green  
Magenta  
Red  
Blue  
Black  
286mV  
350mV  
-350mV  
350mV  
-350mV  
[mV]  
WHITE  
YELLOW  
-350  
CYAN  
118  
500  
GREEN  
-232  
418  
MAGENTA  
232  
RED  
-118  
213  
BLUE  
350  
82  
BLACK  
Cb  
Y
Cr  
0
714  
0
0
0
0
632  
57  
296  
293  
-350  
-293  
350  
-57  
Y Signal Level  
:
1.00Vpp  
Y ( Video Signal Level ) : 0.714V  
Y ( Sync level )  
Setup  
:
:
0.286V  
None  
Cb/Cr Signal Level :  
± 0.350V  
Rev.1.1  
25  
2000/01  
ASAHI KASEI  
[AK8811/12]  
I2C Control Sequence  
AK8811/12 is controlled by I2C bus. The slave address can be selected as 40H or 42H by  
selecting SELA pin.  
SELA pull-down  
Pull-up  
40H  
42H  
Operation :  
Write Sequence:  
S Slave Address W  
A
Sub Address  
A
Data_1 A  
Data_n A/A Stp  
*Continuous data writing is capable for the all registers.  
Sequential Read: (Only Sub Address of 24H, 25H, 26H could be read )  
S Slave  
W
A
Sub Address 24H  
A rS Slave  
R
A
A
DATA_26H  
DATA_24H  
A
DATA_25H  
A Stp  
S : Start Condition  
by Host  
A : Acknowledge(SDA LOW)  
A: Not Acknowledge(SDA HIGH)  
Stp : Stop Condition  
R/W: 1: Read  
by AK8811/12  
0:Write  
- It ignores the general call  
Rev.1.1  
26  
2000/01  
ASAHI KASEI  
Sub Address  
[AK8811/12]  
AK8811/12 REGISTER MAP  
Name  
R/W  
W
Explanation  
00H  
01H  
02H  
03H  
Interface Mode  
Video Process 1  
Video Process 2  
Video Process 3  
Setting Interface mode  
W
Setting Standard (NTSC, PAL etc.)  
W
Setting Closed Caption/Extended Data/VBID  
Setting Composite signal or Component Signal  
Adjusting chroma/Luma Delay  
W
04H  
05H  
06H  
07H  
RESERVED  
DAC Mode  
W
W
W
Each DAC On/Off Switch  
Sub C. Freq.  
Sub C. Phase  
Adjusting Sub-carrier frequency  
Adjusting Sub-carrier phase  
08H-15H RESERVED  
16H  
17H  
18H  
19H  
1AH  
1BH  
Closed Caption R  
W
W
W
W
W
W
Closed Caption Lower byte Data  
Closed Caption Upper byte Data  
Extended Lower byte Data  
Extended Upper byte Data  
Video ID Lower byte Data  
Video ID Upper byte Data  
Closed Caption R  
Closed Caption R  
Closed Caption R  
Video ID Data  
Video ID Data  
1CH-23H RESERVED  
24H  
25H  
26H  
STS Data  
Device ID  
Device REV  
R
R
R
Status  
Device ID  
Revision  
27H-29H RESERVED  
Rev.1.1  
27  
2000/01  
ASAHI KASEI  
[AK8811/12]  
bit 1 bit 0  
Interface Mode Register (W only default A4H)  
Sub Add  
00H  
bit 7  
BLN4  
bit 6  
BLN3  
bit 5  
BLN2  
bit 4  
BLN1  
bit 3  
BLN0  
bit 2  
FID  
MAS  
CCIR  
Symbol  
BLN4 - BLN0  
Value  
*****  
Description  
Line Blanking  
No.  
default  
10100  
FID  
0
Select VSYNC  
Select FID  
Slave mode  
Master mode  
valid  
1
0
1
default  
default  
MAS  
When CCIR=0,it’s  
CCIR  
0
1
CCIR656 non-decode  
CCIR656 decode  
default  
Video Process 1 Register (W only default 18H)  
Sub Add  
01H  
bit 7  
Reserved  
bit 6  
CBG  
bit 5  
SETUP  
bit 4  
SCR  
bit 3  
VM3  
bit 2  
VM2  
bit 1  
VM1  
bit 0  
VM0  
Symbol  
Value  
Description  
CBG  
SETUP  
SCR  
0
1
0
1
0
1
Video Encode  
Generates color bar  
No Set-up  
7.5 IRE Set-up  
Sub C. Phase Reset off  
Standard Field Reset  
default  
default  
default  
default  
VM3 – VM2  
00 525/60  
01 525/60 PAL (PAL-M etc.)  
10 Reserved  
11 PAL  
VM1-VM0  
00 3.57954545 MHz  
default  
01 3.57561188 MHz (PAL-M only)  
10 3.5820558 MHz  
11 4.43361875 MHz  
Register Setting of each standard is showend as following ;  
VM3-VM0  
NTSC-M  
0000  
1111  
0101  
0111  
0011  
PAL-B,D,G,H,I  
PAL-M  
PAL-60  
NTSC4.43  
When SCR is “ON”, the Subcarrier Phase is reset every 4 fields for NTSC, every 8  
fields for PAL.  
Even when SETUP is “ON”, there is no Set-up (Pedestal) during the blanking lines.  
Rev.1.1  
28  
2000/01  
ASAHI KASEI  
[AK8811/12]  
bit 1 bit 0  
Video Process 2 Register (W only default 00H)  
Sub Add  
02H  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
CC284  
Reserved Reserved Reserved Reserved Reserved  
CC21  
VBID  
Symbol  
CC284  
Value  
Description  
Extended Data OFF  
0
default  
default  
default  
1
0
1
0
1
ON  
CC21  
VBID  
Closed Caption OFF  
ON  
Video ID OFF  
ON  
Video Process 3 Register (W only default 00H)  
Sub Add  
03H  
bit 7  
Reserved  
bit 6  
VS  
bit 5  
SYD2  
bit 4  
SYD1  
bit 3  
SYD0  
bit 2  
CYD2  
bit 1  
CYD1  
bit 0  
CYD0  
Symbol  
Value  
Description  
Video Set  
0
1
Composite, S-Video set  
Component set  
default  
SYD2 - SYD0  
CYD2 - CYD0  
S-Video Y Component  
delay no. from Chroma: 2's comp.  
Composite Y Component  
delay no. from Chroma: 2's comp.  
default  
000  
default  
000  
VS-bit selects the one of the setting of signals from the 2 signal sets (Composite, Y /C  
or Y/Cb/Cr)  
S video and Y component of the composite signal can be shifted for the chroma signal  
independently at ±3-system clock (27MHz).  
Rev.1.1  
29  
2000/01  
ASAHI KASEI  
[AK8811/12]  
bit 1 bit 0  
DAC Mode Register (W only default 00H)  
Sub Add  
05H  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
Reserved Reserved Reserved Reserved Reserved  
OUTCP OUTC  
OUTY  
Symbol Value  
OUTCP  
Description  
0 Composite video signal or U signal output : OFF default  
1 Composite video singal or U signal output : ON  
OUTC  
OUTY  
0 Chroma signal or V signal output : OFF  
1 Chroma signal or V signal output : ON  
0 Y signal output : OFF  
default  
default  
1 Y signal output : ON  
Video output of AK8811/12 (DAC) can be forced “OFF” independently.  
The output of DAC that is forced “OFF” is Hi-impedance. When three DACs are  
forced “OFF”, then the internal VREF is also forced “OFF”. In this case, it takes  
several miliseconds before the internal VREF reaches the proper voltage after any  
DAC becomes “ON”.  
SubC Freq. Register (W only default 00H)  
Sub Add  
06H  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
SUBF7 SUBF6 SUBF5 SUBF4 SUBF3 SUBF2 SUBF1 SUBF0  
Symbol  
Value  
Description  
SUBF7-SUBF0  
Adjustment of frequency between  
+127 and –128 step of 0.8Hz  
default 0  
AK8811/12 generates the necessary sub-carrier frequency from a system clock by DFS  
(Digital Frequency Synthesizer)  
Frequency of default is adjustable by specifying this bit. This bit adjusts the default  
frequency.  
SubC Phase Register (W only default 00H)  
Sub Add  
07H  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
SUBP7 SUBP6 SUBP5 SUBP4 SUBP3 SUBP2 SUBP1 SUBP0  
Symbol  
Value  
description  
SUBP7 – SUBP0  
Step: (360° /256°)  
default 0  
Sub- carrier phase is adjustable by (360° /256) step.  
Rev.1.1  
30  
2000/01  
ASAHI KASEI  
[AK8811/12]  
bit 1 bit 0  
Closed Caption Register (W only default 00H)  
Sub Add  
16H  
17H  
18H  
19H  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
CC1[7] CC1[6] CC1[5] CC1[4] CC1[3] CC1[2] CC1[1] CC1[0]  
CC2[7] CC2[6] CC2[5] CC2[4] CC2[3] CC2[2] CC2[1] CC2[0]  
CC3[7] CC3[6] CC3[5] CC3[4] CC3[3] CC3[2] CC3[1] CC3[0]  
CC4[7] CC4[6] CC4[5] CC4[4] CC4[3] CC4[2] CC4[1] CC4[0]  
Symbol  
Description  
CC1[7] – CC1[0] Line 21 –1  
CC2[7] – CC2[0] Line 21 –2  
CC3[7] – CC3[0] Line 284 -1  
CC4[7] – CC4[0] Line 284 -2  
Closed Caption  
Extended Data  
When the 2nd byte of Closed Caption Data and Extended Data is written in,  
AK8811/12 recognizes the renewed data and encodes it in the video line. When the  
data is not renewed AK8811/12 outputs NULL code.  
Video ID Data Register (W only default 00H)  
Sub Add  
1AH  
1BH  
bit 7  
bit 6  
bit 5  
bit 1  
bit 9  
bit 4  
bit 2  
bit 10  
bit 3  
bit 3  
bit 11  
bit 2  
bit 4  
bit 12  
bit 1  
bit 5  
bit 13  
bit 0  
bit 6  
bit 14  
Reserved Reserved  
bit 7  
bit 8  
Please write value 0 at Reserved bit.  
Bit numbers correspond to Fig. 5 VBID code assignment.  
AK8811/12 generates CRC 6 bit data automatically.  
Rev.1.1  
31  
2000/01  
ASAHI KASEI  
[AK8811/12]  
Followings are read only register  
STATUS REGISTER (R only)  
Sub Add  
24H  
bit7  
bit6  
bit5  
EN284  
bit4  
EN21  
bit3  
SYNC  
bit2  
STS2  
bit1  
STS1  
bit0  
STS 0  
Reserved Reserved  
Symbol  
EN284  
Value  
Description  
0
1
0
1
0
Wait for the appointed video line to encode.  
Ready for the C.C. data input to the register.  
Wait for the appointed video line to encode.  
Ready for the C.C. data input to the register.  
Missing synchronization in slave mode.  
Synchronization was achieved.  
EN21  
SYNC  
1
STS2 - STS 0  
***  
Shows the processing field No.  
Status Register becomes effective when SYNC bit turns to “1”. When in master mode  
operation, this bit is ”1”.  
STS2-STS2 holds the field number of processing. Some time lag is inevitable for the I2C  
acquisition.  
Closed caption data should be renewed after firm that the EN* flag is “1”. EN* flag bit is  
cleared after the second byte( Sub address 17H,19H) was accessed.  
Reserved-bit is always value 0.  
Device ID (R only default 21H)  
Sub Add  
25H  
bit7  
0
bit6  
0
bit5  
0
bit4  
1
Bit3  
0
bit2  
0
bit1  
0
bit0  
1
Represents device ID. AK8811 is assigned 11H.  
Sub Add  
25H  
bit7  
0
bit6  
0
bit5  
0
bit4  
1
Bit3  
0
bit2  
0
bit1  
1
bit0  
0
Represents device ID. AK8811/12 is assigned 12H.  
Device REV (R only default 01H)  
Sub Add  
26H  
bit7  
0
bit6  
0
bit5  
0
bit4  
0
Bit3  
0
bit2  
0
bit1  
0
bit0  
1
Represents device revision. Initial is 01H.  
Rev.1.1  
32  
2000/01  
ASAHI KASEI  
[AK8811/12]  
SYSTEM CONNECTION EXAMPLE  
COMPOSITE -  
Amp + Filter  
D0 - D7  
LUMA  
-
-
CHROMA  
390 Ω  
75 Ω  
MPEG2  
Decoder  
SYSCLK  
VREFOUT  
VREFIN  
FID/ VSYNC  
HSYNC  
0.1u  
10uF  
AK8811/12  
SDA  
SCL  
I2C Bus  
IREF  
12 kΩ  
Digital 3.3V  
DVDD DVSS  
AVSS  
AVDD  
Analog 3.3V  
10u  
0.1u  
0.1u  
10u  
Digital GND  
Analog GND  
Rev.1.1  
33  
2000/01  
ASAHI KASEI  
48pin LQFP  
[AK8811/12]  
PACKAGE  
1.70 Max  
1.4 TYP  
9.0 ± 0.2  
7.0  
0.13 ± 0.13  
48  
1
0.17 ± 0.08  
0.22 ± 0.08  
0.5  
M
0.10  
0° 10°  
Units = mm  
0.5 ± 0.2  
0.10  
Package & Lead frame material  
Package molding compound : Epoxy  
Lead frame material : Cu  
Lead frame surface treatment : Solder plate  
Rev.1.1  
34  
2000/01  
ASAHI KASEI  
[AK8811/12]  
MARKING  
1) Pin #1 indication  
2) Date Code : XXXXXXX (7 digits)  
3) Marketing Code : AK8811/AK8812  
4) Country of Origin  
5) Asahi Kasei Logo  
Rev.1.1  
35  
2000/01  
ASAHI KASEI  
[AK8811/12]  
IMPORTANT NOTICE  
These products and their specifications are subject to change without notice. Before considering any use or application,  
consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current  
status.  
AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use  
of any information contained herein.  
Any export of these products, or devices or systems containing them, may require an export license or other official  
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or  
strategic materials.  
AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other  
hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express  
written consent of the Representative Director of AKM. As used here:  
(a)  
A hazard related device or system is one designed or intended for life support or maintenance of safety or for  
applications in medicine, aerospace, unclear energy, or other fields, in which its failure to function or perform  
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.  
A critical component is one whose failure to function or perform may reasonably be expected to result, whether  
directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which  
must therefore meet very high standards of performance and reliability.  
(b)  
It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places  
the product with a third party to notify that party in advance of the above content and conditions, and the buyer or  
distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims  
arising from the use of said product in the absence of such notification.  
Rev.1.1  
36  
2000/01  
配单直通车
AK8812产品参数
型号:AK8812
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Obsolete
IHS 制造商:ASAHI KASEI MICRODEVICES CORP
零件包装代码:QFP
包装说明:PLASTIC, LQFP-48
针数:48
Reach Compliance Code:unknown
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.84
Is Samacsys:N
商用集成电路类型:COLOR SIGNAL ENCODER
输入类型:R-Y; B-Y; Y
JESD-30 代码:S-PQFP-G48
JESD-609代码:e0
长度:7 mm
功能数量:1
端子数量:48
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP
封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):240
认证状态:Not Qualified
座面最大高度:1.7 mm
最大压摆率:72 mA
最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:TIN LEAD
端子形式:GULL WING
端子节距:0.5 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:10
视频标准:PAL; NTSC
宽度:7 mm
Base Number Matches:1
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