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ALC655

ALC655-LF

SIX-CHANNEL AC’97 2.3 AUDIO CODEC

DATASHEET

Rev. 1.3

16 March 2006

Track ID: JATR-1076-21

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan

Tel.: +886-3-578-0211. Fax: +886-3-577-6047

www.realtek.com.tw

ALC655 Datasheet

COPYRIGHT

transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written

permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited

to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this

document at any time. This document could include technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are

trademarks/registered trademarks of their respective owners.

CONFIDENTIALITY

This document is confidential and should not be provided to a third-party without the permission of Realtek Semiconductor

Corporation.

USING THIS DOCUMENT

This document is intended for the hardware and software engineer’s general information on the Realtek ALC655 Audio

CODEC chip.

Though every effort has been made to assure that this document is current and accurate, more information may have become

available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional

information that may help in the development process.

REVISION HISTORY

Revision

0.30

0.40

Release Date

2003/03/19

2003/04/04

Summary

Preliminary version release.

1.Update application circuit for automatic jack sensing function.

2.Add a FRONT-MIC2 for stereo microphone input for front panel

application. (Ver.D or later)

1.00

1.01

1.10

1.2

2003/07/10

2003/11/20

2005/03/15

2006/01/25

Change Version from 0.4 to 1.0 for release.

Correct dimension typing error in section 11.

Add lead(Pb)-free package & version identification.

Update section 6.1.11 MX1A Record Select, page 11, and section 12.

Ordering Information, page 38.

1.3

2006/03/16

Add a note to, and change Susceptibility Voltage data in section 7.1.1

Absolute Maximum Ratings, page 23.

Six-Channel AC’97 2.3 Audio Codec

i

Rev 1.3

ALC655 Datasheet

Table of Contents

1. Features............................................................................2

2. General Description........................................................2

3. Block Diagram.................................................................3

4. Pin Assignments ..............................................................4

4.1 Lead (Pb)-Free Package and Version Identification...4

5. Pin Description................................................................5

5.1 Digital I/O Pins ..........................................................5

5.2 Analog I/O Pins..........................................................5

5.3 Filter/Reference..........................................................6

5.4 Power/Ground ............................................................6

6. Registers...........................................................................7

6.1 Mixer Registers..........................................................7

6.1.1 MX00 Reset........................................................8

6.1.2 MX02 (Front) Master Volume............................8

6.1.3 MX06 MONO_OUT Volume.............................8

6.1.4 MX0A PC BEEP Volume ..................................9

6.1.5 MX0C PHONE Volume.....................................9

6.1.6 MX0E MIC Volume...........................................9

6.1.7 MX10 LINE_IN Volume..................................10

6.1.8 MX12 CD Volume ...........................................10

6.1.9 MX16 AUX Volume ........................................10

6.1.10 MX18 PCM_OUT Volume ............................11

6.1.11 MX1A Record Select......................................11

6.1.12 MX1C Record Gain........................................11

6.1.13 MX20 General Purpose Register ....................12

6.1.14 MX24 Audio Interrupt and Paging .................12

6.1.15 MX26 Power Down Control/Status................13

6.1.16 MX28 Extended Audio ID..............................14

6.1.17 MX2A Extended Audio Status and Control

6.2.5 MX6A Data Flow Control ............................... 18

6.3 Discovery Descriptor (Page ID-01h) ....................... 19

6.3.1 MX62 PCI Sub System ID............................... 19

6.3.2 MX64 PCI Sub Vendor ID............................... 19

6.3.3 MX66 Sense Function Select........................... 19

6.3.4 MX68 Sense Function Information.................. 20

6.3.5 MX6A Sense Detail ......................................... 20

6.4 Extension Registers ................................................. 20

6.4.1 MX78 GPIO(JD) Interrupt Control & Status... 20

6.4.2 MX7AMiscellaneousControl ................................ 22

6.4.4 MX7C VENDOR ID1..................................... 22

6.4.5 MX7E VENDOR ID2..................................... 22

7. Electrical Characteristics............................................. 23

7.1.1 Absolute Maximum Ratings ............................ 23

7.1.2 Threshold Hold Voltage................................... 23

7.1.3 Digital Filter Characteristics ............................ 23

7.1.4 S/PDIF Output Characteristics......................... 24

7.2 AC Timing Characteristics ...................................... 24

7.2.1 Cold Reset........................................................ 24

7.2.2 Warm Reset...................................................... 24

7.2.3 AC-Link Clocks............................................... 25

7.2.4 Data Output and Input Timing ......................... 25

7.2.5 Signal Rise and Fall Timing............................. 26

7.2.6 AC-Link Low Power Mode Timing................. 26

7.2.7 ATE Test Mode................................................ 27

7.2.8 AC-Link IO Pin Capacitance and Loading ...... 27

7.2.9 SPDIF Output................................................... 27

8. Analog Performance Characteristics.......................... 28

9. Design Suggestions........................................................ 30

9.1 Clocking .................................................................. 30

9.2 AC-Link................................................................... 30

9.3 Reset ........................................................................ 31

9.4 CD Input.................................................................. 31

9.5 Odd Addressed Register Access.............................. 31

9.6 Power-Down Mode.................................................. 31

9.7 Test Mode................................................................ 31

9.7.1 ATE In Circuit Test Mode ............................... 31

9.7.2 Vendor Specific Test Mode ............................. 31

9.8 POWER OFF CD Function ..................................... 32

10. Application Circuits ................................................... 33

11. Mechanical Dimensions.............................................. 37

12. Ordering Information ................................................ 38

Register......................................................................14

6.1.18 MX2C PCM Front/Center Output Sample Rate....15

6.1.19 MX2E PCM Surround Output Sample Rate......15

6.1.20 MX30 PCM LFE Output Sample Rate...........15

6.1.21 MX32 PCM Input Sample Rate......................15

6.1.22 MX36 LFE/Center Master Volume ................15

6.1.23 MX38 Surround Master Volume ....................16

6.1.24 MX3AS/PDIFOutputChannelStatusandControl....16

6.2 Vendor Defined Registers (Page ID-00h) ................17

6.2.1 MX60 S/PDIF Input Channel Status [15:0]......17

6.2.2 MX62 S/PDIF Input Channel Status [29:15]....17

6.2.3 MX64 Surround DAC Volume.........................18

6.2.4 MX66 Center/LFE DAC Volume.....................18

Six-Channel AC’97 2.3 Audio Codec

ii

Rev 1.3

ALC655 Datasheet

1. Features

z Meets performance requirements for audio on

PC99/2001 systems

z External Amplifier Power Down (EAPD)

capability

z Meets Microsoft WHQL/WLP 2.0 audio

requirements

z Power management and enhanced power saving

features

z 16-bit Stereo full-duplex CODEC with 48KHz

sampling rate

z Compliant with AC’97 2.3 specifications

-Front-Out, Surround-Out, MIC-In and LINE-In

Jack Sensing

z Stereo MIC record for AEC/BF application

z Supports Power Off CD function

z Adjustable VREFOUT control

z Supports double sampling rate (96KHz) of DVD

audio playback

-14.318MHz-Æ24.576MHz PLL to save crystal

-12.288MHz BITCLK input can be consumed

-Integrated PCBEEP generator to save buzzer

-Interrupt capability

z Support 48KHz of S/PDIF output is compliant with

AC’97 rev2.3 specification

z Support 32K/44.1K/48KHz of S/PDIF input

z Standard 48-Pin LQFP Package

z EAX™ 1.0&2.0 compatible

z Direct Sound 3D™ compatible

z A3D™ compatible

z Three analog line-level stereo inputs with 5-bit

volume control: LINE_IN, CD, AUX

z High quality differential CD input

z Two analog line-level mono input: PCBEEP,

PHONE-IN

z Two software selectable MIC inputs

z A dedicated Front-MIC input for front panel

applications (software selectable)

z Boost preamplifier for MIC input

z LINE Input shared with surround output; MIC

input shared with Center and LFE output

z Both Front-out and Surround-Out built-in

50mW/20Ω amplifier

z I3DL2 compatible

z HRTF 3D Positional Audio

z Sensaura™ 3D Enhancement (optional)

z 10 Bands of Software Equalizer

z Voice Cancellation and Key Shifting in Kara OK

mode

z AVRack^®Media Player

z Configuration Panel to improve Experience of User

2. General Description

The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six-channel audio CODEC designed for PC multimedia systems,

including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter technology to meet

performance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of stereo outputs with 5-Bit

volume controls, a mono output, and multiple stereo and mono inputs, along with flexible mixing, gain and mute functions to

provide a complete integrated audio solution for PCs. The digital interface circuitry of the ALC655 CODEC operates from a

3.3V power supply for use in notebook and PC applications. The ALC655 integrates 50mW/20ohm headset audio amplifiers at

Front-Out and Surr-Out, built-in 14.318MÆ24.576MHz PLL and PCBEEP generator, those can save BOM costs. The ALC655

also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer electronic products, such

as AC3 decoder/speaker and mini disk devices. ALC655 supports host/soft audio from Intel ICHx chipsets as well as audio

controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows series drivers (WinXP/ME/2000/98/NT), EAX/

Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities (supporting Karaoke, 26-kind of environment sound emulation,

10-band equalizer), HRTF 3D positional audio and Sensaura™ 3D (optional) provide an excellent entertainment package and

game experience for PC users. The ALC655 includes Realtek’s impedance sensing techniques that allow device loads on inputs

and outputs to be detected.

Six-Channel AC’97 2.3 Audio Codec

2

Rev 1.3

ALC655 Datasheet

3. Block Diagram

Six-Channel AC’97 2.3 Audio Codec

3

Rev 1.3

ALC655 Datasheet

4. Pin Assignments

36 35 34 33 32 31 30 29 28 27 26 25

2

LINE-IN-R

LINE-IN-L

MIC2

MIC1

CD-R

CD-GND

CD-L

JD1/GPIO1

JD2

AUX-R

MONO-OUT

AVDD2

SURR-OUT-L

NC

37

38

39

40

41

42

43

44

45

46

47

48

4

23

22

21

20

19

18

17

16

15

14

13

SURR-OUT-R

AVSS2

CEN-OUT

LFE-OUT

JD0/GPIO0

XTLSEL

SPDIFI/EAPD

SPDIFO

ALC655

LLLLLLL

TXXXV

AUX-L

PHONE

1 2 3 4 5 6 7 8 9 10 11 12

Figure 1. Pin Assignments

4.1 Lead (Pb)-Free Package and Version Identification

Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 1. The version number is shown in the

location marked ‘V’.

Six-Channel AC’97 2.3 Audio Codec

4

Rev 1.3

ALC655 Datasheet

5. Pin Description

5.1 Digital I/O Pins

Name

XTL-IN

XTL-OUT

SDATA-

OUT

Type Pin No

Description

Crystal input pad (24.576Mhz)

Crystal output pad

Characteristic Definition

Crystal input pad

Crystal output pad

CMOS input

I

O

I

2

3

5

Serial TDM AC’97 output

BIT-CLK

IO

O

6

8

Bit clock output (12.288Mhz)

Serial TDM AC’97 input

CMOS input/output, Vt=0.35Vdd, internal pulled

low by a 100K resistor.

CMOS output, internal pulled low by a 100K

resistor.

SDATA-IN

SYNC

RESET#

JD1/GPIO1 I / O

I

10

11

17

Sample Sync (48Khz)

AC'97 master H/W reset

Jack Detect 1 / General Purpose

I/O 1

CMOS input

Internally pulled high to AVDD by a 100K resistor

JD2

JD0/GPIO0

I

16

45

Jack Detect 2

Jack Detect 0 / General Purpose

I/O 0

Internally pulled high to AVDD by a 100K resistor

I/O

XTLSEL

SPDIFI /

EAPD

I

I/O

46

47

Crystal Selection

Internally pulled high

Digital input / output

S/PDIF input / External

Amplifier power down control

S/PDIF output

SPDIFO

O

48

Digital output

TOTAL: 13 Pins

XTLSEL=floating, bypass 14.318MHzÆ24.576MHz digital PLL. The clock source is 24.576MHz crystal or external clock.

XTLSEL=pull low, select 14.318MHzÆ24.576MHz digital PLL

5.2 Analog I/O Pins

Name

PC-BEEP

PHONE

AUX-L

AUX-R

CD-L

CD-GND

CD-R

MIC1

Type Pin No

Description

PC speaker input

Speaker phone input

AUX Left channel

AUX Right channel

CD audio Left channel

CD audio analog GND

CD audio Right channel

First Mic in / CEN-OUT

Secondary Mic in / CEN-OUT

Line-In Left channel / S-OUT-L

Characteristic Definition

Analog input (1Vrms)

I

12

13

14

15

18

19

20

21

22

23

24

34

32

I / O

I

Analog input (1Vrms) / Analog output (1Vrms)

MIC2

LINE-L

LINE-R

Front-MIC1

Front-MIC2

Line-In Right channel/ S-OUT-R Analog input (1Vrms) / Analog output (1Vrms)

Dedicated MIC Input 1

(Supported by D version or later)

Line-Out Left channel

Line-Out Right channel

Speaker Phone output

Surround Out Left channel

Surround Out Right channel

Center Out channel

Analog input (1Vrms) for front panel MIC input

I

LINE-OUT-L

LINE-OUT-R

MONO-OUT

S-OUT-L

S-OUT-R

CEN-OUT

LFE-OUT

O

35

36

37

39

41

43

44

Analog output (1Vrms)

Low Frequency Effect Out

channel

TOTAL: 20 Pins

Six-Channel AC’97 2.3 Audio Codec

5

Rev 1.3

ALC655 Datasheet

5.3 Filter/Reference

Name

VREF

Type Pin No

Description

Reference voltage

Ref. voltage out with 5mA drive Analog output (2.5V/4.0V)

ADC anti-aliasing filter capacitor 1nf cap to AVSS

Characteristic Definition

Analog output. +4.7uf and 0.1uf cap to AVSS

O

27

28

29

30

31

VREFOUT

AFILT1

AFILT2

VRDA

NC

Vref for DAC

Not connected

1uf cap to AVSS

33,40

TOTAL: 7 Pins

5.4 Power/Ground

Name

AVDD1

Type

I

Pin No

Description

Analog VDD (5.0V typically)

Characteristic Definition

See section 7.1.1 Absolute Maximum Ratings, page

23 for details.

25

AVDD2

I

38

Analog VDD (5.0V typically)

See section 7.1.1 Absolute Maximum Ratings, page

23 for details.

AVSS1

AVSS2

DVDD1

DVDD2

DVSS1

DVSS2

I

26

42

1

9

4

Analog GND

Digital VDD (3.3V)

Digital GND

7

Digital GND

TOTAL: 8 Pins

Six-Channel AC’97 2.3 Audio Codec

6

Rev 1.3

ALC655 Datasheet

6. Registers

6.1 Mixer Registers

Access to registers with an odd number will return a 0. Reading unimplemented registers will also return a 0.

Reg.

(hex)

00h

NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT

Reset

0

0000h

8000h

02h

Master

Mute

X

ML4 ML3 ML2 ML1 ML0 Mute*

*

X

MR4 MR3 MR2 MR1 MR0

Volume

06h

0Ah

0Ch

Mono-Out Mute

Volume

X

F7

X

F6

X

F5

X

F4

X

F3

X

F2

X

F1

X

F0

X

MM4 MM3 MM2 MM1 MM0

8000h

8008h

PC_BEEP Mute

Volume

PB3 PB2 PB1 PB0

X

PHONE

Volume

Mute

PH4 PH3 PH2 PH1 PH0

0Eh

10h

MIC Volume Mute

X

20dB

X

MI4 MI3 MI2 MI1 MI0

NR4 NR3 NR2 NR1 NR0

8008h

8808h

Line-In

Volume

Mute

NL4 NL3 NL2 NL1 NL0

12h

16h

18h

CD Volume Mute

Aux Volume Mute

X

CL4 CL3 CL2 CL1 CL0

AL4 AL3 AL2 AL1 AL0

PL4 PL3 PL2 PL1 PL0

X

CR4 CR3 CR2 CR1 CR0

AR4 AR3 AR2 AR1 AR0

PR4 PR3 PR2 PR1 PR0

8808h

PCM Out

Volume

Mute

1Ah Record Select

X

LRS2 LRS1 LRS0

X

RRS2 RRS1 RRS0

0000h

8000h

0000h

1Ch

20h

Record Gain Mute

LRG3 LRG2 LRG1 LRG0

RRG3 RRG2 RRG1 RRG0

General

Purpose

X

MIX MS LBK

X

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

36h

38h

3Ah

64h

66h

Audio Int. &

Paging

I4

I3

X

0

I2

I1

I0

X

PG3 PG2 PG1 PG0

REF ANL DAC ADC

0000h

000Fh

09C4h

0040h

BB80h

8080h

2000h

0808h

0000h

60A2h

Power Down EAPD

Ctrl/Status

PR5 PR4 PR3 PR2 PR1 PR0

Extended

Audio ID

0

X

1

X

REV1 REV0

0

X

1

LDAC SDAC CDAC

X

0

SPDIF

X

0

VRA

Extended

Audio Status

X

0

PRK PRJ PRI SPCV

LDAC SDAC CDAC SPSA SPSA

SPDIF

VRA

1

0

PCM front

Sample Rate

1

0

1

0

PCM Surr.

Sample Rate

1

0

1

0

PCM LFE.

Sample Rate

1

0

1

0

PCM Input

Sample Rate

1

0

1

0

Center/LFE Mute

Volume

X

0

X

LFE4 LFE3 LFE2 LFE1 LFE0 Mute

LSR4 LSR3 LSR2 LSR1 LSR0 Mute

X

CNT4 CNT3 CNT2 CNT1 CNT0

RSR4 RSR3 RSR2 RSR1 RSR0

Surround

Volume

Mute

X

S/PDIF Ctl

V

SPSR1SPSR0

L

CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUDI PRO

O

Surr. DAC Mute

Volume

X

0

X

0

LSD4 LSD3 LSD2 LSD1 LSD0

X

0

X

0

X

0

RSD4 RSD3 RSD2 RSD1 RSD0

CEN/LFE

Mute

LD4 LD3 LD2 LD1 LD0

CD4 CD3 CD2 CD1 CD0

DAC Volume

6Ah Multi-channel

Ctl

0

7Ah

Extension

Control

0

7Ch

7Eh

Vendor ID1

Vendor ID2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

414Ch

4760h

X: reserved bit

*: MX36 is the master volume control of CENTER/LFE output.

MX38 is the master volume control of surround output.

Six-Channel AC’97 2.3 Audio Codec

7

Rev 1.3

ALC655 Datasheet

6.1.1 MX00 Reset

Default: 0000H

Writing any value to this register will start a register reset, and causes all of the registers to revert to their default values. Reading this

register returns the ID code of the specific part.

Bit

15:10

Type

-

Function

Reserved

9

8

7

6

5

4

3

2

1

0

R

Read as 0 (Does not support 20-bit ADC)

Read as 0 (Does not support 18-bit ADC)

Read as 0 (Does not support 20-bit DAC)

Read as 0 (Does not support 18-bit DAC)

Read as 0 (No Loudness support)

Read as 0 (No True Line Level output support)

Read as 0 (No simulated stereo for analog 3D block use)

Read as 0 (No Bass & Treble Control)

Read as 0 (No Modem Line support)

R

Read as 0 (No Dedicated Mic PCM input channel)

n Writing any data into this register will reset all mixer registers to their default value. The

written data is ignored.

6.1.2 MX02 (Front) Master Volume

Default: 8000H

These registers control the volume level of Front-Out. Each step on the left and right channels corresponds to a 1.5dB

increase/decrease in volume.

Bit

15

14:13

12:8

7:5

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W Master Left Volume (ML[4:0]) in 1.5 dB steps

Reserved

-

4:0

R/W Master Right Volume (MR[4:0]) in 1.5 dB steps

n For MR/ML, 00h 0 dB

1Fh 46.5 dB attenuation

6.1.3 MX06 MONO_OUT Volume

Default: 8000H

Register 06H controls the mono volume output. Mono output is the same data sent on all output channels. Each step in bits 0:4

corresponds to a 1.5dB increase/decrease in volume, allowing 32 levels of volume from 00000 to 11111.

Bit

15

14:5

4:0

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W Mono Master Volume (MM[4:0]) in 1.5 dB steps

n For MM, 00h

0 dB attenuation

1Fh

46.5 dB attenuation

Six-Channel AC’97 2.3 Audio Codec

8

Rev 1.3

ALC655 Datasheet

6.1.4 MX0A PC BEEP Volume

Default: 0000H

This register controls the input volume for the PC beep signal. Each step in bits 4:1 corresponds to a 3dB increase/decrease in

volume. 16 levels of volume are available, from 0000 to 1111.

The purpose of this register is to allow the PC Beep signals to pass through the ALC655, eliminating the need for an external system

speaker/buzzer. The PC BEEP pin is directly routed (internally hardwired) to the Front-Out. If the PC speaker/buzzer is eliminated, it is

recommended to connect the external speakers at all times so the POST codes can be heard during reset.

Bit

15

Type

R/W

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

14:13

12:5

Reserved

R/W Internal PCBEEP Frequency, F[7:0]

The internal PCBEEP frequency is the result of dividing the 48KHz clock by 4 times the number

specified in F[7:0].

The lowest tone is 48KHz/(255*4)=47Hz.

The highest tone is 48KHz/(1*4)=12KHz.

A value of 00h in F[7:0] disables internal PCBEEP generator and allows external PCBEEP input.

R/W PC Beep Volume (PBV[3:0]) in 3 dB steps

Reserved

4:1

0

n For PB,

00h

0Fh

0 dB attenuation

45 dB attenuation

6.1.5 MX0C PHONE Volume

Default: 8008H

Register 0CH controls the telephone input volume for software modem applications. Because software modem applications may not

have a speaker, the CODEC can offer a speaker-out service. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in

volume, allowing 32 levels of volume, from 00000 to 11111.

Bit

15

14:5

4:0

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W Phone Volume (PV[4:0]) in 1.5 dB steps

n For PV,

00h

08h

1Fh

+12 dB Gain

0dB gain

-34.5dB Gain

6.1.6 MX0E MIC Volume

Default: 8008H

Register 0EH controls the microphone input volume. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in volume,

allowing 32 levels of volume, from 00000 to 11111. Each step in bit 6 corresponds to a magnification of 20dB increase in volume.

Bit

15

14:7

6

5

4:0

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W 20 dB Boost Control 0: Normal 1: 20 dB boost

Reserved

R/W Mic Volume (MV[4:0]) in 1.5 dB steps

-

n For MV,

00h

08h

1Fh

+12 dB Gain

0dB gain

-34.5dB Gain

Six-Channel AC’97 2.3 Audio Codec

9

Rev 1.3

ALC655 Datasheet

6.1.7 MX10 LINE_IN Volume

Default: 8808H

Register 10H controls the LINE_IN input volume. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in volume for the

right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 corresponds to a 1.5dB increase/decrease in

volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.

Bit

15

14:13

12:8

7:5

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W Line-In Left Volume (NL[4:0]) in 1.5 dB steps

Reserved

R/W Line-In Right Volume (NR[4:0]) in 1.5 dB steps

-

4:0

n For NL/NR,

00h +12 dB Gain

08h 0dB gain

1Fh -34.5dB Gain

6.1.8 MX12 CD Volume

Default: 8808H

Register 12H controls the CD input volume. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in volume for the right

channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 corresponds to a 1.5dB increase/decrease in

volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.

it

15

14:13

12:8

7:5

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W CD Left Volume (CL[4:0]) in 1.5 dB steps

Reserved

R/W CD Right Volume (CR[4:0]) in 1.5 dB steps

-

4:0

n For CL/CR, 00h

+12 dB Gain

0dB gain

-34.5dB Gain

08h

1Fh

6.1.9 MX16 AUX Volume

Default: 8808H

Register 16H controls the auxiliary input volume. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease in volume for the

right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 corresponds to a 1.5dB increase/decrease in

volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.

Bit

15

14:13

12:8

7:5

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W AUX Left Volume (AL[4:0]) in 1.5 dB steps

Reserved

R/W AUX Right Volume (AR[4:0]) in 1.5 dB steps

-

4:0

n For AL/AR,

00h +12 dB Gain

08h 0dB gain

1Fh -34.5dB Gain

Six-Channel AC’97 2.3 Audio Codec

10

Rev 1.3

ALC655 Datasheet

6.1.10 MX18 PCM_OUT Volume

Default: 8808H

Register 18H controls the PCM_OUT output volume of front DAC. Each step in bits 4:0 corresponds to a 1.5dB increase/decrease

in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 corresponds to a 1.5dB

increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.

Bit

15

14:13

12:8

7:5

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W PCM Left Volume (PL[4:0]) in 1.5 dB steps

Reserved

R/W PCM Right Volume (PR[4:0]) in 1.5 dB steps

-

4:0

n For PL/PR,

00h +12 dB Gain

08h 0dB gain

1Fh -34.5dB Gain

6.1.11 MX1A Record Select

Default: 0000H

Register 1AH controls the record input source. Each step in bits 2:0 selects a recording source for the right channel. Each step in bits

10:8 selects a recording source for the left channel.

Bit

15:11

10:8

7:3

Type

-

Function

Reserved

R/W Left Record Source Select (LRS[2:0])

Reserved

-

2:0

R/W Right Record Source Select (RRS[2:0])

n For LRS

0

MIC

1

CD LEFT

2

Muted

3

AUX LEFT

4

LINE LEFT

5

6

7

STEREO MIXER OUTPUT LEFT

MONO MIXER OUTPUT

PHONE

o For RRS

0

1

2

3

4

5

6

7

MIC

CD RIGHT

Muted

AUX RIGHT

LINE RIGHT

STEREO MIXER OUTPUT RIGHT

MONO MIXER OUTPUT

PHONE

6.1.12 MX1C Record Gain

Default: 8000H

Register 1CH controls the record gain. Each step in bits 3:0 corresponds to a 1.5dB increase/decrease in gain for the right channel,

allowing 16 levels of gain, from 0000 to 1111. Each step in bits 11:8 corresponds to a 1.5dB increase/decrease in gain for the left

channel, allowing 16 levels of gain, from 0000 to 1111.

Bit

15

14:12

11:8

7:4

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W Left Record Gain Select (LRG[3:0]) in 1.5 dB steps

Reserved

R/W Right Record Gain Select (RRG[3:0]) in 1.5 dB steps

-

3:0

n For LRG/RRG,

0Fh

00h

+22.5dB

0 dB (No Gain)

Six-Channel AC’97 2.3 Audio Codec

11

Rev 1.3

ALC655 Datasheet

6.1.13 MX20 General Purpose Register

Default: 0000H

This register is used to control several functions. Bit 13 enables or disables 3D control. Bit 9 allows selection of mono output.

Bit 8 controls the mic selector. Bit 7 enables loopback of the AD output to the DA input without involving the AC-Link,

allowing for full system performance measurements.

Bit

Type

Function

15:12

11:10

-

R

Reserved, Read as 0

DRSS[1:0], Double Rate Slot Select

01: PCM(n+1) data is on Slots 7/8 (Default)

00,10,11: Reserved

9

8

7

R/W Mono Output Select 0: MIX 1: MIC

R/W Mic Select MIC select 0: MIC 1+(Front-MIC) 1: MIC2+ (Front-MIC)

R/W AD to DA Loop-Back Control 0: Disable 1: Enable

6:0

-

Reserved

n Bit 7 enables ADC to front DAC loop-back.

6.1.14 MX24 Audio Interrupt and Paging

Default: 0000h

Bit

Type

Function

15

Interrupt Status, I4

0: Interrupt is clear.

1: Interrupt was generated

Interrupt event and status are clear by writing a 1 to this bit. The status will change regardless of interrupt

enable (I0).

14

13

R

Interrupt Cause, I3

Reserved, read as 0

Interrupt Cause, I2

I2=0: Sense value in page ID-01h MX6A.[12:8] has not changed.

1: Sense cycle completed or new sense value in page ID-01h MX6A.[12:8] is available.

This bit reflects the cause of the first interrupt event generated. Software should read it after interrupt

status (I4) has been confirmed as interrupting. I2 will be zero when I4 is cleared.

12

11

R/W Sense Cycle, I1

0: Sense cycle not in progress

1: Sense cycle start

Writing a ‘1’ to this bit causes a sense cycle start. If a sense cycle is in progress, writing a ‘0’ to this bit

will abort the sense cycle.

Whether the data in the sense result register (page ID-01h MX6A) is valid or not is determined by the IV

bit in MX6A, Page ID-1h.

R/W Interrupt Enable, I0

0: Interrupt is masked, interrupt status (I4) will not be shown in bit 0 in Slot 12 in SDATA-IN.

1: Interrupt is un-masked, interrupt status (I4) will be shown in bit 0 in Slot 12 in SDATA-IN.

In ALC655, this bit controls the interrupt of sense cycle.

10:4

3:0

NA

Reserved, read as 0

R/W Page Selector, PG[3:0]

0000b: Vendor Specific

0001b: Page ID 01 (AC’97 2.3 Discovery Descriptor Definition)

Others: Reserved.

This register is used to select a descriptor of 16 word pages between registers MX60 to MX6F. Value of

0 is used to select vendor specific space to maintain compatibility with AC’97 2.2 vendor specific

register. Once PG[3:0] is not 0000b and 0001b, ALC655 will return zero data for ACLINK mixer read

command.

Six-Channel AC’97 2.3 Audio Codec

12

Rev 1.3

ALC655 Datasheet

6.1.15 MX26 Power Down Control/Status

Default: 0000H

This read/write register is used to program power down states and monitor subsystem readiness. The lower half of this

register is read only status; a “1” indicating that the subsection is “ready.” Ready is defined as the subsection’s ability to

perform in its nominal state.

When the AC-Link “CODEC Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC’97

control and status registers are in a fully operational state. The AC’97 controller must further probe this powerdown control

/status register to determine exactly which subsections, if any are ready.

Bit

Type

Function

15

R/W PR7 External Amplifier Power Down (EAPD)

0: EAPD output low (enable external amplifier)

1: EAPD output high (shut down external amplifier)

14

13

-

Reserved

R/W PR5 0: Normal

1: Disable internal clock usage (BCLK still be output for modem CODEC)

12

11

10

9

R/W PR4 0: Normal 1: Power down AC-Link

R/W PR3 0: Normal 1: Power down Mixer (Vref off)

R/W PR2 0: Normal 1: Power down Mixer (Vref still on)

R/W PR1 0: Normal 1: Power down PCM DAC (front DAC)

R/W PR0 0: Normal 1: Power down PCM ADC and input MUX

8

7:4

3

2

1

0

-

Reserved, Read as 0

R

Vref Status 1: Vref is up to normal level 0: Not yet

Analog Mixer Status 1: Ready 0: Not yet

DAC Status 1: Ready 0: Not yet

ADC Status 1: Ready 0: Not yet

Truthe table for power down mode:

CDAC SDAC LDAC ADC DAC Mixer Vref ACLINK Int CLK EAPD

*

PR0=1

PR1=1

PR2=1

PR3=1

PR4=1

PR5=1

PR7=1

PRI=1

PRJ=1

PRK=1

PD

High

PD

PD: Power down

Blank: Don’t care

High: output high

* SDAC= Surround DAC, LDAC= LFE DAC, CDAC= Center DAC.

PRI: Center DAC power down control bit defined in MX2A.11

PRJ: Surround DAC power down control bit defined in MX2A.12

PRK: LFE DAC power down control bit defined in MX2A.13

Six-Channel AC’97 2.3 Audio Codec

13

Rev 1.3

ALC655 Datasheet

6.1.16 MX28 Extended Audio ID

Default: 09C6H

The Extended Audio ID register is a read only register used to communicate information to the digital controller.

Bit

15:14

13:12

Type

R

-

Function

ID[1:0]. Always read as 0

Reserved, Read as 0

11:10

9

8

7

6

R

-

R

REV [1:0]=10 to indicate that the ALC655 is AC’97 rev2.3 compliant

AMAP, Read as 0.

LDAC, Read as 1 (LFE DAC is supported, according to AC’97 rev2.3)

SDAC, Read as 1 (Surround DAC is supported, according to AC’97 rev2.3)

CDAC, Read as 1 (Center DAC is supported, according to AC’97 rev2.3)

Reserved, Read as 0

5:3

2

SPDIF, Read as 1 (S/PDIF output is supported)

1

0

R

DRA, Read as 1 (Double Rate Audio is supported)

VRA, Read as 0 (Variable Rate Audio is not supported)

6.1.17 MX2A Extended Audio Status and Control Register

Default: 05F0H

This register contains two active bits for power down and status of the surrounding DACs. Bits 1 & 2 are read/write bits which are

used to enable or disable DRA and SPDIF respectively. Bits 4 & 5 are read/write bits used to determine the AC-LINK slot

assignment of the S/PDIF. Bits 6, 7 & 8 are read only bits which tell the controller when the Center, Surround and LFE DACs are

ready to receive data. Bit 10 is a read only bit which tells the controller if the S/PDIF configuration is valid. Bits 11, 12 & 13 are

read/write bits which are used to power down the Center, Surround and LFE DACs respectively.

Bit

Type

Function

15

R/W VCFG, Validity Configuration of S/PDIF Output

Combined with MX3A.15 to decide validity control in S/PDIF output signal.

14

13

-

Reserved.

R/W Power Down LFE DAC. (PRK)

0: Normal

1: Power down LFE DAC

R/W Power Down Surround DAC. (PRJ)

0: Normal

1: Power down Surround DAC

R/W Power Down Center DAC. (PRI)

0: Normal

12

11

10

1: Power down Center DAC

R

SPCV (S/PDIF Configuration Valid)

0: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid

1: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid

Reserved

9

8

7

-

R

LFE DAC Status (LDAC).

Surround DAC Status (SDAC). 0: Not yet

Center DAC Status (CDAC). 0: Not yet

0: Not yet

1: Ready

6

5:4

R/W SPSA[1:0] (S/PDIF Slot Assignment)

00: S/PDIF source data assigned to AC-LINK slot3/4

01: S/PDIF source data assigned to AC-LINK slot7/8

10: S/PDIF source data assigned to AC-LINK slot6/9

11: S/PDIF source data assigned to AC-LINK slot10/11 (default)

Reserved

3

2

1

0

-

R/W SPDIF Enable. 1: Enable 0: Disable (Hi-Z)

R/W DRA Enable. 1: Enable 0: Disable ‡

-

Reserved.

nSPCV is a read only bit that indicates whether the current S/PDIF-Out configuration is

supported or not. If the configuration is supported, SPCV is set as 1 by H/W. So driver can

Six-Channel AC’97 2.3 Audio Codec

14

Rev 1.3

ALC655 Datasheet

check this bit to determine the status of the S/PDIF transmitter system. SPCV is always

operating, independent of the SPDIF enable bit (MX2A.2). The S/PDIF output is active if

MX2A.2 is set in spite of SPCV. Once S/PDIF output is enabled but SPCV is invalid

(SPCV=0), channel status is still output, but the output data bits will be all zero. The condition

to allow S/PDIF output is SPDIF(MX2A.2)=1 & SPACV=1, otherwise the S/PDIF

output will be all zero when MX2A.2=1 and SPACV=0 (invalid).

oOnly front DACs supports 96KHz sample rate when DRA=1. MX2A.1 just selects clock source

for front DACs. Software must mute surround DACs and CEN/LFE DACs.

6.1.18 MX2C PCM Front/Center Output Sample Rate

Default: BB80H

Bit

Type

Function

15:0

R

Read as BB80h. (ALC655 supports 48KHz sample rate.)

6.1.19 MX2E PCM Surround Output Sample Rate

Default: BB80H

Bit

Type

Function

15:0

R

Read as BB80h. (ALC655 supports 48KHz sample rate.)

6.1.20 MX30 PCM LFE Output Sample Rate

Default: BB80H

Bit

Type

Function

15:0

R

Read as BB80h. (ALC655 supports 48KHz sample rate.)

6.1.21 MX32 PCM Input Sample Rate

Default: BB80H

Bit

Type

Function

15:0

R

Read as BB80h. (ALC655 supports 48KHz sample rate.)

6.1.22 MX36 LFE/Center Master Volume

Default: 8080H

Bit

15

14:13

12:8

7

Type

R/W

-

Function

LFE Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W LFE Master Volume (LFE[4:0]) in 1.5 dB steps

R/W

-

Center Mute Control 0: Normal 1: Mute (-∞ dB)

6:5

Reserved

4:0

R/W Center Master Volume (CNT[4:0]) in 1.5 dB steps

n For LFE/CEN, 00h

0dB

1Fh

46.5dB attenuation

Six-Channel AC’97 2.3 Audio Codec

15

Rev 1.3

ALC655 Datasheet

6.1.23 MX38 Surround Master Volume

Default: 8080H

Bit

15

Type

R/W

-

Function

Left Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W Surround Master Left Volume (LSR[4:0]) in 1.5 dB steps

14:13

12:8

7

R/W

-

Right Mute Control 0: Normal 1: Mute (-∞ dB)

6:5

Reserved

4:0

R/W Surround Master Right Volume (RSR[4:0]) in 1.5 dB steps

n For LSR/RSR, 00h 0dB

1Fh -46.5dB attenuation

6.1.24 MX3A S/PDIF Output Channel Status and Control

Default: 2000H

Bit

Type

Function

15

R/W Validity Control (control V bit in Sub-Frame)

0: The V bit (valid flag) in sub-frame depends on whether or not the S/PDIF data is under-run

1: The V bit in sub-frame is always send as 1 to indicate the invalid data is not suitable for receiver

DRS (Double Rate S/PDIF)

14

R

The ALC655 does not support double rate S/PDIF, this bit is always 0.

13:12

R/W SPSR [1:0] (S/PDIF Sample Rate)

10: Sample rate set to 48KHz. Fs[0:3]=0100 (default)

00,01,11: Reserved

11

10:4

3

R/W LEVEL (Generation Level)

R/W CC [6:0] (Category Code)

R/W PRE (Preemphasis)

0: None

R/W COPY (Copyright)

0: Asserted

1: Filter preemphasis is 50/15 µsec

2

1

0

1: Not asserted

R/W /AUDIO (Non-Audio Data type)

0: PCM data

1: AC3 or other digital non-audio data

R

PRO (Professional or Consumer format)

0: Consumer format

1: Professional format

ALC655 supports consumer channel status format, this bit is always 0

nTo ensure the control and status information started up correctly at the beginning of S/PDIF

transmission, MX3A.[14:0] should only be written to when S/PDIF transmitter is disabled

(MX2A.2=0).

oIf validity control is set (MX3A.15=1), those data bits (bit 8 ~ bit 27) should be forced to 0 to

get better compatibility with mini disc.

Six-Channel AC’97 2.3 Audio Codec

16

Rev 1.3

ALC655 Datasheet

6.2 Vendor Defined Registers (Page ID-00h)

These registers are available to Realtek and Realtek customers for specialized functions.

6.2.1 MX60 S/PDIF Input Channel Status [15:0]

Default: 0000h

The data in MX60 are captured from channel status [15:0] of S/PDIF-IN signal.

Bit

15

14:8

7:6

5:3

2

Type

R

Function

LEVEL (Generation Level)

CC[6:0] (Category Code)

Mode[1:0]

PRE[2:0] (Pre-Emphasis)

COPY (Copyright)

R

0: asserted

1: Not asserted

1

0

R

/AUDIO (Non-Audio Data type)

0: PCM data

PRO (Professional or Consumer format)

0: consumer format 1: professional format

1: AC3 or other digital non-audio data

6.2.2 MX62 S/PDIF Input Channel Status [29:15]

Default: 0000h

The data in MX62 are captured from channel status [29:16] of S/PDIF-IN signal.

Bit

Type

Function

15

R

“V” bit in sub-frame of SPDIFI

0: Data X and Y are valid

1: At least one of data X and Y is invalid

This bit is real-time updated. It has meaning when S/PDIF-IN is locked

S/PDIF-IN Input Signal Locked by hardware

0: Unlocked 1: Locked

14

R

13:12

11:8

R

Ca[1:0] ( Clock Accuracy)

Fs[3:0]. (Sample Frequency in channel status)

0000: 44.1KHz

0010: 48 KHz

0011: 32 KHz

Others: Reserved

7:4

3:0

R

Cn[3:0] (Channel Number)

Sn[3:0] (Source Number)

nThe bits [13:0] are captured from channel status [29:16] of SPDIFI.

oThe consumer channel status of SPDIFI (bit0~bit31):

0

PRO

8

CC0

16

1

2

3

PRE0

11

CC3

19

4

PRE1

12

CC4

20

5

PRE2

13

CC5

21

6

Mode0

14

CC6

22

7

/AUDIO COPY

Mode1

15

LEVEL

23

9

CC1

17

10

CC2

18

Sn0

24

Sn1

25

Sn2

26

Sn3

27

Cn0

28

Cn1

29

Cn2

30

Cn3

31

Fs0

Fs1

Fs2

Fs3

Ca0

Ca1

0

pThe data from SPDIF input is forced to 0 once the SPDIF input signal is unlocked. Software must check this

‘LOCK’ bit before dealing with SPDIF input operations.

Six-Channel AC’97 2.3 Audio Codec

17

Rev 1.3

ALC655 Datasheet

6.2.3 MX64 Surround DAC Volume

Default: 0808H

Bit

15

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W Surround DAC Left Volume (SDL[4:0]) in 1.5 dB steps

Reserved

R/W Surround DAC Right Volume (SDR[4:0]) in 1.5 dB steps

14:13

12:8

7:5

-

4:0

n For SDL/SDR,

00h

08h

1Fh

+12 dB gain

0dB

-34.5dB attenuation

o The default value is 0808H (unmuted).

6.2.4 MX66 Center/LFE DAC Volume

Default: 0808H

Bit

15

Type

R/W

-

Function

Mute Control 0: Normal 1: Mute (-∞ dB)

Reserved

R/W LFE DAC Volume (LD[4:0]) in 1.5 dB steps

Reserved

R/W Center DAC Volume (CD[4:0]) in 1.5 dB steps

14:13

12:8

7:5

-

4:0

n For LD/CD,

00h +12 dB gain

08h 0dB

1Fh -34.5dB attenuation

o The default value is 0808H (unmuted).

6.2.5 MX6A Data Flow Control

Default: 0000h

This register is used to control various parts of the ALC655 multi-channel functions.

Bit

Type

Function

15

RW SPDIF Input Enable

0: Disable (Default) 1: Enable

R/W SPDIF-In Monitoring Control

0: Disable, SPDIFI data is not added into PCM data to DAC. (Default)

1: Enable, MSB 16-bit of SPDIFI data will be added into PCM data to DAC if SPDIFI is locked.

R/W S/PDIF Output Source

14

13:12

00: S/PDIF output data is from ACLINK (default)

01: S/PDIF output data is from ADC

10: Directly bypass S/PDIF-In signal to S/PDIF-Out

11: Reserved.

11

10

9

R/W PCM Data to AC-LINK

0: PCM Data are from ADC (default)

1: PCM Data are from SPDIF input.

R/W MIC1 & MIC2 / CENTER & LFE Output Control

0: pin-21 is MIC1, pin-22 is MIC2 (default)

1: pin-21 is CENTER-Out, pin-22 is LFE-Out.

R/W Line-In / Surround Output Control

0: pin-23 and pin-24 are analog input (Line-In). (default)

1: pin-23 and pin-24 are duplicated output of surround channel (Surround-Out)

8:6

5

-

Reserved

R/W Analog Input Pass to Center/LFE Control

Six-Channel AC’97 2.3 Audio Codec

18

Rev 1.3

ALC655 Datasheet

Bit

Type

Function

0: off 1: on

4

R/W Analog Input Pass to Surround Control

0: off 1: on

3:1

0

-

Reserved

R/W Surround Output Source.

0: S-OUT is the real surround output. (default)

1: S-OUT is the duplicated output of LINE-OUT

6.3 Discovery Descriptor (Page ID-01h)

These registers are defined in AC’97 2.3 for sensing and analog plug&play functions.

6.3.1 MX62 PCI Sub System ID

Default: FFFFh

Bit

Type

Function

15:0

R/W PCI Sub System Vendor ID

This register can be written once only after power on, and is not affected by AC97 cold reset. System

manufacture’s BIOS can set its own sub-system ID.

The default value FFFFh means this register is implemented and data is not set by BIOS.

6.3.2 MX64 PCI Sub Vendor ID

Default: FFFFh

Bit

Type

Function

15:0

R/W PCI Vendor ID

This register can be written once only after power on, and is not affected by AC97 cold reset. System

manufacture’s BIOS can set its own sub-vendor ID.

The default value FFFFh means this register is implemented and data is not set by the BIOS.

6.3.3 MX66 Sense Function Select

Default: 0000h

Bit

15:5

4:1

Type

Function

Reserved

R/W Function Code bits, FC[3:0]

These bits specify the type of audio function described in page ID-01h MX66, MX68, and MX6A.

0h: FRONT OUT

1h: SURROUND OUT

5h: MIC1 In

6h: MIC2 In

7h: LINE In

Others: Not supported

0

R/W Tip or Ring Selection, T/R

This bit sets which jack conductor the sense value is measured from. It is combined with FC[3:0].

0: Tip (Left channel)

1: Ring (Right channel)

Six-Channel AC’97 2.3 Audio Codec

19

Rev 1.3

ALC655 Datasheet

6.3.4 MX68 Sense Function Information

Default: 02F1h

Bit

15:5

4

Type

Function

-

Reserved

R/W Information Valid bit, IV

0: After a sense cycle is completed indicates that no information is provided on the sensing method

1: After a sense cycle is completed indicates that information is provided on the sensing method

Clearing this bit by writing “1”, writing “0” to this bit has no effect.

Reserved

3:1

0

NA

R

Function Information Present, FIP

This bit is set to a ‘0’ indicates that the G[4:0], INV, DL[4:0] and ST[2:0] bits are not supported.

6.3.5 MX6A Sense Detail

Default: 0000h

Bit

15:13

12:8

Type

Function

-

Reserved

R

Sense bits, S[4:0] (Default value depends on sensed result after Cold Reset)

For output devices:

02h: Not specificed or unknown 05h: Powered speaker

Other: Not supported

06h: Earphone or passive speaker

For input deices:

12h: Not specified or unknown 13h: Mono Microphone 15h: Stereo Line-In

Other: Not supported

This field reports the type of output/input peripheral plugged in the jack after sensing.

7:0

R

Always read as 0.

6.4 Extension Registers

6.4.1 MX78 GPIO(JD) Interrupt Control & Status

Default: 0000h

Bit

Type

Function

15

R/W GPIO Statue Indication in SDATA_IN

0:The status of GPIO0(JD0)/GPIO1(JD1)/JD2 and its valid tag are not indicated in SDATA_IN.

1: The status of GPIO0(JD0)/GPIO1(JD1)/JD2 and its valid tag are indicated in SDATA_IN

14

13

12

R/W JD2 interrupt Enable

0: Disable 1: Enable.

A low to high transaction will trigger the interrupt in bit0 in SDATA_IN’s slot-12.

R/W GPIO1(JD1) interrupt Enable (when GPIO1/JD1 is used as input)

0: Disable 1: Enable.

A low to high transaction will trigger the interrupt in bit0 in SDATA_IN’s slot-12.

R/W GPIO0(JD0) interrupt Enable (when GPIO0/JD0 is used as input)

0: Disable 1: Enable.

A low to high transaction will trigger the interrupt in bit0 in SDATA_IN’s slot-12.

11:10

9

NA

Reserved

R/W GPIO1Primitiveness Control

0: Set GPIO1(JD1) as input pin.

1: Set GPIO1(JD1) as output pin.

R/W GPIO0 Primitiveness Control

0: Set GPIO0(JD0) as input pin.

1: Set GPIO0(JD0) as output pin.

8

Six-Channel AC’97 2.3 Audio Codec

20

Rev 1.3

ALC655 Datasheet

Bit

7

Type

NA

Function

Reserved

6

R/W JD2 Interrupt Status (JD2_IS)

0: No JD2 interrupt.

1: JD2 interrupt.

JD2_IS= (MX78.14==1) & (JD2 transition).

Write 1 to clear this status bit.

5

4

R/W GPIO1/JD1 Interrupt Status (JD1_IS). (When GPIO1 is used as input)

0: No JD1 interrupt.

1: JD1 interrupt.

JD1_IS= (MX78.13==1)&(MX78.9==0) & (JD1 transition).

Write 1 to clear this status bit.

R/W GPIO0/JD0 Interrupt Status (JD0_IS). (When GPIO0 is used as input)

0: No JD0 interrupt.

1: JD0 interrupt.

JD0_IS= (MX78.12==1)&(MX78.8==0) & (JD0 transition)

Write 1 to clear this status bit.

3

2

NA

R

Reserved

JD2 Input Status

0: JD2 is driven low by external device (input).

1: JD2 is driven high by external device (input).

1

0

R/W GPIO1(JD1) Input/Output Status

0: GPIO1 is driven low by/to external device.

1: GPIO1 is driven high by/to external device.

R/W GPIO0(JD0) Input/Output Status

0: GPIO0 is driven low by/to external device.

1: GPIO0 is driven high by/to external device.

nGPINT in bit0 of SDATA_IN’s slot-12 = (MX78.4 | MX78.5 | MX78.6 ) | (MX24.15&MX24.11)

oWhen GPIO1/0 is used as input pin, its status will be also reflected in bit2/1 of SDIN’s slot-12. Once GPIO1/0 is

used as output pin, the bit2/1 of SDATA_IN’s slot-12 is always 0.

The GPIOx is internally pulled high by a weak resistor (Weak resistor of approximately

50K~100K ohm).

Six-Channel AC’97 2.3 Audio Codec

21

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ALC655 Datasheet

6.4.2 MX7A Miscellaneous Control

Default: 60A2H

This register is used for three types of information. Bit 0 is a read/write bit which enables/disables the S/PDIF input receiver. Bit 1 is

used to switch pin 47, which is duplexed due for pin-count reduction, between EAPD and S/PDIF modes. Bit 2 is used to select the

clock source for the ALC655.

Bit

Type

Function

15

R

Clock Source Selection (XTLSEL)

0: Disable 14.318MÆ24.576M digital PLL. (Default if XTSEL is floating)

1: Enable 14.318MÆ24.576M digital PLL. (Default if XTLSEL is pull low)

Reserved

14:13

12

-

R/W Vrefout Disable

0: Vrefout is driven by the internal reference (Default)

1: Vrefout is in high-Z mode.

Software must set this bit to disable Vrefout output before MX6A.10 is set (MIC1 and MIC2 are shared

as Center and LFE output).

11

R/W Independent Left/Right Mute Control for MX02

0: Disable, only bit15 is a mute bit for left and right channel (Default)

1: Enable, bit15 mute left channel, bit7 mute right channel.

10:4

3

-

Reserved

R/W JD2 Control Surround-Out, Center-Out and LFE-Out

0: Disable. (Default)

1: Enable, when (MX7A.3=1 & MX78.2=1), Surr-Out and CEN/LFE-Out are muted.

R/W JD1 Control Surround-Out, Center-Out and LFE-Out

0: Disable. (Default)

2

1: Enable, when (MX7A.2=1 & MX78.1=1 & MX78.9=0), Surr-Out and CEN/LFE-Out are muted.

1

0

R/W

Pin-47 Function Selection

0: EAPD 1: SPDIF Input (Default)

R/W JD0 Control Surround-Out, Center-Out and LFE-Out

0: Disable. (Default)

1: Enable, when (MX7A.0=1 & MX78.0=1 & MX78.8=0), Surr-Out and CEN/LFE-Out are muted.

(Internal MX36.15, MX36.7, MX38.15 and MX38.7 are all set to 1.)

This function should be implement by digital designer.

6.4.4 MX7C VENDOR ID1

Default: 414CH

The two registers (MX7C Vendor ID1 and MX7E Vendor ID2) contain four 8-bit ID codes. The first three codes have been

assigned by Microsoft for Plug and Play definitions. The fourth code is a Realtek assigned code identifying the ALC655. The

MX7C Vendor ID1 register contains the value 414Ch, which is the first and second characters of the Microsoft ID code. The

MX7C Vendor ID2 register contains the value 4760h, which is the third of the Microsoft ID code.

Bit

Type

Function

15:0

R

Vendor ID- “AL”

6.4.5 MX7E VENDOR ID2

Default: 4760H

Bit

15:8

7:4

Type

R

Function

Vendor ID- “G”

R

Chip ID- 0110b (ALC655)

Version number- 0000b.

3:0

Six-Channel AC’97 2.3 Audio Codec

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ALC655 Datasheet

7. Electrical Characteristics

7.1.1 Absolute Maximum Ratings

Parameter

Symbol

Minimum

Typical

Maximum

Units

Power Supplies

Digital

Analog

DVDD

AVDD**

Ta

3.0

3.5

0

3.3

5.0

-

3.6

5.5

+70

+125

V

Operating Ambient Temperature

Storage Temperature

^oC

Ts

ESD (Electrostatic Discharge)

Susceptibility Voltage

4500V

Note ** : The standard testing condition before shipping is AVDD = 5.0V unless specified. Customer designing with a

different AVDD should contact Realtek technical support for special testing support.

7.1.2 Threshold Hold Voltage

Dvdd= 3.3V±5%, T_ambient=25⁰C, with 50pF external load.

Parameter

Input voltage range

Symbol

V_in

V_IL

Minimum

Typical

Maximum

Dvdd+0.30

0.35Dvdd

Units

V

-0.30

-

0.7

Low level input voltage

(SYNC,SDATA_OUT,RESET#)

Low level input voltage

(XTAL_IN,BIT_CLK)

Low level input voltage

(Other digital pins)

High level input voltage

(SYNC,SDATA_OUT,RESET#)

High level input voltage

(XTAL_IN,BIT_CLK)

High level input voltage

(Other digital pins)

V_IL

V_IH

-

1.0

1.2

1.7

2.2

1.7

0.35Dvdd

V

-

0.35Dvdd

0.4DVdd

-

High level output voltage

Low level output voltage

Input leakage current

Output leakage current

(Hi-Z)

V_OH

V_OL

-

0.9DVdd

-

0.1DVdd

10

V

µA

-

-10

10

Output buffer drive current

Internal pull up resistance

-

5

50k

-

mA

Ω

30k

100k

7.1.3 Digital Filter Characteristics

Filter

ADC Lowpass Filter

Symbol

Passband

Stopband

Minimum

Typical

Maximum

Units

KHz

dB

0

28.8

-

19.2

Stopband Rejection

Passband

-76.0

+- 0.20

dB

Frequency Response

DAC Lowpass Filter

Passband

Stopband

Stopband Rejection

Passband

0

28.8

-

19.2

KHz

dB

-78.5

+- 0.20

dB

Frequency Response

Six-Channel AC’97 2.3 Audio Codec

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Rev 1.3

ALC655 Datasheet

7.1.4 S/PDIF Output Characteristics

Dvdd= 3.3V, T_ambient=25⁰C, with 75Ω external load.

Parameter

High level output voltage

Low level output voltage

Symbol

V_OH

V_OL

Minimum

Typical

3.3

0

Maximum

Units

V

3.0

-

0.5

7.2 AC Timing Characteristics

7.2.1 Cold Reset

Parameter

RESET# active low pulse width

RESET# inactive to BIT_CLK

Startup delay

Symbol

T_{rst_low}

T_rst2clk

Minimum

1.0

Typical

Maximum

Units

µs

ns

-

162.8

Cold Reset Timing Diagram

7.2.2 Warm Reset

Parameter

SYNC active high pulse width

SYNC inactive to BIT_CLK

Startup delay

Symbol

T_{sync_high}

T_sync2clk

Minimum

1.0

Typical

Maximum

Units

µs

ns

-

162.8

Warm Reset Timing Diagram

Six-Channel AC’97 2.3 Audio Codec

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Rev 1.3

ALC655 Datasheet

7.2.3 AC-Link Clocks

Parameter

BIT_CLK frequency

BIT_CLK period

BIT_CLK output jitter

BIT_CLK high pulse width (note

2)

BIT_CLK low pulse width (note 2)

SYNC frequency

SYNC period

Symbol

T_{clk_period}

T_{clk_high}

T_{clk_low}

Minimum

Typical

12.288

81.4

Maximum

Units

MHz

ns

ps

ns

-

750

45

36

40.7

36

-

40.7

48.0

20.8

1.3

45

-

ns

KHz

µs

T_{sync_period}

T_{sync_high}

T_{sync_low}

SYNC high pulse width

SYNC low pulse width

19.5

Note 1: Worse case duty cycle restricted to 45/55.

BIT_CLK and SYNC Timing Diagram

7.2.4 Data Output and Input Timing

Parameter

Output Valid Delay from rising

edge of BIT_CLK

Symbol

Minimum

Typical

Maximum

Units

ns

t_co

-

15

Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.

Note 2: 50pF external load

Parameter

Input Setup to falling edge of

BIT_CLK

Symbol

t_setup

Minimum

Typical

Maximum

Units

ns

10

-

Input Hold from falling edge of

BIT_CLK

t_hold

10

-

ns

Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.

Parameter

BIT_CLK combined rise or fall

plus flight time

Symbol

Minimum

Typical

Maximum

Units

ns

-

7

SDATA combined rise or fall

plus flight time

-

7

ns

Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes.

Data Output and Input Timing Diagram

Six-Channel AC’97 2.3 Audio Codec

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Rev 1.3

ALC655 Datasheet

7.2.5 Signal Rise and Fall Timing

Parameter

BIT_CLK rise time

BIT_CLK fall time

SYNC rise time

Symbol

Trise_clk

Tfall_clk

Trise_sync

Tfall_sync

Trise_din

Tfall_din

Trise_dout

Tfall_dout

Minimum

Typical

Maximum

Units

ns

-

6

SYNC fall time

SDATA_IN rise time

SDATA_IN fall time

SDATA_OUT rise time

SDATA_OUT fall time

Note 1: 75pF external load (50 pF in AC’97 rev2.1)

Note 2: rise is from 10% to 90% of Vdd (V_olto V_oh)

Note 3: fall is from 90% to 10% of Vdd (V_ohto V_ol)

Signal Rise and Fall Timing Diagram

7.2.6 AC-Link Low Power Mode Timing

Parameter

End of slot 2 to BIT_CLK,

SDATA_IN low

Symbol

T_{s2_pdown}

Minimum

Typical

Maximum

Units

µs

-

1.0

AC-Link Low Power Mode Timing Diagram

Six-Channel AC’97 2.3 Audio Codec

26

Rev 1.3

ALC655 Datasheet

7.2.7 ATE Test Mode

To meet AC’97 rev2.3 specifications, EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in test mode.

Parameter

Setup to trailing edge of RESET#

(also applies to SYNC)

Rising edge of RESET# to Hi-Z

delay

Symbol

T_setup2rst

Minimum

Typical

Maximum

Units

ns

15.0

-

T_off

-

25.0

ns

ATE Test Mode Timing Diagram

7.2.8 AC-Link IO Pin Capacitance and Loading

Output Pin

BIT_CLK (must support ≥ 2

CODECs)

1 CODEC

2 CODEC

62.5pF

3 CODEC

4 CODEC

55pF

75pF

85pF

SDATA_IN

47.5pF

55pF

60pF

62.5pF

7.2.9 SPDIF Output

SPDIF_OUT

Rise time/fall time

Duty cycle

Minimum

Typical

Maximum

Units

%

0

45

10

55

T_(h)

T_(l)

90%

10%

50%

T_(r)

Rise time = 100 * T_(r)/ (T_(l)+ T_(h))%

T_(f)

Notes:

Fall time = 100 * T_(f)/ (T_(l)+ T_(h))%

Duty cycle = 100 * T_(h)/ (T_(l)+ T_(h))%

Six-Channel AC’97 2.3 Audio Codec

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Rev 1.3

ALC655 Datasheet

8. Analog Performance Characteristics

Standard test conditions: T_ambient=25⁰C, Dvdd=3.3V ±5%,Avdd=5.0V±5%

1KHz input sine wave; Sampling frequency=48KHz; 0dB=1Vrms

10KΩ/50pF load; Test bench Characterization BW: 10Hz~22KHz

0dB attenuation; tone and 3D disabled

Parameter

Minimum

Typical

1.6

1.0

1.6

0.16

Maximum

Units

Full scale input voltage: Line inputs (Mixers)

Line inputs (A/D)

-

Vrms

Mic input (0 dB)

Mic input (20 dB boost)

Full scale output voltage

FRONT-OUT / SURROUND-OUT

CEN/LFE-OUT

-

10

-

20

19,200

28,800

-75

-

6

1.25

90

-

86

-70

-75

-

-65

-

Vrms

dB

Analog to Analog S/N:

CD to LINE-OUT

Other to LINE-OUT

Analog frequency response

S/N (A-weighted):

22,000

Hz

dB

D/A

A/D

D/A

A/D

-

Total Harmonic Distortion:

dB

D/A & A/D frequency response

Transition Band

Stop Band

Stop Band Rejection

Out-of-Band Rejection

Group delay

19,200

28,800

Hz

dB

ms

dB

∞

-

1

-

Power Supply Rejection

MIC Boost Gain

-65

30

Master Volume (FRONT/SURR/CEN/LFE): 32 step

Step Size

Attenuation Control Range

Master Volume (MONO-OUT): 32 step

Step Size

Attenuation Control Range

PC Beep Volume 16 steps:

Step Size

Attenuation Control Range

Analog Mixer Volume 32 steps:

Step Size

-

0

1.5

-

dB

-46.5

-

0

1.5

-

dB

-46.5

-

0

3.0

-

dB

-45

-

1.5

-

dB

Gain Control Range

-34.5

+12

Record Gain 16 steps:

Step Size

Gain Control Range

-

0

1.5

-

dB

+22.5

Input impedance (gain = 0dB, mixer = off)

LINE-IN, CD-IN, AUX-IN, MIC1 / MIC2

PCBEEP, PHONE

-

64

16

-

KΩ

Six-Channel AC’97 2.3 Audio Codec

28

Rev 1.3

ALC655 Datasheet

Parameter

Minimum

Typical

Maximum

Units

Output Impedance

FRONT-OUT / SURROUND-OUT

CEN/LFE-OUT

MONO-OUT

-

5

200

500

-

Ω

Amplifier Maximum Output Power

@20Ω load

-

50

mW

Power Supply Current

VA=5.0V

VD=3.3V

-

50

15

-

mA

Power Down Current

VA=5.0V

VD=3.3V

Vrefout/Vrefout2/Vrefout3

Vrefout Drive Current

-

1000

700

4.0

-

uA

V

2.50

5

mA

Six-Channel AC’97 2.3 Audio Codec

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Rev 1.3

ALC655 Datasheet

9. Design Suggestions

9.1 Clocking

The clock source is decided by XTLSEL latched from pin-46 after power-on reset. The clock source of various configurations

is listed below:

Configuration

Pin-46(XTLSEL)

Operation & ID0

ID0

BIT-CLK

Clock Source

NC

Low

NC

0 (Primary) Output

Crystal or ext. 24.576MHz is attached

12.288MHz at XTL-IN

0 (Primary) Output

0 (Primary) Input

Crystal or ext. 14.318MHz is attached

12.288MHz at XTL-IN

12.288M input at BIT-CLKn

*Low: Pulled low by a 0 ohm resistor. NC: Not connected or pulled high.

*Pin-46is internally pulled high by a weak resistor.

nAccording to AC’97 ver 2.3, the primary mode while RESET# is asserted, if a clock is present at BIT-CLK pin for at least 5

cycles before RESET# is de-asserted, ALC655 is a consumer of BITCLK. The ALC655 should use external 12.288MHz

BITCLK as its clock source.

9.2 AC-Link

When the ALC655 receives serial data from the AC97 controller, it samples SDATA_OUT on the falling edge of BIT_CLK.

When the ALC655 sends serial data to the AC97 controller, it starts to drive SDATA_IN on the rising edge of BIT_CLK.

The ALC655 will return any uninstalled bits or registers with 0 for read operations. The ALC655 also stuffs the

unimplemented slot or bit with 0 in SDATA_IN. Note that AC-LINK is MSB-justified.

Refer to the ‘Audio CODEC ’97 Component Specification Revision 2.3’ for details.

Slot#

0

1

2

3

4

5

6

7

8

9

10

11 12

SYNC

TAG CMD DATA PCM PCM

CEN SURR SURR LFE SPDIF SPDIF

SDATA-OUT

L

R

L

R

L

R

SDATA-IN

TAG ADD DATA PCM PCM

L

R

Default ALC655 Slot Arrangement – CODEC ID = 00 (ALC655 supports only primary mode)

Six-Channel AC’97 2.3 Audio Codec

30

Rev 1.3

ALC655 Datasheet

9.3 Reset

There are 3 types of reset operations: Cold, Warm, and Register.

Reset Type

Trigger Condition

CODEC Response

Cold

Assert RESET# for a specified period

Reset all hardware logic and all registers to its default

value.

Register

Warm

Write register indexed 00h

Driven SYNC high for specified period without Reactivates AC-LINK, no change to register values.

BIT_CLK

Reset all registers to its default value.

The AC97 controller should drive SYNC and SDATA_OUT low during the period of RESET# assertion to ensure that the

ALC655 has reset successfully.

9.4 CD Input

It is important to pay attention to differential CD input. Below is an example of differential CD input.

Example of Differential CD Input

9.5 Odd Addressed Register Access

The ALC655 will return ‘0000h’ when odd-addressed and unimplemented registers are read.

9.6 Power-Down Mode

It is important to pay special attention to the power down control register (index 26h), especially PR4 (power down AC-link).

9.7 Test Mode

To provide compatibility with AC’97 rev2.2, the ALC655 will float its digital output pins in both ATE and Vendor-Specific

test modes. Please refer to AC’97 rev2.2 section 9.2 for a detailed description of the test modes.

9.7.1 ATE In Circuit Test Mode

SDATA_OUT is sampled high at the trailing edge of RESET#. In this mode, the ALC655 will drive BIT_CLK, SDATA_IN,

EAPD and SPDIFO to high impedance.

9.7.2 Vendor Specific Test Mode

The Vendor Specific Test mode is no longer supported.

Six-Channel AC’97 2.3 Audio Codec

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Rev 1.3

ALC655 Datasheet

9.8 POWER OFF CD Function

The ‘POWER OFF CD’ function describes a state after the system has been shut down (digital power is off) and a +5V analog

power is supplied, the ALC655 will turn on the CD-IN op and output amplifier. It is possible to design a system which will

save op-amp circuitry and pass CD output directly to the speaker.

The figure below indicates the system application circuitry to support the ‘POWER OFF CD’ function. The operation mode is

defined by +3.3VCC and +5VA analog power without VAUX is required for ALC20x series codecs.

+3.3VCC

No (0)

Yes (1)

+5VA

No (0)

Yes (1)

-

No (0)

Yes (1)

+5Vstandby

Operation Mode

Shut Down

Power Off CD

Digital on, Analog is off

Normal

No (0)

-

Yes (1)

No (0)

-

+5VA

+5Vstandby

+3.3VCC

D1

1N5817M/CYL

D2

+

1N5817M/CYL

0.1u

10u

0.1u

2

3

XTL-IN

XTL-OUT

35

36

37

FRONT-OUT-L

FRONT-OUT-R

MONO-OUT

11

6

10

5

27

28

RESET#

BITCLK

SYNC

SDOUT

SDIN

VREF

VREFOUT

29

30

AFILT1

AFILT2

8

31

32

33

34

43

44

45

46

47

48

39

40

41

VRDA

VRAD

NC

12

13

14

15

16

17

18

20

21

22

23

24

PC-BEEP

PHONE

AUX-L

AUX-R

JD2

JD1/GPIO1

CD-L

CD-R

MIC1

MIC2

LINE-L

LINE-R

ALC655

FRONT-MIC

CEN-OUT

LFE-OUT

JD0/GPIO0

XTLSEL

SPDIFI/EAPD

SPDIFO

SURR-OUT-L

NC

SURR-OUT-R

0

1u

1

2

3

4

0

CD-IN

1u

Six-Channel AC’97 2.3 Audio Codec

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Rev 1.3

ALC655 Datasheet

10. Application Circuits

The application circuit is for design reference only. System designers are suggested to visit Realtek’s web site to download the

latest application circuits. To get the best compatibility in hardware design and software driver, any modifications of

application circuits should be confirmed by Realtek.

FRONT-MIC2

R38

0@658

JD4

C75

VREFOUT2 for UAJ2

R43 0@658

+5VAUX

D1

1u@655

Reserved for ALC655/658 (Power Off CD)

R43 is only for ALC658(UAJ2 bias voltage)

1N4148@655/658

Reserve for fine tune accuracy

of Jack Sensing

C9

+12V

R55

U1

FRONT-MIC1 C4

1u

C13 1u@650

C1

5.6K@ALC655/658

+5VA

LM7805CT/200mA

1u@650

L3

FERB

+

10u

3

1

OUT IN

VREFOUT

FRONT-OUT-L

FRONT-OUT-R

C5

100u

+5VA

C7

+

C12

C10

1000P

C8

+10u

C11

0.1u

C6

C15

10u

+10u

+

C16

1u

+

VREFOUT3 for UAJ1

R46

0@658

C14

1000P

10u

U8

R46 is for ALC658(UAJ1 bias voltage)

+5VA

C21

C22

1u

LINE-IN-R

LINE-IN-L

+

C19

10u

C20

1u

LINE-IN-L

37

38

39

40

41

42

43

44

45

24

23

22

21

20

19

18

17

16

15

14

13

MONO-O

LINE-IN-R

C24

C25

1u

MIC2-IN

MIC1-IN

MIC2-IN

AVDD2

LINE-IN-L

MIC2

SURR-OUT-L

JD3

C23 1u

MIC1-IN

J4

SURR-OUT-L/HP-OUT-L

JD3

NC

MIC1

C27 1u

C28 1u

C30 1u

R1

R2

R3

0

CD-IN Header

4

3

2

1

SURR-OUT-R

C26 1u

SURR-OUT-R/HP-OUT-R

AVSS2

CD-R

CD-GND

CD-L

ALC650/655/658

CENTER-OUT

LFE-OUT

JD0

C29

C31

1u

CEN-OUT

LFE-OUT

J16

1

2

3

4

C67

JD1/VIDEO-R

JD2/VIDEO-L

AUX-R

VIDEO-IN Header

1u@650

C68

JD0

JD0/GPIO0

XTLSEL/ID1#

SPDIFI/EAPD

SPDIFO

R4

0@EXT-14.318M 46

J5

1u@650

SPDIFI

47

48

C37

R34 0@655/658 JD1

JD1

JD2

AUX-L

4

3

2

1

1u@655/650

C39

R44 0@655/658 JD2

PHONE

Spilt by DGND

1u@655/650

AUX-IN Header

C69

C70

220u@658

UAJ2-R

UAJ2-L

SPDIFO

ALC-AC97

+3.3VDD

C41 1u R7

0

Audio-From-Modem

C42

0.1u

C43

10u

C44

0.1u

+

R12B1 10K

C12A1

1u

Signal-From-PCSPK

C12B1

100P

R12A1

1K

+3.3VDD

R8 0@EXT-14.318M Y1

AC97-RESET#

AC97-SYNC

EXT 14.318MHz

24.576MHz

R9

22

R10

22

C45

22P

C46

22P

AC97-SDIN

AC97-BCLK

AC97-SDOUT

DGND

AGND

C50

22P

Crysatl Saving:

R8,R4=0; Y1,C45,C46=X (EXT-14.318MHz clock)

Tied at one point only under

the codec or near the codec

R8,R4=X; Y1=24.576M, C45,C46=22p (24.576MHz crystal)

ALC655

ALC658

ALC650

C67

C68

R34

R44

C37

C39

C69

C70

C13

C9

X

1u

X

Arrangement of Jack Detection Pin:(ALC655)

0

JD0 for MIC-IN

JD1 for FRONT-OUT

JD2 for LINE-IN

0

X

1u

X

1u

X

100u

X

Arrangement of Jack Detection Pin:(ALC658)

JD0 for MIC-IN

X

JD1 for UAJ1(Front-Pannel)

JD2 for UAJ2 (Front-Pannel)

JD3 for FRONT-OUT

X

1u

X

JD4 for LINE-IN

C75

R46

R43

1u

X

1u

0

X

0

X

Compatible Filter Connection with ALC655

Six-Channel AC’97 2.3 Audio Codec

33

Rev 1.3

ALC655 Datasheet

INTEL Front Panel I/O Design Guide V1.0

J11

FRONT-MIC1

R26

0

+5VA

1

2

R27 10K

3

5

7

9

11

13

15

4

6

8

10

12

14

16

+5VA

JD1 R61

FRONT-OUT-R R28

20

AUD-RET-R

AUD-RET-L

0@658

J8

KEY

SURR-OUT-L

AGND

DGND

SPDIF-IN

DGND

SURR-OUT-R

AGND

+3.3VDD

+5VDD

SPDIF-OUT

FRONT-OUT-L R29

20

AUD-RET-L

SURR-OUT-L

SPDIF-OUT

SURR-OUT-L

SPDIF-IN

1

3

5

7

9

2

4

6

8

10

JD0 R51

0@Reserve

SURR-OUT-R R39

20@Reserve

SURR-OUT-L

R40

Onboard Header for Back Panel Bracket

Onboard Header for Front Panel

VREFOUT2 for UAJ2

VREFOUT3 for UAJ1

UAJ2-R R48 20@655 FRONT-MIC2

FRONT-MIC1 R47 20@655

UAJ2-L

JD2

R62

0@658

REALTEK Front Panel I/O for UAJ

R26

R61

R62

R51

R47

R48

ALC655/658/650(with Intel Front Pannel)

0

X

0

X

0

X

ALC658(with Realtek Front Pannel

function)

- UAJ

Onboard Headers for Back Panel Bracket and Front Panel

For Automatic Jack Sensing Only

For ALC650:

JD Block=X

R42 10K

JD0

VREFOUT

For ALC655 and ALC658:

JD Block=0

VREFOUT

+

C74

3.3u

JD Block

R12

4.7K@655/658(Stereo MIC)

R13

4.7K/2.2K

J7

FERB

MIC2-IN

MIC1-IN

R15

R17

0

L8

L9

1

2

3

4

5

MIC2-IN

MIC1-IN

R57

22K

R58

22K

C52

C53

Microphone In / Center-LFE Out

100P

For Automatic Jack Sensing Only

For ALC650:

JD Block=X

For ALC650:

R12=X R13=2.2K

R45 10K

For ALC655:

R71

R72

0@658

0@655

For ALC655 and ALC658 use Mono MIC:

R12=X R13=2.2K

JD4

JD2

R71=X R72=0

+

C73

3.3u

For ALC658:

R71=0 R72=X

JD Block

For ALC655 and ALC658 use Stereo MIC:

R12=4.7K R13=4.7K

J10

FERB

LINE-IN-R

LINE-IN-L

R20

R21

0

L10

L11

1

2

3

4

5

LINE-IN-R

LINE-IN-L

FERB

R22

22K

R23

C55

C56

Line In / Surround Out

22K

100P

For Automatic Jack Sensing Only

For ALC650:

JD Block=X

R56 10K

R73

R74

0@658

0@655

JD3

JD1

For ALC655:

R73=X R74=0

+

C72

3.3u

JD Block

For ALC658:

R73=0 R74=X

J13

L13

L15

FERB

AUD-RET-R

AUD-RET-L

1

2

3

4

5

AUD-RET-R

AUD-RET-L

R59

22K

R60

22K

C60

100P

C61

100P

LINE Out (AMP-Out)

Analog I/O Connection

Six-Channel AC’97 2.3 Audio Codec

34

Rev 1.3

ALC655 Datasheet

J1

L1

L2

FERB

SURR-OUT-R

SURR-OUT-L

1

2

3

4

5

Optical

Transmitter

U3

Back Panel Bracket

TOTX178

C3

5

4

C2

N.C

100P

Surround Out

J3

L4

L5

FERB

LFE-OUT

1

2

3

4

5

C32

0.1u

CENTER-OUT

+5VDD

J6

C18

C17

C38

R5

100

100P

1

SPDIF-OUT

Center/Lfe Out

S/PDIF OUTPUT

Only for ALC650/655/658

C40 0.01u

100P

R6

(Coaxial)

220

J2

SURR-OUT-L

AGND

DGND

SPDIF-IN

DGND

SURR-OUT-R

AGND

+3.3VDD

+5VDD

SURR-OUT-L

SURR-OUT-R

SPDIF-IN

1

3

5

7

9

2

4

6

8

10

SPDIF-OUT

Bracket Connector

+3.3VDD

+5VDD

TORX176/173 with ATC control is recommended

TORX178/179 can be used without connecting RCA

U5

C33

10u

C34

0.1u

C35

10u

C36

0.1u

Optical

Receiver

Optical

Receiver

U4

+

TORX178

TORX176/173

5

6

4

5

CASE

R11

10

SPDIF-IN

L6 47uH

R14

+3.3VDD

L7

47uH

C47

0.1u

+5VDD

2.2K

C49

+5VDD

C48

0.1u

R16

10K

0.01u

R18 10

J9

1

C51 0.01u

SPDIF-IN

R19

10K

C54

S/PDIF INPUT

100P

Only for ALC650/655/658

Back Panel Bracket for Surround/CEN/LFE Outputs and S/PDIF I/O

Six-Channel AC’97 2.3 Audio Codec

35

Rev 1.3

ALC655 Datasheet

R50 10K@UAJ

FRONT-JACK2-ON

+

R24

10K

C71

3.3u@UAJ

+5VA

C57

UAJ Block

1u@Norm

J12

L12

FERB

1

2

3

4

5

L14

AUD-MIC

R35

0

C59

C58

R25

10K

Front Panel MIC / UAJ2

+5VA

100P

R31

Front Panel Module

UAJ2-IO-R

UAJ2-IO-L

R53

0@655/658

0@658

22K@655/658

R54

J14

AUD-MIC

AUD-MIC-BIAS

AUD-OUT-R

FRONT-JACK1-ON

AUD-OUT-L

+5VA

RET-R

1

3

5

7

2

4

6

R52

VREFOUT2-UAJ2

KEY

8

RET-L

9

10

12

14

16

11

13

15

UAJ Block

VREFOUT2-UAJ2

VREFOUT3-UAJ1

UAJ2-IO-R

UAJ2-IO-L

FRONT-JACK2-ON

Front Connector

FRONT-JACK1-ON

R32 10K

1~10 pin connector: INTEL Front Panel I/O Design Guide V1.0

11~16 pin: REALTEK Front Panel I/O for UAJ

+

C66

3.3u

C64

100u/ 0ohm

RET-R

J15

L16

L17

FERB

AUD-OUT-R

1

2

3

4

5

AUD-OUT-L

C63

C62

R49 0@658

Front Panel Out / UAJ1

RET-L

VREFOUT3-UAJ1

UAJ Block

R30

100P 100P

22K@655/658

C65

100u/ 0ohm

UAJ

Block

R64

R65

R32

R66

R30

R31

R24

R57

R35

R25

R53

R54

ALC655/658/650(with Intel Front Pannel)

0

X

4.7K

X

1u

X

0

X

0

X

0

X

10K

3.3u

22K

ON

ALC658(with Realtek Front Pannel

function)

- UAJ

Front Panel Connection

Six-Channel AC’97 2.3 Audio Codec

36

Rev 1.3

ALC655 Datasheet

11. Mechanical Dimensions

L

L1

SYMBOL

MILLIMETER

INCH

TITLE: LQFP-48 (7.0x7.0x1.6mm)

PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm

TYPICAL

MIN.

MAX. MIN.

1.60

0.15 0.002

MAX

0.063

0.006

0.057

0.008

A

A1

A2

C

LEADFRAME MATERIAL

0.05

1.35

0.09

APPROVE

CHECK

DOC. NO.

1.40

1.45 0.053 0.055

0.20 0.004

VERSION 02

DWG NO. PKGC-065

DATE

D

9.00 BSC

7.00 BSC

5.50

0.354 BSC

0.276 BSC

0.217

D1

D2

E

E1

E2

b

REALTEK SEMICONDUCTOR CORP.

9.00 BSC

7.00BSC

5.50

0.354 BSC

0.276 BSC

0.217

0.17

0.20

0.27 0.007 0.008

0.011

7^o

e

TH

L

0.50 BSC

0.0197 BSC

0^o

0.45

3.5^o

7^o

0^o3.5^o

0.60

1.00

0.75 0.018 0.0236 0.030

0.0393

L1

Six-Channel AC’97 2.3 Audio Codec

37

Rev 1.3

ALC655 Datasheet

12. Ordering Information

Table 1. Ordering Information

Part Number

ALC655

ALC655-LF

Package

Status

Standard product. LQFP-48

ALC655 with Lead (Pb)-Free package

Note 1: See page 4 for lead (Pb)-free package and version identification.

Note 2: Above parts are tested under AVDD =5.0V. If customers have lower AVDD request, please contact

Realtek sales representatives or agents.

Realtek Semiconductor Corp.

Headquarters

No. 2, Innovation Road II

Hsinchu Science Park, Hsinchu 300, Taiwan

Tel.: +886-3-578-0211. Fax: +886-3-577-6047

www.realtek.com.tw

Six-Channel AC’97 2.3 Audio Codec

38

Rev 1.3

型号:	ALC886-GR
是否Rohs认证：	符合
生命周期：	Active
包装说明：	LFQFP,
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.7
滤波器：	YES
JESD-30 代码：	S-PQFP-G48
长度：	7 mm
功能数量：	1
端子数量：	48
工作模式：	SYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP
封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
座面最大高度：	1.6 mm
标称供电电压：	3.3 V
表面贴装：	YES
电信集成电路类型：	PCM CODEC
温度等级：	COMMERCIAL
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
宽度：	7 mm
Base Number Matches：	1

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