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产品型号AMC1305L25DWR的概述

AMC1305L25DWR芯片概述 AMC1305L25DWR是一款由德州仪器公司（Texas Instruments）设计和生产的高精度、隔离式模拟前端（AFE）芯片，专门用于工业和电力电子应用。该芯片用于测量高电压信号，并通过其内置的隔离技术将测量结果安全传输到系统的低压部分。它满足了现代电气测量系统对低功耗、低失真和高精度的需求。详细参数 AMC1305L25DWR芯片的主要参数如下： - 工作电压：3.15 V至5.5 V的电源电压范围，适应不同的应用需求。 - 电源功耗：在3.3 V供电下，功耗低至150 mW，适合电池供电的环境。 - 增益：具有2.5 V/V的固定增益，适合于宽范围的输入信号处理。 - 输入信号范围：能够处理高达±2500 V的输入信号，这使其在电力和能源监测等领域的应用非常广泛。 - 分辨率：该芯片提供了16位的数字分辨率，确保了对输入信号的高精度采样...

产品型号AMC1305L25DWR的Datasheet PDF文件预览

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AMC1305L25, AMC1305M05, AMC1305M25

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

AMC1305x

高精度、增强隔离式 Δ-Σ 调制器

1 特性

3 说明

•

针对基于分流电阻的电流测量进行优化的引脚兼容

系列：

AMC1305 器件是一款高精度 Δ-Σ (ΔΣ) 调制器，通过

磁场抗扰度较高的电容式双隔离栅隔离输出与输入电

路。根据 DIN V VDE V 0884-10、UL1577 和 CSA 标

准，该隔离栅经认证可提供高达 7000 V_峰值的增强型

隔离。当与隔离电源配合使用时，该器件可防止共模高

电压线路上的噪声电流进入本地系统接地，从而干扰或

损害低电压电路。

–

输入电压范围为 ±50mV 或 ±250mV

互补金属氧化物半导体 (CMOS) 或低压差分信

令 (LVDS) 数字接口选项

•

出色的直流性能，支持系统级高精度感测：

–

偏移误差：±50µV 或 ±150µV（最大值）

偏移漂移：1.3µV/°C（最大值）

增益误差：±0.3%（最大值）

AMC1305 针对直接连接分流电阻器或其它低电压等级

信号源进行了优化，同时具有出色的直流和交流性能。

分流电阻器通常用于感测电机驱动、绿色能源发电系统

或其它工业应用中的电流。通过使用适当的数字滤波

器（即，集成于 TMS320F2837x）来抽取位流，该器

件可在 78kSPS 数据速率下实现 85dB (13.8 ENOB)

动态范围的 16 位分辨率。

增益漂移：±40ppm/°C（最大值）

•

安全相关认证：

–

7000 V_PK增强型隔离，符合 DIN V VDE V

0884-10 (VDE V 0884-10): 2006-12 标准

符合 UL 1577 标准且长达 1 分钟的 5000 V_RMS

隔离

CAN/CSA No. 5A 组件接受服务通知、IEC

60950-1 和 IEC 60065 终端设备标准

在高侧，调制器由 5V (AVDD) 标称电压供电，而隔离

数字接口则由 3.3V 或 5V 电源 (DVDD) 供电。

•

瞬态抗扰度：15kV/µs（最小值）

AMC1305 采用宽体小外形尺寸集成电路 (SOIC)-16

(DW) 封装，工作温度范围为 –40°C 至 +125°C。

高电磁场抗扰度

（请参见应用手册 SLLA181A）

•

外部 5MHz 至 20MHz 时钟输入

可更加轻松地实现系统级同步

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

可在扩展工业温度范围内运行

AMC1305x

SOIC (16)

10.30mm x 7.50mm

(1) 如需了解所有可用封装，请参见数据表末尾的可订购产品附

录。

2 应用

•

基于分流电阻的电流感测用于下列应用：

–

工业电机驱动

光电逆变器

不间断电源

•

隔离电压感测

简化电路原理图

Floating

Power Supply

HV+

AMC1305

DVDD

Gate Driver

5.0 V

AVDD

3.3 V, or 5.0 V

AGND

DGND

R_SHUNT

To Load

AINN

AINP

DOUT

CLKIN

SD-Dx

SD-Cx

PWMx

Gate Driver

TMS320F2837x

HV-

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS654

AMC1305L25, AMC1305M05, AMC1305M25

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

www.ti.com.cn

8.1 Overview ................................................................. 21

8.2 Functional Block Diagram ....................................... 21

8.3 Feature Description................................................. 22

8.4 Device Functional Modes........................................ 24

Application and Implementation ........................ 25

9.1 Application Information............................................ 25

9.2 Typical Applications ................................................ 26

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Power Ratings........................................................... 5

7.6 Insulation Specifications............................................ 6

7.7 Safety-Related Certifications..................................... 7

7.8 Safety Limiting Values .............................................. 7

7.9 Electrical Characteristics: AMC1305M05.................. 8

7.10 Electrical Characteristics: AMC1305x25............... 10

7.11 Switching Characteristics...................................... 12

7.12 Insulation Characteristics Curves ......................... 13

7.13 Typical Characteristics.......................................... 14

Detailed Description ............................................ 21

10 Power-Supply Recommendations ..................... 30

11 Layout................................................................... 31

11.1 Layout Guidelines ................................................. 31

11.2 Layout Examples................................................... 31

12 器件和文档支持 ..................................................... 33

12.1 文档支持................................................................ 33

12.2 相关链接................................................................ 33

12.3 接收文档更新通知 ................................................. 33

12.4 社区资源................................................................ 33

12.5 商标....................................................................... 33

12.6 静电放电警告......................................................... 33

12.7 Glossary................................................................ 33

13 机械、封装和可订购信息....................................... 34

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision E (January 2017) to Revision F

Page

•

Changed minimum specification from DGND – 0.3 to DGND – 0.5 and maximum specification from DVDD + 0.3 to

DVDD + 0.5 in Digital input voltage parameter row of Absolute Maximum Ratings table...................................................... 5

Changes from Revision D (August 2016) to Revision E

Page

•

Changed V_(ESD)for Human-body model (HBM) from ±1000 V to ±2500 V............................................................................. 5

Changes from Revision C (December 2014) to Revision D

Page

•

已添加后两个“特性” 要点的措辞.............................................................................................................................................. 1

已更改简化原理图................................................................................................................................................................... 1

Moved Power Rating, Insulation Specifications, Regulatory Information, and Safety Limiting Values tables ....................... 5

Changed Insulation Specifications table as per ISO standard .............................................................................................. 6

Added Insulation Characteristics Curves section ................................................................................................................ 13

Changed Figure 54 .............................................................................................................................................................. 26

Changed Figure 58 .............................................................................................................................................................. 30

Changes from Revision B (October 2014) to Revision C

Page

•

已将 AMC1305M05 的器件状态更改为“量产数据”.................................................................................................................. 1

已将文档状态从“混合状态”更改为“量产数据” .......................................................................................................................... 1

Updated ESD Ratings table to latest standard ...................................................................................................................... 5

AMC1305L25, AMC1305M05, AMC1305M25

www.ti.com.cn

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

Changes from Revision A (November 2014) to Revision B

Page

•

已将 AMC1305M25 的器件状态更改为量产数据 .................................................................................................................... 1

已更改特性要点“安全及管理批准”至“安全相关认证” ............................................................................................................. 1

Changes from Original (June 2014) to Revision A

Page

•

已更改产品预览数据表............................................................................................................................................................ 1

AMC1305L25, AMC1305M05, AMC1305M25

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

www.ti.com.cn

5 Device Comparison Table

INPUT VOLTAGE

DIFFERENTIAL INPUT

RESISTANCE

SNR (sinc³Filter,

78 kSPS)

PART NUMBER

AMC1305L25

AMC1305M05

AMC1305M25

RANGE

±250 mV

±50 mV

OUTPUT INTERFACE

25 kΩ

5 kΩ

82 dB

76 dB

82 dB

LVDS

CMOS

±250 mV

25 kΩ

6 Pin Configuration and Functions

DW Package

16-Pin SOIC

Top View

DW Package

16-Pin SOIC

Top View

AINP

AINN

AGND

16 DGND

AINP

AINN

AGND

16 DGND

DVDD

CLKIN

CLKIN_N

DOUT

DOUT_N

DGND

DVDD

CLKIN

DOUT

AVDD

AGND

AVDD

AGND

DGND

LVDS Versions (AMC1305L25)

CMOS Versions (AMC1305Mx)

Pin Functions

I/O

NAME

NO.

DESCRIPTION

This pin is internally connected to pin 8 and can be left unconnected or tied to high-side

ground

—

AGND

—

High-side ground reference

Inverting analog input

AINN

AINP

Noninverting analog input

High-side power supply, 4.5 V to 5.5 V.

See the Power-Supply Recommendations section for decoupling recommendations.

AVDD

—

CLKIN

CLKIN_N

DGND

Modulator clock input, 5 MHz to 20.1 MHz

AMC1305L25 only: inverted modulator clock input

Controller-side ground reference

9, 16

—

DOUT

Modulator data output

DOUT_N

DVDD

AMC1305L25 only: inverted modulator data output

Controller-side power supply, 3.0 to 5.5 V

This pin can be connected to AVDD or can be left unconnected

This pin can be left unconnected or tied to AGND only

These pins have no internal connection (pins 10 and 12 on the AMC1305Mx only).

This pin can be left unconnected or tied to DVDD only

6, 10, 12

AMC1305L25, AMC1305M05, AMC1305M25

www.ti.com.cn

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

7 Specifications

7.1 Absolute Maximum Ratings

over the operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

6.5

UNIT

Supply voltage, AVDD to AGND or DVDD to DGND

Analog input voltage at AINP, AINN

AGND – 6

DGND – 0.5

–10

AVDD + 0.5

DVDD + 0.5

Digital input voltage at CLKIN, CLKIN_N

Input current to any pin except supply pins

Maximum virtual junction temperature, T_J

Storage temperature, T_stg

°C

150

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2500

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

5.0

MAX

UNIT

AVDD

DVDD

T_A

High-side (analog) supply voltage

Controller-side (digital) supply voltage

Operating ambient temperature range

5.5

3.0

3.3

–40

125

°C

7.4 Thermal Information

AMC1305x

THERMAL METRIC⁽¹⁾

DW (SOIC)

16 PINS

80.2

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

40.5

45.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

11.9

ψ_JB

44.5

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Power Ratings

PARAMETER

TEST CONDITIONS

VALUE

UNIT

Maximum power dissipation

(both sides)

P_D

AVDD = 5.5 V, DVDD = 5.5 V, LVDS, R_LOAD= 100 Ω

89.1

Maximum power dissipation

(high-side supply)

P_D1

P_D2

AVDD = 5.5 V

45.1

Maximum power dissipation

(low-side supply)

DVDD = 5.5 V, LVDS, R_LOAD= 100 Ω

AMC1305L25, AMC1305M05, AMC1305M25

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

www.ti.com.cn

UNIT

7.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

GENERAL

CLR

Minimum air gap (clearance)⁽¹⁾

Shortest pin-to-pin distance through air

≥ 8

Shortest pin-to-pin distance across the package

surface

CPG

Minimum external tracking (creepage)⁽¹⁾

Minimum internal gap (internal clearance) of the

double insulation (2 × 0.0135 mm)

DTI

CTI

Distance through insulation

0.027

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

≥ 600

Rated mains voltage ≤ 300 V_RMS

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

I-II

Overvoltage category per IEC 60664-1

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12⁽²⁾

Maximum repetitive peak isolation

voltage

V_IORM

At ac voltage (bipolar or unipolar)

1414

V_PK

At ac voltage (sine wave)

At dc voltage

1000

1500

7000

V_RMS

V_DC

Maximum-rated isolation working

voltage

V_IOWM

V_TEST= V_IOTM, t = 60 s (qualification test)

V_IOTM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

V_PK

V_TEST= 1.2 x V_IOTM, t = 1 s (100% production

test)

8400

Test method per IEC 60065, 1.2/50-μs

waveform, V_TEST= 1.6 x V_IOSM= 10000 V_PK

(qualification)

V_IOSM

6250

V_PK

Method a, after input/output safety test subgroup

2 / 3, V_ini= V_IOTM, t_ini= 60 s, V_pd(m)= 1.2 x V_IORM

= 1697 V_PK, t_m= 10 s

≤ 5

Method a, after environmental tests subgroup 1,

q_pd

Apparent charge⁽⁴⁾

V_ini= V_IOTM, t_ini= 60 s, V_pd(m)= 1.6 x V_IORM

2263 V_PK, t_m= 10 s

Method b1, at routine test (100% production) and

preconditioning (type test), V_ini= V_IOTM, t_ini= 1 s,

V_pd(m)= 1.875 x V_IORM= 2652 V_PK, t_m= 1 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

Pollution degree

V_IO= 0.5 V_PPat 1 MHz

1.2

> 10⁹

V_IO= 500 V at T_S= 150°C

Ω

Climatic category

40/125/21

UL1577

V_TEST= V_ISO= 5000 V_RMSor 7000 V_DC, t = 60 s

(qualification test), V_TEST= 1.2 x V_ISO= 6000

V_RMS, t = 1 s (100% production test)

V_ISO

Withstand isolation voltage

5000

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed

circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as

inserting grooves or ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier are tied together, creating a two-pin device.

AMC1305L25, AMC1305M05, AMC1305M25

www.ti.com.cn

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

7.7 Safety-Related Certifications

VDE

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):

2006-12, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN

60095 (VDE 0860): 2005-11

Recognized under UL1577 component recognition and CSA

component acceptance NO 5 programs

Reinforced insulation

Single protection

File number: 40040142

File number: E181974

7.8 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A

failure of the I/O circuitry may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient

power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

θ_JA= 80.2°C/W, AVDD = DVDD = 5.5 V, T_J= 150°C,

T_A= 25°C, see Figure 3

283

I_S

Safety input, output, or supply current

θ_JA= 80.2°C/W, AVDD = DVDD = 3.6 V, T_J= 150°C,

T_A= 25°C, see Figure 3

432

P_SSafety input, output, or total power

T_SMaximum safety temperature

θ_JA= 80.2°C/W, T_J= 150°C, T_A= 25°C, see Figure 4

1558⁽¹⁾

150

°C

(1) Input, output, or the sum of input and output power must not exceed this value.

The maximum safety temperature is the maximum junction temperature specified for the device. The power

dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines

the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that

of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended

maximum input voltage times the current. The junction temperature is then the ambient temperature plus the

power times the junction-to-air thermal resistance.

AMC1305L25, AMC1305M05, AMC1305M25

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

www.ti.com.cn

7.9 Electrical Characteristics: AMC1305M05

All minimum and maximum specifications at T_A= –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =

–50 mV to 50 mV, AINN = 0 V, and sinc³filter with OSR = 256, unless otherwise noted. Typical values are at T_A= 25°C,

CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

Maximum differential voltage input range

(AINP-AINN)

V_Clipping

FSR

±62.5

Specified linear full-scale range

(AINP-AINN)

–50

V_CM

C_ID

I_IB

Operating common-mode input range

Differential input capacitance

Input current

–0.032

AVDD – 2

–72

Inputs shorted to AGND

–97

-57

μA

R_ID

I_OS

Differential input resistance

Input offset current

kΩ

±5

CMTI

Common-mode transient immunity

kV/μs

f_IN= 0 Hz,

_{CM min}≤ V_IN≤ V_{CM max}

–104

CMRR

Common-mode rejection ratio

Input bandwidth

f_INfrom 0.1 Hz to 50 kHz,

_{CM min}≤ V_IN≤ V_{CM max}

–75

800

kHz

DC ACCURACY

DNL

INL

Differential nonlinearity

Integral nonlinearity⁽¹⁾

Resolution: 16 bits

Initial, at 25°C

–0.99

–4

0.99

LSB

µV

±1.5

±2.5

E_O

Offset error

–50

TCE_O

E_G

Offset error thermal drift⁽²⁾

Gain error

Gain error thermal drift⁽³⁾

–1.3

–0.3%

–40

1.3

0.3%

μV/°C

Initial, at 25°C

–0.02%

±20

TCE_G

PSRR

ppm/°C

Power-supply rejection ratio

V_AVDDfrom 4.5 to 5.5V, at dc

105

AC ACCURACY

SNR

Signal-to-noise ratio

f_IN= 1 kHz

SINAD

THD

Signal-to-noise + distortion

Total harmonic distortion

Spurious-free dynamic range

–90

–83

SFDR

DIGITAL INPUTS/OUTPUTS

External Clock

f_CLKIN

Input clock frequency

Duty cycle

20.1

60%

MHz

Duty_CLKIN

5 MHz ≤ f_CLKIN≤ 20.1 MHz

DGND ≤ V_IN≤ DVDD

40%

50%

CMOS Logic Family, CMOS with Schmitt-Trigger

I_IN

Input current

–1

μA

C_IN

V_IH

Input capacitance

High-level input voltage

Low-level input voltage

Output load capacitance

0.7 × DVDD

–0.3

DVDD + 0.3

0.3 × DVDD

V_IL

C_LOAD

f_CLKIN= 20 MHz

I_OH= –20 µA

I_OH= –4 mA

I_OL= 20 µA

DVDD – 0.1

DVDD – 0.4

V_OH

High-level output voltage

Low-level output voltage

0.1

0.4

V_OL

I_OL= 4 mA

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

value_MAX- value_MIN

TCE_O

TempRange

(2) Offset error drift is calculated using the box method as described by the following equation:

≈ value _MAX- value _MIN

’

∆

TCE_G( ppm) =

ì10

value ìTempRange

◊

(3) Gain error drift is calculated using the box method as described by the following equation:

AMC1305L25, AMC1305M05, AMC1305M25

www.ti.com.cn

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

Electrical Characteristics: AMC1305M05 (continued)

All minimum and maximum specifications at T_A= –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =

–50 mV to 50 mV, AINN = 0 V, and sinc³filter with OSR = 256, unless otherwise noted. Typical values are at T_A= 25°C,

CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

AVDD

I_AVDD

High-side supply voltage

High-side supply current

High-side power dissipation

Controller-side supply voltage

4.5

5.0

6.5

5.5

8.2

P_AVDD

DVDD

32.5

3.3

45.1

5.5

3.0

3.0 V ≤ DVDD ≤ 3.6 V

2.7

4.0

I_DVDD

Controller-side supply current

4.5 V ≤ DVDD ≤ 5.5 V

3.0 V ≤ DVDD ≤ 3.6 V

4.5 V ≤ DVDD ≤ 5.5 V

3.2

5.5

8.9

14.4

30.3

P_DVDD

Controller-side power dissipation

16.0

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7.10 Electrical Characteristics: AMC1305x25

All minimum and maximum specifications at T_A= –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =

–250 mV to 250 mV, AINN = 0 V, and sinc³filter with OSR = 256, unless otherwise noted. Typical values are at T_A= 25°C,

CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

Maximum differential voltage input range

(AINP-AINN)

V_Clipping

FSR

±312.5

Specified linear full-scale range

(AINP-AINN)

–250

250

V_CM

C_ID

I_IB

Operating common-mode input range

Differential input capacitance

Input current

–0.16

AVDD – 2

–60

Inputs shorted to AGND

–82

–48

μA

R_ID

I_OS

Differential input resistance

Input offset current

kΩ

±5

CMTI

Common-mode transient immunity

kV/μs

f_IN= 0 Hz,

_{CM min}≤ V_IN≤ V_{CM max}

–95

CMRR

Common-mode rejection ratio

Input bandwidth

f_INfrom 0.1 Hz to 50 kHz,

_{CM min}≤ V_IN≤ V_{CM max}

–76

1000

kHz

DC ACCURACY

DNL

INL

Differential nonlinearity

Integral nonlinearity⁽¹⁾

Resolution: 16 bits

Initial, at 25°C

–0.99

–4

0.99

LSB

±1.5

±40

E_O

Offset error

–150

–1.3

–0.3

–40

150

1.3

0.3

µV

TCE_O

E_G

Offset error thermal drift⁽²⁾

Gain error

Gain error thermal drift⁽³⁾

μV/°C

%FS

ppm/°C

Initial, at 25°C

–0.02

±20

TCE_G

PSRR

Power-supply rejection ratio

V_AVDDfrom 4.5 V to 5.5 V, at dc

AC ACCURACY

SNR

Signal-to-noise ratio

f_IN= 1 kHz

SINAD

THD

Signal-to-noise + distortion

Total harmonic distortion

Spurious-free dynamic range

–90

–83

SFDR

DIGITAL INPUTS/OUTPUTS

External Clock

f_CLKIN

Input clock frequency

Duty cycle

20.1

60%

MHz

Duty_CLKIN

5 MHz ≤ f_CLKIN≤ 20.1 MHz

40%

50%

CMOS Logic Family (AMC1305M25), CMOS with Schmitt-Trigger

I_IN

Input current

DGND ≤ V_IN≤ DVDD

–1

μA

C_IN

V_IH

Input capacitance

High-level input voltage

Low-level input voltage

Output load capacitance

0.7 × DVDD

–0.3

DVDD + 0.3

0.3 × DVDD

V_IL

C_LOAD

f_CLKIN= 20 MHz

I_OH= –20 µA

I_OH= –4 mA

I_OL= 20 µA

DVDD – 0.1

DVDD – 0.4

V_OH

High-level output voltage

Low-level output voltage

0.1

0.4

V_OL

I_OL= 4 mA

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as the number of LSBs or as a percent of the specified linear full-scale range FSR.

value_MAX- value_MIN

TCE_O

TempRange

(2) Offset error drift is calculated using the box method as described by the following equation:

≈ value _MAX- value _MIN

’

∆

TCE_G( ppm) =

ì10

value ìTempRange

◊

(3) Gain error drift is calculated using the box method as described by the following equation:

AMC1305L25, AMC1305M05, AMC1305M25

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Electrical Characteristics: AMC1305x25 (continued)

All minimum and maximum specifications at T_A= –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP =

–250 mV to 250 mV, AINN = 0 V, and sinc³filter with OSR = 256, unless otherwise noted. Typical values are at T_A= 25°C,

CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVDS Logic Family (AMC1305L25)

V_OD

V_OCM

I_S

Differential output voltage

Output common-mode voltage

Output short-circuit current

Input common-mode voltage

Differential input voltage

Input current

R_LOAD= 100 Ω

250

350

450

1.375

1.125

1.23

V_ICM

V_ID

V_ID= 100 mV

0.05

100

–24

1.25

350

3.25

600

µA

I_IN

DGND ≤ V_IN≤ 3.3 V

POWER SUPPLY

AVDD

I_AVDD

High-side supply voltage

4.5

3.0

5.0

6.5

5.5

8.2

High-side supply current

P_AVDD

DVDD

High-side power dissipation

Controller-side supply voltage

32.5

3.3

45.1

5.5

AMC1305L25, R_LOAD= 100 Ω

6.1

8.0

AMC1305M25, 3.0 ≤ DVDD ≤ 3.6 V,

C_LOAD= 5 pF

2.7

4.0

I_DVDD

Controller-side supply current

AMC1305M25, 4.5 ≤ DVDD ≤ 5.5 V,

C_LOAD= 5 pF

3.2

20.1

8.9

5.5

44.0

14.4

AMC1305L25, R_LOAD= 100 Ω

AMC1305M25, 3.0 ≤ DVDD ≤ 3.6 V,

C_LOAD= 5 pF

P_DVDD

Controller-side power dissipation

AMC1305M25, 4.5 ≤ DVDD ≤ 5.5 V,

C_LOAD= 5 pF

16.0

30.3

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7.11 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

49.75

19.9

TYP

MAX

200

120

UNIT

t_CLK

t_HIGH

t_LOW

t_D

CLKIN, CLKIN_N clock period

CLKIN, CLKIN_N clock high time

CLKIN, CLKIN_N clock low time

19.9

Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay,

C_LOAD= 5 pF

Interface startup time

(DVDD at 3.0 V min to DOUT, DOUT_N valid with AVDD ≥ 4.5 V)

CLKIN

cycles

t_ISTART

t_ASTART

Analog startup time (AVDD step up to 4.5 V with DVDD ≥ 3.0 V)

t_CLK

t_HIGH

/[YLb

/[YLb_b

t_LOW

t_D

5hÜÇ

5hÜÇ_b

Figure 1. Digital Interface Timing

5ë55

/[YLb

5hÜÇ

...

5ata not valid

ëalid data

t_ISTART= 32 CLKIN cycles

Figure 2. Digital Interface Startup Timing

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7.12 Insulation Characteristics Curves

500

1600

1400

1200

1000

800

600

400

200

AVDD = DVDD = 3.6 V

AVDD = DVDD = 5.5 V

400

300

200

100

150

200

100

150

200

T_A(°C)

D043

D044

Figure 3. Thermal Derating Curve for Safety Limiting

Current per VDE

Figure 4. Thermal Derating Curve for Safety Limiting Power

per VDE

T_Aup to 150°C, stress voltage frequency = 60 Hz

Figure 5. Reinforced Isolation Capacitor Lifetime Projection

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7.13 Typical Characteristics

At T_A= 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256, unless otherwise noted.

-20

1305x25

1305M05

-40

-60

-20

-40

-60

-80

-100

1305x25

1305M05

-120

-0.5

0.5

1.5

2.5

0.001

0.01

0.1 0.2 0.5

f_IN(kHz)

2 3 5 710 20 50 100

V_CM(V)

D001

D002

Figure 6. Input Current vs Input Common-Mode Voltage

Figure 7. Common-Mode Rejection Ratio vs

Input Signal Frequency

3.5

2.5

-1

1.5

-2

-3

0.5

-4

-0.25 -0.2 -0.15 -0.1 -0.05

0.05 0.1 0.15 0.2 0.25

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

V_IN(mV)

D003

D004

Figure 8. Integral Nonlinearity vs Input Signal Amplitude

Figure 9. Integral Nonlinearity vs Temperature

150

125

100

-25

-50

-75

-100

-125

-150

-10

-20

-30

-40

-50

4.5 4.6 4.7 4.8 4.9

5.1 5.2 5.3 5.4 5.5

4.5 4.6 4.7 4.8 4.9

5.1 5.2 5.3 5.4 5.5

AVDD (V)

D005

D006

AMC1305x25

Figure 10. Offset Error vs High-Side Supply Voltage

AMC1305M05

Figure 11. Offset Error vs High-Side Supply Voltage

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256, unless otherwise noted.

150

125

100

-25

-50

-75

-100

-125

-150

-10

-20

-30

-40

-50

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

D007

D008

AMC1305x25

AMC1305M05

Figure 12. Offset Error vs Temperature

Figure 13. Offset Error vs Temperature

150

125

100

0.3

0.2

0.1

1305x25

1305M05

-25

-50

-75

-100

-125

-150

-0.1

-0.2

-0.3

4.5 4.6 4.7 4.8 4.9

5.1 5.2 5.3 5.4 5.5

f_CLKIN(MHz)

AVDD (V)

D009

D010

Figure 14. Offset Error vs Clock Frequency

Figure 15. Gain Error vs High-Side Supply Voltage

0.3

0.2

0.1

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

f_CLKIN(MHz)

D011

D012

Figure 16. Gain Error vs Temperature

Figure 17. Gain Error vs Clock Frequency

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256, unless otherwise noted.

100

1305x25

1305M05

SNR (x25)

SINAD (x25)

SNR (M05)

SINAD (M05)

-20

-40

-60

-80

-100

-120

0.001

0.01

0.1

100

4.5 4.6 4.7 4.8 4.9

5.1 5.2 5.3 5.4 5.5

Ripple Frequency (kHz)

AVDD (V)

D013

D014

Figure 18. Power-Supply Rejection Ratio vs

Ripple Frequency

Figure 19. SNR and SINAD vs High-Side Supply Voltage

100

SNR (x25)

SINAD (x25)

SNR (M05)

SNR (x25)

SINAD (x25)

SNR (M05)

SINAD (M05)

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

f_CLKIN(MHz)

D015

D016

Figure 20. SNR and SINAD vs Temperature

Figure 21. SNR and SINAD vs Clock Frequency

100

SNR (x25)

SNR

SINAD

SINAD (x25)

SNR (M05)

SINAD (M05)

0.1

100

50 100 150 200 250 300 350 400 450 500

V_IN(mVpp)

f_IN(kHz)

D017

D018

AMC1305x25

Figure 22. SNR and SINAD vs Input Signal Frequency

Figure 23. SNR and SINAD vs Input Signal Amplitude

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256, unless otherwise noted.

100

-60

SNR

SINAD

-65

-70

-75

-80

-85

-90

-95

-100

-105

-110

90 100

4.5 4.6 4.7 4.8 4.9

5.1 5.2 5.3 5.4 5.5

V_IN(mVpp)

AVDD (V)

D019

D020

AMC1305M05

Figure 24. SNR and SINAD vs Input Signal Amplitude

Figure 25. Total Harmonic Distortion vs

High-Side Supply Voltage

-60

-65

-70

-75

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

f_CLKIN(MHz)

D021

D022

Figure 26. Total Harmonic Distortion vs Temperature

Figure 27. Total Harmonic Distortion vs Clock Frequency

-60

-65

-70

-65

-70

-75

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

0.1

100

50 100 150 200 250 300 350 400 450 500

V_IN(mVpp)

f_IN(kHz)

D023

D024

AMC1305x25

Figure 28. Total Harmonic Distortion vs

Input Signal Frequency

Figure 29. Total Harmonic Distortion vs

Input Signal Amplitude

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256, unless otherwise noted.

-60

110

105

100

-65

-70

-75

-80

-85

-90

-95

-100

-105

-110

100

150

4.5 4.6 4.7 4.8 4.9

5.1 5.2 5.3 5.4 5.5

V_IN(mVpp)

AVDD (V)

D025

D026

AMC1305M05

Figure 30. Total Harmonic Distortion vs

Input Signal Amplitude

Figure 31. Spurious-Free Dynamic Range vs

High-Side Supply Voltage

110

105

100

110

105

100

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

f_CLKIN(MHz)

D027

D028

Figure 32. Spurious-Free Dynamic Range vs Temperature

Figure 33. Spurious-Free Dynamic Range vs

Clock Frequency

110

105

100

110

105

100

0.1

100

50 100 150 200 250 300 350 400 450 500

V_IN(mVpp)

f_IN(kHz)

D029

D030

AMC1305x25

Figure 34. Spurious-Free Dynamic Range vs

Input Signal Frequency

Figure 35. Spurious-Free Dynamic Range vs

Input Signal Amplitude

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256, unless otherwise noted.

110

105

100

-20

-40

-60

-80

-100

-120

-140

100

150

V_IN(mVpp)

Frequency (kHz)

D031

D032

AMC1305M05

AMC1305x25, 4096-point FFT, V_IN= 500 mV_PP

Figure 36. Spurious-Free Dynamic Range vs

Input Signal Amplitude

Figure 37. Frequency Spectrum with 1-kHz Input Signal

-20

-40

-60

-80

-40

-60

-80

-100

-120

-140

-100

-120

-140

Frequency (kHz)

D033

D034

AMC1305x25, 4096-point FFT, V_IN= 500 mV_PP

AMC1305M05, 4096-point FFT, V_IN= 500 mV_PP

Figure 38. Frequency Spectrum with 5-kHz Input Signal

Figure 39. Frequency Spectrum with 1-kHz Input Signal

-20

-40

-60

-80

-100

-120

-140

4.5 4.6 4.7 4.8 4.9

5.1 5.2 5.3 5.4 5.5

Frequency (kHz)

AVDD (V)

D035

D036

AMC1305M05, 4096-point FFT, V_IN= 500 mV_PP

Figure 40. Frequency Spectrum with 5-kHz Input Signal

Figure 41. High-Side Supply Current vs

High-Side Supply Voltage

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5.0 V, DVDD = 3.3 V, AINP = –250 mV to 250 mV, AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256, unless otherwise noted.

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

f_CLKIN(MHz)

D037

D038

Figure 42. High-Side Supply Current vs Temperature

Figure 43. High-Side Supply Current vs Clock Frequency

LVDS

CMOS

LVDS

CMOS

3.1

3.2

3.3

3.4

3.5

3.6

4.5 4.6 4.7 4.8 4.9

5.1 5.2 5.3 5.4 5.5

DVDD (V)

D039

D040

Figure 44. Controller-Side Supply Current vs

Controller-Side Supply Voltage (3.3 V, nom)

Figure 45. Controller-Side Supply Current vs

Controller-Side Supply Voltage (5 V, nom)

LVDS 5 V

LVDS 3.3 V

CMOS 5 V

LVDS 5V

LVDS 3.3V

CMOS 5 V

CMOS 3.3 V

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

Clock Frequency (MHz)

D041

D042

Figure 46. Controller-Side Supply Current vs Temperature

Figure 47. Controller-Side Supply Current vs

Clock Frequency

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8 Detailed Description

8.1 Overview

The differential analog input (AINP and AINN) of the AMC1305 is a fully-differential amplifier feeding the

switched-capacitor input of a second-order delta-sigma (ΔΣ) modulator stage that digitizes the input signal into a

1-bit output stream. The isolated data output (DOUT) of the converter provides a stream of digital ones and zeros

synchronous to the externally-provided clock source at the CLKIN pin with a frequency in the range of 5 MHz to

20.1 MHz. The time average of this serial bit-stream output is proportional to the analog input voltage.

The Functional Block Diagram section shows a detailed block diagram of the AMC1305. The analog input range

is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The SiO₂-

based capacitive isolation barrier supports a high level of magnetic field immunity as described in the application

report ISO72x Digital Isolator Magnetic-Field Immunity (SLLA181A), available for download at www.ti.com. The

external clock input simplifies the synchronization of multiple current-sense channels on the system level. The

extended frequency range of up to 20.1 MHz supports higher performance levels compared to other solutions

available on the market.

8.2 Functional Block Diagram

DVDD

AVDD

AINP

AINN

BUF

DOUT

ûꢀ-Modulator

DOUT_N (AMC1305L25 only)

CLKIN

1.25-V

Reference

BUF

CLKIN_N (AMC1305L25 only)

AMC1305

DGND

AGND

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8.3 Feature Description

8.3.1 Analog Input

The AMC1305 incorporates front-end circuitry that contains a differential amplifier and sampling stage, followed

by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for

devices with a specified input voltage range of ±250 mV (for the AMC1305x25), or to a factor of 20 for devices

with a ±50-mV input voltage range (for the AMC1305M05), resulting in a differential input impedance of 5 kΩ (for

the AMC1305M05) or 25 kΩ (for the AMC1305x25).

Consider the input impedance of the AMC1305 in designs with high-impedance signal sources that can cause

degradation of gain and offset specifications. The importance of this effect, however, depends on the desired

system performance. Additionally, the input bias current caused by the internal common-mode voltage at the

output of the differential amplifier causes an offset that depends on the actual amplitude of the input signal. See

the Isolated Voltage Sensing section for more details on reducing these effects.

There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the

range of AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input

electrostatic discharge (ESD) protection diodes turn on. In addition, the linearity and noise performance of the

device are ensured only when the differential analog input voltage remains within the specified linear full-scale

range (FSR), that is ±250 mV (for the AMC1305x25) or ±50 mV (for the AMC1305M05), and within the specified

input common-mode range.

8.3.2 Modulator

The modulator implemented in the AMC1305 is a second-order, switched-capacitor, feed-forward ΔΣ modulator,

such as the one conceptualized in Figure 48. The analog input voltage V_INand the output V₅of the 1-bit digital-

to-analog converter (DAC) are differentiated, providing an analog voltage V₁at the input of the first integrator

stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage

V₃that is differentiated with the input signal V_INand the output of the first integrator V₂. Depending on the polarity

of the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC responds on the

next clock pulse by changing its analog output voltage V₅, causing the integrators to progress in the opposite

direction while forcing the value of the integrator output to track the average value of the input.

f_/[YLb

ë₁

ë₂

ë₃

ë₄

ë_Lb

Integrator 1

Integrator 2

ꢀ

/at

0 ë

ë₅

DAC

Figure 48. Block Diagram of a Second-Order Modulator

The modulator shifts the quantization noise to high frequencies; see Figure 49. Therefore, use a low-pass digital

filter at the output of the device to increase overall performance. This filter is also used to convert from the 1-bit

data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's microcontroller

family TMS320F2837x offers a suitable programmable, hardwired filter structure termed a sigma-delta filter

module (SDFM) optimized for usage with the AMC1305 family. Also, SD24_B converters on the MSP430F677x

microcontrollers offer a path to directly access the integrated sinc-filters, thus offering a system-level solution for

multichannel isolated current sensing. An additional option is to use a suitable application-specific device (such

as the AMC1210, a four-channel digital sinc-filter). Alternatively, a field-programmable gate array (FPGA) can be

used to implement the digital filter.

AMC1305L25, AMC1305M05, AMC1305M25

www.ti.com.cn

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

Feature Description (continued)

-20

-40

-60

-80

-100

-120

-140

100

10k

100k

10M

Frequency (Hz)

Figure 49. Quantization Noise Shaping

8.3.3 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A

differential input of 250 mV (for the AMC1305x25) or 50 mV (for the AMC1305M05) produces a stream of ones

and zeros that are high 90% of the time. A differential input of –250 mV (–50 mV for the AMC1305M05)

produces a stream of ones and zeros that are high 10% of the time. These input voltages are also the specified

linear ranges of the different AMC1305 versions with performance as specified in this document. If the input

voltage value exceeds these ranges, the output of the modulator shows non-linear behavior while the

quantization noise increases. The output of the modulator would clip with a stream of only zeros with an input

less than or equal to –312.5 mV (–62.5 mV for the AMC1305M05) or with a stream of only ones with an input

greater than or equal to 312.5 mV (62.5 mV for the AMC1305M05). In this case, however, the AMC1305

generates a single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device

function (see the Fail-Safe Output section for more details). The input voltage versus the output modulator signal

is shown in Figure 50.

The density of ones in the output bit-stream for any input voltage value (with the exception of a full-scale input

signal as described in Output Behavior in Case of Full-Scale Input ) can be calculated using Equation 1:

V _IN+ V_Clipping

2 * V_Clipping

(1)

The AMC1305 system clock is typically 20 MHz and is provided externally at the CLKIN pin. Data are

synchronously provided at 20 MHz at the DOUT pin. Data change at the CLKIN falling edge. For more details,

see the Switching Characteristics table.

Modulator Output

+FS (Analog Input)

-FS (Analog Input)

Analog Input

Figure 50. Analog Input versus AMC1305 Modulator Output

AMC1305L25, AMC1305M05, AMC1305M25

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

www.ti.com.cn

8.4 Device Functional Modes

8.4.1 Fail-Safe Output

In the case of a missing high-side supply voltage (AVDD), the output of a ΔΣ modulator is not defined and could

cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable.

Therefore, the AMC1305 implements a fail-safe output function that ensures the device maintains its output level

in case of a missing AVDD, as shown in Figure 51.

/[YLb

!ë55

5hÜÇ

!ë55 Dhh5

!ë55 C!L[

/ase 1: 5hÜÇ = Z1[ ÁZꢀv !ë55 (ꢁ]o•

/ase 2: 5hÜÇ = Z0[ ÁZꢀv !ë55 (ꢁ]o•

Figure 51. Fail-Safe Output of the AMC1305

8.4.2 Output Behavior in Case of Full-Scale Input

If a full-scale input signal is applied to the AMC1305 (that is, V_IN≥ V_Clipping), the device generates a single one or

zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed, as shown in Figure 52.

In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the system level.

/[YLb

...

5hÜÇ

ëLb ≤ 312.5 mV (AMC1305M05: 61.5 mV)

...

ëLb ≥ 312.5 mV (AMC1305M05: 61.5 mV)

127 /[YLb cycles

Figure 52. Overrange Output of the AMC1305

AMC1305L25, AMC1305M05, AMC1305M25

www.ti.com.cn

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Digital Filter Usage

The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a

conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort

and hardware, is a sinc³-type filter, as shown in Equation 2:

-OSR

≈

’

1- z

∆

H(z) =

1- z^-1

◊

(2)

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-

order modulator. All the characterization in this document is also done with a sinc³filter with an over-sampling

ratio (OSR) of 256 and an output word width of 16 bits.

SNR

1.76

6.02

ENOB

(3)

sinc1

sinc2

sinc3

100

1000

OSR

D053

Figure 53. Measured Effective Number of Bits versus Oversampling Ratio

An example code for an implementation of a sinc³filter in an FPGA, see the application note Combining

ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications (SBAA094), available

for download at www.ti.com.

AMC1305L25, AMC1305M05, AMC1305M25

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

www.ti.com.cn

9.2 Typical Applications

9.2.1 Frequency Inverter Application

Because to their high ac and dc performance, isolated ΔΣ modulators are being widely used in new generation

frequency inverter designs. Frequency inverters are critical parts of industrial motor drives, photovoltaic inverters

(string and central inverters), uninterruptible power supplies (UPS), electrical and hybrid electrical vehicles, and

other industrial applications. The input structure of the AMC1305 is optimized for use with low-impedance shunt

resistors and is therefore tailored for isolated current sensing using shunts.

DC link

Gate Driver

R_SHUNT

Gate Driver

AMC1305

TMS320F2837x

SD-D1

AVDD

DVDD

DOUT

CLKIN

DGND

5.0 V

3.3 V

AINP

AINN

AGND

SD-C1

AMC1305

AVDD

DVDD

DOUT

CLKIN

DGND

5.0 V

3.3 V

AINP

AINN

AGND

SD-D2

SD-C3

AMC1305

AVDD DVDD

AMC1305

5.0 V

3.3 V

AVDD

DVDD

DOUT

CLKIN

DGND

5.0 V

3.3 V

AINP

AINN

AGND

DOUT

CLKIN

DGND

SD-D4

SD-C4

AINP

AINN

AGND

PWMx

SD-D5

SD-C5

Figure 54. The AMC1305 in a Frequency Inverter Application

9.2.1.1 Design Requirements

A typical operation of the device in a frequency inverter application is shown in Figure 54. When the inverter

stage is part of a motor drive system, measurement of the motor phase current is done via the shunt resistors

(R_SHUNT). Depending on the system design, either all three or only two phase currents are sensed.

In this example, an additional fourth AMC1305 is used to support isolated voltage sensing of the dc link. This

high voltage is reduced using a high-impedance resistive divider before being sensed by the device across a

smaller resistor. The value of this resistor can degrade the performance of the measurement, as described in the

Isolated Voltage Sensing section.

9.2.1.2 Detailed Design Procedure

The usually recommended RC filter in front of a ΔΣ modulator to improve signal-to-noise performance of the

signal path, is not required for the AMC1305. By design, the input bandwidth of the analog front-end of the

device is limited to 1 MHz.

For modulator output bit-stream filtering, a device from TI's TMS320F2837x family of dual-core MCUs is

recommended. This family supports up to eight channels of dedicated hardwired filter structures that significantly

simplify system level design by offering two filtering paths per channel: one providing high accuracy results for

the control loop and one fast response path for overcurrent detection.

AMC1305L25, AMC1305M05, AMC1305M25

www.ti.com.cn

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

Typical Applications (continued)

9.2.1.3 Application Curve

In motor control applications, a very fast response time for overcurrent detection is required. The time for fully

settling the filter in case of a step-signal at the input of the modulator depends on its order; that is, a sinc³filter

requires three data updates for full settling (with f_DATA= f_CLK/ OSR). Therefore, for overcurrent protection, filter

types other than sinc³can be a better choice; an alternative is the sinc²filter. Figure 55 compares the settling

times of different filter orders.

sinc1

sinc2

sinc3

settling time (µs)

D054

Figure 55. Measured Effective Number of Bits versus Settling Time

The delay time of the sinc filter with a continuous signal is half of its settling time.

AMC1305L25, AMC1305M05, AMC1305M25

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

www.ti.com.cn

Typical Applications (continued)

9.2.2 Isolated Voltage Sensing

The AMC1305 is optimized for usage in current-sensing applications using low-impedance shunts. However, the

device can also be used in isolated voltage-sensing applications if the impact of the (usually higher) impedance

of the resistor used in this case is considered.

High voltage

potential

5 V

AVDD

AINP

AMC1305

I_IB

R_ID

ûꢀ-Modulator

AINN

R3'

R4'

R5'

AGND

VCM = 2 V

GND

Figure 56. Using AMC1305 for Isolated Voltage Sensing

9.2.2.1 Design Requirements

Figure 56 shows a simplified circuit typically used in high-voltage sensing applications. The high impedance

resistors (R1 and R2) are used as voltage dividers and dominate the current value definition. The resistance of

the sensing resistor R3 is chosen to meet the input voltage range of the AMC1305. This resistor and the

differential input impedance of the device (the AMC1305x25 is 25 kΩ, the AMC1305M05 is 5 kΩ) also create a

voltage divider that results in an additional gain error. With the assumption of R1, R2, and R_INhaving a

considerably higher value than R3, the resulting total gain error can be estimated using Equation 4, with E_G

being the gain error of the AMC1305.

R₃

E_Gtot= E_G

R_IN

(4)

This gain error can be easily minimized during the initial system level gain calibration procedure.

9.2.2.2 Detailed Design Procedure

As indicated in Figure 56, the output of the integrated differential amplifier is internally biased to a common-mode

voltage of 2 V. This voltage results in a bias current I_IBthrough the resistive network R4 and R5 (or R4' and R5')

used for setting the gain of the amplifier. The value range of this current is specified in the Electrical

Characteristics table. This bias current generates additional offset error that depends on the value of the resistor

R3. Because the value of this bias current depends on the actual common-mode amplitude of the input signal (as

shown in Figure 57), the initial system offset calibration does not minimize its effect. Therefore, in systems with

high accuracy requirements TI recommends using a series resistor at the negative input (AINN) of the AMC1305

with a value equal to the shunt resistor R3 (that is R3' = R3 in Figure 56) to eliminate the effect of the bias

current.

AMC1305L25, AMC1305M05, AMC1305M25

www.ti.com.cn

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

Typical Applications (continued)

This additional series resistor (R3') influences the gain error of the circuit. The effect can be calculated using

Equation 5 with R5 = R5' = 50 kΩ and R4 = R4' = 2.5 kΩ (for the AMC1305M05) or 12.5 kΩ (for the

AMC1305x25).

≈

’

E (%) = 1 -

*100%

∆

R4'+R3'

◊

(5)

9.2.2.3 Application Curve

Figure 57 shows the dependency of the input bias current on the common-mode voltage at the input of the

AMC1305.

-20

-40

-60

1305x25

1305M05

-80

-0.5

0.5

1.5

2.5

V_CM(V)

D001

Figure 57. Input Current vs Input Common-Mode Voltage

AMC1305L25, AMC1305M05, AMC1305M25

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

www.ti.com.cn

10 Power-Supply Recommendations

In a typical frequency inverter application, the high-side power supply (AVDD) for the device is derived from the

floating power supply of the upper gate driver. For lowest cost, a Zener diode can be used to limit the voltage to

5 V ±10%. Alternatively a low-cost low-drop regulator (LDO), for example the LM317-N, can be used to minimize

noise on the power supply. A low-ESR decoupling capacitor of 0.1 µF is recommended for filtering this power-

supply path. Place this capacitor (C₂in Figure 58) as close as possible to the AVDD pin of the AMC1305 for best

performance. If better filtering is required, an additional 10-µF capacitor can be used. The floating ground

reference (AGND) is derived from the end of the shunt resistor, which is connected to the negative input (AINN)

of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads, while AGND is

connected to one of the outer leads of the shunt.

For decoupling of the digital power supply on controller side, TI recommends using a 0.1-µF capacitor assembled

as close to the DVDD pin of the AMC1305 as possible, followed by an additional capacitor in the range of 1 µF to

10 µF.

Floating

Power Supply

HV+

20 V

800ꢀ

AMC1305

Gate Driver

5.1 V

DVDD

AVDD

3.3 V, or 5.0 V

10ꢁF

0.1ꢁF

2.2ꢁF

1N751A

AGND

AINN

DGND

DOUT

TMS320F2837x

SD-Dx

R_SHUNT

to load

SD-Cx

PWMx

AINP

CLKIN

Gate Driver

HV-

Figure 58. Zener-Diode-Based High-Side Power Supply

AMC1305L25, AMC1305M05, AMC1305M25

www.ti.com.cn

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

11 Layout

11.1 Layout Guidelines

A layout recommendation showing the critical placement of the decoupling capacitors (as close as possible to the

AMC1305) and placement of the other components required by the device is shown in Figure 59.

For the AMC1305L25 version, place the 100-Ω termination resistor as close as possible to the CLKIN, CLKIN_N

inputs of the device to achieve highest signal integrity. If not integrated, an additional termination resistor is

required as close as possible to the LVDS data inputs of the MCU or filter device; see Figure 60.

11.2 Layout Examples

Top View

Clearance area

to be kept free of any

conductive materials

AINP

AINN

AGND

DGND

0.1 µF

SMD

0603

From shunt

resistor

DVDD

CLKIN

AMC1305Mxx

to/from

MCU

(filter)

DOUT

LEGEND

TOP layer:

copper pour & traces

AVDD

AGND

0.1 µF

high-side area

SMD

0603

controller-side area

DGND

via to ground plane

via to supply plane

Figure 59. Recommended Layout of the AMC1305Mx

AMC1305L25, AMC1305M05, AMC1305M25

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

www.ti.com.cn

Layout Examples (continued)

Top View

Clearance area

to be kept free of any

conductive materials

DGND

0.1 µF

AINP

SMD

0603

From shunt

resistor

AINN

AGND

DVDD

CLKIN

CLKIN_N

DOUT

DOUT_N

DGND

100 W

AMC1305L25

SMD

0603

to/from

MCU

(filter)

LEGEND

100 W

TOP layer:

copper pour & traces

SMD

0603

AVDD

0.1 µF

high-side area

SMD

0603

controller-side area

AGND

via to ground plane

via to supply plane

Figure 60. Recommended Layout of the AMC1305L25

AMC1305L25, AMC1305M05, AMC1305M25

www.ti.com.cn

ZHCSCZ0F –JUNE 2014–REVISED MARCH 2017

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

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AMC1305L25DWR产品参数

型号:	AMC1305L25DWR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP,
针数：	16
Reach Compliance Code：	compliant
Factory Lead Time：	12 weeks
风险等级：	5.56
模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4
长度：	10.3 mm
湿度敏感等级：	3
功能数量：	1
端子数量：	16
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
座面最大高度：	2.65 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm
Base Number Matches：	1

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