AOZ8802A
Protecting USB Ports from ESD
Because electrostatic discharge (ESD) is common in
electronic systems, a device that provides protection
from the undesirable effects of ESD must be included in
the system design. Designing ESD protection structures
is becoming more and more challenging with the system
bus and I/O operating more often at high-speed data
rates. An Integrated Circuit (IC) connected to external
ports can be damaged by ESD from the operating
environment. The result of ever-shrinking IC process
technology is the decrease of ESD robustness because
of the smaller geometry of the silicon die.
The very low 0.6pF (typical) line capacitance of the
AOZ8802A ensures less distortion of the 480 Mbit/s
USB 2.0 signal; the chips also protect against
electrostatic discharge up to the stringent IEC61000-4-2
level 4, 8kV (Contact Discharge) and 15kV standard
(Air Discharge). They also provide ultra low matching
capacitance to help improve the signal quality of
differential data lines. Monolithic integration provides
high device reliability, and an optimized pin-out allows
EMI-free board layouts. Figure 2 illustrates the flow
through design of the PCB layout with the AOZ8802A
package design. The pinout of the AOZ8802A is
designed to simply drop onto the IO lines of a USB 2.0
design without having to divert the signal lines that may
add more parasitic inductance. Pins 1, 2 & 3 is connected
to the internal TVS devices and ground. and pins 4, 5, 6
are no connects. The no connects is in place so the
package can be securely soldered onto the PCB surface.
Since USB is a hot insertion and removal system, the
USB components are subjected to ESD and cable
discharge event more frequently. Traditional methods of
ESD protection include metal oxide varistors (MOVs),
and regular CMOS or bipolar clamping diodes. At higher
data rates the parasitic characteristics of those devices
can cause distortion, deterioration and data loss of the
signal integrity. AOZ8802A offers ESD protection for
high-speed data rates and for diode array chips for ease
of design.
D+
D-
D+
D-
Ground
Ground
Figure 2. Flow-through Layout
Rev. 1.0 October 2010
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