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产品型号AS7C3256-15JC的概述

芯片AS7C3256-15JC的概述 AS7C3256-15JC是一款高性能的静态随机存取存储器（SRAM），属于ATP（ASi Semiconductor）的产品系列。这款芯片主要用于各种嵌入式系统中，其高运行速度和低功耗特性使其在工业控制、电信、网络设备以及消费电子产品等领域有着广泛的应用。SRAM由于其存取速度快、无需刷新等优点，逐渐成为需要快速数据存取的应用的首选。在科技日益发展的今天，数据存储器的需求不断上升，尤其是在大数据分析、人工智能等新兴领域中。AS7C3256-15JC凭借其较低的功耗以及较高的数据处理能力，成为设计师在开发新产品时的重要选择。芯片AS7C3256-15JC的详细参数 AS7C3256-15JC具体参数如下： - 容量：256K位（32K x 8位） - 访问时间：15纳秒 - 电源电压：2.7V 至 3.6V - 功耗： - 芯片静态功耗：通...

产品型号AS7C3256-15JC的Datasheet PDF文件预览

January 2001

Advance Information

AS7C256

AS7C3256

5V/3.3V 32K X 8 CMOS SRAM (Common I/O)

Features

• AS7C256 (5V version)

• AS7C3256 (3.3V version)

- 7.2 mW (AS7C3256) / max CMOS I/O

• 2.0V data retention

• Easy memory expansion with CE and OE inputs

• TTL-compatible, three-state I/O

• 28-pin JEDEC standard packages

- 300 mil PDIP

- 300 mil SOJ

- 8 × 13.4 TSOP

• Industrial and commercial temperature

• Organization: 262,144 words × 16 bits

• High speed

- 12/15/20 ns address access time

- 5/6/7/9 ns output enable access time

• Very low power consumption: ACTIVE

- 660mW (AS7C256) / max @ 12 ns

- 216mW (AS7C3256) / max @ 12 ns

• Very low power consumption: STANDBY

- 22 mW (AS7C256) / max CMOS I/O

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Logic block diagram

Pin arrangement

28-pin TSOP I (8×13.4)

28-pin DIP, SOJ (300 mil)

GND

Input buffer

A14

A12

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

A11

A10

(22)

(23)

(24)

(25)

(26)

(27)

(28)

(1)

(21) 28

(20) 27

(19) 26

(18) 25

(17) 24

(16) 23

(15) 22

(14) 21

(13) 20

(12) 19

(11) 18

(10) 17

(9) 16

(8) 15

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

I/O7

I/O0

A13

256 X 128 X 8

Array

AS7C256

AS7C3256

A14

A12

(2)

(3)

(4)

(262,144)

(5)

(6)

I/O0

I/O1

I/O2

GND

(7)

A14

Note: This part is compatible with both pin numbering

conventions used by various manufacturers.

Column decoder

Control

circuit

10 11 12 13

Selection guide

AS7C256-10

AS7C256-12

AS7C256-15

AS7C256-20

AS7C3256-10

AS7C3256-12

AS7C3256-15

AS7C3256-20

Unit

Maximum address access time

Maximum output enable access time

AS7C256

AS7C3256

120

115

110

Maximum operating current

AS7C256

Maximum CMOS standby

current

AS7C3256

1/10/2001

Alliance Semiconductor

P. 1 of 9

AS7C256

AS7C3256

Functional description

The AS7C(3)256 is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized

as 262,144 words × 16 bits. It is designed for memory applications requiring fast data access at low voltage, including

Pentium^TM, PowerPC^TM, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V

operation without sacrificing performance or operating margins.

The device enters standby mode when CE is high. CMOS standby mode consumes ≤3.6 mW. Normal operation offers 75% power

reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions

of the AS7C256 offer 2.0V data retention.

Equal address access and cycle times (t_AA, t_RC, t_WC) of 12/15/20 ns with output enable access times (t_OE) of 5/6/7/9 ns are

ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank

memory organizations.

A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is

written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive

I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The

chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write

enable is low, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.3 0.3V supply. The

AS7C(3)256A is packaged in high volume industry standard packages.

Absolute maximum ratings

Parameter

Device

Symbol

V_t1

Min

–0.5

–

Max

Unit

AS7C256

AS7C3256

+7.0

+5.0

V_CC+ 0.5

1.0

Voltage on V_CCrelative to GND

V_t1

Voltage on any pin relative to GND

Power dissipation

V_t2

P_D

^oC

Storage temperature (plastic)

Ambient temperature with V_CCapplied

DC current into outputs (low)

T_stg

–65

–55

–

+150

+125

T_bias

I_OUT

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-

imum rating conditions for extended periods may affect reliability.

Truth table

Data

Mode

High Z

D_OUT

D_IN

Standby (I_SB, I_SB1)

Output disable (I_CC)

Read (I_CC

Write (I_CC)

)

Key: X = Don’t care, L = Low, H = High

1/10/2001

Alliance Semiconductor

P. 2 of 9

AS7C256

AS7C3256

Recommended operating conditions

Parameter

Device

Symbol

Min

4.5

3.0

2.2

2.0

-0.5^*

Typical

Max

5.5

Unit

AS7C256 V_CC

5.0

3.3

–

Supply voltage

AS7C3256 V_CC

AS7C256 V_IH

3.6

V_CC+0.5

0.8

Input voltage

AS7C3256 V_IH

–

—

V_IL

–

commercial T_A

industrial T_A

–

^oC

Ambient operating temperature

–40

–

min = –2.0V for pulse width less than t /2.

DC operating characteristics (over the operating range)¹

-10

-12

-15

-20

Parameter

Sym Test conditions

Device

Min Max Min Max Min Max Min Max Unit

Input leakage

current

_CC= Max,

|I_LI|

|I_LO

–

µA

V_in= GND to V_CC

Output leakage

current

V_CC= Max,

V_OUT= GND to V_CC

Operating

power supply I_CC

current

AS7C256

–

120

–

115

–

110

V_CC= Max, CE ≤ V_IL

f = f_Max, I_OUT= 0mA

AS7C3256

AS7C256

AS7C3256

AS7C256

–

V_CC= Max, CE ≤ V_IL

f = f_Max, I_OUT= 0mA

I_SB

Standby power

supply current

4.0

V_CC= Max, CE > V_CC–0.2V

I_SB1

_IN< GND + 0.2V or

_IN> V_CC–0.2V, f = 0

AS7C3256

–

2.0

–

2.0

–

2.0

V_OLI_OL= 8 mA, V_CC= Min

V_OHI_OH= –4 mA, V_CC= Min

–

0.4

–

0.4

–

0.4

–

Output voltage

2.4

Capacitance (f = 1MHz, T = room temperature, V = NOMINAL)²

Parameter

Symbol

Signals

Test conditions

Max

Unit

Input capacitance

I/O capacitance

C_IN

V_in= 0V

A, CE

I/O

, WE, OE

C_I/O

V_in= V_out= 0V

1/10/2001

Alliance Semiconductor

P. 3 of 9

AS7C256

AS7C3256

Read cycle (over the operating range)^3,9

-10

-12

-15

-20

Parameter

Symbol Min Max Min Max Min Max Min Max

Unit Notes

Read cycle time

t_RC

–

Address access time

t_AA

t_ACE

t_OE

–

Chip enable (CE) access time

Output enable (OE) access time

Output hold from address change

CE LOW to output in low Z

CE HIGH to output in high Z

OE LOW to output in low Z

OE HIGH to output in high Z

Power up time

–

t_OH

t_CLZ

t_CHZ

t_OLZ

t_OHZ

t_PU

–

4, 5

–

Power down time

t_PD

Key to switching waveforms

Rising input

Falling input

Undefined output/don’t care

Read waveform 1 (address controlled)^3,6,7,9

Address

t_AA

Data valid

out

Read waveform 2 (CE controlled)^3,6,8,9

C E

O E

OLZ

OHZ

CHZ

ACE

out

Data valid

CLZ

Supply

current

50%

1/10/2001

Alliance Semiconductor

P. 4 of 9

AS7C256

AS7C3256

Write cycle (over the operating range)¹¹

-10

-12

-15

-20

Parameter

Symbol

t_WC

t_CW

t_AW

t_AS

Min Max Min Max Min Max

Unit

Notes

Write cycle time

–

Chip enable to write end

Address setup to write end

Address setup time

Write pulse width

t_WP

t_AH

t_DW

t_DH

t_WZ

t_OW

Address hold from end of write

Data valid to write end

Data hold time

4, 5

Write enable to output in high Z

Output active from write end

Shaded areas contain advance information.

–

Write waveform 1 (WE controlled)^10,11

Address

W E

Data valid

out

Write waveform 2 (CE controlled)^10,11

Address

C E

W E

Data valid

out

1/10/2001

Alliance Semiconductor

P. 5 of 9

AS7C256

AS7C3256

Data retention characteristics (over the operating range)¹³

Parameter

Symbol

Test conditions

Min

2.0

–

Max

–

Unit

V_CCfor data retention

V_DR

V_CC= 2.0V

500

–

µA

Data retention current

I_CCDR

CE ≥ V_CC–0.2V

–

V_IN≥ V_CC–0.2V

V_IN≤ 0.2V

Chip enable to data retention time t_CDR

–

Operation recovery time

Input leakage current

t_R

t_RC

–

| I_LI|

µA

Data retention waveform

Data retention mode

VCC

_DR≥ 2.0V

t_CDR

C E

AC test conditions

- Output load: see Figure B or Figure C.

Thevenin equivalent

168

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

Ω

+1.72V (5V and 3.3V)

out

+3.3V

+5V

320

Ω

480

Ω

out

+3.0V

90%

10%

90%

10%

350

Ω

C(14)

GND

255

Ω

C(14)

GND

2 ns

Figure A: Input pulse

GND

Figure C: Output load

Figure B: Output load

Notes

During V power-up, a pull-up resistor to V on CE is required to meet I specification.

CC CC SB

This parameter is sampled, but not 100% tested.

For test conditions, see AC Test Conditions, Figures A, B, C.

These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ±500mV from steady-state voltage.

This parameter is guaranteed, but not tested.

WE is High for read cycle.

CE and OE are Low for read cycle.

Address valid prior to or coincident with CE transition Low.

All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1 and CE2 have identical timing.

13 2V data retention applies to the commercial operating range only.

14 C=30pF, except on High Z and Low Z parameters, where C=5pF.

1/10/2001

Alliance Semiconductor

P. 6 of 9

AS7C256

AS7C3256

Typical DC and AC characteristics

Normalized supply current I_CC, I_SB

vs. supply voltage V_CC

1.4

Normalized supply current I_CC, I_SB

Normalized supply current ISB1

vs. ambient temperature T

vs. ambient temperature T_a

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

625

I_CC

V_CC= V_CC(NOMINAL)

I_CC

1.0

0.8

0.6

I_SB

0.4

0.2

0.04

0.2

0.0

MIN

NOMINAL

–55

–10

-55

-10

MAX

125

Supply voltage (V)

Ambient temperature (°C)

Normalized access time t_AA

vs. supply voltage V_CC

Normalized access time t_AA

vs. ambient temperature T_a

Normalized supply current I_CC

vs. cycle frequency 1/t_RC, 1/t_WC

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.4

1.3

1.2

1.1

1.0

0.9

0.8

T_a= 25°C

V_CC= V_CC(NOMINAL)

T_a= 25°C

MIN

NOMINAL

–55

–10

MAX

125

100

Supply voltage (V)

Ambient temperature (°C)

Cycle frequency (MHz)

Output source current I_OH

vs. output voltage V_OH

Output sink current I_OL

vs. output voltage V_OL

Typical access time change ∆t_AA

vs. output capacitive loading

140

120

100

140

120

100

V_CC= V_CC(NOMINAL)PL

T_a= 25°C

V_CC= V_CC(NOMINAL)

T = 25°C

250

500

750

V_CC

1000

Output voltage (V)

Capacitance (pF)

1/10/2001

Alliance Semiconductor

P. 7 of 9

AS7C256

AS7C3256

Package diagrams

28-pin PDIP

Min

Max

0.175

0.010

0.058

0.016

0.008

0.064

0.022

0.014

1.400

0.320

0.298

0.295

0.278

Seating

Plane

0.100 BSC

Pin 1

0.330

0.120

0°

0.370

0.140

15°

0.055

28-pin SOJ

Min

Max

0.140

E1 E2

0.025

0.095

Seating

Plane

0.105

Pin 1

0.028 TYP

0.018 TYP

0.010 TYP

0.730

0.285

0.305

0.347

0.245

0.295

0.327

0.050 BSC

28-pin

8×13.4

Min

–

Max

1.20

pin 1(22)

pin 1(7)

pin 8(21)

pin 5(8)

0.10

0.95

0.15

0.20

1.05

0.25

0.10

0.20

11.60

11.80

28-pin

0.55 nominal

Note: This part is compatible with both pin numbering

conventions used by various manufacturers.

1/10/2001

Alliance Semiconductor

P. 8 of 9

AS7C256

AS7C3256

Ordering information

Package / Access time

Volt/Temp

10 ns

12 ns

15 ns

20 ns

5V commercial

3.3V commercial

5V commercial

3.3V commercial

5V industrial

AS7C256-10PC

AS7C3256-10PC

AS7C256-10JC

AS7C3256-10JC

AS7C256-10JI

AS7C3256-10JI

AS7C256-10TC

AS7C3256-10TC

AS7C256-10TI

AS7C3256-10TI

AS7C256-12PC

AS7C3256-12PC

AS7C256-12JC

AS7C3256-12JC

AS7C256-12JI

AS7C256-15PC

AS7C3256-15PC

AS7C256-15JC

AS7C3256-15JC

AS7C256-15JI

AS7C3256-15JI

AS7C256-15TC

AS7C3256-15TC

AS7C256-15TI

AS7C3256-15TI

AS7C256-20PC

Plastic DIP, 300 mil

AS7C3256-20PC

AS7C256-20JC

AS7C3256-20JC

AS7C256-20JI

AS7C3256-20JI

AS7C256-20TC

AS7C3256-20TC

AS7C256-20TI

AS7C3256-20TI

Plastic SOJ, 300 mil

3.3V industrial

5V commercial

3.3V commercial

5V industrial

AS7C3256-12JI

AS7C256-12TC

AS7C3256-12TC

AS7C256-12TI

AS7C3256-12TI

TSOP 8x13.4

3.3V industrial

Part numbering system

AS7C

256

–XX

C or I

Commercial temperature range:

0 ^oC to 70 ⁰C

Package: J = SOJ 300 mil

SRAM prefix

3 = 3.3V supply Device number Access time

= TSOP 8x13.4

Industrial temperature range:

-40C to 85C

1/10/2001

Alliance Semiconductor

P. 9 of 9

© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names

may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors

that may appear in this document. The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without

notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information

for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the

application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a par-

ticular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alli-

ance products are made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works

rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or

failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and

agrees to indemnify Alliance against all claims arising from such use.

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AS7C3256-15JC产品参数

型号:	AS7C3256-15JC
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	SOJ
包装说明：	SOJ, SOJ28,.34
针数：	28
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.41
风险等级：	5.67
Is Samacsys：	N
最长访问时间：	15 ns
I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-J28
JESD-609代码：	e0
内存密度：	262144 bit
内存集成电路类型：	STANDARD SRAM
内存宽度：	8
功能数量：	1
端子数量：	28
字数：	32768 words
字数代码：	32000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	32KX8
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOJ
封装等效代码：	SOJ28,.34
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
并行/串行：	PARALLEL
电源：	3.3 V
认证状态：	Not Qualified
座面最大高度：	3.556 mm
最大待机电流：	0.0005 A
最小待机电流：	2 V
子类别：	SRAMs
最大压摆率：	0.05 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND
端子节距：	1.27 mm
端子位置：	DUAL
宽度：	7.62 mm
Base Number Matches：	1

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