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ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Low Power µP Supervisor Circuits

General Description

Features

•

Precision power supply monitor

The ASM705 / 706 / 707 / 708 and AS813L are cost effective

CMOS supervisor circuits that monitor power-supply and

battery voltage level, and µP/µC operation.

•4.65V threshold (ASM705/707/813L)

•4.40V threshold (ASM706/708)

Debounced manual reset input

Voltage monitor

•

The family offers several functional options. Each device

generates a reset signal during power-up, power-down and

during brownout conditions. A reset is generated when the

supply drops below 4.65V (ASM705/707/813L) or 4.40V

(ASM706/708). For 3V power supply applications, refer to the

ASM705P/R/S/T data sheet. In addition, the ASM705/706/813L

feature a 1.6 second watchdog timer. The ASM707/708 have

both active-HIGH and active-LOW reset outputs but no

watchdog function. The ASM813L has the same pin-out and

functions as the ASM705 but has an active-HIGH reset output.

A versatile power-fail circuit has a 1.25V threshold, useful in low

battery detection and for monitoring non-5V supplies. All

devices have a manual reset (MR) input. The watchdog timer

output will trigger a reset if connected to MR.

•1.25V threshold

•Battery monitor / Auxiliary supply monitor

Watchdog timer (ASM705/706/813L)

200ms reset pulse width

•

Active HIGH reset output (ASM707/708/813L)

MicroSO package

Applications

•

Computers and embedded controllers

Portable/Battery-operated systems

Intelligent instruments

Wireless communication systems

PDAs and hendheld equipment

Automative Systems

Safety Systems

All devices are available in 8-pin DIP, SO and MicroSO

packages.

Typical Operating Circuit

Unregulated DC

+5V Regulator

µP

V_CC

R₁

V_CC

RESET

(RESET)

PFI

WDI

I/O LINE

ASM705

ASM706

(ASM813L)

NMI

WDO

PFO

R₂

MR

INTERRUPT

Alliance Semiconductor

2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Block Diagrams

Transition

Detector

Watchdog

Timer

WDI

MR

WDO

RESET

V

CC

V

CC

Timebase

0.25mA

RESET

Generator

RESET

Generator

MR

RESET

(RESET) ASM813L

+

-

V

+

CC

V

CC

-

+

4.65V (ASM707)

4.40V (ASM708)

+

4.65V (ASM705/813L)

4.40V (ASM706)

PFI

+

-

+

PFO

-

ASM705

ASM706

ASM813L

1.25V

ASM707

ASM708

GND

Pin Configuration

MicroSO

DIP/SO

8

RESET

1

NC

RESET (RESET)

WDO

1

WDI

8

1

2

3

RESET

MR

WDO

ASM705

ASM706

ASM705

ASM706

2

3

ASM707

ASM708

V_CC

7

6

5

2

3

(RESET)

RESET

7

6

5

2

3

RESET

PFO

PFI

RESET

NC

PFO

PFI

7

6

7

6

5

ASM707

ASM708

MR

GND

PFI

WDI

PFO

GND

PFI

(ASM813L)

V_CC

GND

4

GND

4

5

4

PFO

2 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Pin Description

Pin Number

ASM707/708

ASM705/706

ASM813L

Name

Function

DIP/

SO

DIP/

SO

MicroSO

SO

MicroSO

Manual reset input. The active LOW input triggers a reset

pulse. A 250 µA pull-up current allows the pin to be

driven by TTL/CMOS logic or shorted to ground with a

switch.

1

3

1

3

1

3

MR

V_CC

2

3

4

5

2

3

4

5

2

3

4

5

+5V power supply input.

GND

Ground reference for all signals.

Power-fail input voltage monitor. With PFI less than

1.25V, PFO goes LOW. Connect PFI to Ground or V_CC

4

5

6

7

4

5

6

7

4

5

6

7

PFI

when not in use.

Power-fail output. The output is active LOW and sinks

current when PFI is less than 1.25V.

PFO

Watchdog input. WDI controls the internal watchdog

timer. A HIGH or LOW signal for 1.6sec at WDI allows

the internal timer to run-out, setting WDO LOW. The

watchdog function is disabled by floating WDI or by con-

necting WDI to a high impedance three-state buffer. The

internal watchdog timer clears when: RESET is asserted;

WDI is three-stated ; or WDI sees a rising or falling edge.

6

8

-

6

8

WDI

-

6

7

8

1

-

NC

Not Connected

Active LOW reset output. Pulses LOW for 200ms when

triggered, and stays LOW whenever V_CCis below the

reset threshold. RESET remains LOW for 200ms after

7

1

RESET

V

_CCrises above the reset threshold or MR goes from

LOW to HIGH. A watchdog timeout will not trigger

RESET unless WDO is connected to MR.

Watchdog output. WDO goes LOW when the 1.6 second

internal watchdog timer times-out and does not go HIGH

until the watchdog is cleared. In addition, when V_CCfalls

8

-

2

-

8

7

2

1

WDO

below the reset threshold, WDO goes LOW. Unlike

RESET, WDO does not have a minimum pulse width and

as soon as V_CCexceeds the reset threshold, WDO goes

HIGH with no delay.

Active HIGH reset output. The inverse of RESET. The

ASM813L has only a RESET output.

8

2

RESET

3 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

V

Detailed Description

RT

A

proper reset input enables

a

microprocessor

/

5V

0V

5V

V

CC

microcontroller to start in a known state. ASM70X and

ASM813L assert reset to prevent code execution errors

during power-up, power-down and brown-out conditions.

t

RS

t

RS

RESET

0V

RESET/RESET Timing

The RESET/RESET signals are designed to start a µP/µC in

a known state or return the system to a known state.

5V

0V

MR externally

set low

MR

t

MD

t

MR

The ASM707/708 have two reset outputs, one active-HIGH

RESET and one active-LOW RESET output. The ASM813L

has only an active-HIGH output. RESET is simply the

complement of RESET.

5V

0V

WDO

Figure 1: WDI Three-state operation

RESET is guaranteed to be LOW with V_CCabove 1.2V.

During a power-up sequence, RESET remains low until the

supply rises above the threshold level, either 4.65V or 4.40V.

RESET goes high approximately 200ms after crossing the

threshold.

Manual Reset (MR)

The active-LOW manual reset input is pulled high by a 250µA

pull-up current and can be driven low by CMOS/TTL logic or

a mechanical switch to ground. An external debounce circuit

is unnecessary since the 140ms minimum reset time will

debounce mechanical pushbutton switches.

During power-down, RESET goes LOW as V_CCfalls below

the threshold level and is guaranteed to be under 0.4V with

V

_CCabove 1.2V.

By connecting the watchdog output (WDO) and MR, a

watchdog timeout forces RESET to be generated. The

ASM813L should be used when an active-HIGH RESET is

required.

In a brownout situation where V_CCfalls below the threshold

level, RESET pulses low. If a brownout occurs during an

already initiated reset, the pulse will continue for a minimum

of 140ms.

Watchdog Timer

The watchdog timer available on the ASM705/706/813L

monitors µP/µC activity. An output line on the processor is

used to toggle the WDI line. If this line is not toggled within

1.6 seconds, the internal timer puts the watchdog output,

WDO, into a LOW state. WDO will remain LOW until a toggle

is detected at WDI.

Power Failure Detection With Auxiliary Comparator

All devices have an auxiliary comparator with 1.25V trip point

and uncommitted output (PFO) and noninverting input (PFI).

This comparator can be used as a supply voltage monitor

with an external resistor voltage divider. The attenuated

voltage at PFI should be set just below the 1.25 threshold. As

the supply level falls, PFI is reduced causing the PFO output

to transit LOW. Normally PFO interrupts the processor so the

system can be shut down in a controlled manner.

If WDI is floated or connected to a three-stated circuit, the

watchdog function is disabled, meaning, it is cleared and not

counting. The watchdog timer is also disabled if RESET is

asserted. When RESET becomes inactive and the WDI input

sees a high or low transition as short as 50ns, the watchdog

timer will begin

a

1.6 second countdown. Additional

4 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

transitions at WDI will reset the watchdog timer and initiate a

new countdown sequence.

BUF

Buffered

RESET

WDO will also become LOW and remain so, whenever the

supply voltage, V_CC, falls below the device threshold level.

V_CC

WDO goes HIGH as soon as V_CCtransitions above the

threshold. There is no minimum pulse width for WDO as

there is for the RESET outputs. If WDI is floated, WDO

essentially acts as a low-power output indicator.

µC or µP

ASM70x

RESET

GND

Supply Voltage

4.7kΩ

RESET

Input

GND

WDI

Bi-directional I/O Pin

Figure 3: Bi-directional Reset Pin Interfacing

Monitoring Voltages Other Than V_CC

WDO

The ASM705-708 can monitor voltages other than V_CCusing

the Power Fail circuitry. If a resistive divider is connected

from the voltage to be monitored to the Power Fail input

(PFI), the PFO will go LOW if the voltage at PFI goes below

1.25V reference. Should hysteresis be desired, connect a

resistor (equal to approximately 10 times the sum of the two

resistors in the divider) between the PFI and PFO pins. A

capacitor between PFI and GND will reduce circuit sensitivity

to input high-frequency noise. If it is desired to assert a

RESET for voltages other than V_CCthen the PFO output is to

RESET

Figure 2: Watchdog Timing

be connected to the MR.

Application Information

V_IN

Ensuring That RESET is Valid Down to V_CC= 0V

+5V

When V_CCfalls below 1.1V, the ASM705-708 RESET output

V_CC

no longer pulls down; it becomes indeterminate. To avoid the

possibility that stray charges build up and force RESET to the

wrong state, a pull-down resistor should be connected to the

RESET pin, thus draining such charges to ground and

holding RESET low. The resistor value is not critical. A 100kΩ

resistor will pull RESET to ground without loading it.

R₁

MR

ASM70X

PFO

PFI

RESET

To µP

R₂

GND

Bi-directional Reset Pin Interfacing

The ASM705/6/7/8 can interface with µP/µC bi-directional

reset pins by connecting a 4.7kΩ resistor in series with the

RESET output and the µP/µC bi-directional RESET pin.

Figure 4: Monitoring +5V and an additional supply V_IN

5 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Monitoring a Negative Voltage

V_CC

The Power-Fail circuitry can also monitor a negative supply

rail. When the negative rail is OK, PFO will be LOW, and

when the negative rail is failing (not negative enough), PFO

goes HIGH (the opposite of when positive voltages are

monitored). To trigger a reset, these outputs need to be

inverted: adding the resistors and transistor as shown

achieves this. The RESET output will then have the same

sense as for positive voltages: good = HIGH, bad = LOW. It

should be noted that this circuit’s accuracy depends on the

+

R₁

R₃

V_CC

MR

R₄

2N3904

ASM70X

PFO

PFI

R₂

V_CCline, the PFI threshold tolerance, and the resistors.

RESET

To µP

- 1.25

GND

V

1.25 - VTRIP

CC

=

Negative Input Voltage

R

2

R

1

Figure 5: Monitoring a negative voltage

6 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Absolute Maximum Ratings

Parameter

Min

Max

Unit

Pin Terminal Voltage with Respect to Ground

V

-0.3

6.0

V

CC

1

V

+ 0.3

All other inputs

CC

Input Current at V and GND

20

mA

V/µs

CC

Output Current: All outputs

Rate of Rise at V

100

CC

Plastic DIP Power Dissipation

(Derate 9mW/°C above 70°C)

700

470

330

mV

mW‘

mW

SO Power Dissipation

(Derate 5.9mW/°C above 70°C)

MicroSO Power Dissipation

(Derate 4.1mW/°C above 70°C)

Operating Temperature Range

ASM705E/706E/707E/708E/813LE

ASM706C/707C/708C/813LC

Storage Temperature Range

Lead Temperature (Soldering 10sec)

Note:

-40

0

+85

70

°C

-65

160

300

1. The input voltage limits of PFI and MR can be exceeded if the input current is less than 10mA.

These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for pro-

longed time periods may affect device reliability.

7 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Electrical Characteristics

Unless otherwise noted, specifications are over the operating temperature range and V_CCsupply voltages are 2.7V to 5.5V (ASM706P,

ASM708R), 3.0 V to 5.5V (ASM706/708S), 3.15V to 5.5V (ASM706/708T) and 4.1V to 5.5.V (ASM706/708J)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

ASM705/6/7/8C

ASM813L

1.2

1.1

1.2

5.5

Operating Voltage

Range

V_CC

V

ASM705/6/7/8E, ASM813E

ASM705/706C/813LC

ASM705E/706E/813LE

ASM707C/708C

5.5

75

140

4.75

4.50

Supply Current

I_CC

µA

50

ASM707E/708E

50

ASM705/707/813L, Note 1

ASM706/708 Note 1

4.50

4.25

4.65

4.40

V_RT

RESET Threshold

V

RESET Threshold

Hysteresis

Note 1

40

mV

t_RS

t_MR

RESET Pulse Width

MR Pulse Width

140

200

280

ms

µs

0.15

MR to RESET Out

Delay

t_MD

Note 1

0.25

µs

V_IH

V_IL

2.0

MR Input Threshold

MR Pullup current

V

0.8

MR = 0V

100

250

600

µA

I_SOURCE= 800µA

V_CC- 1.5

RESET Output Voltage

I_SINK= 3.2mA

0.4

0.3

V

ASM705/5/7/8, V_CC= 1.2V, I_SINK= 100µA

ASM707/8/813L, I_SOURCE= 800µA

ASM707/8, I_SINK= 1.2mA

ASM813L, I_SINK=3.2mA

ASM813L, V_CC= 1.2V, I_SOURCE= 4µA

V_CC-1.5

0.4

RESET Output Voltage

V

0.9

8 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

s

Watchdog Timeout

Period

t_WD

ASM705/6/813L

V_IL= 0.4V, V_IH=0.8V_CC

1.00

1.60

2.25

t_WP

V_IH

V_IL

,

WDI Pulse Width

50

ns

3.5

ASM705/706/813L, V_CC= 5V

ASM705/6/813L, WDI = V_CC

WDI Input Threshold

V

µA

V

0.8

50

150

WDI Input Current

ASM705/6/813L, WDI = 0V

-150

-50

V_OH

V_OL

ASM705/6/813L, I_SOURCE= 800µA

ASM705/6/813L, I_SINK= 1.2mA

V_CC- 1.5

WDO Output Voltage

0.4

1.3

25

V_CC= 5V

PFI Input Threshold

PFI Input Current

1.2

-25

1.25

0.01

V

nA

V_OH

V_OL

I_SOURCE= 800µA

I_SINK= 3.2mA

V_CC- 1.5

PFO Output Voltage

V

0.4

Notes 1: RESET (ASM705/6/7/8), RESET(ASM707/8, ASM813L)

9 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Package Dimensions

8-Pin MicroSO

D

E

E1

A2

A

a

C

0.10mm

0.004in

e

A1

L

b

Inches

Millimeteres

Min

-

Max

0.10

0.15

0.95

0.40

0.23

3.10

A

A1

A2

b

0.0433

0.0059

0.0374

0.0157

0.0091

0.1220

-

0.0020

0.0295

0.0098

0.0051

0.1142

0.050

0.75

0.25

0.13

2.90

C

D

e

0.0256 BSC

0.193 BSC

0.65 BSC

4.90 BSC

E

E1

L

0.1142

0.1220

0.0276

6°

2.90

0.40

0°

3.10

0.70

6°

0.0157

0°

a

10 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Package Dimensions (contd)

Plastic DIP (8-Pin)

D1

E

D

E1

A1

A

0° -15°

L

b2

eC

eA

e

b

eB

Inches

Millimeteres

Min

Max

Min

Max

A

A1

A2

b

-

0.210

-

5.33

0.015

0.115

0.014

0.045

0.030

0.355

0.005

0.300

0.240

0.100

0.300

-

0.38

2.92

0.36

1.14

0.80

9.02

0.13

7.62

6.10

2.54

7.62

-

0.195

0.022

0.070

0.045

0.400

-

4.95

0.56

1.78

1.14

10.16

-

b2

b3

D

D1

E

0.325

0.280

-

8.26

7.11

E1

e

eA

eB

eC

L

-

0.430

0.060

0.150

10.92

3.81

-

0.115

2.92

11 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Package Dimensions (contd)

SO (8-Pin)

Inches

Millimeteres

Min Max

Min

Max

0.069

0.010

0.020

0.010

A

A1

B

0.053

0.004

0.013

0.007

1.35

0.10

0.33

0.19

1.75

0.25

0.51

0.25

C

e

0.050

1.27

E

0.150

0.228

0.016

0.189

0.157

0.244

0.050

0.197

3.80

5.80

0.40

4.80

4.00

6.20

1.27

2.00

H

L

D

12 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Ordering Codes

Part Number

Reset Threshold (V)

Temperature Range

Pins-Package

ASM705 Active LOW Reset, Watchdog Output And Manual RESET

ASM705CPA

ASM705CSA

ASM705CUA

ASM705EPA

ASM705ESA

ASM705EUA

4.65

0°C to +70 °C

-40°C to +85°C

8-Plastic DIP

8-SO

8-MicroSO

8-Plastic DIP

8-SO

8-MicroSO

ASM706 Active LOW Reset, Watchdog Output And Manual RESET

ASM706CPA

ASM706CSA

ASM706CUA

ASM706EPA

ASM706ESA

4.40

0°C to +70 °C

-40°C to +85°C

8-Plastic DIP

8-SO

8-MicroSO

8-Plastic DIP

8-SO

ASM707 Active LOW & HIGH Reset with Manual RESET

ASM707CPA

ASM707CSA

ASM707CUA

ASM707EPA

ASM707ESA

4.65

0°C to +70 °C

-40°C to +85°C

8-Plastic DIP

8-SO

8-MicroSO

8-Plastic DIP

8-SO

ASM708Active LOW & HIGH Reset with Manual RESET

ASM708CPA

ASM708CSA

ASM708CUA

ASM708EPA

ASM708ESA

4.40

0°C to +70 °C

-40°C to +85°C

8-Plastic DIP

8-SO

8-MicroSO

8-Plastic DIP

8-SO

ASM813L Active HIGH Reset, Watchdog Output And Manual RESET

ASM813LCPA

ASM813LCSA

ASM813LCUA

ASM813LEPA

ASM813LESA

4.65

0°C to +70 °C

-40°C to +85°C

8-Plastic DIP

8-SO

8-MicroSO

8-Plastic DIP

8-SO

13 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

July 2004

rev 1.2

Feature Summary

ASM705

ASM706

ASM707

ASM708

ASM813L

Power fail detector

Brownout detection

Manual RESET input

Power-up/down RESET

Watchdog Timer

Active HIGH RESET output

Active LOW RESET output

RESET Threshold (V)

4.65

4.40

4.65

4.40

4.65

14 of 15

Low Power µP Supervisor Circuits

Notice: The information in this document is subject to change without notice

ASM705 / 706 / 707 / 708

ASM813L

Part Number:ASM705 / 706 / 707 / 708

ASM813L

Alliance Semiconductor Corporation

2575, Augustine Drive,

Santa Clara, CA 95054

Tel: 408 - 855 - 4900

Fax: 408 - 855 - 4999

www.alsc.com

Document Version: 1.2

registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the

right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may

appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the

right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these

specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and

users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility

or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale

and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any

intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of

Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not

convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third

parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may

reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that

the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

型号:	ASM705CPA
是否Rohs认证：	不符合
生命周期：	Transferred
包装说明：	PLASTIC, DIP-8
Reach Compliance Code：	unknown
风险等级：	5.76
其他特性：	RESET THRESHOLD VOLTAGE IS 4.65V; MANUAL RESET INPUT
可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0
长度：	9.59 mm
信道数量：	1
功能数量：	1
端子数量：	8
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
座面最大高度：	5.33 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	1.2 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm
Base Number Matches：	1

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