AT17N002-10TQC全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

Features

• EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and

4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field

Programmable Gate Arrays (FPGAs)

• Available as a 3.3V ( 10%) Commercial and Industrial Version

• Simple Interface to SRAM FPGAs

• Pin Compatible with Xilinx^®XC17SXXXA and XC17SXXXXL PROMs

• Compatible with Xilinx Spartan^®-II, Spartan-IIE and Spartan XL FPGAs in Master Serial

Mode

• Very Low-power CMOS EEPROM Process

• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC

Packages), 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a

Specific Density

• Low-power Standby Mode

• High-reliability

FPGA

Configuration

Memory

– Endurance: Minimum 10 Write Cycles

– Data Retention: 20 Years at 85°C

AT17N256

AT17N512

AT17N010

AT17N002

AT17N040

Description

The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-

use, cost-effective configuration memory for Field Programmable Gate Arrays. The

AT17N series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead

SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple

serial-access procedure to configure one or more FPGA devices.

The AT17N series configurators can be programmed with industry-standard program-

mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and

factory programming.

Table 1. AT17N Series Packages

3.3V

AT17N512/

AT17N010

Package

AT17N256

AT17N002

AT17N040

System Support

8-lead LAP

8-lead PDIP

8-lead SOIC

20-lead SOIC

44-lead TQFP

–

Yes

–

Yes

–

Yes

–

Use 8-lead LAP⁽¹⁾

–

Yes

–

Yes

–

Yes

Note:

1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-

lead SOIC package is not available for the AT17N512/010/002 devices, it is possi-

ble to use an 8-lead LAP package instead.

Rev. 3020A–CNFG–05/03

1

Pin Configuration

8-lead LAP

8 VCC

DATA 1

CLK 2

7 VCC (SER_EN)

6 DC

RESET/OE 3

CE 4

5 GND

8-lead SOIC

DATA

CLK

1

8

VCC

2

3

4

7

6

5

VCC (SER_EN)

RESET/OE

CE

DC

GND

8-lead PDIP

DATA

CLK

1

8

7

6

5

VCC

2

3

4

VCC (SER_EN)

RESET/OE

CE

DC

GND

20-lead SOIC

DATA

NC

1

20

19

18

17

16

15

14

13

12

11

VCC

2

NC

CLK

3

VCC (SER_EN)

NC

4

NC

DC

NC

GND

NC

5

NC

6

NC

7

RESET/OE

NC

8

9

CE

10

2

AT17N256/512/010/002/040

3020A–CNFG–04/10/03

AT17N256/512/010/002/040

44 TQFP

NC

DC

NC

1

33

32

31

30

29

28

27

26

25

24

23

NC

DC

2

3

4

5

6

7

8

9

10

11

3

3020A–CNFG–04/10/03

Block Diagram

SER_EN

POWER ON

RESET

Device Description

The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-

face directly with the FPGA device control signals. All FPGA devices can control the

entire configuration process and retrieve data from the configuration EEPROM without

requiring an external intelligent controller.

The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the

DATA output pin and enable the address counter. When RESET/OE is driven High, the

configuration EEPROM resets its address counter and tri-states its DATA pin. The CE

pin also controls the output of the AT17N series configurator. If CE is held High after the

RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.

When OE is subsequently driven Low, the counter and the DATA output pin are

enabled. When RESET/OE is driven High again, the address counter is reset and the

DATA output pin is tri-stated, regardless of the state of CE. Upon power-up, the address

counter is automatically reset.

4

AT17N256/512/010/002/040

3020A–CNFG–04/10/03

AT17N256/512/010/002/040

Pin Description

AT17N512/

AT17N010

AT17N256

AT17N002

AT17N040

8

DIP/

SOIC

20

SOIC

DIP/

LAP

20

SOIC

8

LAP

20

SOIC

44

TQFP

44

TQFP

Name

DATA

I/O

1

2

3

4

5

6

–

7

8

1

3

1

2

3

4

5

6

–

7

8

1

3

1

2

3

4

5

6

–

7

8

1

3

40

43

13

15

18

21

23

35

38

40

43

13

15

18

21

23

35

38

CLK

I

RESET/OE

CE

8

10

11

13

–

10

11

13

–

10

11

13

–

GND

DC

O

I

DC

VCC(SER_EN)

V_CC

18

20

18

20

18

20

DATA

Three-state DATA output for configuration. Open-collector bi-directional pin for

programming.

CLK

Clock input. Used to increment the internal address and bit counter for reading and

programming.

RESET/OE

Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low

level on RESET/OE resets both the address and bit counters. A High level (with CE

Low) enables the data output driver. The logic polarity of this input is programmable as

either RESET/OE or RESET/OE. For most applications, RESET should be programmed

active Low. This document describes the pin as RESET/OE.

CE

Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the

address counter and enables the data output driver. A High level on CE disables both

the address and bit counters and forces the device into a low-power standby mode.

Note that this pin will not enable/disable the device in the Two-Wire Serial Programming

mode (SER_EN Low).

GND

Ground pin. A 0.2 µF decoupling capacitor between V_CCand GND is recommended.

VCC(SER_EN)

Serial enable must be held High during FPGA loading operations. Bringing SER_EN

Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,

SER_EN should be tied to V_CC

.

V_CC

NC

DC

3.3V ( 10%) Commercial and Industrial power supply pin.

NC pins are No Connect pins, which are not internally bonded out to the die.

DC pins are No Connect pins internally connected to the die. It is not recommended to

connect these pins to any external signal.

5

3020A–CNFG–04/10/03

FPGA Master Serial

Mode Summary

The I/O and logic functions of any SRAM-based FPGA are established by a configura-

tion program. The program is loaded either automatically upon power-up, or on

command, depending on the state of the FPGA mode pins. In Master mode, the FPGA

automatically loads the configuration program from an external memory. The AT17N

Serial Configuration EEPROM has been designed for compatibility with the Master

Serial mode.

This document discusses the master serial mode configuration of Atmel AT17N series

configuration memories, pin compatible with Spartan-II, Spartan-IIE and Spartan XL

OTP PROMs.

Control of

Configuration

Most connections between the FPGA device and the AT17N Serial EEPROM are simple

and self-explanatory.

•

The DATA output of the AT17N series configurator drives DIN of the FPGA devices.

The master FPGA CCLK output drives the CLK input of the AT17N series

configurator.

•

SER_EN must be connected to V_CC(except during ISP).

The CE and OE/Reset are driven by the FPGA to enable output data buffer of the

EEPROM.

Programming Mode

Standby Mode

The programming mode is entered by bringing SER_EN Low. In this mode the chip can

be programmed by the Two-Wire serial bus. The programming is done at V_CCsupply

only. Programming super voltages are generated inside the chip.

The AT17N series configurators enter a low-power standby mode whenever CE is

asserted High. In this mode, the AT17N256 configurator consumes less than 50 µA of

current at 3.3V (100 µA for the AT17N512/010 and 200 µA for the AT17N002/040).

6

AT17N256/512/010/002/040

3020A–CNFG–04/10/03

AT17N256/512/010/002/040

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those listed under oper-

ating conditions is not implied. Exposure to Abso-

lute Maximum Rating conditions for extended

periods of time may affect device reliability.

Operating Temperature.................................... -40°C to +85°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground..............................-0.1V to V_CC+0.5V

Supply Voltage (V_CC) ..........................................3.0V to +3.6V

Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C

ESD (R_ZAP= 1.5K, C_ZAP= 100 pF)................................. 2000V

Operating Conditions

3.3V

Symbol

Description

Min

Max

Units

Supply voltage relative to GND

-0°C to +70°C

Commercial

3.0

3.6

V

V_CC

Supply voltage relative to GND

-40°C to +85°C

Industrial

3.0

3.6

V

7

3020A–CNFG–04/10/03

DC Characteristics

V_CC= 3.3V 10%

AT17N512/

AT17N010

AT17N002/

AT17N040

AT17N256

Symbol

V_IH

Description

Min

Max

V_CC

0.8

Min

Max

Min

Max

Units

High-level Input Voltage

Low-level Input Voltage

2.0

0

2.0

0

V_CC

0.8

2.0

0

V_CC

0.8

V

V_IL

High-level Output Voltage

(I_OH= -2.5 mA)

V_OH

V_OL

V_OH

2.4

V

Low-level Output Voltage

(I_OL= +3 mA)

Commercial

Industrial

0.4

High-level Output Voltage

(I_OH= -2 mA)

2.4

Low-level Output Voltage

(I_OL= +3 mA)

V_OL

0.4

5

0.4

5

0.4

5

V

I_CCA

Supply Current, Active Mode

mA

Input or Output Leakage Current

(V_IN= V_CCor GND)

I_L

-10

10

50

-10

10

-10

10

µA

Commercial

Industrial

100

150

I_CCS

Supply Current, Standby Mode

100

AC Characteristics

V_CC= 3.3V 10%

AT17N256

Commercial Industrial

Min Max

AT17N512/010/002/040

Commercial Industrial

Min Max

Symbol

Description

Min

Max

50

Min

Max

50

Units

ns

(1)

T_OE

OE to Data Delay

55

60

80

55

60

(1)

T_CE

CE to Data Delay

60

55

ns

(1)

T_CAC

CLK to Data Delay

Data Hold from CE, OE, or CLK

CE or OE to Data Float Delay

CLK Low Time

75

55

ns

T_OH

0

ns

(2)

T_DF

55

50

ns

T_LC

25

35

25

60

25

30

25

35

ns

T_HC

T_SCE

CLK High Time

ns

CE Setup Time to CLK

ns

(to guarantee proper counting)

T_HCE

CE Hold Time from CLK

0

ns

(to guarantee proper counting)

T_HOE

F_MAX

OE High Time (guarantees counter is reset)

Maximum Clock Frequency

25

ns

10

15

10

MHz

Notes: 1. AC test lead = 50 pF.

2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.

8

AT17N256/512/010/002/040

3020A–CNFG–04/10/03

AT17N256/512/010/002/040

AC Characteristics

CE

T_SCE

T_HCE

T_SCE

RESET/OE

CLK

T_HOE

T_LC

T_HC

T_OH

T_OE

T_CAC

T_DF

T_CE

DATA

T_OH

9

3020A–CNFG–04/10/03

Thermal Resistance Coefficients⁽¹⁾

AT17N512/

AT17N010

Package Type

AT17N256

AT17N002

45

AT17N040

8CN4

Leadless Array Package (LAP)

θ

_JC[°C/W]

–

45

–

θ_JA

135.71

159.60

[°C/W]⁽²⁾

8P3

Plastic Dual Inline Package

(PDIP)

θ

_JC[°C/W]

37

–

θ_JA

107

[°C/W]⁽²⁾

8S1

Plastic Gull Wing Small Outline

(SOIC)

θ

_JC[°C/W]

45

–

θ_JA

150

[°C/W]⁽²⁾

20S2

44A

Plastic Gull Wing Small Outline

(SOIC)

θ

_JC[°C/W]

–

θ_JA

[°C/W]⁽²⁾

Thin Plastic Quad Flat

Package (TQFP)

θ_JC[°C/W]

–

17

62

17

62

θ_JA

[°C/W]⁽²⁾

Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site.

2. Airflow = 0 ft/min.

10

AT17N256/512/010/002/040

3020A–CNFG–04/10/03

AT17N256/512/010/002/040

Figure 1. Ordering Code

AT17N256-10PC

Voltage

Size (Bits)

Package

Temperature

+

-

256 = 256K

512 = 512K

010 = 1M

002 = 2M

040 = 4M

C

3.3V 10%

= 8CN4

C = Commercial

I = Industrial

P

= 8P3

= 8S1

= 20S2

= 44A

N

S

TQ

Package Type

8CN4

8P3

8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)

20S2

44A

11

3020A–CNFG–04/10/03

Ordering Information

Memory Size

Ordering Code

Package

Operation Range

256-Kbit

AT17N256-10PC

AT17N256-10NC

AT17N256-10SC

8P3

8S1

20S2

Commercial

(0°C to 70°C)

AT17N256-10PI

AT17N256-10NI

AT17N256-10SI

8P3

8S1

20S2

Industrial

(-40°C to 85°C)

512-Kbit

1-Mbit

2-Mbit

4-Mbit

AT17N512-10CC

AT17N512-10PC

AT17N512-10SC

8CN4

8P3

20S2

Commercial

(0°C to 70°C)

AT17N512-10CI

AT17N512-10PI

AT17N512-10SI

8CN4

8P3

20S2

Industrial

(-40°C to 85°C)

AT17N010-10CC

AT17N010-10PC

AT17N010-10SC

8CN4

8P3

20S2

Commercial

(0°C to 70°C)

AT17N010-10CI

AT17N010-10PI

AT17N010-10SI

8CN4

8P3

20S2

Industrial

(-40°C to 85°C)

AT17N002-10CC

AT17N002-10SC

AT17N002-10TQC

8CN4

20S2

44A

Commercial

(0°C to 70°C)

AT17N002-10CI

AT17N002-10SI

AT17N002-10TQI

8CN4

20S2

44A

Industrial

(-40°C to 85°C)

AT17N040-10TQC

44A

Commercial

(0°C to 70°C)

AT17N040-10TQI

44A

Industrial

(-40°C to 85°C)

12

AT17N256/512/010/002/040

3020A–CNFG–04/10/03

AT17N256/512/010/002/040

Packaging Information

8CN4 – LAP

Marked Pin1 Indentifier

E

A

D

A1

Top View

Side View

Pin1 Corner

L1

0.10 mm

TYP

8

7

1

e

COMMON DIMENSIONS

(Unit of Measure = mm)

2

3

MIN

0.94

0.30

0.45

5.89

4.89

MAX

1.14

0.38

0.55

6.09

NOM

1.04

NOTE

SYMBOL

A

6

5

A1

b

0.34

b

0.50

1

4

D

5.99

E

5.99

e1

L

e

1.27 BSC

1.10 REF

1.00

e1

L

Bottom View

0.95

1.25

1.05

1.35

1

L1

1.30

Note: 1. Metal Pad Dimensions.

11/14/01

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm,

Leadless Array Package (LAP)

A

8CN4

R

13

3020A–CNFG–04/10/03

8P3 – PDIP

E

1

E1

N

Top View

c

eA

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

D

e

MIN

MAX

NOM

NOTE

SYMBOL

D1

A2 A

A

0.210

0.195

0.022

0.070

0.045

0.014

0.400

2

A2

b

0.115

0.014

0.045

0.030

0.008

0.355

0.005

0.300

0.240

0.130

0.018

0.060

0.039

0.010

0.365

5

6

b2

b3

c

D

3

4

3

b2

L

D1

E

b3

4 PLCS

0.310

0.250

0.325

0.280

b

E1

e

0.100 BSC

0.300 BSC

0.130

Side View

eA

L

4

2

0.115

0.150

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

01/09/02

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

San Jose, CA 95131

8P3, 8-lead, 0.300" Wide Body, Plastic Dual

In-line Package (PDIP)

8P3

B

R

14

AT17N256/512/010/002/040

3020A–CNFG–04/10/03

AT17N256/512/010/002/040

8S1 – SOIC

1

3

2

H

N

Top View

e

B

A

D

COMMON DIMENSIONS

(Unit of Measure = mm)

Side View

MIN

–

MAX

1.75

0.51

0.25

5.00

4.00

NOM

NOTE

SYMBOL

A

B

C

D

E

e

–

A2

L

–

1.27 BSC

E

H

L

–

6.20

1.27

End View

Note:

This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.

10/10/01

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

San Jose, CA 95131

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

8S1

A

R

Small Outline (JEDEC SOIC)

15

3020A–CNFG–04/10/03

20S2 – SOIC

C

1

H

E

N

A1

Top View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

MIN

MAX

NOM

NOTE

SYMBOL

e

b

A

A1

b

0.0926

0.0040

0.0130

0.0091

0.4961

0.2914

0.3940

0.0160

0.1043

0.0118

0.0200

0.0125

0.5118

0.2992

0.4190

0.050

A

4

C

D

E

H

L

D

1

2

Side View

3

e

0.050 BSC

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.

2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006") per side.

3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm

(0.010") per side.

4. "L" is the length of the terminal for soldering to a substrate.

5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm

1/9/02

(0.024") per side.

TITLE

DRAWING NO.

REV.

20S2, 20-lead, 0.300" Wide Body, Plastic Gull

Wing Small Outline Package (SOIC)

2325 Orchard Parkway

San Jose, CA 95131

A

20S2

R

16

AT17N256/512/010/002/040

3020A–CNFG–04/10/03

AT17N256/512/010/002/040

44A – TQFP

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

11.75

9.90

11.75

9.90

0.30

0.09

0.45

0.15

1.00

12.00

10.00

12.00

10.00

–

1.05

12.25

D1

E

10.10 Note 2

12.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

10.10 Note 2

0.45

C

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

L

–

0.75

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

44A

B

R

17

3020A–CNFG–04/10/03

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Atmel Programmable SLI Hotline

e-mail

literature@atmel.com

(408) 436-4119

Atmel Programmable SLI e-mail

Web Site

http://www.atmel.com

configurator@atmel.com

FAQ

Available on web site

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

of Atmel.

FLEX^™is the trademark of Altera Corporation; ORCA^™is the trademark of Lattice Semiconductors;

SPARTAN^®and Virtex^®are the registered trademarks of Xilinx, Inc.; XC3000^™, XC4000^™and XC5200^™are

Printed on recycled paper.

the trademarks of Xilinx, Inc.; APEX^™is the trademark of MIPS Technologies; Other terms and product names

may be the trademarks of others.

3020A–CNFG–04/10/03

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