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产品型号AT24C256C-SSHL-T的概述

AT24C256C-SSHL-T 芯片概述及其详细参数分析在现代电子产品中，存储器的选择是设计中不可或缺的一部分。AT24C256C-SSHL-T是一款广泛应用的EEPROM芯片，这种非易失性存储器能够保持其数据，即使在无电源的情况下，其特性使其在需要长时间保存数据的场合尤为突出。本文将深入探讨AT24C256C-SSHL-T的主要特点、参数、制造商信息、引脚布局及电路图示，以及它的实际应用案例。芯片概述 AT24C256C-SSHL-T是一款基于I2C（Inter-Integrated Circuit）协议的256Kb EEPROM，具有较高的存储密度和可扩展性。这使得AT24C256C-SSHL-T成为需要大量数据存储的应用的理想选择。该芯片通常用于数据记录和保存、设备参数存储、配置设定等场景。与传统的闪存和DRAM不同，EEPROM允许逐字节写入和擦除，因此在某些应用场合具有...

产品型号AT24C256C-SSHL-T的Datasheet PDF文件预览

Features

• Low-voltage and Standard-voltage Operation

⎯ V_CC= 1.7V to 5.5V

• Internally Organized as 32,768 x 8

• Two-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

Two-wire

Serial EEPROM

• 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.7V) Compatibility

• Write Protect Pin for Hardware and Software Data Protection

• 64-byte Page Write Mode (Partial Page Writes Allowed)

• Self-timed Write Cycle (5 ms Max)

256K (32,768 x 8)

• High Reliability

⎯ Endurance: One Million Write Cycles

⎯ Data Retention: 40 Years

AT24C256C

• Lead-free/Halogen-free Devices Available

• 8-lead JEDEC SOIC, 8-lead UDFN, 8-lead TSSOP, and 8-ball VFBGA Packages

• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers

Preliminary

Description

The AT24C256C provides 262,144 bits of serial electrically erasable and

programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits

each. The device’s cascadable feature allows up to eight devices to share a common

two-wire bus. The device is optimized for use in many industrial and commercial

applications where low-power and low-voltage operation are essential. The devices

are available in space-saving 8-lead JEDEC SOIC, 8-lead UDFN, 8-lead TSSOP, and

8-ball VFBGA packages. In addition, this device operates from 1.7V to 5.5V.

Table 1.

Pin Configurations

Function

Pin Name

8-lead SOIC

8-lead TSSOP

V_CC

A0 – A2

SDA

Address Inputs

Serial Data

SCL

SDA

SCL

SDA

GND

SCL

Serial Clock Input

8-lead UDFN

Write Protect

Ground

8-ball VFBGA

V_CC

GND

SCL

SDA

SCL

SDA

GND

Bottom View

8568A–SEEPR–9/09

Absolute Maximum Ratings*

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only

and functional operation of the device at these or

any other conditions beyond those indicated in

the operational sections of this specification are

not implied. Exposure to absolute maximum

rating conditions for extended periods may affect

device reliability.

Operating Temperature...........................• 55°C to +125°C

Storage Temperature ............................• 65°C to + 150°C

Voltage on Any Pin

with Respect to Ground................................• 1.0 V +7.0V

Maximum Operating Voltage.....................................6.25V

DC Output Current ..................................................5.0 mA

Figure 1.

Block Diagram

GND

START

STOP

LOGIC

SCL

SDA

SERIAL

CONTROL

LOGIC

H.V. PUMP/TIMING

DATA RECOVERY

LOAD

COMP

DEVICE

ADDRESS

COMPARATOR

LOAD

INC

A₂

A₁

A₀

R/W

DATA WORD

EEPROM

ADDR/COUNTER

Y DEC

SERIAL MUX

D_OUT/ACK

LOGIC

D_IN

D_OUT

AT24C256C [Preliminary]

8568A–SEEPR–9/09

AT24C256C [Preliminary]

Pin Descriptions

SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and

negative-edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be

wire-ORed with any number of other open-drain or open-collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired

(directly to GND or to V_CC) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight

256K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device

Addressing”_Device_Addressing) A device is selected when a corresponding hardware and software match is

true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to

capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address

pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP

is connected directly to V_CC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be

internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications,

Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel

recommends using 10kΩ or less.

8568A–SEEPR–9/09

Memory Organization

AT24C256C, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64 bytes each. Random word

addressing requires a 15-bit data word address.

Table 2.

Pin Capacitance⁽¹⁾

Applicable over recommended operating range from:

TA = 25°C, f = 1.0 MHz, V_CC= +1.7V

Symbol

C_I/O

Test Condition

Input/Output Capacitance (SDA)

Input Capacitance (A₀, A₁, SCL)

Max

Units

Conditions

V_I/O= 0V

C_IN

V_IN= 0V

Note: 1. This parameter is characterized and is not 100% tested.

Table 3.

DC Characteristics

Applicable over recommended operating range from:

T_AI= − 40°C to +85°C, V_CC= +1.7V to +5.5V (unless otherwise noted)

Symbol

V_CC1

I_CC1

I_CC2

Parameter

Supply Voltage

Supply Current

Test Condition

Min

Typ

Max

Units

1.7

5.5

2.0

3.0

1.0

V_CC= 5.0V

V_CC= 1.7V

READ at 400 kHz

1.0

2.0

μA

WRITE at 400 kHz

Standby Current

(1.7V option)

I_SB1

V_IN= V_CCor V_SS

V_CC= 5.0V

6.0

3.0

μA

Input Leakage

I_LI

_IN= V_CCor V_SS

0.10

0.05

Currentt V_CC= 5.0V

Output Leakage

I_LO

V_OUT= V_CCor V_SS

3.0

μA

Currentt V_CC= 5.0V

V_IL

Input Low Level⁽¹⁾

Input High Level⁽¹⁾

Output Low Level

-0.6

V_CCx 0.3

V_CC+ 0.5

0.4

V_IH

V_CCx 0.7

V_OL2

V_OL1

V_CC= 3.0V

V_CC= 1.7V

I_OL= 2.1 mA

I_OL= 0.15 mA

0.2

Note:

1. V_ILmin and V_IHmax are reference only and are not tested.

AT24C256C [Preliminary]

8568A–SEEPR–9/09

AT24C256C [Preliminary]

Table 4.

AC Characteristics (Industrial Temperature)

Applicable over recommended operating range from:

T_AI= − 40°C to +85°C, V_CC= +1.7V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.

1.7-volt

2.5, 5.0-volt

Symbol

Parameter

Units

Min

Max

Min

Max

f_SCL

Clock Frequency, SCL

Clock Pulse Width Low

Clock Pulse Width High

Noise Suppression Time⁽¹⁾

400

1000

kHz

μs

t_LOW

1.3

0.6

0.4

t_HIGH

t_I

μs

100

0.9

t_AA

Clock Low to Data Out Valid

Time the bus must be free before a new transmission can start⁽¹⁾

Start Hold Time

0.05

1.3

0.6

0.05

0.5

0.55

μs

t_BUF

t_HD.STA

t_SU.STA

t_HD.DAT

t_SU.DAT

t_R

0.25

Start Set-up Time

Data In Hold Time

Data In Set-up Time

100

Inputs Rise Time⁽¹⁾

0.3

t_F

Inputs Fall Time⁽¹⁾

300

100

t_SU.STO

t_DH

Stop Set-up Time

0.6

0.25

Data Out Hold Time

t_WR

Write Cycle Time

Write

Endurance⁽¹⁾

25°C, Page Mode, 3.3V

1,000,000

Cycles

Note: 1. This parameter is ensured by characterization and is not 100% tested.

2. AC measurement conditions:

R_L(connects to V_CC): 1.3 kΩ (2.5V, 5.5V), 10 kΩ (1.7V)

Input pulse voltages: 0.3 V_CCto 0.7 V_CC

Input rise and fall times: ≤ 50 ns

Input and output timing reference voltages: 0.5 V_CC

8568A–SEEPR–9/09

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin

may change only during SCL low time periods (refer to Figure 2). Data changes during SCL high periods will indicate a

start or stop condition as defined below.

Figure 2.

Data Validity

SDA

SCL

DATA STABLE

DATA

CHANGE

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other

command (refer to Figure 3).

Figure 3.

Start and Stop Definition

SDA

SCL

START

STOP

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop

command will place the EEPROM in a standby power mode (refer to Figure 3).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The

EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word.

STANDBY MODE: The AT24C256C features a low-power standby mode that is enabled upon power-up and after the

receipt of the stop bit and the completion of any internal operations.

AT24C256C [Preliminary]

8568A–SEEPR–9/09

AT24C256C [Preliminary]

SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset

by following these steps:

a) Create a start bit condition,

b) Clock 9 cycles,

c) Create another start bit followed by stop bit condition as shown below.

The device is ready for next communication after above steps has been completed.

Figure 4.

Software Reset

Dummy Clock Cycles

Start bit

Stop bit

Start bit

SCL

SDA

Figure 5.

Bus Timing

t_HIGH

t_F

t_R

t_LOW

SCL

t_SU.STA

t_HD.STA

t_HD.DAT

t_SU.DAT

t_SU.STO

SDA IN

t_AA

t_DH

t_BUF

SDA OUT

Figure 6.

Write Cycle Timing

SCL

SDA

ACK

8th BIT

WORDn

(1)

START

CONDITION

STOP

CONDITION

8568A–SEEPR–9/09

Note: 1. The write cycle time t_WRis the time from a valid stop condition of a write sequence to the end of the

internal clear/write cycle.

Figure 7.

Output Acknowledge

SCL

DATA IN

DATA OUT

START

ACKNOWLEDGE

AT24C256C [Preliminary]

8568A–SEEPR–9/09

AT24C256C [Preliminary]

Device Addressing

The 256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or

write operation (refer to Figure 8). The device address word consists of a mandatory “1”, “0” sequence for the first four

most significant bits as shown. This is common to all two-wire EEPROM devices.

Figure 8.

Device Addressing

R/W

MSB

LSB

The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices on the same bus. These

bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary

circuit that biases them to a logic low condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high,

and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the device will return

to a standby state.

DATA SECURITY: The AT24C256C has a hardware data protection scheme that allows the user to write protect the

whole memory when the WP pin is at V_CC.

8568A–SEEPR–9/09

Write Operations

BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and

acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first

8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as

a microcontroller, must then terminate the write sequence with a stop condition. At this time the EEPROM enters an

internally-timed write cycle, t_WR, to the nonvolatile memory. All inputs are disabled during this write cycle and the

EEPROM will not respond until the write is complete (refer to Figure 9).

Figure 9.

Byte Write

Note:

* = DON’T CARE bit

PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the

first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller

can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word received. The

microcontroller must terminate the page write sequence with a stop condition (refer to Figure 10).

Figure 10.

Page Write

Note:

* = DON’T CARE bit

The data word address lower six bits are internally incremented following the receipt of each data word. The higher

data word address bits are not incremented, retaining the memory page row location. When the word address,

internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If

more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will

be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same

page.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,

acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The

read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM

respond with a “0”, allowing the read or write sequence to continue.

AT24C256C [Preliminary]

8568A–SEEPR–9/09

AT24C256C [Preliminary]

Read Operations

Read operations are initiated the same way as write operations with the exception that the read/write select bit in the

device address word is set to “1”. There are three read operations: current address read, random address read, and

sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the

last read or write operation, incremented by one. This address stays valid between operations as long as the chip

power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte

of the first page.

Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the

current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does

generate a following stop condition (refer to Figure 11).

Figure 11.

Current Address Read

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the

device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller

must generate another start condition. The microcontroller now initiates a current address read by sending a device

address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the

data word. The microcontroller does not respond with a “0” but does generate a following stop condition. (Refer to

Figure 12)

Figure 12.

Random Read

Note:

* = DON’T CARE bit

8568A–SEEPR–9/09

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After

the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an

acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When

the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The

sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a

following stop condition (refer to Figure 13).

Figure 13.

Sequential Read

AT24C256C [Preliminary]

8568A–SEEPR–9/09

AT24C256C [Preliminary]

Ordering Information

Ordering Code Detail

7.1.

A T 2 4 C 2 5 6 C - S S H L - B

Atmel Designator

Product Family

Shipping Carrier Option

B or blank = Bulk (tubes)

= Tape and reel

Operating Voltage

= 1.7V to 5.5V

Package Device Grade or

Wafer/Die Thickness

Device Density

256 = 256K

= Green, NiPdAu lead finish,

Industrial Temperature Range

(-40°C to +85°C)

Device Revision

= Green, matte Sn lead finish,

Industrial Temperature Range

(-40°C to +85°C)

11 = 11mil wafer thickness

Package Option

SS = JEDEC SOIC

= TSSOP

MA = UDFN

= wafer

WT = die in tape and reel

= UFBGA

7.2.

AT24C256C Ordering Codes

Ordering Code

Voltage

Package

Operating Range

AT24C256C-SSHL-B⁽¹⁾

AT24C256C-SSHL-T⁽²⁾

AT24C256C-XHL-B⁽¹⁾

AT24C256C-XHL-T⁽²⁾

AT24C256C-MAHL-T⁽²⁾

AT24C256C-CUL-T⁽²⁾

1.7V to 5.5V

8S1

8A2

Lead-free/Halogen-free

8A2

Industrial Temperature (−40°C to 85°C)

8MA2

8U2-1

AT24C256C-W11⁽³⁾

1.7V to 5.5V

Die Sale

Industrial Temperature (−40°C to 85°C)

Note: 1. “-B” denotes bulk.

2. “-T” denotes tape & reel. SOIC = 4K per reel. TSSOP, VFBGA and UDFN = 5K per reel.

3. Bumped die available upon request. Contact Atmel Marketing.

Package Type

8S1

8A2

8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)

8-lead, 4.40mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)

8-ball, die Ball Grid Array Package (VFBGA)

8MA2

8U2-1

8568A–SEEPR–9/09

Part Marketing Scheme

AT24C256C-SSHL

Top Mark

Seal Year

Seal Week

Y = SEAL YEAR

WW = SEAL WEEK

02 = Week 2

04 = Week 4

6: 2006

7: 2007

0: 2010

--- --- --- --- --- --- --- ---

1: 2011

8: 2008

9: 2009

2: 2012

3: 2013

:: : :::: :

:: : :::: ::

--- --- --- --- --- --- --- ---

50 = Week 50

52 = Week 52

Lot Number

--- --- --- --- --- --- --- ---

Lot Number to Use ALL Characters in Marking

BOTTOM MARK

Pin 1 Indicator (Dot)

No Bottom Mark

AT24C256C-XHL

Top Mark

Pin 1 Indicator (Dot)

--- --- --- ---

Y = SEAL YEAR

WW = SEAL WEEK

02 = Week 2

04 = Week 4

6: 2006

7: 2007

0: 2010

1: 2011

8: 2008

9: 2009

2: 2012

3: 2013

:: : :::: :

:: : :::: ::

--- --- --- --- ---

50 = Week 50

52 = Week 52

--- --- --- --- ---

Bottom Mark

--- --- --- --- --- --- ---

XX = Country of Origin

--- --- --- --- --- --- ---

<- Pin 1 Indicator

AT24C256C-MAHL

Seal Year

Top Mark

Seal Year

Seal Week

Y = SEAL YEAR

WW = SEAL WEEK

02 = Week 2

04 = Week 4

6: 2006

7: 2007

0: 2010

1: 2011

--- --- --- --- --- --- --- ---

8: 2008

9: 2009

2: 2012

3: 2013

:: : :::: :

:: : :::: ::

--- --- --- --- --- --- --- ---

50 = Week 50

52 = Week 52

Lot Number

--- --- --- --- --- --- --- ---

Pin 1 Indicator (Dot)

AT24C256C [Preliminary]

8568A–SEEPR–9/09

AT24C256C [Preliminary]

AT24C256C-CUL

Top Mark

Line 1 ----------->

Line 2 ----------->

2ECU

YMTC

<---

Pin 1 This Corner

Y = ONE DIGIT YEAR CODE

4: 2004

5: 2005

6: 2006

7: 2007

8: 2008

9: 2009

M = SEAL MONTH (USE ALPHA DESIGNATOR A-L)

A = JANUARY

B = FEBRUARY

" " """""""

J = OCTOBER

K = NOVEMBER

L = DECEMBER

TC = TRACE CODE

8568A–SEEPR–9/09

Packaging Information

8S1 – JEDEC SOIC

Figure 1.

8S1 – JEDECSOIC

Top View

End View

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

1.35

0.10

MAX

1.75

0.25

NOM

NOTE

SYMBOL

–

0.31

0.17

4.80

3.81

5.79

–

0.51

0.25

5.00

3.99

6.20

–

1.27 BSC

0.40

0˚

–

1.27

8˚

Side View

Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions,

tolerances, datums, etc.

10/07/03

DRAWING NO. REV.

TITLE

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC)

8S1

AT24C256C [Preliminary]

8568A–SEEPR–9/09

AT24C256C [Preliminary]

8A2 – TSSOP

Figure 14.

8A2 – TSSOP

2 1

Pin 1 indicator

this corner

End View

COMMON DIMENSIONS

(Unit of Measure = mm)

Top View

MIN

MAX

NOM

3.00

NOTE

SYMBOL

2.90

3.10

2, 5

6.40 BSC

4.40

4.30

–

4.50

1.20

1.05

0.30

3, 5

–

0.80

0.19

1.00

–

0.65 BSC

0.60

Side View

0.45

0.75

1.00 REF

Notes:

1. This drawing is for general information only. Refer to JEDEC D rawing MO-153, Variation AA, for proper dimension s,

tolerances, datums, etc.

2. Dimension D does not include mold Flash, prot rusions or gate burrs. Mold Flash, prot rusions and gate burrs shall not

exceed 0.15 mm (0.006 in) per sid e.

3. Dimension E1 does not include inter-lead Flash or prot rusions. Inter-lead Flash and prot rusions shall not exceed

0.25 mm (0.010 in) per sid e.

4. Dimension b does not include Dambar prot rusion. Allowable Dambar prot rusion shall be 0.08 mm total in excess of the

b dimension at maxi mum material condition. Dambar cannot be located on the l ower radius of the foot. Minimum space

between protrusion and adjacent lead is 0.07 mm .

5. Dimension D and E1 to be dete rmined at Datum Plane H .

05/30/02

DRAWING NO. REV.

8A2

TITLE

2325 Orchard Parkway

San Jose, CA 95131

8A2, 8-lead, 4.4 mm Body, Plastic

Thin Shrink Small Outline Package (TSSOP)

8568A–SEEPR–9/09

UDFN

Figure 15.

8MA2 – UDFN

Pin 1 ID

COMMON DIMENSIONS

(Unit of Measure = mm)

b (8x)

MIN

MAX

NOM

2.00 BSC

3.00 BSC

1.50

NOTE

SYMBOL

Pin#1 ID

(R0.10)

0.35

1.40

1.20

0.50

0.0

1.60

1.40

0.60

0.05

0.55

1.30

0.55

0.02

–

e (6x)

0.152 REF

0.35

L (8x)

0.30

0.40

0.50 BSC

0.25

0.18

0.20

0.30

–

4/15/08

TITLE

GPC

YNZ

DRAWING NO. REV.

8MA2, 8-pad,2 x 3 x 0.6 mm Body, Thermally

Enhanced PlasticUltraThin Dual Flat No

Lead Package (UDFN)

Package Drawing Contact:

packagedrawings@atmel.com

8MA2

AT24C256C [Preliminary]

8568A–SEEPR–9/09

AT24C256C [Preliminary]

8U2-1 – VFBGA

Figure 16.

8U2-1 – VFBGA

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

MAX

SYMBOL

NOM

NOTE

0.81 0.91 1.00

0.15 0.20 0.25

0.40 0.45 0.50

0.25 0.30 0.35

2.35 BSC

Notes:

3.73 BSC

0.75 BSC

1. This drawing is for general information.

2. Dimension 'b' is measured at the maximum solder ball diameter.

3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.

0.74 REF

0.75 BSC

0.80 REF

2/25/08

GPC

DRAWING NO.

TITLE

REV.

8U2-1, 8 ball, 2.35 x 3.73 mm Body, 0.75 mm pitch

•

Package Drawing Contact:•

packagedrawings@atmel.com

GWW

8U2-1

VFBGA Package (dBGA2)

8568A–SEEPR–9/09

Appendix A. Revision History

Doc. Rev.

Date

Comments

8568A

09/2009

Initial document release

AT24C256C [Preliminary]

8568A–SEEPR–9/09

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8568A–SEEPR–9/09

AT24C256C-SSHL-T相关文章

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AT24C256C-SSHL-T产品参数

型号:	AT24C256C-SSHL-T
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	MICROCHIP TECHNOLOGY INC
包装说明：	0.150 INCH, GREEN, PLASTIC, MS-012AA, SOIC-8
Reach Compliance Code：	compliant
Factory Lead Time：	7 weeks
风险等级：	1.27
Samacsys Description：	EEPROM 256K (32K X 8), 2-WI 1.8V
最大时钟频率 (fCLK)：	1 MHz
数据保留时间-最小值：	40
耐久性：	1000000 Write/Erase Cycles
I2C控制字节：	1010DDDR
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
内存密度：	262144 bit
内存集成电路类型：	EEPROM
内存宽度：	8
湿度敏感等级：	3
功能数量：	1
端子数量：	8
字数：	32768 words
字数代码：	32000
工作模式：	SYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	32KX8
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260
电源：	2/5 V
认证状态：	Not Qualified
座面最大高度：	1.75 mm
串行总线类型：	I2C
最大待机电流：	0.000001 A
子类别：	EEPROMs
最大压摆率：	0.003 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm
最长写入周期时间 (tWC)：	5 ms
写保护：	HARDWARE/SOFTWARE

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