欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
  •  
  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • AT25160B-PU
  • 数量-
  • 厂家-
  • 封装-
  • 批号-
  • -
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
更多
  • AT25160B-PU图
  • 集好芯城

     该会员已使用本站13年以上
  • AT25160B-PU
  • 数量1068 
  • 厂家Microchip Technology 
  • 封装 
  • 批号最新批次 
  • 原厂原装公司现货
  • QQ:3008092965QQ:3008092965 复制
    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • AT25160B-PU图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • AT25160B-PU
  • 数量15735 
  • 厂家Atmel 
  • 封装8-DIP 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • AT25160B-PU图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • AT25160B-PU
  • 数量3817 
  • 厂家Microchip 
  • 封装8-DIP(0.300,7.62mm) 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
    QQ:2881894393QQ:2881894393 复制
  • 0755-82556029 QQ:2881894392QQ:2881894393
  • AT25160B-PU图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • AT25160B-PU
  • 数量11530 
  • 厂家Atmel 
  • 封装8-DIP 
  • 批号23+ 
  • 全新原装现货热卖
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • AT25160B-PU图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • AT25160B-PU
  • 数量5000 
  • 厂家Atmel 
  • 封装贴/插片 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104791 QQ:857273081QQ:1594462451
  • AT25160B-PU图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • AT25160B-PU
  • 数量15300 
  • 厂家Microchip Technology 
  • 封装8-DIP(0.300,7.62mm) 
  • 批号24+ 
  • 只做原装★真实库存★含13点增值税票!
  • QQ:2353549508QQ:2353549508 复制
    QQ:2885134615QQ:2885134615 复制
  • 0755-83201583 QQ:2353549508QQ:2885134615
  • AT25160B-PU图
  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • AT25160B-PU
  • 数量5600 
  • 厂家Atmel 
  • 封装8-PDIP 
  • 批号2024+ 
  • 原装正品,假一罚十
  • QQ:2880824479QQ:2880824479 复制
    QQ:1344056792QQ:1344056792 复制
  • 010-62104931 QQ:2880824479QQ:1344056792
  • AT25160B-PU图
  • 深圳市思诺康科技有限公司

     该会员已使用本站16年以上
  • AT25160B-PU
  • 数量1000 
  • 厂家Microchip Technology 
  • 封装8-DIP 
  • 批号23+ 
  • IC-存储器
  • QQ:2881281130QQ:2881281130 复制
    QQ:2881281133QQ:2881281133 复制
  • 0755-83286481 QQ:2881281130QQ:2881281133
  • AT25160B-PU图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • AT25160B-PU
  • 数量660000 
  • 厂家Microchip Technology 
  • 封装原厂原装 
  • 批号23+ 
  • 支持实单/只做原装
  • QQ:3008961398QQ:3008961398 复制
  • 0755-21006672 QQ:3008961398
  • AT25160B-PU图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • AT25160B-PU
  • 数量6500000 
  • 厂家微芯 
  • 封装原厂原装 
  • 批号22+ 
  • 万三科技 秉承原装 实单可议
  • QQ:3008961396QQ:3008961396 复制
  • 0755-21008751 QQ:3008961396
  • AT25160B-PU图
  • 深圳市一线半导体有限公司

     该会员已使用本站11年以上
  • AT25160B-PU
  • 数量5117 
  • 厂家Microchip Technology 
  • 封装 
  • 批号 
  • 全新原装部分现货其他订货
  • QQ:2881493920QQ:2881493920 复制
    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921
  • AT25160B-PU图
  • 深圳市科雨电子有限公司

     该会员已使用本站9年以上
  • AT25160B-PU
  • 数量1001 
  • 厂家MICROCHIP 
  • 封装DIP-8 
  • 批号24+ 
  • ★体验愉快问购元件!!就找我吧!《停产物料》
  • QQ:97671956QQ:97671956 复制
  • 171-4729-1886(微信同号) QQ:97671956

产品型号AT25160B-PU的Datasheet PDF文件预览

Features  
Serial Peripheral Interface (SPI) Compatible  
Supports SPI Modes 0 (0,0) and 3 (1,1)  
– Datasheet Describes Mode 0 Operation  
Low-voltage and Standard-voltage Operation  
– 1.8 (VCC = 1.8V to 5.5V)  
20 MHz Clock Rate (5V)  
32-byte Page Mode  
Block Write Protection  
SPI Serial  
EEPROMs  
8K (1024 x 8)  
16K (2048 x 8)  
– Protect 1/4, 1/2, or Entire Array  
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software  
Data Protection  
Self-timed Write Cycle (5 ms max)  
High Reliability  
– Endurance: One Million Write Cycles  
– Data Retention: 100 Years  
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead  
TSSOP and 8-ball dBGA2 Packages  
Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers  
AT25080B  
AT25160B  
Description  
The AT25080B/160B provides 8192/16384 bits of serial electrically-erasable program-  
mable read-only memory (EEPROM) organized as 1024/2048 words of 8 bits each.  
The device is optimized for use in many industrial and commercial applications where  
low-power and low-voltage operation are essential. The AT25080B/160B is available  
in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP  
2x3) and 8-lead TSSOP packages.  
Preliminary  
The AT25080B/160B is enabled through the Chip Select pin (CS) and accessed via a  
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and  
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-  
rate erase cycle is required before write.  
Table 0-1.  
Pin Name  
CS  
Pin Configuration  
Function  
8-lead PDIP  
Chip Select  
SCK  
Serial Data Clock  
Serial Data Input  
Serial Data Output  
Ground  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
SI  
WP  
SO  
GND  
GND  
VCC  
Power Supply  
Write Protect  
WP  
8-lead TSSOP  
HOLD  
Suspends Serial Input  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
WP  
GND  
5228B–SEEPR–7/08  
8-lead SOIC  
8-ball dBGA2  
8-lead Ultra Thin Mini-MAP (MLP 2x3)  
VCC  
8
CS  
SO  
WP  
SI  
1
2
3
4
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
VCC 8  
HOLD 7  
SCK 6  
SI 5  
1 CS  
HOLD 7  
SCK 6  
SI 5  
2 SO  
3 WP  
4 GND  
WP  
GND  
Bottom View  
Bottom View  
Block write protection is enabled by programming the status register with one of four blocks of  
write protection. Separate program enable and program disable instructions are provided for  
additional data protection. Hardware data protection is provided via the WP pin to protect  
against inadvertent write attempts to the status register. The HOLD pin may be used to suspend  
any serial communication without resetting the serial sequence.  
Absolute Maximum Ratings*  
*NOTICE:  
Stresses beyond those listed under “Absolute  
Maximum Ratings” may cause permanent dam-  
age to the device. This is a stress rating only and  
functional operation of the device at these or any  
other conditions beyond those indicated in the  
operational sections of this specification is not  
implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device  
reliability.  
Operating Temperature..................................–55°C to +125°C  
Storage Temperature.....................................–65°C to +150°C  
Voltage on Any Pin  
with Respect to Ground....................................1.0V to +7.0V  
Maximum Operating Voltage .......................................... 6.25V  
DC Output Current........................................................ 5.0 mA  
2
AT25080B/160B [Preliminary]  
5228B–SEEPR–7/08  
AT25080B/160B [Preliminary]  
Figure 0-1. Block Diagram  
Table 0-2.  
Pin Capacitance(1)  
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)  
Symbol  
COUT  
CIN  
Test Conditions  
Max  
8
Units  
pF  
Conditions  
VOUT = 0V  
VIN = 0V  
Output Capacitance (SO)  
Input Capacitance (CS, SCK, SI, WP, HOLD)  
6
pF  
Note:  
1. This parameter is characterized and is not 100% tested.  
Table 0-3.  
DC Characteristics  
Applicable over recommended operating range from: TAI = 40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)  
Symbol  
VCC1  
Parameter  
Test Condition  
Min  
1.8  
2.7  
4.5  
Typ  
Max  
5.5  
Units  
V
Supply Voltage  
Supply Voltage  
Supply Voltage  
Supply Current  
VCC2  
5.5  
V
VCC3  
5.5  
V
ICC1  
VCC = 5.0V at 20 MHz, SO = Open, Read  
7.5  
4.0  
10.0  
mA  
VCC = 5.0V at 20 MHz, SO = Open, Read,  
ICC2  
Supply Current  
10.0  
mA  
Write  
3
5228B–SEEPR–7/08  
Applicable over recommended operating range from: TAI = 40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)  
Symbol  
Parameter  
Test Condition  
Min  
Typ  
Max  
Units  
VCC = 5.0V at 5 MHz, SO = Open,  
Read, Write  
ICC3  
Supply Current  
4.0  
6.0  
mA  
ISB1  
ISB2  
ISB3  
IIL  
Standby Current  
Standby Current  
Standby Current  
Input Leakage  
VCC = 1.8V, CS = VCC  
VCC = 2.7V, CS = VCC  
VCC = 5.0V, CS = VCC  
VIN = 0V to VCC  
< 0.1  
0.3  
6.0(2)  
7.0(2)  
µA  
µA  
µA  
µA  
µA  
V
2.0  
10.0(2)  
–3.0  
–3.0  
3.0  
IOL  
Output Leakage  
VIN = 0V to VCC, TAC = 0°C to 70°C  
3.0  
(1)  
VIL  
Input Low-voltage  
Input High-voltage  
Output Low-voltage  
Output High-voltage  
Output Low-voltage  
Output High-voltage  
–0.6  
VCC x 0.3  
VCC + 0.5  
0.4  
(1)  
VIH  
VCC x 0.7  
V
VOL1  
VOH1  
VOL2  
VOH2  
I
OL = 3.0 mA  
V
4.5V VCC 5.5V  
1.8V VCC 3.6V  
IOH = 1.6 mA  
VCC - 0.8  
VCC - 0.2  
V
IOL = 0.15 mA  
0.2  
V
IOH = 100 µA  
V
Notes: 1. VIL min and VIH max are reference only and are not tested.  
2. Worst case measured at 85°C  
4
AT25080B/160B [Preliminary]  
5228B–SEEPR–7/08  
AT25080B/160B [Preliminary]  
Table 0-4.  
AC Characteristics  
Applicable over recommended operating range from TAI = 40°C to +85°C, VCC = As Specified,  
CL = 1 TTL Gate and 30 pF (unless otherwise noted)  
Symbol  
Parameter  
Voltage  
Min  
Max  
Units  
4.5–5.5  
2.7–5.5  
1.8–5.5  
0
0
0
20  
10  
5
fSCK  
SCK Clock Frequency  
MHz  
4.5–5.5  
2.7–5.5  
1.8–5.5  
2
2
2
tRI  
Input Rise Time  
Input Fall Time  
SCK High Time  
µs  
µs  
ns  
4.5–5.5  
2.7–5.5  
1.8–5.5  
2
2
2
tFI  
20  
40  
4.5–5.5  
2.7–5.5  
1.8–5.5  
tWH  
80  
20  
40  
4.5–5.5  
2.7–5.5  
1.8–5.5  
tWL  
tCS  
tCSS  
tCSH  
tSU  
tH  
SCK Low Time  
CS High Time  
ns  
ns  
ns  
ns  
ns  
ns  
80  
4.5–5.5  
2.7–5.5  
1.8–5.5  
25  
50  
100  
4.5–5.5  
2.7–5.5  
1.8–5.5  
25  
50  
100  
CS Setup Time  
CS Hold Time  
4.5–5.5  
2.7–5.5  
1.8–5.5  
25  
50  
100  
4.5–5.5  
2.7–5.5  
1.8–5.5  
5
10  
20  
Data In Setup Time  
Data In Hold Time  
HOLD Setup Time  
HOLD Hold Time  
Output Valid  
4.5–5.5  
2.7–5.5  
1.8–5.5  
5
10  
20  
4.5–5.5  
2.7–5.5  
1.8–5.5  
5
10  
20  
tHD  
tCD  
tV  
4.5–5.5  
2.7–5.5  
1.8–5.5  
5
10  
20  
ns  
ns  
ns  
20  
40  
4.5–5.5  
2.7–5.5  
1.8–5.5  
0
0
0
80  
4.5–5.5  
2.7–5.5  
1.8–5.5  
0
0
0
tHO  
Output Hold Time  
5
5228B–SEEPR–7/08  
Table 0-4.  
AC Characteristics (Continued)  
Applicable over recommended operating range from TAI = 40°C to +85°C, VCC = As Specified,  
CL = 1 TTL Gate and 30 pF (unless otherwise noted)  
Symbol  
Parameter  
Voltage  
Min  
Max  
Units  
4.5–5.5  
2.7–5.5  
1.8–5.5  
0
0
0
25  
50  
100  
tLZ  
HOLD to Output Low Z  
ns  
4.5–5.5  
2.7–5.5  
1.8–5.5  
40  
80  
200  
tHZ  
HOLD to Output High Z  
Output Disable Time  
ns  
ns  
4.5–5.5  
2.7–5.5  
1.8–5.5  
40  
80  
200  
tDIS  
4.5–5.5  
2.7–5.5  
1.8–5.5  
5
5
5
tWC  
Write Cycle Time  
ms  
Endurance(1)  
3.3V, 25°C, Page Mode  
1M  
Write Cycles  
Note:  
1. This parameter is characterized and is not 100% tested.  
1. Serial Interface Description  
MASTER: The device that generates the serial clock.  
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080B/160B always  
operates as a slave.  
TRANSMITTER/RECEIVER: The AT25080B/160B has separate pins designated for data trans-  
mission (SO) and reception (SI).  
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.  
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be  
received. This byte contains the op-code that defines the operations to be performed.  
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the  
AT25080B/160B, and the serial output pin (SO) will remain in a high impedance state until the  
falling edge of CS is detected again. This will reinitialize the serial communication.  
CHIP SELECT: The AT25080B/160B is selected when the CS pin is low. When the device is not  
selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a  
high impedance state.  
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25080B/160B.  
When the device is selected and a serial sequence is underway, HOLD can be used to pause  
the serial communication with the master device without resetting the serial sequence. To  
pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communi-  
cation, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during  
HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.  
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held  
high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status reg-  
ister are inhibited. WP going low while CS is still low will interrupt a write to the status register. If  
the internal write cycle has already been initiated, WP going low will have no effect on any write  
6
AT25080B/160B [Preliminary]  
5228B–SEEPR–7/08  
AT25080B/160B [Preliminary]  
operation to the status register. The WP pin function is blocked when the WPEN bit in the status  
register is “0”. This will allow the user to install the AT25080B/160B in a system with the WP pin  
tied to ground and still be able to write to the status register. All WP pin functions are enabled  
when the WPEN bit is set to “1”.  
Figure 1-1. SPI Serial Interface  
AT25080B/160B  
2. Functional Description  
The AT25080B/160B is designed to interface directly with the synchronous serial peripheral  
interface (SPI) of the 6805 and 68HC11 series of microcontrollers.  
The AT25080B/160B utilizes an 8-bit instruction register. The list of instructions and their opera-  
tion codes are contained in Table 2-1. All instructions, addresses, and data are transferred with  
the MSB first and start with a high-to-low CS transition.  
Table 2-1.  
Instruction Set for the AT25080B/160B  
Instruction Name  
WREN  
Instruction Format  
0000 X110  
Operation  
Set Write Enable Latch  
Reset Write Enable Latch  
Read Status Register  
WRDI  
0000 X100  
RDSR  
0000 X101  
7
5228B–SEEPR–7/08  
Table 2-1.  
Instruction Set for the AT25080B/160B  
Instruction Name  
WRSR  
Instruction Format  
0000 X001  
Operation  
Write Status Register  
Read Data from Memory Array  
Write Data to Memory Array  
READ  
0000 X011  
WRITE  
0000 X010  
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is  
applied. All programming instructions must therefore be preceded by a Write Enable instruction.  
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable  
instruction disables all programming modes. The WRDI instruction is independent of the status  
of the WP pin.  
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to  
the status register. The READY/BUSY and Write Enable status of the device can be determined  
by the RDSR instruction. Similarly, the Block Write Protection Bits indicate the extent of protec-  
tion employed. These bits are set by using the WRSR instruction.  
Table 2-2.  
Bit 7  
Status Register Format  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
WPEN  
X
X
X
BP1  
BP0  
WEN  
RDY  
Table 2-3.  
Bit  
Read Status Register Bit Definition  
Definition  
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle  
is in progress.  
Bit 0 (RDY)  
Bit 1 (WEN)  
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the  
device is write enabled.  
Bit 2 (BP0)  
Bit 3 (BP1)  
See Table 2-4 on page 9.  
See Table 2-4 on page 9.  
Bits 4–6 are “0”s when device is not in an internal write cycle.  
Bit 7 (WPEN) See Table 2-5 on page 9.  
Bits 0–7 are “1”s during an internal write cycle.  
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of  
four levels of protection. The AT25080B/160B is divided into four array segments. One-quarter,  
one-half, or all of the memory segments can be protected. Any of the data within any selected  
segment will therefore be read only. The block write protection levels and corresponding status  
register control bits are shown in Table 2-4.  
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and  
functions as the regular memory cells (e.g., WREN, tWC, RDSR).  
8
AT25080B/160B [Preliminary]  
5228B–SEEPR–7/08  
AT25080B/160B [Preliminary]  
Table 2-4.  
Block Write Protect Bits  
Status Register Bits  
Array Addresses Protected  
AT25080B AT25160B  
None None  
Level  
0
BP1  
BP0  
0
0
1
1
0
1
0
1
1(1/4)  
2(1/2)  
3(All)  
030003FF  
020003FF  
000003FF  
060007FF  
040007FF  
000007FF  
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin  
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled  
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when  
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,  
writes to the status register, including the block protect bits and the WPEN bit, and the block-pro-  
tected sections in the memory array are disabled. Writes are only allowed to sections of the  
memory that are not block-protected.  
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as  
long as the WP pin is held low.  
Table 2-5.  
WPEN Operation  
Protected  
Blocks  
Unprotected  
Blocks  
Status  
Register  
WPEN  
WP  
X
WEN  
0
0
1
1
X
X
0
1
0
1
0
1
Protected  
Protected  
Protected  
Protected  
Protected  
Protected  
Protected  
Writeable  
Protected  
Writeable  
Protected  
Writeable  
Protected  
Writeable  
Protected  
Protected  
Protected  
Writeable  
X
Low  
Low  
High  
High  
READ SEQUENCE (READ): Reading the AT25080B/160B via the Serial Output (SO) pin  
requires the following sequence. After the CS line is pulled low to select a device, the read op-  
code is transmitted via the SI line followed by the byte address to be read (A15A0, see Table 2-  
6). Upon completion, any data on the SI line will be ignored. The data (D7D0) at the specified  
address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be  
driven high after the data comes out. The read sequence can be continued since the byte  
address is automatically incremented and data will continue to be shifted out. When the highest  
address is reached, the address counter will roll over to the lowest address allowing the entire  
memory to be read in one continuous read cycle.  
WRITE SEQUENCE (WRITE): In order to program the AT25080B/160B, two separate instruc-  
tions must be executed. First, the device must be write enabled via the WREN instruction.  
Then a write (WRITE) instruction may be executed. Also, the address of the memory location(s)  
to be programmed must be outside the protected address field location selected by the block  
write protection level. During an internal write cycle, all commands will be ignored except the  
RDSR instruction.  
9
5228B–SEEPR–7/08  
A write instruction requires the following sequence. After the CS line is pulled low to select the  
device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15A0)  
and the data (D7D0) to be programmed (see Table 2-6). Programming will start after the CS pin  
is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time  
immediately after clocking in the D0 (LSB) data bit.  
The READY/BUSY status of the device can be determined by initiating a read status register  
(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle  
has ended. Only the RDSR instruction is enabled during the write programming cycle.  
The AT25080B/160B is capable of a 32-byte page write operation. After each byte of data is  
received, the five low-order address bits are internally incremented by one; the high-order bits of  
the address will remain constant. If more than 32 bytes of data are transmitted, the address  
counter will roll over and the previously written data will be overwritten. The AT25080B/160B is  
automatically returned to the write disable state at the completion of a write cycle.  
NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction and  
will return to the standby state, when CS is brought high. A new CS falling edge is required to  
reinitiate the serial communication.  
Table 2-6.  
Address Key  
Address  
AN  
Don’t Care Bits  
AT25080B  
A9–A0  
AT25160B  
A10–A0  
A15–A10  
A15–A11  
3. Timing Diagrams  
Figure 3-1. Synchronous Data Timing (for Mode 0)  
tCS  
VIH  
CS  
VIL  
tCSH  
tCSS  
VIH  
tWH  
tWL  
SCK  
VIL  
tSU  
tH  
VIH  
VIL  
SI  
VALID IN  
tHO  
tDIS  
tV  
VOH  
VOL  
HI-Z  
HI-Z  
SO  
10  
AT25080B/160B [Preliminary]  
5228B–SEEPR–7/08  
AT25080B/160B [Preliminary]  
Figure 3-2. WREN Timing  
Figure 3-3. WRDI Timing  
Figure 3-4. RDSR Timing  
CS  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
SCK  
INSTRUCTION  
SI  
DATA OUT  
HIGH IMPEDANCE  
7
6
5
4
3
2
1
0
SO  
MSB  
11  
5228B–SEEPR–7/08  
Figure 3-5. WRSR Timing  
CS  
0
1
2
3
4
5
6
7
8
9
6
10 11 12 13 14 15  
SCK  
DATA IN  
INSTRUCTION  
SI  
7
5
4
3
2
1
0
HIGH IMPEDANCE  
SO  
Figure 3-6. READ Timing  
CS  
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31  
SCK  
SI  
BYTE ADDRESS  
...  
INSTRUCTION  
15 14 13  
3 2 1 0  
DATA OUT  
HIGH IMPEDANCE  
SO  
7 6 5 4 3 2 1 0  
MSB  
Figure 3-7. WRITE Timing  
CS  
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31  
SCK  
BYTE ADDRESS  
DATA IN  
...  
INSTRUCTION  
SI  
15 14 13  
3 2 1 0  
7 6 5 4 3 2 1 0  
HIGH IMPEDANCE  
SO  
12  
AT25080B/160B [Preliminary]  
5228B–SEEPR–7/08  
AT25080B/160B [Preliminary]  
Figure 3-8. HOLD Timing  
CS  
tCD  
tCD  
SCK  
tHD  
tHD  
HOLD  
tHZ  
SO  
tLZ  
13  
5228B–SEEPR–7/08  
4. AT25080B Ordering Information  
Ordering Code  
Voltage  
1.8  
Package  
8P3  
Operation Range  
AT25080B-PU (Bulk form only)  
AT25080BN-SH-B(1) (NiPdAu Lead Finish)  
AT25080BN-SH-T(2) (NiPdAu Lead Finish)  
AT25080B-TH-B(1) (NiPdAu Lead Finish)  
AT25080B-TH-T(2) (NiPdAu Lead Finish)  
AT25080BY6-YH-T(2) (NiPdAu Lead Finish)  
AT25080BD3-DH-T(2)  
1.8  
8S1  
1.8  
8S1  
Lead-free/Halogen-free/  
Industrial Temperature  
1.8  
8A2  
1.8  
8A2  
(40 to 85°C)  
1.8  
8Y6  
1.8  
8D3  
AT25080BU3-UU-T(2) (NiPdAu Lead Finish)  
1.8  
8U3-1  
Industrial Temperature  
AT25080B-W-11(3)  
1.8  
Die Sale  
(40 to 85°C)  
Notes: 1. “B” denotes bulk.  
2. “-T” deontes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.  
3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon  
request. Please contact Serial Interface Marketing.  
Package Type  
8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)  
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)  
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)  
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)  
8-lead, 1.8 mm x 2.2 mm Body, Ultra axLanda Grid Array (ULLGA)  
8-ball, die Ball Grid Array Package (dBGA2)  
8P3  
8S1  
8A2  
8Y6  
8D3  
8U3-1  
Options  
1.8  
Low Voltage (1.8 to 5.5V)  
14  
AT25080B/160B [Preliminary]  
5228B–SEEPR–7/08  
AT25080B/160B [Preliminary]  
5. AT25160B Ordering Information  
Ordering Code  
Voltage  
1.8  
Package  
8P3  
Operation Range  
AT25160B-PU (Bulk form only)  
AT25160BN-SH-B(1) (NiPdAu Lead Finish)  
AT25160BN-SH-T(2) (NiPdAu Lead Finish)  
AT25160B-TH-B(1) (NiPdAu Lead Finish)  
AT25160B-TH-T(2) (NiPdAu Lead Finish)  
AT25160BY6-YH-T(2) (NiPdAu Lead Finish)  
AT25160BD3-DH-T(2)  
1.8  
8S1  
1.8  
8S1  
Lead-free/Halogen-free/  
Industrial Temperature  
(40 to 85°C)  
1.8  
8A2  
1.8  
8A2  
1.8  
8Y6  
1.8  
8D3  
AT25160BU3-UU-T(2)  
1.8  
8U3-1  
Industrial Temperature  
AT25160B-W-11(3)  
1.8  
Die Sale  
(40 to 85°C)  
Notes: 1. “B” denotes bulk.  
2. “-T” deontes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.  
3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please  
contact Serial Interface Marketing.  
Package Type  
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)  
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)  
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)  
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3mm)  
8-lead, 1.8 mm x 2.2 mm Body, Ultra axLanda Grid Array (ULLGA)  
8-ball, die Ball Grid Array Package (dBGA2)  
8P3  
8S1  
8A2  
8Y6  
8D3  
8U3-1  
Options  
1.8  
Low Voltage (1.8 to 5.5V)  
15  
5228B–SEEPR–7/08  
6. Packaging Information  
8P3 – PDIP  
E
1
E1  
N
Top View  
c
eA  
End View  
COMMON DIMENSIONS  
(Unit of Measure = inches)  
D
e
MIN  
MAX  
0.210  
0.195  
0.022  
0.070  
0.045  
0.014  
0.400  
NOM  
NOTE  
SYMBOL  
D1  
A2 A  
A
2
A2  
b
0.115  
0.014  
0.045  
0.030  
0.008  
0.355  
0.005  
0.300  
0.240  
0.130  
0.018  
0.060  
0.039  
0.010  
0.365  
5
6
6
b2  
b3  
c
D
3
3
4
3
b2  
L
D1  
E
b3  
4 PLCS  
0.310  
0.250  
0.100 BSC  
0.300 BSC  
0.130  
0.325  
0.280  
b
E1  
e
Side View  
eA  
L
4
2
0.115  
0.150  
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.  
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.  
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.  
4. E and eA measured with the leads constrained to be perpendicular to datum.  
5. Pointed or rounded lead tips are preferred to ease insertion.  
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).  
01/09/02  
TITLE  
DRAWING NO.  
REV.  
2325 Orchard Parkway  
San Jose, CA 95131  
8P3, 8-lead, 0.300" Wide Body, Plastic Dual  
In-line Package (PDIP)  
8P3  
B
R
16  
AT25080B/160B [Preliminary]  
5228B–SEEPR–7/08  
AT25080B/160B [Preliminary]  
8S1 – JEDEC SOIC  
C
1
E
E1  
L
N
Top View  
End View  
e
B
COMMON DIMENSIONS  
(Unit of Measure = mm)  
A
MIN  
1.35  
0.10  
MAX  
1.75  
0.25  
NOM  
NOTE  
SYMBOL  
A1  
A
A1  
b
0.31  
0.17  
4.80  
3.81  
5.79  
0.51  
0.25  
5.00  
3.99  
6.20  
C
D
E1  
E
D
Side View  
e
1.27 BSC  
L
0.40  
0˚  
1.27  
8˚  
Note:  
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.  
10/7/03  
REV.  
TITLE  
DRAWING NO.  
1150 E. Cheyenne Mtn. Blvd.  
Colorado Springs, CO 80906  
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing  
8S1  
B
R
Small Outline (JEDEC SOIC)  
17  
5228B–SEEPR–7/08  
8A2 – TSSOP  
3
2 1  
Pin 1 indicator  
this corner  
E1  
E
L1  
N
L
Top View  
End View  
COMMON DIMENSIONS  
(Unit of Measure = mm)  
MIN  
MAX  
NOM  
3.00  
NOTE  
SYMBOL  
D
2.90  
3.10  
2, 5  
A
b
E
6.40 BSC  
4.40  
E1  
A
4.30  
4.50  
1.20  
1.05  
0.30  
3, 5  
4
A2  
b
0.80  
0.19  
1.00  
e
A2  
D
e
0.65 BSC  
0.60  
L
0.45  
0.75  
Side View  
L1  
1.00 REF  
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,  
datums, etc.  
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed  
0.15 mm (0.006 in) per side.  
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm  
(0.010 in) per side.  
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the  
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between  
protrusion and adjacent lead is 0.07 mm.  
5. Dimension D and E1 to be determined at Datum Plane H.  
5/30/02  
DRAWING NO.  
TITLE  
REV.  
2325 Orchard Parkway  
San Jose, CA 95131  
8A2, 8-lead, 4.4 mm Body, Plastic  
Thin Shrink Small Outline Package (TSSOP)  
B
8A2  
R
18  
AT25080B/160B [Preliminary]  
5228B–SEEPR–7/08  
AT25080B/160B [Preliminary]  
8Y6 – Mini MAP  
A
D2  
b
(8X)  
Pin 1  
Index  
Area  
Pin 1 ID  
L (8X)  
D
e (6X)  
A2  
A1  
1.50 REF.  
A3  
COMMON DIMENSIONS  
(Unit of Measure = mm)  
MIN  
MAX  
NOM  
2.00 BSC  
3.00 BSC  
1.50  
NOTE  
SYMBOL  
D
E
D2  
E2  
A
1.40  
1.60  
1.40  
0.60  
0.05  
0.55  
-
-
-
-
A1  
A2  
A3  
L
0.0  
-
0.02  
-
0.20 REF  
0.30  
0.20  
0.20  
0.40  
0.30  
e
0.50 BSC  
0.25  
b
2
Notes:  
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,  
tolerances, datums, etc.  
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the  
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.  
8/26/05  
DRAWING NO. REV.  
TITLE  
2325 Orchard Parkway  
San Jose, CA 95131  
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,  
Dual No Lead Package (DFN) ,(MLP 2x3)  
8Y6  
C
R
19  
5228B–SEEPR–7/08  
8D3 - ULLGA  
D
e1  
b
7
5
6
8
L
E
PIN #1 ID  
0.10  
PIN #1 ID  
A1  
0.15  
2
4
1
3
b
e
A
BOTTOM VIEW  
SIDE VIEW  
TOP VIEW  
COMMON DIMENSIONS  
(Unit of Measure = mm)  
SYMBOL  
MIN  
MAX  
0.40  
0.05  
1.90  
2.30  
0.25  
NOM  
NOTE  
A
A1  
D
E
0.00  
1.70  
2.10  
0.15  
1.80  
2.20  
b
0.20  
e
0.40 TYP  
1.20 REF  
0.30  
e1  
L
0.25  
0.35  
11/15/05  
TITLE  
DRAWING NO.  
8D3  
REV.  
1150 E. Cheyenne Mtn. Blvd.  
Colorado Springs, CO 80906  
8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe  
Land Grid Array (ULLGA) D3  
0
R
20  
AT25080B/160B [Preliminary]  
5228B–SEEPR–7/08  
AT25080B/160B [Preliminary]  
7. Revision History  
Lit No.  
Date  
Comments  
5228B  
5228A  
7/2008  
9/2007  
Changed ‘Endurance’ parameter on page 6  
Initial document release.  
21  
5228B–SEEPR–7/08  
Headquarters  
International  
Atmel Corporation  
2325 Orchard Parkway  
San Jose, CA 95131  
USA  
Tel: 1(408) 441-0311  
Fax: 1(408) 487-2600  
Atmel Asia  
Room 1219  
Chinachem Golden Plaza  
77 Mody Road Tsimshatsui  
East Kowloon  
Hong Kong  
Tel: (852) 2721-9778  
Fax: (852) 2722-1369  
Atmel Europe  
Le Krebs  
Atmel Japan  
9F, Tonetsu Shinkawa Bldg.  
1-24-8 Shinkawa  
Chuo-ku, Tokyo 104-0033  
Japan  
Tel: (81) 3-3523-3551  
Fax: (81) 3-3523-7581  
8, Rue Jean-Pierre Timbaud  
BP 309  
78054 Saint-Quentin-en-  
Yvelines Cedex  
France  
Tel: (33) 1-30-60-70-00  
Fax: (33) 1-30-60-71-11  
Product Contact  
Web Site  
Technical Support  
Sales Contact  
www.atmel.com  
s_eeprom@atmel.com  
www.atmel.com/contacts  
Literature Requests  
www.atmel.com/literature  
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any  
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMELS TERMS AND CONDI-  
TIONS OF SALE LOCATED ON ATMELS WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY  
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR  
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-  
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF  
THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no  
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications  
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided  
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use  
as components in applications intended to support or sustain life.  
© 2008 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, and others, are registered trademarks or trademarks  
of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.  
5228B–SEEPR–7/08  
配单直通车
AT25160B-SSHL-B产品参数
型号:AT25160B-SSHL-B
是否Rohs认证: 符合
生命周期:Transferred
IHS 制造商:ATMEL CORP
零件包装代码:SOIC
包装说明:SOP, SOP8,.25
针数:8
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.32.00.51
风险等级:3.72
Samacsys Description:AT25160B-SSHL-B, Serial EEPROM Memory 16kbit, Serial-SPI, 80ns, 1.8V, 8-Pin SOIC
最大时钟频率 (fCLK):5 MHz
数据保留时间-最小值:100
耐久性:1000000 Write/Erase Cycles
JESD-30 代码:R-PDSO-G8
JESD-609代码:e4
长度:4.925 mm
内存密度:16384 bit
内存集成电路类型:EEPROM
内存宽度:8
湿度敏感等级:2
功能数量:1
端子数量:8
字数:2048 words
字数代码:2000
工作模式:SYNCHRONOUS
最高工作温度:85 °C
最低工作温度:-40 °C
组织:2KX8
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP8,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
并行/串行:SERIAL
峰值回流温度(摄氏度):260
电源:2/5 V
认证状态:Not Qualified
座面最大高度:1.75 mm
串行总线类型:SPI
最大待机电流:0.000006 A
子类别:EEPROMs
最大压摆率:0.01 mA
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2.5 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:40
宽度:3.9 mm
最长写入周期时间 (tWC):5 ms
写保护:HARDWARE/SOFTWARE
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!