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产品型号AT89C2051的概述

AT89C2051芯片概述 AT89C2051是由Atmel（现为Microchip Technology）公司生产的一款8位单片微控制器，属于8051系列微控制器的一个变种。这种微控制器以其兼容性、高度集成、强大的性能、以及灵活的I/O端口配置而受到广泛欢迎。AT89C2051设计用于成本效益高且功能强大的嵌入式系统，适合多种应用，如家用电器、汽车电子和工业控制等领域。其内置的Flash存储器使得编程与重编程变得简单，用户可以在不需要特殊设备的情况下完成软件的更新。此外，AT89C2051还具有的低功耗特性使其适用于对电源要求严格的场景。详细参数 AT89C2051微控制器提供如下主要参数： - 处理器架构：8051 - 运行电压：2.7V至6V - 主频：最大12MHz - Flash程序存储器：2KB - RAM数据存储器：128字节 - I/O端口：15个通用I/O端口 -...

产品型号AT89C2051的Datasheet PDF文件预览

Features

• Compatible with MCS-51™ Products

• 2K Bytes of Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

• 2.7V to 6V Operating Range

• Fully Static Operation: 0 Hz to 24 MHz

• Two-Level Program Memory Lock

• 128 x 8-Bit Internal RAM

• 15 Programmable I/O Lines

• Two 16-Bit Timer/Counters

• Six Interrupt Sources

• Programmable Serial UART Channel

• Direct LED Drive Outputs

8-Bit

Microcontroller

with 2K Bytes

Flash

• On-Chip Analog Comparator

• Low Power Idle and Power Down Modes

Description

The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with

2K Bytes of Flash programmable and erasable read only memory (PEROM). The

device is manufactured using Atmel’s high density nonvolatile memory technology

and is compatible with the industry standard MCS-51™ instruction set. By combining

a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a pow-

erful microcomputer which provides a highly flexible and cost effective solution to

many embedded control applications.

AT89C2051

The AT89C2051 provides the following standard features: 2K Bytes of Flash, 128

bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt

architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator

and clock circuitry. In addition, the AT89C2051 is designed with static logic for opera-

tion down to zero frequency and supports two software selectable power saving

modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial

port and interrupt system to continue functioning. The Power Down Mode saves the

RAM contents but freezes the oscillator disabling all other chip functions until the next

hardware reset.

Pin Configuration

PDIP/SOIC

/VPP

0368D-B–12/97

4-15

Block Diagram

AT89C2051

4-16

AT89C2051

XTAL2

Pin Description

V_CC

Output from the inverting oscillator amplifier.

Supply voltage.

Oscillator Characteristics

GND

XTAL1 and XTAL2 are the input and output, respectively,

of an inverting amplifier which can be configured for use as

an on-chip oscillator, as shown in Figure 1. Either a quartz

crystal or ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven as shown in Figure 2.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is through a divide-by-two flip-flop, but minimum and maxi-

mum voltage high and low time specifications must be

observed.

Ground.

Port 1

Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to

P1.7 provide internal pullups. P1.0 and P1.1 require exter-

nal pullups. P1.0 and P1.1 also serve as the positive input

(AIN0) and the negative input (AIN1), respectively, of the

on-chip precision analog comparator. The Port 1 output

buffers can sink 20 mA and can drive LED displays directly.

When 1s are written to Port 1 pins, they can be used as

inputs. When pins P1.2 to P1.7 are used as inputs and are

externally pulled low, they will source current (I_IL) because

of the internal pullups.

Figure 1. Oscillator Connections

Port 1 also receives code data during Flash programming

and verification.

Port 3

Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O

pins with internal pullups. P3.6 is hard-wired as an input to

the output of the on-chip comparator and is not accessible

as a general purpose I/O pin. The Port 3 output buffers can

sink 20 mA. When 1s are written to Port 3 pins they are

pulled high by the internal pullups and can be used as

inputs. As inputs, Port 3 pins that are externally being

pulled low will source current (I_IL) because of the pullups.

Port 3 also serves the functions of various special features

of the AT89C2051 as listed below:

Port Pin

P3.0

Alternate Functions

Note:

C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

RXD (serial input port)

TXD (serial output port)

INT0 (external interrupt 0)

INT1 (external interrupt 1)

T0 (timer 0 external input)

T1 (timer 1 external input)

P3.1

Figure 2. External Clock Drive Configuration

P3.2

P3.3

P3.4

P3.5

Port 3 also receives some control signals for Flash pro-

gramming and verification.

RST

Reset input. All I/O pins are reset to 1s as soon as RST

goes high. Holding the RST pin high for two machine cycles

while the oscillator is running resets the device.

Each machine cycle takes 12 oscillator or clock cycles.

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

4-17

Special Function Registers

A map of the on-chip memory area called the Special Func-

tion Register (SFR) space is shown in the table below.

User software should not write 1s to these unlisted loca-

tions, since they may be used in future products to invoke

new features. In that case, the reset or inactive values of

the new bits will always be 0.

Note that not all of the addresses are occupied, and unoc-

cupied addresses may not be implemented on the chip.

Read accesses to these addresses will in general return

random data, and write accesses will have an indetermi-

nate effect.

Table 1. AT89C2051 SFR Map and Reset Values

0F8H

0FFH

0F7H

0EFH

0E7H

0DFH

0D7H

0CFH

0C7H

0BFH

0B7H

0AFH

0A7H

9FH

0F0H

0E8H

0E0H

0D8H

0D0H

0C8H

0C0H

0B8H

0B0H

0A8H

0A0H

98H

00000000

ACC

00000000

PSW

00000000

XXX00000

11111111

0XX00000

SCON

SBUF

00000000

XXXXXXXX

90H

97H

11111111

88H

TCON

00000000

TMOD

00000000

TL0

00000000

TL1

00000000

TH0

00000000

TH1

00000000

8FH

87H

80H

DPL

DPH

PCON

00000111

00000000

0XXX0000

AT89C2051

4-18

AT89C2051

Restrictions on Certain Instructions

Program Memory Lock Bits

On the chip are two lock bits which can be left unpro-

grammed (U) or can be programmed (P) to obtain the addi-

tional features listed in the table below:

The AT89C2051 and is an economical and cost-effective

member of Atmel’s growing family of microcontrollers. It

contains 2K bytes of flash program memory. It is fully com-

patible with the MCS-51 architecture, and can be pro-

grammed using the MCS-51 instruction set. However,

there are a few considerations one must keep in mind when

utilizing certain instructions to program this device.

(1)

Lock Bit Protection Modes

Program Lock Bits

All the instructions related to jumping or branching should

be restricted such that the destination address falls within

the physical program memory space of the device, which is

2K for the AT89C2051. This should be the responsibility of

the software programmer. For example, LJMP 7E0H would

be a valid instruction for the AT89C2051 (with 2K of mem-

ory), whereas LJMP 900H would not.

LB1

LB2

Protection Type

No program lock features.

Further programming of the Flash

is disabled.

Same as mode 2, also verify is

disabled.

1. Branching instructions:

LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR

Note:

1. The Lock Bits can only be erased with the Chip Erase

operation.

These unconditional branching instructions will execute

correctly as long as the programmer keeps in mind that the

destination branching address must fall within the physical

boundaries of the program memory size (locations 00H to

7FFH for the 89C2051). Violating the physical space limits

may cause unknown program behavior.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With

these conditional branching instructions the same rule

above applies. Again, violating the memory boundaries

may cause erratic execution.

P1.0 and P1.1 should be set to ’0’ if no external pullups are

used, or set to ’1’ if external pullups are used.

For applications involving interrupts the normal interrupt

service routine address locations of the 80C51 family archi-

tecture have been preserved.

It should be noted that when idle is terminated by a hard-

ware reset, the device normally resumes program execu-

tion, from where it left off, up to two machine cycles before

the internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when Idle is terminated by

reset, the instruction following the one that invokes Idle

should not be one that writes to a port pin or to external

memory.

2. MOVX-related instructions, Data Memory:

The AT89C2051 contains 128 bytes of internal data mem-

ory. Thus, in the AT89C2051 the stack depth is limited to

128 bytes, the amount of available RAM. External DATA

memory access is not supported in this device, nor is exter-

nal PROGRAM memory execution. Therefore, no MOVX

[...] instructions should be included in the program.

A typical 80C51 assembler will still assemble instructions,

even if they are written in violation of the restrictions men-

tioned above. It is the responsibility of the controller user to

know the physical features and limitations of the device

being used and adjust the instructions used correspond-

ingly.

Power Down Mode

In the power down mode the oscillator is stopped, and the

instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power down mode is termi-

nated. The only exit from power down is a hardware reset.

Reset redefines the SFRs but does not change the on-chip

RAM. The reset should not be activated before V_CCis

restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and sta-

bilize.

P1.0 and P1.1 should be set to ’0’ if no external pullups are

used, or set to ’1’ if external pullups are used.

4-19

Ready/Busy: The Progress of byte programming can also

be monitored by the RDY/BSY output signal. Pin P3.1 is

pulled low after P3.2 goes High during programming to indi-

cate BUSY. P3.1 is pulled High again when programming is

done to indicate READY.

Programming The Flash

The AT89C2051 is shipped with the 2K bytes of on-chip

PEROM code memory array in the erased state (i.e., con-

tents = FFH) and ready to be programmed. The code mem-

ory array is programmed one byte at a time. Once the array

is programmed, to re-program any non-blank byte, the

entire memory array needs to be erased electrically.

Program Verify: If lock bits LB1 and LB2 have not been

programmed code data can be read back via the data lines

for verification:

Internal Address Counter: The AT89C2051 contains an

internal PEROM address counter which is always reset to

000H on the rising edge of RST and is advanced by apply-

ing a positive going pulse to pin XTAL1.

1. Reset the internal address counter to 000H by bringing

RST from ’L’ to ’H’.

2. Apply the appropriate control signals for Read Code data

and read the output data at the port P1 pins.

Programming Algorithm: To program the AT89C2051,

the following sequence is recommended.

3. Pulse pin XTAL1 once to advance the internal address

counter.

4. Read the next code data byte at the port P1 pins.

5. Repeat steps 3 and 4 until the entire array is read.

1. Power-up sequence:

Apply power between V_CCand GND pins

Set RST and XTAL1 to GND

The lock bits cannot be verified directly. Verification of the

lock bits is achieved by observing that their features are

enabled.

2. Set pin RST to ’H’

Set pin P3.2 to ’H’

3. Apply the appropriate combination of ’H’ or ’L’ logic

levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the

programming operations shown in the PEROM Pro-

gramming Modes table.

Chip Erase: The entire PEROM array (2K bytes) and the

two Lock Bits are erased electrically by using the proper

combination of control signals and by holding P3.2 low for

10 ms. The code array is written with all “1”s in the Chip

Erase operation and must be executed before any non-

blank memory byte can be re-programmed.

To Program and Verify the Array:

4. Apply data for Code byte at location 000H to P1.0 to

P1.7.

Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of

locations 000H, 001H, and 002H, except that P3.5 and

P3.7 must be pulled to a logic low. The values returned are

as follows.

5. Raise RST to 12V to enable programming.

6. Pulse P3.2 once to program a byte in the PEROM array

or the lock bits. The byte-write cycle is self-timed and

typically takes 1.2 ms.

7. To verify the programmed data, lower RST from 12V to

logic ’H’ level and set pins P3.3 to P3.7 to the appropiate

levels. Output data can be read at the port P1 pins.

(000H) = 1EH indicates manufactured by Atmel

(001H) = 21H indicates 89C2051

8. To program a byte at the next address location, pulse

XTAL1 pin once to advance the internal address counter.

Apply new data to the port P1 pins.

Programming Interface

Every code byte in the Flash array can be written and the

entire array can be erased by using the appropriate combi-

nation of control signals. The write operation cycle is self-

timed and once initiated, will automatically time itself to

completion.

9. Repeat steps 5 through 8, changing data and advancing

the address counter for the entire 2K bytes array or until

the end of the object file is reached.

10.Power-off sequence:

set XTAL1 to ’L’

All major programming vendors offer worldwide support for

the Atmel microcontroller series. Please contact your local

programming vendor for the appropriate software revision.

set RST to ’L’

Turn V_CCpower off

Data Polling: The AT89C2051 features Data Polling to

indicate the end of a write cycle. During a write cycle, an

attempted read of the last byte written will result in the com-

plement of the written data on P1.7. Once the write cycle

has been completed, true data is valid on all outputs, and

the next cycle may begin. Data Polling may begin any time

after a write cycle has been initiated.

AT89C2051

4-20

AT89C2051

Flash Programming Modes

Mode

RST/VPP

P3.2/PROG

P3.3

P3.4

P3.5

P3.7

Write Code Data⁽¹⁾⁽³⁾

12V

Read Code Data⁽¹⁾

Write Lock

Bit - 1

Bit - 2

12V

Chip Erase

(2)

Read Signature Byte

Notes: 1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at

XTAL 1 pin.

2. Chip Erase requires a 10-ms PROG pulse.

3. P3.1 is pulled Low during programming to indicate RDY/BSY.

Figure 3. Programming the Flash Memory

Figure 4. Verifying the Flash Memory

4-21

Flash Programming and Verification Characteristics

T_A= 0°C to 70°C, V_CC= 5.0 ± 10%

Symbol

V_PP

Parameter

Min

Max

12.5

250

Units

Programming Enable Voltage

Programming Enable Current

Data Setup to PROG Low

Data Hold After PROG

P3.4 (ENABLE) High to V_PP

V_PPSetup to PROG Low

V_PPHold After PROG

11.5

I_PP

µA

µs

t_DVGL

t_GHDX

t_EHSH

t_SHGL

t_GHSL

t_GLGH

t_ELQV

t_EHQZ

t_GHBL

t_WC

1.0

PROG Width

110

1.0

ENABLE Low to Data Valid

Data Float After ENABLE

PROG High to BUSY Low

Byte Write Cycle Time

RDY/BSY\ to Increment Clock Delay

Increment Clock High

2.0

µs

t_BHIH

t_IHIL

Note:

1.0

200

1. Only used in 12-volt programming mode.

Flash Programming and Verification Waveforms

AT89C2051

4-22

AT89C2051

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Operating Temperature ................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage............................................. 6.6V

DC Output Current...................................................... 25.0 mA

DC Characteristics

T_A= -40°C to 85°C, V_CC= 2.0V to 6.0V (unless otherwise noted)

Symbol

V_IL

Parameter

Condition

Min

-0.5

Max

0.2 V_CC- 0.1

V_CC+ 0.5

0.5

Units

Input Low Voltage

Input High Voltage

V_IH

(Except XTAL1, RST)

(XTAL1, RST)

0.2 V_CC+ 0.9

0.7 V_CC

V_IH1

V_OL

Output Low Voltage⁽¹⁾

(Ports 1, 3)

I_OL= 20 mA, V_CC= 5V

_OL= 10 mA, V_CC= 2.7V

V_OH

Output High Voltage

(Ports 1, 3)

I_OH= -80 µA, V_CC= 5V ± 10%

I_OH= -30 µA

2.4

0.75 V_CC

0.9 V_CC

_OH= -12 µA

I_IL

I_TL

I_LI

Logical 0 Input Current

(Ports 1, 3)

V_IN= 0.45V

-50

-750

±10

µA

Logical 1 to 0 Transition Current

(Ports 1, 3)

V_IN= 2V, V_CC= 5V ± 10%

0 < V_IN< V_CC

µA

Input Leakage Current

(Port P1.0, P1.1)

V_OS

V_CM

Comparator Input Offset Voltage

V_CC= 5V

Comparator Input Common

Mode Voltage

V_CC

RRST

C_IO

Reset Pulldown Resistor

Pin Capacitance

300

KΩ

Test Freq. = 1 MHz, T_A= 25°C

I_CC

Power Supply Current

Active Mode, 12 MHz, V_CC= 6V/3V

15/5.5

5/1

Idle Mode, 12 MHz, V_CC= 6V/3V

P1.0 & P1.1 = 0V or V_CC

Power Down Mode⁽²⁾

V_CC= 6V P1.0 & P1.1 = 0V or V_CC

V_CC= 3V P1.0 & P1.1 = 0V or V_CC

100

µA

Notes: 1. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 20 mA

Maximum total I_OLfor all output pins: 80 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

2. Minimum V_CCfor Power Down is 2V.

4-23

External Clock Drive Waveforms

External Clock Drive

Symbol

Parameter

V_CC= 2.7V to 6.0V

Min Max

V_CC= 4.0V to 6.0V

Min Max

Units

1/t_CLCL

t_CLCL

Oscillator Frequency

Clock Period

High Time

MHz

83.3

41.6

t_CHCX

t_CLCX

t_CLCH

t_CHCL

Low Time

Rise Time

Fall Time

AT89C2051

4-24

AT89C2051

Serial Port Timing: Shift Register Mode Test Conditions

(V_CC= 5.0V ± 20%; Load Capacitance = 80 pF)

Symbol

Parameter

12 MHz Osc

Variable Oscillator

Units

Min

Max

Min

12t_CLCL

10t_CLCL-133

2t_CLCL-117

Max

t_XLXL

t_QVXH

t_XHQX

t_XHDX

t_XHDV

Serial Port Clock Cycle Time

1.0

700

µs

Output Data Setup to Clock Rising Edge

Output Data Hold After Clock Rising Edge

Input Data Hold After Clock Rising Edge

Clock Rising Edge to Input Data Valid

700

10t_CLCL-133

Shift Register Mode Timing Waveforms

(1)

AC Testing Input/Output Waveforms

Float Waveforms

Note:

1. AC Inputs during testing are driven at V_CC- 0.5V for

a logic 1 and 0.45V for a logic 0. Timing measure-

ments are made at V_IHmin. for a logic 1 and V_IL

max. for a logic 0.

Note:

1. For timing purposes, a port pin is no longer float-

ing when a 100 mV change from load voltage

occurs. A port pin begins to float when 100 mV

change frothe loaded V /V level occurs.

OH OL

4-25

AT89C2051

TYPICAL ICC - ACTIVE (85°C)

Vcc=6.0V

Vcc=5.0V

Vcc=3.0V

FREQUENCY (MHz)

AT89C2051

TYPICAL ICC - IDLE (85°C)

Vcc=6.0V

Vcc=5.0V

Vcc=3.0V

FREQUENCY (MHz)

AT89C2051

TYPICAL ICC vs.VOLTAGE- POWER DOWN (85°C)

3.0V

4.0V

5.0V

6.0V

Vcc VOLTAGE

Notes: 1. XTAL1 tied to GND for I

(power down)

2. P.1.0 and P1.1 = V

or GND

3. Lock bits programmed

AT89C2051

4-26

AT89C2051

Ordering Information

Speed

(MHz)

Power

Supply

Ordering Code

Package

Operation Range

2.7V to 6.0V

AT89C2051-12PC

AT89C2051-12SC

20P3

20S

Commercial

(0°C to 70°C)

AT89C2051-12PI

AT89C2051-12SI

20P3

20S

Industrial

(-40°C to 85°C)

AT89C2051-12PA

AT89C2051-12SA

20P3

20S

Automotive

(-40°C to 105°C)

4.0V to 6.0V

AT89C2051-24PC

AT89C2051-24SC

20P3

20S

Commercial

(0°C to 70°C)

AT89C2051-24PI

AT89C2051-24SI

20P3

20S

Industrial

(-40°C to 85°C)

Package Type

20P3

20S

20 Lead, 0.300” Wide, Plastic Dual In-line Package (PDIP)

20 Lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)

4-27

AT89C2051相关文章

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AT89C2051-12PA产品参数

型号:	AT89C2051-12PA
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	DIP
包装说明：	DIP,
针数：	20
Reach Compliance Code：	not_compliant
HTS代码：	8542.31.00.01
风险等级：	5.43
核心架构：	8051
设备核心：	8051
时钟速度：	24
内存：	0.125
闪存：	2
具有ADC：	NO
地址总线宽度：
位大小：	8
最大时钟频率：	12 MHz
DAC 通道：	NO
DMA 通道：	NO
外部数据总线宽度：
JESD-30 代码：	R-PDIP-T20
JESD-609代码：	e0
长度：	25.9 mm
湿度敏感等级：	1
I/O 线路数量：	15
端子数量：	20
片上程序ROM宽度：	8
最高工作温度：	105 °C
最低工作温度：	-40 °C
PWM 通道：	NO
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified
RAM（字节）：	128
ROM（单词）：	2048
ROM可编程性：	FLASH
座面最大高度：	5.33 mm
速度：	12 MHz
最大供电电压：	6 V
最小供电电压：	2.7 V
表面贴装：	NO
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	7.62 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

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