AT93C46DN-SH-T全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号AT93C46DN-SH-T的概述

AT93C46DN-SH-T 芯片概述 AT93C46DN-SH-T 是一款微控制器与外部存储设备间常用的串行 EEPROM（电可擦可编程只读存储器）芯片，专为高密度存储应用设计。它由 Atmel（现在是 Microchip Technology 的一部分）生产，具备高强度的耐用性和可靠性，适用于多种电子设备中，如家用电器、工业控制器和汽车电子设备。AT93C46DN-SH-T 的主要特性包括其高速度的读写操作、低功耗以及广泛的工作温度范围，使其成为嵌入式系统设计中常用的解决方案。详细参数 AT93C46DN-SH-T 的主要参数包括： - 存储容量：2Kbit（256字） - 工作电压：2.7V - 5.5V - 最高时钟频率：6MHz - 数据输出：8位并行输出 - 写入时间：一般为5ms（最大） - 读出时间：一般为1μs（最大） - 封装类型：SOIC-8, PDIP-8 -...

产品型号AT93C46DN-SH-T的Datasheet PDF文件预览

Features

• Low-voltage and Standard-voltage Operation

– 1.8 (V_CC= 1.8V to 5.5V)

• User-selectable Internal Organization

– 1K: 128 x 8 or 64 x 16

• Three-wire Serial Interface

• 2 MHz Clock Rate (5V)

• Self-timed Write Cycle (5 ms max)

• High Reliability

Three-wire

Serial

EEPROM

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead

TSSOP and 8-ball dBGA2 Packages

• Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers

1K (128 x 8 or 64 x 16)

Description

The AT93C46D provides 1024 bits of serial electrically erasable programmable read-

only memory (EEPROM), organized as 64 words of 16 bits each (when the ORG pin is

connected to VCC), and 128 words of 8 bits each (when the ORG pin is tied to

ground). The device is optimized for use in many industrial and commercial applica-

tions where low-power and low-voltage operations are essential. The AT93C46D is

available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-

MAP (MLP 2x3), 8-lead TSSOP, and 8-lead dBGA2 packages.

AT93C46D

The AT93C46D is enabled through the Chip Select pin (CS) and accessed via a

three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift

Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the

data is clocked out serially on the DO pin. The Write cycle is completely self-timed,

and no separate Erase cycle is required before Write. The Write cycle is only enabled

when the part is in the Erase/Write Enable state. When CS is brought high following

the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.

The AT93C46D is available in 1.8 (1.8V to 5.5V) version.

Table 0-1.

Pin Name

Pin Configurations

Function

8-lead SOIC

8-lead dBGA2

VCC

Chip Select

ORG

GND

ORG

GND

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

Bottom View

8-lead PDIP

8-lead Ultra Thin mini-MAP (MLP 2x3)

VCC

GND

VCC

ORG

Power Supply

Internal Organization

No Connect

ORG

GND

ORG

GND

Bottom View

8-lead TSSOP

VCC

ORG

GND

5193F–SEEPR–1/08

1. Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only, and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability

Operating Temperature......................................−55°C to +125°C

Storage Temperature .........................................−65°C to +150°C

Voltage on Any Pin

with Respect to Ground........................................ −1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1-1. Block Diagram

Notes: 1. When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is con-

nected to ground, the “x 8” organization is selected. If the ORG pin is left unconnected and the

application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then

the “x 16” organization is selected.

2. For the AT93C46D, if the “x 16” organization is the mode of choice and pin 6 (ORG) is left

unconnected, Atmel^®recommends using AT93C46E device. For more details, see the

AT93C46E datasheet.

AT93C46D

5193F–SEEPR–1/08

AT93C46D

Table 1-1.

Applicable over recommended operating range from T_A= 25°C, f = 1.0 MHz, V_CC= +1.8V (unless otherwise noted)

Pin Capacitance⁽¹⁾

Symbol

C_OUT

C_IN

Test Conditions

Max

Units

Conditions

V_OUT= 0V

V_IN= 0V

Output Capacitance (DO)

Input Capacitance (CS, SK, DI)

Note:

1. This parameter is characterized and is not 100% tested.

Table 1-2.

DC Characteristics

Applicable over recommended operating range from: T_AI= −40°C to +85°C, V_CC= +1.8V to +5.5V (unless otherwise noted)

Symbol

V_CC1

Parameter

Test Condition

Min

1.8

2.7

4.5

Typ

Max

5.5

Unit

Supply Voltage

V_CC2

5.5

V_CC3

5.5

READ at 1.0 MHz

WRITE at 1.0 MHz

CS = 0V

0.5

0.4

6.0

10.0

0.1

2.0

µA

I_CC

Supply Current

V_CC= 5.0V

2.0

I_SB1

I_SB2

I_SB3

I_IL

Standby Current

Input Leakage

V_CC= 1.8V

1.0

V_CC= 2.7V

CS = 0V

10.0

15.0

1.0

V_CC= 5.0V

CS = 0V

V_IN= 0V to V_CC

I_OL

Output Leakage

1.0

(1)

V_IL1

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

−0.6

2.0

0.8

2.7V ≤ V_CC≤ 5.5V

(1)

V_IH1

V_CC+ 1

V_CCx 0.3

V_CC+ 1

0.4

(1)

V_IL2

−0.6

1.8V ≤ V_CC≤ 2.7V

(1)

V_IH2

V_CCx 0.7

V_OL1

V_OH1

V_OL2

V_OH2

I_OL= 2.1 mA

I_OH= −0.4 mA

_OL= 0.15 mA

I_OH= −100 µA

2.7V ≤ V_CC≤ 5.5V

2.4

0.2

1.8V ≤ V_CC≤ 2.7V

V_CC– 0.2

Note:

1. V_ILmin and V_IHmax are reference only and are not tested.

5193F–SEEPR–1/08

Table 1-3.

AC Characteristics

Applicable over recommended operating range from T_AI= −40°C to + 85°C, V_CC= +2.7V to +5.5V,

CL = 1 TTL Gate and 100 pF (unless otherwise noted)

Symbol

Parameter

Test Condition

Min

Typ

Max

Units

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

0.25

SK Clock

Frequency

f_SK

MHz

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

250

1000

t_SKH

t_SKL

t_CS

SK High Time

SK Low Time

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

250

1000

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

250

1000

Minimum CS

Low Time

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

200

t_CSS

CS Setup Time

Relative to SK

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

100

400

t_DIS

t_CSH

t_DIH

DI Setup Time

CS Hold Time

DI Hold Time

Relative to SK

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

100

400

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

250

1000

t_PD1

t_PD0

t_SV

Output Delay to “1”

Output Delay to “0”

CS to Status Valid

AC Test

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

250

1000

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

250

1000

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 5.5V

100

150

400

CS to DO in High

Impedance

AC Test

CS = V_IL

t_DF

1.8V ≤ V_CC≤ 5.5V

0.1

t_WP

Write Cycle Time

5.0V, 25°C

(1)

Endurance

Write Cycles

Note:

1. This parameter is ensured by characterization.

AT93C46D

5193F–SEEPR–1/08

AT93C46D

Table 1-4.

Instruction Set for the AT93C46D

Address

Data

Instruction

Code

x 8

x 16

x 8

x 16

Comments

Reads data stored in memory, at

specified address

READ

A₆– A₀

A₅– A₀

Write enable must precede all

programming modes

EWEN

11XXXXX

11XXXX

ERASE

WRITE

A₆– A₀

A₅– A₀

Erases memory location A_n– A₀

Writes memory location A_n– A₀

D₇– D₀

D₁₅– D₀

Erases all memory locations. Valid

only at V_CC= 4.5V to 5.5V

ERAL

10XXXXX

10XXXX

Writes all memory locations. Valid

only at V_CC= 4.5V to 5.5V

WRAL

EWDS

01XXXXX

00XXXXX

01XXXX

00XXXX

D₁₅– D₀

Disables all programming instructions

Note:

The Xs in the address field represent DON’T CARE values and must be clocked.

2. Functional Description

The AT93C46D is accessed via a simple and versatile three-wire serial communication inter-

face. Device operation is controlled by seven instructions issued by the host processor. A valid

instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the

appropriate op code and the desired memory address location.

READ (READ): The Read (READ) instruction contains the address code for the memory loca-

tion to be read. After the instruction and address are decoded, data from the selected memory

location is available at the serial output pin DO. Output data changes are synchronized with the

rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or

16-bit data output string.

ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the

Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)

instruction must be executed first before any programming instructions can be carried out.

Please note that once in the EWEN state, programming remains enabled until an EWDS instruc-

tion is executed or V_CCpower is removed from the part.

ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory

location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and

address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought

high after being kept low for a minimum of 250 ns (t_CS). A logic “1” at pin DO indicates that the

selected memory location has been erased and the part is ready for another instruction.

WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written

into the specified memory location. The self-timed programming cycle t_WPstarts after the last bit

of data is received at serial data input pin DI. The DO pin outputs the Read/Busy status of the

part if CS is brought high after being kept low for a minimum of 250 ns (t_CS). A logic “0” at DO

indicates that programming is still in progress. A logic “1” indicates that the memory location at

the specified address has been written with the data pattern contained in the instruction and the

5193F–SEEPR–1/08

part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is

brought high after the end of the self-timed programming cycle tWP.

ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array

to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the

Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns

(t_CS). The ERAL instruction is valid only at V_CC= 5.0V ± 10%.

WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the

data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if

CS is brought high after being kept low for a minimum of 250 ns (t_CS). The WRAL instruction is

valid only at V_CC= 5.0V 10%.

ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write

Disable (EWDS) instruction disables all programming modes and should be executed after all

programming operations. The operation of the Read instruction is independent of both the

EWEN and EWDS instructions and can be executed at any time.

AT93C46D

5193F–SEEPR–1/08

AT93C46D

3. Timing Diagrams

Figure 3-1. Synchronous Data Timing

μs

Note:

1. This is the minimum SK period.

Table 3-1.

Organization Key for Timing Diagrams

AT93C46D (1K)

I/O

A_N

D_N

x 8

A₆

x 16

A₅

D₇

D₁₅

Figure 3-2. READ Timing

t_CS

High Impedance

5193F–SEEPR–1/08

Figure 3-3. EWEN Timing

t_CS

...

Figure 3-4. EWDS Timing

t_CS

...

Figure 3-5. WRITE Timing

t_CS

...

A_N

D_N

HIGH IMPEDANCE

BUSY

READY

t_WP

AT93C46D

5193F–SEEPR–1/08

AT93C46D

Figure 3-6. WRAL Timing⁽¹⁾

t_CS

...

D_N... D0

BUSY

HIGH IMPEDANCE

READY

t_WP

Note:

1. Valid only at V_CC= 4.5V to 5.5V.

Figure 3-7. ERASE Timing

t_CS

STANDBY

CHECK

STATUS

A_N

...

A_N-1A_N-2

t_DF

t_SV

HIGH IMPEDANCE

BUSY

READY

t_WP

5193F–SEEPR–1/08

Figure 3-8. ERAL Timing⁽¹⁾

t_CS

STANDBY

CHECK

STATUS

t_DF

t_SV

BUSY

HIGH IMPEDANCE

READY

t_WP

Note:

1. Valid only at V_CC= 4.5V to 5.5V.

AT93C46D

5193F–SEEPR–1/08

AT93C46D

4. AT93C46D Ordering Information

Ordering Code

Voltage

1.8

Package

8P3

Operation Range

AT93C46D-PU (Bulk form only)

AT93C46DN-SH-B⁽¹⁾(NiPdAu Lead finish)

AT93C46DN-SH-T⁽²⁾(NiPdAu Lead finish)

AT93C46D-TH-B⁽¹⁾(NiPdAu Lead finish)

AT93C46D-TH-T⁽²⁾(NiPdAu Lead finish)

AT93C46DY6-YH-T⁽²⁾(NiPdAu Lead finish)

AT93C46DU3-UU-T⁽²⁾

1.8

8S1

Lead-free/Halogen-free/

Industrial Temperature

1.8

8S1

1.8

8A2

(−40°C to 85°C)

1.8

8A2

1.8

8Y6

1.8

8U3-1

Industrial

AT93C46D-W-11⁽³⁾

1.8

Die Sale

(−40°C to 85°C)

Notes: 1. “-B” denotes bulk

2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini MAP, and dBGA2 = 5K per reel.

3. Available in tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request.

Please contact Serial Interface Marketing.

Package Type

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

8-ball, Die Ball Grid Array Package (dBGA2)

8P3

8S1

8A2

8U3-1

8Y6

8-lead, 2.00 mm x 3.00 mm Body, 0.50mm Pitch, Ultra-Thin Mini-MAO, Dual No Lead Package. (DFN), (MLP 2x3mm)

Options

−1.8

Low Voltage (1.8V to 5.5V)

5193F–SEEPR–1/08

5. Part Marking Scheme

5.1

AT93C46D 8-PDIP

TOP MARK

Seal Year

Y = SEAL YEAR

WW = SEAL WEEK

02 = Week 2

Seal Week

6: 2006

0: 2010

7: 2007

8: 2008

9: 2009

1: 2011

2: 2012

3: 2013

04 = Week 4

:: : :::: :

:: : :::: ::

|---|---|---|---|---|---|---|---|

50 = Week 50

52 = Week 52

|---|---|---|---|---|---|---|---|

Lot Number

Lot Number to Use ALL Characters in Marking

|---|---|---|---|---|---|---|---|

BOTTOM MARK

Pin 1 Indicator (Dot)

No Bottom Mark

5.2

AT93C46D 8-SOIC

TOP MARK

Seal Year

Y = SEAL YEAR

WW = SEAL WEEK

02 = Week 2

Seal Week

6: 2006

0: 2010

7: 2007

8: 2008

9: 2009

1: 2011

2: 2012

3: 2013

04 = Week 4

:: : :::: :

:: : :::: ::

|---|---|---|---|---|---|---|---|

50 = Week 50

52 = Week 52

|---|---|---|---|---|---|---|---|

Lot Number

Lot Number to Use ALL Characters in Marking

|---|---|---|---|---|---|---|---|

BOTTOM MARK

Pin 1 Indicator (Dot)

No Bottom Mark

AT93C46D

5193F–SEEPR–1/08

AT93C46D

5.3

AT93C46D 8-TSSOP

TOP MARK

Pin 1 Indicator (Dot)

Y = SEAL YEAR

WW = SEAL WEEK

6: 2006

7: 2007

8: 2008

9: 2009

0: 2010

02 = Week 2

04 = Week 4

:: : :::: :

:: : :::: ::

|---|---|---|---|

1: 2011

2: 2012

3: 2013

|---|---|---|---|---|

1 *

|---|---|---|---|---|

50 = Week 50

52 = Week 52

BOTTOM MARK

|---|---|---|---|---|---|---|

<- Pin 1 Indicator

5.4

AT93C46D 8-Ultra Thin Mini MAP

TOP MARK

Y = YEAR OF ASSEMBLY

|---|---|---|

XX = ATMEL LOT NUMBER TO COORESPOND WITH

NSEB TRACE CODE LOG BOOK.

|---|---|---|

(e.g. XX = AA, AB, AC,...AX, AY, AZ)

|---|---|---|

Y = SEAL YEAR

6: 2006

7: 2007

8: 2008

0: 2010

1: 2011

2: 2012

Pin 1 Indicator (Dot)

9: 2009

3: 2013

5193F–SEEPR–1/08

5.5

AT93C46D dBGA2

TOP MARK

LINE 1------->

LINE 2------->

46DU

YMTC

|<-- Pin 1 This Corner

Y = ONE DIGIT YEAR CODE

4: 2004

5: 2005

6: 2006

7: 2007

8: 2008

9: 2009

M = SEAL MONTH (USE ALPHA DESIGNATOR A-L)

A = JANUARY

B = FEBRUARY

" " """""""

J = OCTOBER

K = NOVEMBER

L = DECEMBER

TC = TRACE CODE (ATMEL LOT

NUMBERS TO CORRESPOND

WITH ATK TRACE CODE LOG BOOK)

AT93C46D

5193F–SEEPR–1/08

AT93C46D

6. Package Information

8P3 - PDIP

Top View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

MIN

MAX

NOM

NOTE

SYMBOL

A2 A

0.210

0.195

0.022

0.070

0.045

0.014

0.400

0.115

0.014

0.045

0.030

0.008

0.355

0.005

0.300

0.240

0.130

0.018

0.060

0.039

0.010

0.365

4 PLCS

0.310

0.250

0.325

0.280

0.100 BSC

0.300 BSC

0.130

Side View

0.115

0.150

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

01/09/02

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

San Jose, CA 95131

8P3, 8-lead, 0.300" Wide Body, Plastic Dual

In-line Package (PDIP)

8P3

5193F–SEEPR–1/08

8S1 - JEDEC SOIC

TOP VIEW

END VIEW

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

1.35

0.10

MAX

1.75

0.25

NOM

NOTE

SYMBOL

–

0.31

0.17

4.80

3.81

5.79

–

0.51

0.25

5.05

3.99

6.20

–

SIDE VIEW

1.27 BSC

0.40

0°

–

1.27

8°

Note:

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

3/17/05

TITLE

DRAWING NO.

REV.

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

8S1

Small Outline (JEDEC SOIC)

AT93C46D

5193F–SEEPR–1/08

AT93C46D

8A2 - TSSOP

2 1

Pin 1 indicator

this corner

Top View

End View

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

MAX

NOM

3.00

NOTE

SYMBOL

2.90

3.10

2, 5

6.40 BSC

4.40

4.30

–

4.50

1.20

1.05

0.30

3, 5

–

0.80

0.19

1.00

–

0.65 BSC

0.60

0.45

0.75

Side View

1.00 REF

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm

(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the

b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between

protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

5/30/02

DRAWING NO.

TITLE

REV.

2325 Orchard Parkway

San Jose, CA 95131

8A2, 8-lead, 4.4 mm Body, Plastic

Thin Shrink Small Outline Package (TSSOP)

8A2

5193F–SEEPR–1/08

8U3-1 – dBGA2

A₁

PIN 1 BALL PAD CORNER

A₂

Top View

PIN 1 BALL PAD CORNER

Side Vie

(d1)

COMMON DIMENSIONS

(Unit of Measure - mm)

(e1)

SYMBOL

NOM

MIN

MAX

NOTE

Bottem View

0.73

0.09

0.40

0.20

0.79

0.85

0.19

0.50

0.30

8 SOLDER BALLS

0.14

0.45

0.25

1.50 BSC

2.0 BSC

0.50 BSC

0.25 REF

1.00 BSC

0.25 REF

This drawing is for general information only.

Dimension 'b' is measured at maximum solder ball diameter.

5/3/05

TITLE

REV.

DRAWING NO.

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,

PO8U3-1

Small Die Ball Grid Array Package (dBGA2)

AT93C46D

5193F–SEEPR–1/08

AT93C46D

8Y6 – MLP 2x3

((88XX))

Pin 11

Inddeex

Area

Pinn 11 ID

L (8X)

e (66X)

1.500 RREEFF.

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

MAX

NOM

2.00 BSC

3.00 BSC

1.50

NOTE

SYMBOL

1.40

1.60

1.40

0.60

0.05

0.55

0.0

0.02

0.20 REF

0.30

0.20

0.40

0.50 BSC

0.25

0.30

Notes:

1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,

tolerances, datums, etc.

2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the

terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.

3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the

device through this pad, so if soldered it should be tied to ground

10/16/07

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,

Dual No Lead Package (DFN) ,(MLP 2x3)

8Y6

5193F–SEEPR–1/08

7. Revision History

Doc. Rev.

Date

Comments

5193F

5193E

1/2008

11/2007

Removed ‘preliminary’ status

Modified ‘max’ value in AC Characteristics table

Moved Pinout figure

Added new feature for Die Sales

Modified Ordering Information table layout

Modified Park Marking Schemes

5193D

5193C

8/2007

6/2007

Updated to new template

Added Product Markup Scheme

Added Technical email contact

5193C

5193B

5193A

3/2007

2/2007

1/2007

Corrected Figures 4 and 5.

Added ‘Ultra Thin’ description to 8-lead Mini-MAP package.

Initial document release.

AT93C46D

5193F–SEEPR–1/08

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

Atmel Europe

Le Krebs

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

s_eeprom@atmel.com

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF

THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

5193F–SEEPR–1/08

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AT93C46DN-SH-T产品参数

型号:	AT93C46DN-SH-T
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Transferred
零件包装代码：	SOIC
包装说明：	0.150 INCH, LEAD FREE, PLASTIC, MS-012AA, SOIC-8
针数：	8
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.51
Factory Lead Time：	1 week
风险等级：	3.61
其他特性：	IT CAN ALSO OPERATES ON 2.7 AND 4.5 SUPPLY ALSO
备用内存宽度：	8
最大时钟频率 (fCLK)：	0.25 MHz
数据保留时间-最小值：	100
耐久性：	1000000 Write/Erase Cycles
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
内存密度：	1024 bit
内存集成电路类型：	EEPROM
内存宽度：	16
湿度敏感等级：	1
功能数量：	1
端子数量：	8
字数：	64 words
字数代码：	64
工作模式：	SYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	64X16
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260
电源：	2/5 V
认证状态：	Not Qualified
座面最大高度：	1.75 mm
串行总线类型：	3-WIRE
最大待机电流：	0.000001 A
子类别：	EEPROMs
最大压摆率：	0.002 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	1.8 V
标称供电电压 (Vsup)：	2.7 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	3.9 mm
最长写入周期时间 (tWC)：	5 ms
写保护：	SOFTWARE
Base Number Matches：	1

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