BLUENRG-M2SP全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

BlueNRG-MS

Upgradable Bluetooth^®Low Energy network processor

Datasheet - production data

•

Full link controller and host security

High performance, ultra-low power Cortex-

M0 32-bit based architecture core

Upgradable BLE stack (stored in embedded

Flash memory, via SPI)

•

AES security co-processor

Low power modes

16 or 32 MHz crystal oscillator

12 MHz ring oscillator

32 kHz crystal oscillator

32 kHz ring oscillator

Battery voltage monitor

Compliant with the following radio frequency

regulations: ETSI EN 300 328, EN 300 440,

FCC CFR47 Part 15, ARIB STD-T66

Available in QFN32 (5 x 5 mm) and

WLCSP34 (2.66 x 2.56 mm) packages

Operating temperature range:

-40 °C to 85 °C

•

Features

•

Bluetooth specification v4.1 compliant

master and slave single-mode Bluetooth low

energy network processor

Embedded Bluetooth low energy protocol

stack: GAP, GATT, SM, L2CAP, LL, RF-

PHY

Bluetooth low energy profiles provided

separately

Operating supply voltage: from 1.7 to 3.6 V

8.2 mA maximum TX current (@0 dBm, 3.0

V)

Down to 1.7 µA current consumption with

active BLE stack

Integrated linear regulator and DC-DC step-

down converter

Up to +8 dBm available output power (at

antenna connector)

Applications

•

Watches

Fitness, wellness and sports

Consumer medical

Security/proximity

Remote control

Home and industrial automation

Assisted living

•

Mobile phone peripherals

PC peripherals

Table 1: Device summary

Order code

Package

Packing

QFN32

(5 x 5 mm)

Tape and

reel

•

Excellent RF link budget (up to 96 dB)

Accurate RSSI to allow power control

Proprietary application controller interface

(ACI), SPI based, allows interfacing with an

external host application microcontroller

BLUENRG-MSQTR

BLUENRG-MSCSP

WLCSP34

(2.66 x 2.56 mm)

Tape and

reel

February 2016

DocID027103 Rev 6

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www.st.com

List of tables

BlueNRG-MS

Contents

1

2

3

4

5

Description.......................................................................................5

General description.........................................................................6

Pin description ................................................................................8

Application circuits .......................................................................11

Block diagram and descriptions ..................................................15

5.1

5.2

5.3

5.4

Core, memory and peripherals........................................................15

Power management........................................................................16

Clock management .........................................................................17

Bluetooth low energy radio..............................................................17

6

7

8

9

Operating modes...........................................................................19

Application controller interface....................................................22

Absolute maximum ratings and thermal data .............................23

General characteristics.................................................................24

10 Electrical specification..................................................................25

10.1

10.2

10.3

10.4

10.5

Electrical characteristics..................................................................25

RF general characteristics ..............................................................28

RF transmitter characteristics..........................................................28

RF receiver characteristics..............................................................29

High speed crystal oscillator (HSXOSC) characteristics .................30

10.5.1

High speed crystal oscillator (HSXOSC).......................................... 31

10.6

10.7

10.8

10.9

Low speed crystal oscillator (LSXOSC) characteristics...................32

High speed ring oscillator (HSROSC) characteristics .....................32

Low speed ring oscillator (LSROSC) characteristics.......................32

N-fractional frequency synthesizer characteristics ..........................32

10.10 Auxiliary blocks characteristics........................................................33

10.11 SPI characteristics ..........................................................................33

11 Package information .....................................................................35

11.1

11.2

QFN32 package information ...........................................................36

WLCSP34 package information ......................................................38

12 PCB assembly guidelines.............................................................40

13 Revision history ............................................................................41

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BlueNRG-MS

List of tables

Table 1: Device summary...........................................................................................................................1

Table 2: Pinout description .........................................................................................................................9

Table 3: External component list ..............................................................................................................13

Table 4: SPI interface ...............................................................................................................................15

Table 5: BlueNRG-MS operating modes ..................................................................................................20

Table 6: BlueNRG-MS transition times.....................................................................................................21

Table 7: Absolute maximum ratings .........................................................................................................23

Table 8: Thermal data...............................................................................................................................23

Table 9: Recommended operating conditions ..........................................................................................24

Table 10: RF general characteristics........................................................................................................28

Table 11: RF Transmitter characteristics..................................................................................................28

Table 12: RF receiver characteristics .......................................................................................................29

Table 13: High speed crystal oscillator characteristics.............................................................................30

Table 14: Low speed crystal oscillator characteristics..............................................................................32

Table 15: High speed ring oscillator characteristics .................................................................................32

Table 16: Low speed ring oscillator characteristics..................................................................................32

Table 17: N-fractional frequency synthesizer characteristics ...................................................................33

Table 18: Auxiliary blocks characteristics.................................................................................................33

Table 19: SPI characteristics....................................................................................................................33

Table 20: QFN32 (5 x 5 x 1 pitch 0.5 mm) mechanical data ....................................................................37

Table 21: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data..................................................39

Table 22: Flip Chip CSP (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation .......40

Table 23: Document revision history ........................................................................................................41

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List of figures

BlueNRG-MS

List of figures

Figure 1: BlueNRG-MS application block diagram.....................................................................................7

Figure 2: BlueNRG-MS pinout top view (QFN32).......................................................................................8

Figure 3: BlueNRG-MS pinout top view (WLCSP34) .................................................................................8

Figure 4: BlueNRG-MS pinout bottom view (WLCSP34) ...........................................................................9

Figure 5: BlueNRG-MS application circuit: active DC-DC converter QFN32 package ............................11

Figure 6: BlueNRG-MS application circuit: non active DC-DC converter QFN32 package .....................12

Figure 7: BlueNRG-MS application circuit: active DC-DC converter WLCSP package ...........................12

Figure 8: BlueNRG-MS application circuit: non active DC-DC converter WLCSP package ....................13

Figure 9: Block diagram............................................................................................................................15

Figure 10: Power management strategy using LDO ................................................................................16

Figure 11: Power management strategy using step-down DC-DC converter ..........................................17

Figure 12: Simplified state machine..........................................................................................................20

Figure 13: Simplified block diagram of the amplitude regulated oscillator ...............................................31

Figure 14: SPI timings...............................................................................................................................34

Figure 15: QFN32 (5 x 5 x 1 pitch 0.5 mm) package outline....................................................................36

Figure 16: QFN32 (5 x 5 x 1 pitch 0.5 mm) package detail "A"................................................................37

Figure 17: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline..................................................38

Figure 18: Flip Chip CSP (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation......40

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BlueNRG-MS

Description

1

Description

The BlueNRG-MS is a very low power Bluetooth low energy (BLE) single-mode network

processor, compliant with Bluetooth specification v4.1. The BlueNRG-MS supports multiple

roles simultaneously, and can act at the same time as Bluetooth Smart sensor and hub

device.

The Bluetooth Low Energy stack runs on the embedded ARM Cortex-M0 core. The stack is

stored on the on-chip non-volatile Flash memory and can be easily upgraded via SPI. The

device comes pre-programmed with a production-ready stack image (whose version could

change at any time without notice). A different or more up-to-date stack image can be

downloaded from the ST web site and programmed on the device through the ST provided

software tools.

The BlueNRG-MS allows applications to meet of the tight advisable peak current

requirements imposed with the use of standard coin cell batteries. The maximum peak

current is only 10 mA at 1 dBm of output power. Ultra low-power sleep modes and very

short transition times between operating modes allow very low average current

consumption, resulting in longer battery life. The BlueNRG-MS offers the option of

interfacing with external microcontrollers using SPI transport layer.

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General description

BlueNRG-MS

2

General description

The BlueNRG-MS is a single-mode Bluetooth low energy master/slave network processor,

compliant with the Bluetooth specification v4.1.

It integrates a 2.4 GHz RF transceiver and a powerful Cortex-M0 microcontroller, on which

a complete power-optimized stack for Bluetooth single mode protocol runs, providing:

•

Master, slave role support

GAP: central, peripheral, observer or broadcaster roles

ATT/GATT: client and server

SM: privacy, authentication and authorization

L2CAP

Link Layer: AES-128 encryption and decryption

An on-chip non-volatile Flash memory allows on-field Bluetooth low energy stack upgrade.

In addition, according the Bluetooth specification v4.1 the BlueNRG-MS can support the

following features through firmware updates:

•

Multiple roles simultaneously support

Support simultaneous advertising and scanning

Support being Slave of up to two Masters simultaneously

Privacy V1.1

Low Duty Cycle Directed Advertising

The device allows applications to meet of the tight advisable peak current requirements

imposed with the use of standard coin cell batteries. If the high efficiency embedded DC-

DC step-down converter is used, the maximum input current is only 15 mA at the highest

output power (+8 dBm). Even if the DC-DC converter is not used, the maximum input

current is only 29 mA at the highest output power, still preserving battery life.

Ultra low-power sleep modes and very short transition time between operating modes

result in very low average current consumption during real operating conditions, providing

very long battery life.

Two different external matching networks are suggested: standard mode (TX output power

up to +5 dBm) and high power mode (TX output power up to +8 dBm).

The external host application processor, where the application resides, is interfaced with

the BlueNRG-MS through an application controller interface protocol which is based on a

standard SPI interface.

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BlueNRG-MS

General description

Figure 1: BlueNRG-MS application block diagram

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Pin description

BlueNRG-MS

3

Pin description

The BlueNRG-MS pinout is shown in Figure 2, Figure 3 and Figure 4. In Table 2 a short

description of the pins is provided.

Figure 2: BlueNRG-MS pinout top view (QFN32)

Figure 3: BlueNRG-MS pinout top view (WLCSP34)

Top view (balls are underneath).

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DocID027103 Rev 6

BlueNRG-MS

Pin description

Figure 4: BlueNRG-MS pinout bottom view (WLCSP34)

Table 2: Pinout description

Pins

Name

I/O

Description

QFN32

WLCSP

E2

1

2

SPI_MOSI

SPI_CLK

SPI_IRQ

TEST1

VBAT3

TEST2

TEST3

TEST4

TEST5

TEST6

TEST7

VDD1V8

TEST8

TEST9

I

SPI_MOSI

SPI_CLK

SPI_IRQ

Test pin

E1

3

D2

D1

C1

C2

B1

O

4

I/O

VDD

I/O

O

5

1.7-3.6 battery voltage input

Test pin connected to GND

1.8 V digital core

6

7

8

B2

9

A1

10

11

12

13

14

B3

A2

A3

A4

I/O

Test pin not connected

A5

Test pin not connected

Test pin not connected (QFN32)

15

16

B4

B5

TEST11

TEST12

I/O

Test pin connected to GND (WLCSP)

Test pin not connected (QFN32)

Test pin connected to GND (WLCSP)

17

18

19

20

21

22

23

24

25

26

A6

B6

-

FXTAL1

FXTAL0

VBAT2

I

16/32 MHz crystal

1.8-3.6 battery voltage input

Antenna + matching circuit

32 kHz crystal

I

VDD

I/O

I

C6

D6

E6

E5

D5

E4

F6

RF1

RF0

SXTAL1

SXTAL0

VBAT1

I

32 kHz crystal

VDD

I

1.7-3.6 battery voltage input

Reset

RESETN

SMPSFILT1

O

SMPS output

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Pin description

Pins

BlueNRG-MS

Name

I/O

Description

QFN32

WLCSP

27

28

29

30

31

32

-

NO_SMPS

SMPSFILT2

VDD1V2

TEST10

SPI_CS

SPI_MISO

GND

I

Power management strategy selection

SMPS input/output

1.2 V digital core

TEST pin connected to GND

SPI_CS

F5

F3

E3

F2

F1

C3

D3

D4

F4

I/O

O

I/O

I

O

SPI_MISO

GND

Ground

-

GND

Ground

-

GND

Ground

-

SMPS-GND

SMPS ground

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DocID027103 Rev 6

BlueNRG-MS

Application circuits

4

Application circuits

The schematics below are purely indicative. For more detailed schematics, please refer to

the "Reference design" and "Layout guidelines" which are provided as separate

documents.

Figure 5: BlueNRG-MS application circuit: active DC-DC converter QFN32 package

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Application circuits

BlueNRG-MS

Figure 6: BlueNRG-MS application circuit: non active DC-DC converter QFN32 package

Figure 7: BlueNRG-MS application circuit: active DC-DC converter WLCSP package

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BlueNRG-MS

Application circuits

Figure 8: BlueNRG-MS application circuit: non active DC-DC converter WLCSP package

Table 3: External component list

Description

Component

C1

C2

C3

C4

C5

C6

C7

C8

Decoupling capacitor

DC-DC converter output capacitor

Decoupling capacitor for 1.2 V digital regulator

Decoupling capacitor

32 kHz crystal loading capacitor ⁽¹⁾

RF balun/matching network capacitor High Performance

RF balun/matching network capacitor Standard mode

C9

RF balun/matching network capacitor High Performance

RF balun/matching network capacitor Standard mode

C10

C11

RF balun/matching network capacitor High Performance

RF balun/matching network capacitor Standard mode

C12

C13

Decoupling capacitor

RF balun/matching network capacitor High Performance

RF balun/matching network capacitor Standard mode

C14

C15

RF balun/matching network capacitor High Performance

RF balun/matching network capacitor Standard mode

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Application circuits

Component

BlueNRG-MS

Description

RF balun/matching network capacitor High Performance

RF balun/matching network capacitor Standard mode

C16

C17

C18

C19

C20

16/32 MHz crystal loading capacitor

Decoupling capacitor for 1.8 V digital regulator

RF balun/matching network capacitor High Performance, RF balun/matching network capacitor

Standard mode

C21

L1

DC-DC converter input inductor, Isat > 100 mA, Q > 25

RF balun/matching network inductor High Performance

RF balun/matching network inductor Standard mode

L2

RF balun/matching network inductor High Performance

RF balun/matching network inductor Standard mode

L3

L4

R1

RF balun/matching network inductor High Performance

RF balun/matching network inductor Standard mode

Pull-down resistor on the SPI_IRQ line

(can be replaced by the internal pull-down of the Application MCU)

XTAL1

XTAL2

32 kHz crystal (optional)

16/32 MHz crystal

Notes:

⁽¹⁾Values valid only for the crystal NDK NX3215SA-32.768 kHz-EXS00A-MU00003. For other crystals refer to what specified in

their datasheet.

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BlueNRG-MS

Block diagram and descriptions

5

Block diagram and descriptions

A block diagram of the device is shown in Figure 9: "Block diagram". In the following

subsections a short description of each module is given.

Figure 9: Block diagram

5.1

Core, memory and peripherals

The BlueNRG-MS contains an ARM Cortex-M0 microcontroller core that supports ultra-low

leakage state retention mode and almost instantaneously returning to fully active mode on

critical events.

The memory subsystem consists of 64 KB Flash, and 12 KB RAM, divided in two blocks of

6 KB (RAM1 and RAM2). Flash is used for the M0 program. No RAM or FLASH resources

are available to the external microcontroller driving the BlueNRG-MS.

The application controller interface (ACI) uses a standard SPI slave interface as transport

layer, basing in five physical wires:

•

2 control wires (clock and slave select)

2 data wires with serial shift-out (MOSI and MISO) in full duplex

1 wire to indicate data availability from the slave

Table 4: SPI interface

Name

Direction

Width

Description

SPI slave select = SPI enable.

SPI clock (max 8 MHz).

SPI_CS

In

1

SPI_CLK

SPI_MOSI

SPI_MISO

Master output, slave input.

Master input, slave output.

In

Out

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Block diagram and descriptions

BlueNRG-MS

Name

Direction

Width

Description

Slave has data for master.

SPI_IRQ

Out

1

All the SPI pins have an internal pull-down except for the CSN that has a pull-up. All the

SPI pins, except the CSN, are in high impedance state during the low-power states. The

IRQ pin needs a pull-down external resistor.

The device embeds a battery level detector to monitor the supply voltage. The

characteristics of the battery level detector are defined in Table 19.

5.2

Power management

The BlueNRG-MS integrates both a low dropout voltage regulator (LDO) and a step-down

DC-DC converter, and one of them can be used to power the internal BlueNRG-MS

circuitry. However even when the LDO is used, the stringent maximum current

requirements, which are advisable when coin cell batteries are used, can be met and

further improvements can be obtained with the DC-DC converter at the sole additional cost

of an inductor and a capacitor.

The internal LDOs supplying both the 1.8 V digital blocks and 1.2 V digital blocks require

decoupling capacitors for stable operation. When the VBAT voltage is below 1.8 V, the

LDO 1.8 V output follows the VBAT value.

Figure 10 and Figure 11, show the simplified power management schemes using LDO and

DC-DC converter.

Figure 10: Power management strategy using LDO

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BlueNRG-MS

Block diagram and descriptions

Figure 11: Power management strategy using step-down DC-DC converter

5.3

Clock management

The BlueNRG-MS integrates two low-speed frequency oscillators (LSOSC) and two High

speed (16 MHz or 32 MHz) frequency oscillators (HSOSC).

The low frequency clock is used in Low Power mode and can be supplied either by a 32.7

kHz oscillator that uses an external crystal and guarantee up to ±50 ppm frequency

tolerance, or by a ring oscillator with maximum ±500 ppm frequency tolerance, which does

not require any external components.

The primary high frequency clock is a 16 MHz or 32 MHz crystal oscillator. There is also a

fast-starting 12 MHz ring oscillator that provides the clock while the crystal oscillator is

starting up. Frequency tolerance of high speed crystal oscillator is ±50 ppm.

The usage of the 16 MHz (or 32 MHz) crystal is strictly necessary.

5.4

Bluetooth low energy radio

The BlueNRG-MS integrates a RF transceiver compliant to the Bluetooth specification and

to the standard national regulations in the unlicensed 2.4 GHz ISM band.

The RF transceiver requires very few external discrete components. It provides 96 dB link

budgets with excellent link reliability, keeping the maximum peak current below 15 mA.

In Transmit mode, the power amplifier (PA) drives the signal generated by the frequency

synthesizer out to the antenna terminal through a very simple external network. The power

delivered as well as the harmonic content depends on the external impedance seen by the

PA.

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Block diagram and descriptions

BlueNRG-MS

The output power is programmable from -18 dBm to +8 dBm, to allow a user-defined power

control system and to guarantee optimum power consumption for each scenario.

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DocID027103 Rev 6

BlueNRG-MS

Operating modes

6

Operating modes

Several operating modes are defined for the BlueNRG-MS:

•

Reset mode

Sleep mode

Standby mode

Active mode

Radio mode

−

Receive Radio mode

Transmit Radio mode

In Reset mode, the BlueNRG-MS is in ultra-low power consumption: all voltage regulators,

clocks and the RF interface are not powered. The BlueNRG-MS enters Reset mode by

asserting the external reset signal. As soon as it is de-asserted, the device follows the

normal activation sequence to transit to Active mode.

In Sleep mode either the low speed crystal oscillator or the low speed ring oscillator are

running, whereas the high speed oscillators are powered down as well as the RF interface.

The state of the BlueNRG-MS is retained and the content of the RAM is preserved.

Depending on the application, part of the RAM (RAM2 block) can be switched off during

sleep to save more power (refer to stack mode 1, described in UM1868).

While in Sleep mode, the BlueNRG-MS waits until an internal timer expires and then it

goes into Active mode. The transition from Sleep mode to Active mode can also be

activated through the SPI interface.

Standby mode and Sleep mode are equivalent but the low speed frequency oscillators are

powered down. In Standby mode the BlueNRG-MS can be activated through the SPI

interface.

In Active mode the BlueNRG-MS is fully operational: all interfaces, including SPI and RF,

are active as well as all internal power supplies together with the high speed frequency

oscillator. The MCU core is also running.

Radio mode differs from Active mode as also the RF transceiver is active and it is capable

of either transmitting or receiving.

Figure 12 reports the simplified state machine:

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Operating modes

BlueNRG-MS

Figure 12: Simplified state machine

Table 5: BlueNRG-MS operating modes

SPI LSOSC HSOSC Core

RF

synt.

RX

chain

TX

chain

State

Digital LDO

OFF

Reset

Register contents

lost

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

Standby

Sleep

Active

RX

Register contents

retained

OFF

ON

Register contents

retained

ON

Register contents

retained

-

ON

Register contents

retained

ON

TX

Register contents

retained

ON

OFF

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DocID027103 Rev 6

BlueNRG-MS

Operating modes

Condition

Table 6: BlueNRG-MS transition times

Maximum time

Transition

1.5 ms

7 ms

32 kHz not available

Reset-active ⁽¹⁾

32 kHz RO

32 kHz XO

94 ms

0.42 ms

6.2 ms

93 ms

0.42 ms

125 µs

61 µs

32 kHz not available

32 kHz RO

Standby-active ⁽¹⁾

32 kHz XO

Sleep-active ⁽¹⁾

Active-RX

Channel change

No channel change

Channel change

No channel change

131 µs

67 µs

Active-TX

RX-TX or TX-RX

Notes:

150 µs

⁽¹⁾These measurements are taken using NX3225SA-16.000 MHz-EXS00A-CS05997.

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Application controller interface

BlueNRG-MS

7

Application controller interface

The application controller interface (ACI) is based on a standard SPI module with speeds

up to 8 MHz. The ACI defines a protocol providing access to all the services offered by the

layers of the embedded Bluetooth stack. The ACI commands are described in the

BlueNRG-MS ACI command interface document (UM1865). In addition, the ACI provides a

set of commands that allow to program BlueNRG-MS firmware from an external device

connected to SPI. The complete description of updater commands and procedures is

provided in a separate application note (AN4491).

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BlueNRG-MS

Absolute maximum ratings and thermal data

8

Absolute maximum ratings and thermal data

Absolute maximum ratings are those values above which damage to the device may occur.

Functional operation under these conditions is not implied. All voltages are referred to

GND.

Table 7: Absolute maximum ratings

Parameter

Value

Unit

DC-DC converter supply voltage

input and output

5, 19, 24, 26, 28

-0.3 to +3.9

V

DC voltage on linear voltage

regulator

12, 29

-0.3 to +3.9

V

1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 25, 27,

30, 31, 32

DC voltage on digital input/output

pins

13, 14, 15,16

17, 18, 22, 23

20, 21 ⁽¹⁾

DC voltage on analog pins

DC voltage on XTAL pins

DC voltage on RF pins

-0.3 to +3.9

-0.3 to +1.4

-40 to +125

±2.0

V

T_STG

Storage temperature range

Electrostatic discharge voltage

°C

kV

V_{ESD HBM}

-

Notes:

⁽¹⁾+8 dBm input power at antenna connector in Standard mode, +11 dBm in High Power mode, with given

reference design.

Table 8: Thermal data

Symbol

Parameter

Value

Unit

34 (QFN32)

R_thj-amb

Thermal resistance junction-ambient

°C/W

50 (WLCSP36)

2.5 (QFN32)

R_thj-c

Thermal resistance junction-case

25 (WLCSP36)

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General characteristics

BlueNRG-MS

9

General characteristics

Table 9: Recommended operating conditions

Symbol

V _BAT

T _A

Parameter

Operating battery supply voltage

Operating ambient temperature range

Min.

1.7

Typ.

Max.

Unit

V

3.6

-40

+85

°C

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BlueNRG-MS

Electrical specification

10

Electrical specification

10.1

Electrical characteristics

Characteristics measured over recommended operating conditions unless otherwise

specified. Typical value are referred to T_A= 25 °C, V_BAT= 3.0 V. All performance data are

referred to a 50 W antenna connector, via reference design, QFN32 package version.

Symbol

Parameter

Test conditions

Min.

Typ. Max. Unit

Power consumption when DC-DC converter active

Reset

5

1.3

2

nA

µA

RAM2 OFF

RAM2 ON

Standby

32 kHz XO

ON (RAM2

OFF)

1.7

2.4

2.8

3.5

32 kHz XO

ON (RAM2

ON)

Sleep

µA

32 kHz RO

ON (RAM2

OFF)

32 kHz RO

ON (RAM2

ON)

CPU, Flash

and RAM off

2

Active

mA

CPU, Flash

and RAM on

3.3

7.7

7.3

IBAT

Supply current

High Power

mode

RX

Standard

mode

+5 dBm

0 dBm

11

8.2

7.2

6.7

6.3

-2 dBm

-6 dBm

-9 dBm

Standard

mode

TX

mA

-12

dBm

6.1

5.9

-15

dBm

-18

dBm

5.8

TX

+8 dBm

15.1

mA

High Power

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Electrical specification

Symbol

BlueNRG-MS

Parameter

Test conditions

Min.

Typ. Max. Unit

mode

+4 dBm

+2 dBm

-2 dBm

-5 dBm

10.9

9

8.3

7.7

Power consumption when DC-DC converter not active

Reset

5

1.4

2

nA

µA

RAM2 OFF

RAM2 ON

Standby

32 kHz XO

ON (RAM2

OFF)

1.7

2.4

2.8

3.5

32 kHz XO

ON (RAM2

ON)

Sleep

µA

32 kHZ RO

ON (RAM2

OFF)

32 kHZ RO

ON (RAM2

ON)

CPU, flash

and RAM off

Active

RX

2.3

mA

high power

mode

14.5

14.3

standard

mode

IBAT

Supply current

+5 dBm

0 dBm

21

15.4

13.3

12.2

11.5

11

-2 dBm

-6 dBm

-9 dBm

-12 dBm

-15 dBm

-18 dBm

+8 dBm

+4 dBm

+2 dBm

-2 dBm

-5 dBm

-8 dBm

-11 dBm

TX standard mode

mA

10.6

10.4

28.8

20.5

17.2

15.3

14

TX High Power

mode

mA

13

12.3

26/42

DocID027103 Rev 6

BlueNRG-MS

Symbol

Electrical specification

Parameter

Test conditions

-14 dBm

Min.

Typ. Max. Unit

12

Digital I/O

CIN

Port I/O

capacitance

1.29

5

1.38 1.67

pF

ns

0.1*VDD to

0.9*VDD, CL=50pF

TRISE

Rise time

19

0.9*VDD to

0.1*VDD, CL=50pF

TFALL

T(RST)L

Fall time

6

22

ns

Hold time for

reset

1.5

ms

TC

VBAT range

3

3.3

2.5

1.8

3.6

2.75

1.98

0.8

V

TC1

TC2

2.25

1.7

-0.3

2

VBAT range: TC

VBAT range: TC1

VBAT range: TC2

VIL

Input low voltage

0.7

V

0.63

3.6

VBAT range: TC

VIH

VOL

VOH

IOL

Input high voltage VBAT range: TC1

VBAT range: TC2

1.7

1.17

3.6

VBAT range: TC

0.4

Output low

VBAT range: TC1

voltage

0.7

VBAT range: TC2

0.45

VBAT range: TC

2.4

1.7

1.35

3.4

3.8

1.6

5.5

3.7

1.4

Output high

VBAT range: TC1

voltage

VBAT range: TC2

VBAT range: TC

Low level output

current @VOL

(max)

5.6

6.6

3

7.9

VBAT range: TC1

VBAT range: TC2

VBAT range: TC

VBATrange: TC1

VBAT range: TC2

10.1 mA

5

10.6 17.6

High level output

current @VOH

(min)

IOH

7.2

3

12

mA

5.6

DocID027103 Rev 6

27/42

Electrical specification

BlueNRG-MS

10.2

RF general characteristics

Characteristics measured over recommended operating conditions unless otherwise

specified. Typical value are referred to T _A= 25 °C, V _BAT=3.0 V. All performance data are

referred to a 50 W antenna connector, via reference design, QFN32 package version.

Table 10: RF general characteristics

Symbol

FREQ

F _CH

Parameter

Frequency range

Channel spacing

Test conditions

Min.

Typ.

Max.

Unit

MHz

2400

2483.5

2

RF channel center

frequency

RF _ch

2402

2480

MHz

10.3

RF transmitter characteristics

Characteristics measured over recommended operating conditions unless otherwise

specified. Typical value are referred to T_A= 25 °C, V_BAT= 3.0 V. All performance data are

referred to a 50 W antenna connector, via reference design, QFN32 package version.

Table 11: RF Transmitter characteristics

Symbol

Parameter

Test conditions

Min.

Typ.

Max. Unit

MOD

Modulation scheme

GFSK

Bandwidth-bit period

product

BT

0.5

M_index

DR

Modulation index

Air data rate

0.45

0.5

1

0.55

Mbps

Symbol time

accuracy

ST_acc

50

ppm

Maximum output

power at antenna

connector

+8

+5

+10

+7

High power

dBm

P_MAX

Standard mode

High power

-15

-18

Minimum output

power

P_RFC

P_BW1M

dB

Standard mode

RF power accuracy

±2

6 dB bandwidth for

modulated carrier (1

Mbps)

Using resolution bandwidth of

100 kHz

500

kHz

dBm

kHz

1^stadjacent channel

transmit power 2

MHz

Using resolution bandwidth of

100 kHz and average

detector

P_RF1

-20

-30

2^ndadjacent channel Using resolution bandwidth of

P_RF2

transmit power >3

MHz

100 kHz and average

detector

Harmonics included. Using

resolution bandwidth of 1

MHz and average detector

P_SPUR

Spurious emission

-41

During the packet and

including both initial

frequency offset and drift

Center frequency

deviation

CF_dev

±150

28/42

DocID027103 Rev 6

BlueNRG-MS

Electrical specification

Symbol

Parameter

Test conditions

Min.

Typ.

Max. Unit

Freq_drift

Frequency drift

During the packet

±50

±20

kHz

Initial carrier

frequency drift

IFreq_drift

DriftRate_maxMaximum drift rate

400 Hz/µs

25.9 +

j44.4

Standard mode @ 2440 MHz

Optimum differential

Z_LOAD

load

Ω

High power mode @ 2440

MHz

25.4 +

j20.8

10.4

RF receiver characteristics

Characteristics measured over recommended operating conditions unless otherwise

specified. Typical value are referred to T _A= 25 °C, V _BAT=3.0 V. All performance data are

referred to a 50 W antenna connector, via reference design, QFN32 package version.

Table 12: RF receiver characteristics

Symbol

Parameter

Sensitivity

Test conditions

BER <0.1%

Min.

Typ.

Max. Unit

RX _SENS

-88

dBm

Saturation

8

P _SAT

Standard mode

High power mode

BER <0.1%

dBm

11

-

Standard mode @ 2440 MHz

31.4 - j26.6

28.8 - j18.5

z _IN

Input differential impedance

Ω

High power mode @ 2440

MHz

RF selectivity with BLE equal modulation on interfering signal

C/I _CO-

channel

Wanted signal = -67 dBm,

BER ≤ 0.1%

9

dBc

Co-channel interference

Adjacent (+1 MHz)

Interference

Wanted signal = -67 dBm,

BER ≤ 0.1%

2

C/I _{1 MHz}

C/I _{2 MHz}

C/I _{3 MHz}

C/I _{≥4 MHz}

C/I _{≥6 MHz}

C/I _{≥25 MHz}

Adjacent (+2 MHz)

Interference

Wanted signal = -67 dBm,

BER ≤ 0.1%

-34

-40

-34

-45

-64

Adjacent (+3 MHz)

Interference

Wanted signal = -67 dBm,

BER ≤ 0.1%

-

Adjacent (≥±4 MHz)

Interference

Wanted signal = -67 dBm,

BER ≤ 0.1%

Adjacent (≥±6 MHz

Interference

Wanted signal = -67 dBm

BER ≤ 0.1%

Adjacent (≥±25 MHz)

Interference

Wanted signal = -67 dBm,

BER ≤ 0.1%

Image frequency

Interference

Wanted signal = -67 dBm,

BER ≤ 0.1%

-20

dBc

C/I _Image

-2MHz

DocID027103 Rev 6

29/42

Electrical specification

BlueNRG-MS

Max. Unit

Symbol

Parameter

Test conditions

Min.

Typ.

Adjacent (±1 MHz)

Interference to in-band

image frequency

5

C/I

_Image±1MHz

Wanted signal = -67 dBm,

BER ≤ 0.1%

dBc

-25

-1MHz

-3MHz

Out of Band Blocking (Interfering signal CW)

Wanted signal = -67 dBm,

Interfering signal frequency

30 MHz – 2000 MHz

-30

-35

-30

dBm

C/I _Block

BER ≤ 0.1%, Measurement

resolution 10 MHz

-

Wanted signal = -67 dBm,

BER ≤ 0.1%, Measurement

resolution 3 MHz

Interfering signal frequency

2003 MHz – 2399 MHz

Wanted signal = -67 dBm,

BER ≤ 0.1%, measurement

resolution 3 MHz

Interfering signal frequency

2484 MHz – 2997 MHz

-

Wanted signal = -67 dBm,

BER ≤ 0.1%, measurement

resolution 25 MHz

Interfering signal frequency

3000 MHz – 12.75 GHz

Intermodulation characteristics (CW signal at f ₁, BLE interfering signal at f ₂)

Input power of IM interferes

Wanted signal = -64 dBm,

-33

dBm

P_IM(3)

P_IM(-3)

P_IM(4)

P_IM(5)

at 3 and 6 MHz distance

from wanted signal

BER ≤ 0.1%

Input power of IM interferes

at -3 and -6 MHz distance

from wanted signal

Wanted signal = -64 dBm,

BER ≤ 0.1%

-43

-33

-

Input power of IM interferes

at ±4 and ±8 MHz distance

from wanted signal

Wanted signal = -64 dBm,

BER ≤ 0.1%

Input power of IM interferes

at ±5 and ±10 MHz distance

from wanted signal

Wanted signal = -64 dBm,

BER ≤ 0.1%

10.5

High speed crystal oscillator (HSXOSC) characteristics

Characteristics measured over recommended operating conditions unless otherwise

specified. Typical value are referred to T _A= 25 °C, V _BAT= 3.0 V.

Table 13: High speed crystal oscillator characteristics

Symbol

Parameter

Nominal

Test conditions

Min. Typ. Max. Unit

f _NOM

16/32

MHz

ppm

frequency

Includes initial accuracy, stability over temperature,

aging and frequency pulling due to incorrect load

capacitance.

Frequency

tolerance

f _TOL

±50

Equivalent series

resistance

ESR

P _D

100

Ω

Drive level

µW

30/42

DocID027103 Rev 6

BlueNRG-MS

Electrical specification

10.5.1

High speed crystal oscillator (HSXOSC)

The BlueNRG-MS includes a fully integrated, low power 16/32 MHz Xtal oscillator with an

embedded amplitude regulation loop. In order to achieve low power operation and good

frequency stability of the Xtal oscillator, certain considerations with respect to the quartz

load capacitance C0 need to be taken into account. Figure 13 shows a simplified block

diagram of the amplitude regulated oscillator used on the BlueNRG-MS.

Figure 13: Simplified block diagram of the amplitude regulated oscillator

Low power consumption and fast startup time is achieved by choosing a quartz crystal with

a low load capacitance C0. To achieve good frequency stability, the following equation

needs to be satisfied:

ꢀ₁^′∗ ꢀ₂^′

ꢀ₀=

ꢀ₁^′+ ꢀ₂^′

Where C1’=C1+CPCB1+CPAD, C2’= C2+CPCB2+CPAD, where C1 and C2 are external

(SMD) components, CPCB1 and CPCB2 are PCB routing parasites and CPAD is the

equivalent small-signal pad-capacitance. The value of CPAD is around 0.5 pF for each

pad. The routing parasites should be minimized by placing quartz and C1/C2 capacitors

close to the chip, not only for an easier matching of the load capacitance C0, but also to

ensure robustness against noise injection. Connect each capacitor of the Xtal oscillator to

ground by a separate via.

DocID027103 Rev 6

31/42

Electrical specification

BlueNRG-MS

10.6

Low speed crystal oscillator (LSXOSC) characteristics

Characteristics measured over recommended operating conditions unless otherwise

specified. Typical value are referred to T _A= 25 °C, V _BAT=3.0 V.

Table 14: Low speed crystal oscillator characteristics

Symbol

Parameter

Test conditions

Min.

Typ.

Max. Unit

Nominal

frequency

f _NOM

32.768

kHz

Includes initial accuracy, stability over

temperature, aging and frequency

pulling due to incorrect load capacitance.

Frequency

tolerance

f _TOL

±50

ppm

Equivalent

series resistance

ESR

P _D

90

kΩ

Drive level

0.1

µW

These values are the correct ones for NX3215SA-32.768 kHz-EXS00A-MU00003.

10.7

High speed ring oscillator (HSROSC) characteristics

Characteristics measured over recommended operating conditions unless otherwise

specified. Typical value are referred to T _A= 25 °C, V _BAT=3.0 V, QFN32 package version.

Table 15: High speed ring oscillator characteristics

Symbol

Parameter

Test conditions

Min.

Typ.

12

Max.

16

Unit

MHz

f _NOM

Nominal frequency

10.8

Low speed ring oscillator (LSROSC) characteristics

Characteristics measured over recommended operating conditions unless otherwise

specified. Typical value are referred to T _A= 25 °C, V _BAT=3.0 V, QFN32 package version.

Table 16: Low speed ring oscillator characteristics

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

32 kHz ring oscillator (LSROSC)

f _NOM

f _TOL

Nominal frequency

Frequency tolerance

37.4

kHz

ppm

±500

10.9

N-fractional frequency synthesizer characteristics

Characteristics measured over recommended operating conditions unless otherwise

specified. Typical value are referred to T _A= 25 °C, V _BAT=3.0 V, f _c= 2440 MHz.

32/42

DocID027103 Rev 6

BlueNRG-MS

Symbol

Electrical specification

Table 17: N-fractional frequency synthesizer characteristics

Parameter

Test conditions

Min. Typ. Max.

Unit

dBc/Hz

µs

At ±1 MHz offset from carrier

At ±3 MHz offset from carrier

-113

-119

40

RF carrier phase

noise

PN _SYNTH

LOCK _TIME

TO _TIME

PLL lock time

PLL turn on / hop

time

Including calibration

150

µs

10.10

Auxiliary blocks characteristics

Characteristics measured over recommended operating conditions unless otherwise

specified. Typical value are referred to T _A= 25 °C, V _BAT=3.0 V, f _c= 2440 MHz. QFN32

package version.

Table 18: Auxiliary blocks characteristics

Symbol

Parameter

Test conditions

Min. Typ.

Max. Unit

Battery indicator and brown-out reset (BOR) ⁽¹⁾

V _BLT1

V _BLT2

V _BLT3

V _BLT4

A _BLT

Battery level thresholds 1

2.7

2.5

2.3

2.1

V

Battery level thresholds 2

Battery level thresholds 3

Battery level thresholds 4

Battery level thresholds accuracy

Ascending brown-out threshold

Descending brown-out threshold

5

%

V

V _ABOR

V _DBOR

1.79

1.73

V

Notes:

⁽¹⁾BOR is disabled by default and it can be enabled by software.

10.11

SPI characteristics

Table 19: SPI characteristics

Symbol

Parameter

Min

Typ

Max

Unit

f _CLK

SPI clock frequency

8

MHz

%

1/t _(CLK)

DuCy _(CLK)

t _s(CS)

SPI clock duty cycle

CS setup time

50

40

t _lh(CS)

t _hh(CS)

t _s(SI)

CS low hold time

CS high hold time

MOSI setup time

MOSI hold time

MISO valid time

10t _(CLK)

20

ns

t _h(SI)

10

t _v(SO)

40

DocID027103 Rev 6

33/42

Electrical specification

BlueNRG-MS

The values for the parameters given in this table are based on characterization, not tested

in production.

Figure 14: SPI timings

34/42

DocID027103 Rev 6

BlueNRG-MS

Package information

11

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK^®packages, depending on their level of environmental compliance. ECOPACK^®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK^®is an ST trademark.

DocID027103 Rev 6

35/42

Package information

BlueNRG-MS

11.1

QFN32 package information

Figure 15: QFN32 (5 x 5 x 1 pitch 0.5 mm) package outline

36/42

DocID027103 Rev 6

BlueNRG-MS

Package information

Table 20: QFN32 (5 x 5 x 1 pitch 0.5 mm) mechanical data

mm

Dim.

Min.

0.80

0

Typ.

0.85

Max.

1.00

0.05

A

A1

A3

b

0.02

0.20 REF

0.25

0.30

D

5.00 BSC

E

D2

E2

e

3.2

3.70

0.5 BSC

0.40

L

0.30

0°

0.50

14°

Ф

K

0.20

Figure 16: QFN32 (5 x 5 x 1 pitch 0.5 mm) package detail "A"

DocID027103 Rev 6

37/42

Package information

BlueNRG-MS

11.2

WLCSP34 package information

Figure 17: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline

See Note 1

WLCSP34_POA_8165249

1. The corner of terminal A1 must be identified on the top surface by using a laser

marking dot.

38/42

DocID027103 Rev 6

BlueNRG-MS

Package information

Table 21: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data

mm.

Typ.

Dim.

Notes

Min.

Max.

A

A1

b

0.50

0.20

0.27

2.56

2.00

2.66

2.00

0.40

0.28

0.33

(1)

(2)

D

2.50

2.60

2.58

2.68

D1

E

(3)

E1

e

f

g

ccc

0.05

Notes:

⁽¹⁾The typical ball diameter before mounting is 0.25 mm.

⁽²⁾D = f + D1 + f.

⁽³⁾E = g + E1 + g.

DocID027103 Rev 6

39/42

PCB assembly guidelines

BlueNRG-MS

12

PCB assembly guidelines

For Flip Chip mounting on the PCB, STMicroelectronics recommends the use of a solder

stencil aperture of 330 x 330 µm maximum and a typical stencil thickness of 125 µm.

Flip Chips are fully compatible with the use of near eutectic 95.8% Sn, 3.5% Ag, 0.7% Cu

solder paste with no-clean flux. ST's recommendations for Flip Chip board mounting are

illustrated on the soldering reflow profile shown in Figure 17.

Figure 18: Flip Chip CSP (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile

recommendation

Table 22: Flip Chip CSP (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile

recommendation

Value

Profile

Typ.

0.9 °C/s

2 °C/s

Max.

3 °C/s

260 °C

90 s

Temp. gradient in preheat (T = 70 – 180 °C)

Temp. gradient (T = 200 – 225 °C)

Peak temp. in reflow

240 - 245 °C

60 s

Time above 220 °C

Temp. gradient in cooling

Time from 50 to 220 °C

-2 to - 3 °C/s

-6 °C/s

160 to 220 s

Dwell time in the soldering zone (with temperature higher than 220 °C) has to be kept as

short as possible to prevent component and substrate damage. Peak temperature must not

exceed 260 °C. Controlled atmosphere (N ₂or N ₂H ₂) is recommended during the whole

reflow, especially above 150 °C.

Flip Chips are able to withstand three times the previous recommended reflow profile to be

compatible with a double reflow when SMDs are mounted on both sides of the PCB plus

one additional repair.

A maximum of three soldering reflows are allowed for these lead-free packages (with repair

step included).

The use of a no-clean paste is highly recommended to avoid any cleaning operation. To

prevent any bump cracks, ultrasonic cleaning methods are not recommended.

40/42

DocID027103 Rev 6

BlueNRG-MS

Revision history

13

Revision history

Table 23: Document revision history

Changes

Date

Revision

24-Nov-2014

1

Initial release.

Document status promoted from “Preliminary data” to “Production

data”.

Minor changes in the structure of the document to improve

readability. Updated: Figure in cover page, Section 2: General

description, Figure 5, Figure 6, Figure 7, Figure 8, Section 10:

Electrical specification. Added: Figure 15: QFN32 (5 x 5 x 1 pitch 0.5

mm) package detail "A".

19-Jun-2015

2

01-Oct-2015

29-Oct-2015

3

4

Modified: Figure 5, Figure 6, Figure 7 and Figure 8

Updated: General description.

Added: SPI characteristics.

Updated title, Features , Section 1: "Description" and Section 2:

"General description".

16-Nov-2015

01-Feb-2016

5

6

Updated Section 8: "Application controller interface"

DocID027103 Rev 6

41/42

BlueNRG-MS

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST

products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order

acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the

design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

42/42

DocID027103 Rev 6

型号:	BLUENRG-MSCSP
Brand Name：	STMicroelectronics
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	STMICROELECTRONICS
包装说明：	VFLGA,
Reach Compliance Code：	compliant
ECCN代码：	5A992.C
HTS代码：	8542.39.00.01
Factory Lead Time：	16 weeks
风险等级：	1.59
Samacsys Confidence：	4
Samacsys Status：	Released
Samacsys PartID：	253745
Samacsys Pin Count：	34
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	BGA
Samacsys Footprint Name：	WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm)
Samacsys Released Date：	2018-03-14 17:31:37
Is Samacsys：	N
JESD-30 代码：	R-PBGA-B34
长度：	2.66 mm
功能数量：	1
端子数量：	34
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	VFLGA
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	0.5 mm
标称供电电压：	3 V
表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL
端子形式：	BUTT
端子节距：	0.4 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	2.56 mm
Base Number Matches：	1

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