BQ24721CRHBR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

bq24721, bq24721C

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

ADVANCED MULTI-CHEMISTRY AND MULTI-CELL SYNCHRONOUS SWITCH-MODE

CHARGER AND SYSTEM POWER SELECTOR

FEATURES

APPLICATIONS

•

Portable Notebook Computers

Portable DVD Players

Webpads, PC Tablets

•

High Efficiency NMOS-NMOS Synchronous

Buck Converter With User-Selectable 300 kHz

or 500 kHz frequency

•

bq24721C Offers Softer Turn-On, Stronger

Turn-Off

SBS-Like ⁽¹⁾SMBus Interface for Control and

Status Communications With Host

DESCRIPTION

The bq24721 is a high efficiency synchronous

battery pack charger with high level of integration for

portable applications. This device implements a high

performance analog front-end that interfaces to the

system power management micro-controller through

a simplified SBS-like SMBus interface.

Programmable Battery Voltage, Charge

Current, and AC Adapter Current via SBS-Like

SMBus Interface

•

0.4% Charge Voltage Regulation Accuracy

3% Charge Current Regulation Accuracy

The dynamic power management (DPM) function

modifies the charge current depending on system

load conditions, avoiding ac adapter overload.

3% Adapter Current Regulation Accuracy

Dynamic Power Management (DPM)

High accuracy current sense amplifiers enable

accurate measurement of either the charge current

or the ac adapter current, allowing termination of

nonsmart packs and monitoring of overall system

power.

•

2% Accuracy Integrated Charge and AC

Adapter 20× Current Amplifier Output

3-Cell and 4-Cell Li-Ion Voltage Regulation

9 V, 12 V–14.4 V, 16 V–19.2 V

Battery Pack Voltage Operating Range

0 V–19.2 V

The adapter isolation diode can be bypassed or

entirely replaced with an external MOSFET using a

control signal provided by the bq24721, thus

reducing overall power dissipation.

•

AC Adapter Operating Range 8 V–28 V

99.5% Max Duty Cycle

Integrated features such as charger soft start, charge

overcurrent protection, and IC temperature

monitoring provide a second level of protection, in

addition to pack and system protection functions.

Internal Soft Start

Integrated 5% 5-V LDO When AC Adapter

Applied

•

6-V Drive Supply Voltage for Increased

Efficiency

5x5 QFN PACKAGE (TOP VIEW)

Reverse Battery to Adapter Discharge

Protection

1

2

24

23

22

21

20

19

CHGEN

BATDRV

SYS

Battery/Adapter to System Power Selector

Function

ACDRV

ACN

3

4

5

6

7

8

SYNP

SYNN

SRP

•

Charge and Adapter Overcurrent Protection

Battery Thermistor Sense, TS, Comparators

Available in 32-Pin 5x5-mm QFN Package

ACP

bq24721,

bq24721C

ACDET

SRN

BYPASS

EAO

18 BAT

17

EAI

IOUT

(1) SBS-Like interface is not 100% SBS compliant. SBS-Like

interface is SMBus1.1 complaint but does not support Packet

Error Correction (PEC). The control and status registers were

changed to simplify and enhance notebook charger control.

An 8-bit address (0x12) is used. See Table 1 for a

comparison between SBS-like vs SBS Specification.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24721, bq24721C

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

BATTERY SHORTED

(VERY LOW BATTERY

VOLTAGE) OPERATION

THERMISTOR

SENSE

ORDERING NUMBER

(TAPE AND REEL)

PART NO.

PACKAGE

QUANTITY

bq24721RHBR

bq24721RHBT

bq24721CRHBR

bq24721CRHBT

3000

250

32 PIN

5x5mm QFN

Charge Current Changes to

C/8

bq24721

TS

3000

250

32 PIN

5x5mm QFN

Charge Current Changes to

C/8

bq24721C

PACKAGE THERMAL DATA

TA ≤ 40°C

POWER RATING

DERATING FACTOR

ABOVE T_A= 25°C

PACKAGE⁽¹⁾

RHB⁽²⁾

θ_JA

36°C/W

2.36 W

0.028 W/°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is

connected to the ground plane by a 2×3 via matrix.

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NO.

NAME

Charge enable logic level low input. Logic HI on the CHGEN pin disables the charger. Logic LO on the

CHGEN pin enables the charger. When the SMBus control register = bit0, CHGEN is also LO.

1

CHGEN

AC adapter to system switch driver output. Connect directly to the gate of the ACFET PMOS power

FET. Connect the FET source to the PVCC node and negative side of the input current-sense resistor.

Connect the FET drain to the system load side. Recommend placing a 10-kΩ resistor from the gate to

the source of the Bypass FET. If needed, an optional capacitor from gate to source of the ACFET is

used to help slow down the ON and OFF times. The internal gate drive is asymmetrical allowing a

quick turn-off and slower turn-off in addition to the internal break-before-make logic with respect to the

BATDRV.

2

ACDRV

Adapter current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from this

pin to AGND for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN to

ACP to provide differential-mode filtering.

3

4

ACN

ACP

Adapter current sense resistor, positive input. Place this on the adapter side of the input current sense

resistor. Recommend placing a 0.1-µF ceramic capacitor from ACP to AGND to provide

common-mode filtering.

AC adapter detected sense voltage input. Connect a voltage divider resistor from adapter input (before

Bypass FET) to ACDET, and another resistor from ACDET to AGND, in order to program adapter

detect threshold of 1.2 V. ACDET threshold should be greater than maximum battery regulation

voltage, and lower than the minimum adapter voltage.

5

ACDET

Gate drive for the adapter input BYPASS switch to prevent reverse discharge from the battery to the

input. Connect this pin directly to the gate of the input bypass PMOS power FET. The source of the

FET is connected to the adapter input voltage node. Recommend placing a 10-kΩ resistor from the

gate to the source of the BYPASS FET. The drain of the FET is connected to the positive node of the

input current-sense resistor. An optional capacitor can be placed from the gate to the source to

slow-down the switching times. Adjusting the turn-on and turn-off times is typically not needed for this

FET.

6

7

BYPASS

EAO

Error amplifier output for compensation. Connect the feedback compensation components from EAO

to EAI. Typically a capacitor in parallel with a series resistor and capacitor. See the compensation

calculation procedures. This node is internally compared to the PWM saw-tooth oscillator.

2

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

DESCRIPTION

NO.

NAME

Error amplifier input for compensation, also connect the feedback compensation components from EAI

to EAO. Connect the input compensation components from FBO to EAI. See the compensation

calculation procedures.

8

EAI

Feedback output for compensation. Connect the input compensation components from FBO to EAI.

Typically, a resistor in parallel with a series resistor and capacitor. See the compensation calculation

procedures.

9

FBO

Analog ground. Ground connection for low current sensitive analog and digital signals. Only connect to

the PGND node by connecting to the PowerPAD™ underneath the IC.

10

11

AGND

VREF5

5-V regulated voltage output, used for internal bias and the reference for programming the TS

thermistor sense network. Used to indicate adapter present status. It is enabled by ac detected.

Connect a 1-µF ceramic capacitor from VREF5 pin to AGND as close to IC as possible.

IC analog positive supply. Connect to adapter input, or diode, or by putting a diode from adapter input

and a diode from battery pack to VCC. Put a 1-µF ceramic capacitor from VCC to AGND, as close to

the IC as possible.

12

VCC

SMBus Data input. Connect to SMBus data line from the host controller. A 10-kΩ pullup resistor to the

host controller supply rail is needed.

13

14

SDA

SCL

SMBus Clock input. Connect to SMBus clock line from the host controller. A 10-kΩ pullup resistor to

the host controller supply rail is needed.

Thermistor sense input. Use a voltage divider from VREF5 to TS and AGND. Place a resistor from

VREF to TS, and a resistor from TS to AGND to program the hot and cold battery pack thermistor

temperatures. Charge is disabled when outside the hot/cold window. The TS pin is also used to detect

if a battery is connected.

15

16

TS

Program current threshold for synchronous to nonsynchronous regulation transition. Place a resistor

from ISYNSET to AGND to program the charge undercurrent threshold to force nonsynchronous

converter operation at low output current and prevent negative inductor current. Threshold should be

set from ½ inductor current ripple to full value of inductor current ripple.

ISYNSET

Battery charger or adapter current amplifier output. Current sense amplifier that outputs a voltage 20x

the current sense resistor differential voltage. The output can be selected by SMBus charge control

register (0x12) bit3 to be the input adapter current (ACP-ACN), or the battery charge current

(SRP-SRN). Place a 0.1-µF capacitor from IOUT to AGND for filtering the output ripple. Optionally, add

an RC filter after the output filter for further filtering.

17

IOUT

Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive

terminal to the BAT pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from

BAT to AGND close to the IC to filter high frequency noise.

18

19

BAT

SRN

Charge current sense resistor, negative input. Connect to the charge current sense resistor negative

terminal. Optionally, add a 0.1-µF ceramic capacitor from SRN to AGND near the IC for

common-mode filter.

Charge current sense resistor, positive input. Connect to the charge current sense resistor positive

terminal. Recommend placing a 0.1-µF ceramic capacitor from SRP to AGND near the IC for

common-mode filter. Optionally, place a 0.1-µF ceramic capacitor from SRP to SRN near the IC for

differential-mode filter.

20

21

SRP

Charge overcurrent and charge undercurrent negative sense input. Connect to the charge current

sense resistor negative terminal. If sensing the same sense resistor as SRN, the user can connect

directly to the SRN pin and no further filter capacitors are needed. To sense a different sense resistor,

add a 0.1-µF ceramic capacitor from SYNN to AGND near the IC for common-mode filter.

SYNN

Charge overcurrent and charge undercurrent negative sense input. Connect to the charge current

sense resistor positive terminal. If sensing the same sense resistor as SRP, the user can connect

directly to the SRP pin, and no further filter capacitors are needed. To sense a different sense resistor,

add a 0.1-µF ceramic capacitor from SYNP to AGND near the IC for common-mode filter, and place a

0.1-µF ceramic capacitor from SYNP to SYNN near the IC for differential-mode filter.

22

23

SYNP

SYS

System load, voltage sense. Connect directly to the system load node and the drain of the BAT PMOS

power FET.

3

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME

DESCRIPTION

NO.

Battery to system switch driver output. Gate drive for the battery to system load BAT PMOS power

FET to isolate the system from the battery to prevent current flow from the system to the battery, while

allowing a low impedance path from battery to system while discharging the battery pack to the system

load. Connect this pin directly to the gate of the input BAT PMOS power FET. Connect the source of

the FET to the system load voltage node. Connect the drain of the FET to the battery pack positive

node. Recommend placing a 10-kΩ resistor from the gate to the source of the BAT FET. An optional

capacitor is placed from the gate to the source to slow-down the switching times. The internal gate

drive is asymmetrical allowing a quick turn-off and slower turn-off in addition to the internal

break-before-make logic with respect to the ACDRV.

24

BATDRV

ALARM

Alarm indicating charger status change, open-drain output. The ALARM is pulled low (LO) whenever

the SMBus status register (0x13) has a change. The ALARM output is cleared (HI) when the SMBus

status (0x13) register is read, or there is a reset. This is used to alert the host and initiate an interrupt

with the host instead of having to continuously poll the charger. A 10-kΩ pull-up resistor to the host

controller supply rail is needed.

25

Power ground. Ground connection for the high-current power converter nodes. Only connect to the

AGND node by connecting to the PowerPAD™ underneath the IC.

26

27

PGND

PWM low side driver output. Connect directly to the gate of the low-side NMOS power FET with a

short trace.

LODRV

Low-side driver gate voltage regulator and source for high-side driver bootstrap voltage. Add a 1-µF

ceramic capacitor from REGN pin to PGND pin, close to the IC. Place a small signal Schottky diode

from REGN to BTST for bootstrap voltage.

28

REGN

High-side driver negative supply. Connect directly to the source of the high-side NMOS FET with a

short trace. This node is the common connection between the high-side FET, low-side FET, and

output inductor. Connect a 0.1-µF boot-strap ceramic capacitor from BTST to PH.

29

30

PH

PWM high side driver output. Connect directly to the gate of the high-side NMOS power FET with a

short trace.

HIDRV

High-side driver positive supply, connect pos-side of boot-strap capacitor. Connect a 0.1-µF bootstrap

capacitor from the BTST pin to the PH node. Also, connect a bootstrap diode with the anode

connected to the REGN pin and the cathode connected to the BTST pin. An optional 4.7-Ω - 15-Ω

series resistor is placed between the BTST pin and the bootstrap-diode/capacitor junction to

slow-down the turn-on time of the high-side FET for reducing ringing due to high dv/dt of the phase

node.

31

32

BTST

PVCC

IC power positive supply. Connect directly to the drain of the high-side NMOS power FET.

Recommend placing at least a 10-µF ceramic capacitor directly from the drain of the high-side NMOS

power FET to PGND. Up to 40 µF may be needed to prevent resonance filtering inductance. Also, a

0.1-µF decoupling ceramic capacitor is recommended.

4

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER

VALUE / UNIT

ACN, ACP, PVCC, ACDRV, SYNN, SYNP, SRP, SRN,

BATDRV, BAT, BYPASS, SYS, VCC

–0.3 V to 30 V

–1 V to 30 V

–0.3 V to 7 V

PH

Supply voltage range

LODRV, REGN, FBO, EAI, EAO, ISYNSET, CHGEN, TS ,

VREF5, ACDET, IOUT, ALARM, SCL, SDA

BTST, HIDRV (with respect to AGND and PGND)

AGND-PGND

–1 V to 36 V

–0.3 V to 0.3 V

0.6 V

Maximum differential voltage

Maximum difference voltage

ACP–ACN , SRP–SRN, and SYNP–SYNN

Operating ambient temperature range (T_A)

–40°C to 85°C

150°C

Maximum junction temperature (T_{J_MAX}

Storage temperature range (T_stg

)

–65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to AGND, unless otherwise noted. Currents are positive into, negative out of the specified terminal. Consult

Packaging Section of the Databook for thermal limitations and considerations of packages.

RECOMMENDED OPERATING CONDITIONS

PARAMETER

MIN

NOM

MAX

UNIT

ACN, ACP, PVCC, ACDRV, SRP, SRN,

BATDRV, BAT, BYPASS, SYS, VCC, SYNN,

SYNP

0

24

V

PH

–0.5

0

30

V

LODRV, REGN, VREF5

6.5

Supply voltage range

FBO, EAI, EAO, ISYNSET, CHGEN, TS ,

ACDET, SCL, SDA, ALARM

0

5.5

V

IOUT, ACDET

0

5.5

30

V

BTST, HIDRV

Maximum differential voltage

Maximum difference voltage

Junction temperature Range (T_J)

Storage temperature Range (T_stg

AGND-PGND

0

V

ACP–ACN, SYNN–SYNP, SRP–SRN

0.5

125

150

V

0

°C

)

-55

5

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

ELECTRICAL CHARACTERISTICS

8 Vdc ≤ V_(VCC)≤ 24 Vdc, 0°C ≤ T_J≤ 125°C, all voltages with respect to AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BATTERY VOLTAGE REGULATION

V_{(BAT_ICR)}

VBAT Input voltage range

V_(BAT)

0

–0.4

–0.5

9

PVCC

0.4

V

%

V

T_J= 0°C – 85°C

T_J= 0°C – 125°C

Full valid voltage DAC range,

SMBus DAC register 0×15

Battery Regulation Voltage Accuracy

BAT voltage regulation range

0.5

V_(VBATREG)

19.2

PWM AC ADAPTER INPUT CURRENT REGULATION, DPM (Dynamic Power Management), I_{(REG_DPM)}= V_{(IREG_DPM)}/R_{(SENSE_DPM)}

ACP-ACN differential voltage range

for input current regulation

V_{(IREG_DPM)}= V_(ACP)- V_(ACN)

SMBus DAC register 0×3F, bits b0–b13

V_{(IREG_DPM)}

1.28

162.56

mV

mA

Current regulation LSB programming V_(ACP-ACN)/ 10mΩ

current step

I_{(REG_step_DPM)}

128

Using a 10mΩ sense resistor, R_(SNS)

V_(ACP)– V_(ACN)> 40.96 mV

(4096 mA with 10 mΩ)

–3%

–5%

3%

5%

V

_CC≥ V_CC(min),

(1)

V_CC≥ V_I(BAT)+ V_(DO-MAX)

,

V_(ACP)– V_(ACN)> 20.48 mV

(2048 mA with 10 mΩ)

Current regulation accuracy

Over differential threshold range, V_(IREG)

Does not include error induced by the

tolerance of the sense resistor, R_(SNS)

,

V_(ACP)– V_(ACN)> 5.12 mV

(512 mA with 10 mΩ)

–25%

25%

PWM BATTERY CHARGE CURRENT REGULATION, I_{(REG_CHG)}= V_{(IREG_CHG)}/ R_{(SENSE_CHG)}

SRP-SRN differential voltage range

for input current regulation

V_{(IREG_CHG)}= V_(SRP)- V_(SRN)

SMBus DAC register 0×14, bits b0–b13

V_{(IREG_CHG)}

1.28

162.56

mV

mA

Current regulation LSB programming V_(SRP-SRN)/ 10 mΩ

current step

I_{(REG_step_CHG)}

128

Using a 10mΩ sense resistor, R_(SNS)

V_(SRP-SRN)> 40.96 mV

(4096 mA with 10 mΩ)

–3

–5

3

5

V

_CC≥ V_CC(min),

(1)

V_CC≥ V_I(BAT)+ V_(DO-MAX)

,

V_(SRP-SRN)>20.48 mV

(2048 mA with 10 mΩ)

Current regulation accuracy

Over differential threshold range, V_(IREG)

Does not include error induced by the

tolerance of the sense resistor, R_(SNS)

,

%

V_(SRP-SRN)> 5.12 mV

(512 mA with 10 mΩ)

–25

25

CURRENT SENSE AMPLIFIERS – IBAT AMPLIFIER and IADAPT AMPLIFIER → MUX TO IOUT

SRP, SRN common-mode input

voltage range

2.5

0

20

V

V_{(IOUT_IBAT)}

IOUT output voltage range with IBAT V_(IOUT)= V_{(SRP, SRN)}× A_(IBAT)

selected

3.5

V

(1)

V_(BAT)> 2.5 V or V_(BAT)> V_(IOUT)+ V_(DO-MAX)

G_(IBAT)

Voltage gain

A_(IOUT)= V_(IOUT)/ V_(SRP,

20

V/V

SRN)

V_{(SRP, SRN)}= 40 mV and higher

V_{(SRP, SRN)}= 20 mV and higher

V_{(SRP, SRN)}= 5 mV and higher

–2

–3

2

3

V_(BAT)> 2.5 V or V_(BAT)

V_(IOUT)+ V_(DO-MAX)

>

(1)

Charge current amplifier accuracy

%

V

–25

25

ACP, ACN Common-mode input

voltage range

0

24

V_{(IOUT_IADAPT)}

IOUT output voltage range with

IADAPT selected

V_(IOUT)= V_{(ACP, ACN)}× A_(IADP)

V_(SRP)> 2.5 V or V_(SRP)> V_(IOUT)+ 1 V

3.5

V

G_(IADP)

Voltage gain

A_(IADP)= V_(IOUT)/ V_(ACP,

20

V/V

ACN)

V_{(ACP, ACN)}= 40 mV and higher

V_{(ACP, ACN)}= 30 mV and higher

V_{(ACP, ACN)}= 5 mV and higher

V_{(ACP, ACN)}= 40 mV and higher

V_{(ACP, ACN)}= 30 mV and higher

V_{(ACP, ACN)}= 5 mV and higher

–2

–3

2

3

Adapter current amplifier accuracy,

bq24721

V_(BAT)> 2.5 V or V_(BAT)

V_(IOUT)+ V_(DO-MAX)

>

%

(1)

–25

–2

25

2

Adapter current amplifier accuracy,

bq24721C

V_(BAT)> 2.5 V or V_(BAT)

–5

5

%

(1)

V_(IOUT)+ V_(DO-MAX)

–25

4.5

25

I_{(OUT_LIM)}

IOUT output current limit

IOUT shorted to AGND

mA

OPERATING CONDITIONS

V_(VCC), V_(PVCC), input voltage

V_(INOP)

Selector and charger operational.

8

24

V

operating range

(1) V_(DO-max)is defined as the maximum drop-out voltage. V_(DO-MAX)= 1 V unless other wise specified. In an actual application, V_{(DO - MAX)}

= (R_(SNS)× I_O) + V_{(DSON_HIGH_SIDE_FET)}+ V_{(DSON_BYPASS_FET)}

.

6

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)

8 Vdc ≤ V_(VCC)≤ 24 Vdc, 0°C ≤ T_J≤ 125°C, all voltages with respect to AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

QUIESCENT CURRENT – NO ADAPTER CONNECTED

I_(VCC,PVCC)

I_(ACP,ACN)

I_(BAT)

VCC and PVCC quiescent current

ACP and ACN quiescent current

BAT quiescent current

I_(VCC,PVCC)= ( I_(VCC)+ I_(PVCC)) at V_(VCC)= V_(PVCC)= 16.8 V

I_(ACP,ACN)= ( I_(ACP)+ I_(ACN)) at V_(ACP)= V_(ACN)= V_(VCC)= V_(PVCC)= 16.8 V

I_(BAT)at V_(BAT)= V_(VCC)= V_(PVCC)= 16.8 V

254

1

µA

17

1

I_(SRP,SRN)

I_(SYNN,SYNP)

I_(SYS)

SRP and SRN quiescent current

SYNN and SYNP quiescent current

SYS quiescent current

I_(SRP,SRN)= ( I_(SRP)+ I_(SRN)) at V_(SRP)= V_(SRN)= V_(VCC)= V_(PVCC)= 16.8 V

I_(SYNN,SYNP)= ( I_(SYNN)+ I_(SYNP)) at V_(SYNP)= V_(SYNN)= V_(VCC)= V_(PVCC)= 16.8 V

I_(SYS)at V_(SYS)= V_(VCC)= V_(PVCC)= 16.8 V

1

25

1

I_(PH)

PH quiescent current

I_(PH)at V_(PH)= V_(VCC)= V_(PVCC)= 16.8 V

I_(BTST)

BTST quiescent current

I_(BTST)at V_(BTST)= V_(VCC)= V_(PVCC)= 16.8 V

1

QUIESCENT CURRENT – ADAPTER CONNECTED AND READY TO CHARGE

I_(VCC,PVCC)

I_(ACP,ACN)

I_(BAT)

VCC and PVCC quiescent current

ACP and ACN quiescent current

BAT quiescent current

I_(VCC,PVCC)= (I_(VCC)+ I_(PVCC)at V_(VCC)= V_(PVCC)= 16.8 V

I_(ACP,ACN)= (I_(ACP)+ I_(ACN)) at V_(ACP)= V_(ACN)= V_(VCC)= V_(PVCC)= 16.8 V

I_(BAT)at V_(BAT)= V_(VCC)= V_(PVCC)= 16.8 V

4.45

815

500

305

mA

µA

I_(SRP,SRN)

SRP and SRN quiescent current

I_(SRP,SRN)= ( I_(SRP)+ I_(SRN)) at V_(SRP)= V_(SRN)= V_(VCC)= V_(PVCC)= 16.8 V

SYNN, SYNP, and SYS quiescent

current

I_{(SYNN,SYNP,SYS)}= ( I_(SYNN)+ I_(SYNP)+ I_(SYS)) at V_(SYNP)= V_(SYNN)= V_(SYS)= V_(VCC)

V_(PVCC)= 16.8 V

=

I_{(SYNN,SYNP,SYS)}

321

µA

I_(PH)

PH quiescent current

I_(PH)at V_(PH)= V_(VCC)= V_(PVCC)= 16.8 V

I_(BTST)at V_(BTST)= V_(VCC)= V_(PVCC)= 16.8 V

1

µA

I_(BTST)

BTST quiescent current

I_{(VCC_SW)}= I_(VCC)

FPWM = 300 kHz, charger on (CHGEN = LO) = ENABLED

Q_(G)at HIDRV = Q_(G)at LODRV = 30 nC, [No Load on VREF5]

Gate drive switching current = Q_(G)× FPWM = (30nC + 30nC) × 300kHz =

18mA

VCC Current while converter is

switching including gate drive current

I_{(VCC_SW)}

25

mA

V

5-V REFERENCE LDO VOLTAGE AND AC DETECTION STATUS (VREF5, TURNS ON WHEN AC DETECTED)

Adapter detected (V_ACDET>V_(ACD)), V_CC> 7 V

0 → 10 mA, source current

V_(VREF5)

5V Regulator output voltage

4.75

5

5.25

0.3

Saturation voltage when VREF5 is

off

Adapter not detected, (V_ACDET< V_(ACD))

0 →– 10 mA, ac adapter inserted, C_O= 1 µF, discharge Load

V_{(VREF5_SAT)}

I_{(VREF5_LIM)}

V

Short-circuit current

V_(VREF5)= AGND

20

mA

UNDERVOLTAGE LOCKOUT CIRCUIT

Undervoltage lockout threshold

VREF5 rising, POR mode set at VREF5 < V_(UVLO)

VREF5 falling

3.7

V

UVLO

V_(UVLO)hysteresis

100

mV

SBS-Like SMBus LOGIC LEVELS

V_IL

Input low threshold level

Input high threshold level

Input bias current

2.7 V < V_(pull-up)< 5.5 V, SDA and SCL

0.8

1

V

V_IH

2.1

I_(bias)

µA

ALARM OPEN DRAIN OUTPUT

V_{(ALARM_sat)}ALARM output low saturation level

I_lkg(ALARM)ALARM leakage current

I_(ALARM)= 5mA

V_(ALARM)= 5V

0.5

1

V

µA

THERMAL SHUTDOWN, IC OVERTEMPERATURE PROTECTION

T_(SHUT)

Thermal shutdown Threshold

Hysteresis

T_Jrising, Charge disabled at T_J> T_(SHUT)

T_Jfalling, Charge enabled at T_J< T_(SHUT)– T_(SHUTH)

T_Jrising/falling

145

15

8

°C

ms

T_(SHUTH)

Deglitch time, thermal shutdown

7

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)

8 Vdc ≤ V_(VCC)≤ 24 Vdc, 0°C ≤ T_J≤ 125°C, all voltages with respect to AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

THERMISTOR COMPARATORS, TS

Cold temperature threshold, TS pin

voltage

V_(LTF)

V_(TS)rising

V_(TS)falling

V_(TS)rising

72.8

0.5

73.5

1

74.2 %VREF5

1.5 %VREF5

29.9 %VREF5

V_(LTFH)

V_(TCO)

Hysteresis for LTF threshold

Cutoff temperature threshold, TS pin

voltage

28.7

29.3

Hot temperature threshold, TS pin

voltage

V_(HTF)

V_(TS)rising/falling

V_T(S)rising/falling

33.7

34.4

85

35.1 %VREF5

87.55 %VREF5

µs

V_(TSDET)

Pack thermistor insertion detected

82.45

Deglitch time for temperature out of

range detection

V_(TS)rising above V_(LTF), or V_(TS)falling below V_(TCO), or V_(TS)falling below V_(HTF)

16

Deglitch time for temperature in valid V_(TS)falling below (V_(LTF)- V_(LTFH)), or V_(TS)rising above V_(TCO), or V_(TS)rising

8

16

1

ms

µs

s

range detection

above V_(HTF)

Deglitch time for thermistor removal

detection

V_(TS)rising above V_(TSDET)

V_(TS)> V_(TSDET)(pack removed)

Deglitch time for thermistor insertion

detection

V_(TS)falling below V_(TSDET)

V_(TS)< V_(TSDET)(pack inserted)

CHARGE OVERCURRENT COMPARATOR

V_(OLP)

Overcurrent protection threshold

Hysteresis

V_(SYNP-SYNN)rising

200

20

1

%I_{(REG_CHG)}

µs

V_(OLPH)

V_(SYNP-SYNN)falling

Deglitch time

V_(SYNP-SYNN)rising and falling

SYNCHRONOUS to NONSYNCHRONOUS CURRENT COMPARATOR (ISYNSET)

V_(SYNSET)

K_(SYNSET)

V_{(SYN_HYS)}

ISYNSET pin set voltage

ISYNSET current set factor

1

V

V_(SYNP-SYNN)falling,

I_{SYN_NSYN}= (V_(SYNSET)× K_(SYNSET))/(R_(SYNSET)× R_{(SENSE_CHG)}

500

V/A

)

V_(SYNP-SYNN)hysteresis voltage, rising V_(SYNP-SYNN)rising

Deglitch time, Synch to Non-Synch V_(SYNP-SYNN)rising and falling

1.5

1

mV

µs

ADAPTER OVERCURRENT COMPARATOR (ACOC)

V

_(ACP-ACN)≥ V_(ACOC), where SMBus charge mode register (0×12),

% of

155

110

130

150

170

130

150

170

b6 = 1 = ACOC_protection_enabled, b8 = 0, b7 = 0

I_{(REG_DPM)}

V_(ACP-ACN)≥ V_(ACOC), where SMBus charge mode register (0×12),

% of

175

b6 = 1 = ACOC_protection_enabled, b8 = 0, b7 = 1

I_{(REG_DPM)}

ACOC Input over-current protection

V_(ACOC)

sense resistor voltage threshold

V_(ACP-ACN)≥ V_(ACOC), where SMBus charge mode register (0×12),

% of

195

b6 = 1 = ACOC_protection_enabled, b8 = 1, b7 = 0

I_{(REG_DPM)}

V_(ACP-ACN)≥ V_(ACOC), where SMBus charge mode register (0×12),

% of

215

190

7

b6 1 = ACOC_protection_enabled, b8 = 1, b7 = 1

I_{(REG_DPM)}

V_(ACOCH)

ACOC Hysteresis

V_(SRP-SRN)falling

%I_{(REG_CHG)}

ACOC deglitch time before ACDRV

turns-off

V_(ACP-ACN)rising

16

µs

ACOC delay time after

V_(ACP-ACN)≤V_(ACOC)before ACDRV

V_(ACP-ACN)falling, V_(ACP-ACN)≤V_(ACOC)

8

ms

turn-on

SYSTEM STATUS COMPARATORS INPUT SPECIFICATIONS

Common mode input range at pin:

ACDET

0

0.5

0

5

VREF5

VCC

V

V_ICR

Common mode input range at TS pin

Common mode input voltage range

at pins: BAT, SYS

Input bias currents at pins: ACDET,

TS, BATDEP, SYS

I_(bias)

0.2

µA

BATTERY DEPLETED COMPARATOR (BATDEP)

V_(BATDEP)= 2.2 V + V_(step)× batdep_dac_code, where batdep_dac_code = 0 - 7,

and Vstep = 0.1V, SMBus Charge Mode register 0×12, bits b9, b10, b11

For programmed V_(BATREG)= 9 V, then cell = 2

For programmed V_(BATREG)= 12 V - 14.4 V, then cell = 3

For programmed V_(BATREG)= 16 V - 19.2 V, then cell = 4

V_(BATDEP)

BAT depleted voltage range

2.2

2.9

2%

V/cell

BAT depleted accuracy

-2%

Battery depleted detection deglitch

time

V_(BAT)falling

V_(BAT)rising

1

s

Battery not depleted detection

deglitch time

8

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)

8 Vdc ≤ V_(VCC)≤ 24 Vdc, 0°C ≤ T_J≤ 125°C, all voltages with respect to AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AC ADAPTER DETECT COMPARATOR (ACDET)

V_(ACDET)rising, When adapter detected, VREF5 is enabled, and REGN

regulates to 6 V

V_(ACD)

AC adapter detect threshold

1.176

1.2

1.224

V

V_(ACDH)

AC adapter detect hysteresis

V_(ACDET)falling

V_(ACDET)rising

15

8

mV

ms

AC adapter detected deglitch time

AC adapter not detected deglitch

time

V_(ACDET)falling

1

µs

AC ADAPTER (ACP) - BATTERY (BAT) COMPARATOR

ACP voltage above BAT voltage

V_(ACP-BAT)

threshold

V_(ACP)falling with respect to V_(BAT)

V_(ACP-BAT)rising with respect to V_(BAT)

V_(ACP)falling with respect to V_(BAT)

250

50

300

mV

µs

V_(ACP-BAT)

Hysteresis

V_(ACP-BAT)falling below threshold

deglitch time

16

V_(ACP-BAT)rising above threshold

deglitch time

V_(ACP-BAT)rising with respect to V_(BAT)

8

ms

SYSTEM (SYS) - BATTERY (BAT) COMPARATOR

System voltage above pack voltage

at V_(VS,BAT)> V_(SYS)

V_(SYS-BAT)

V_(SYS)falling with respect to V_(BAT)

V_(SYS-BAT)rising with respect to V_(BAT)

V_(SYS)falling with respect to V_(BAT)

250

50

1

300

mV

µs

V_(SYS-BAT)

Hysteresis

V_(SYS-BAT)falling below threshold

deglitch time

V_(SYS-BAT)rising above threshold

deglitch time

V_(SYS-BAT)rising with respect to V_(BAT)

8

ms

BATTERY SHORTED COMPARATOR

V_(BAT)falling,

Programmed V_(BAT)= 9V

3.230

4.845

6.460

3.4

5.1

6.8

3.570

5.355

7.140

V

V_(BAT)falling,

Programmed V_(BAT)= 12-14.4V

V_(BATSHORT)

Battery shorted threshold⁽²⁾

V_(BAT)falling,

Programmed V_(BAT)= 16-19.2V

V_{(SHRT_HYS)}

Hysteresis

V_(BAT)rising

200

1

mV/cell

s

Battery shorted deglitch time

V_(BAT)rising/falling

BYPASS P-Channel MOSFET DRIVER (BYPASS)

R_{(DS_BYP)}

BYPASS off-state resistance

BYPASS on-state resistance

Driver output = HI, BYPASS = V_(PVCC), V_(PVCC)= 18 V

1

2

kΩ

Hi

Driver output = LO,

BYPASS = V_(PVCC)- V_(REGBYPASS), V_(PVCC)= 18 V

R_{(DS_BYP)}

Lo

Drive regulator turn-on voltage for

BYPASS with respect to V_(PVCC)

V_(REGBYPASS)

V_{(VCC, BYPASS)}, V_(VCC)> 13 V, I_(BYPASS)= 5 mA

-5

-6

-7.5

V

AC ADAPTER P-Channel MOSFET DRIVER (ACDRV)

R_{(DS_AC)}

ACDRV off-state resistance

ACDRV on-state resistance

Driver output = HI, ACDRV = PVCC, V_(PVCC)= 18 V

100

10

150

20

Ω

Hi

R_{(DS_AC)}

Driver output = LO, ACDRV =V_(PVCC)-V_(REGAC), V_(PVCC)= 18 V

kΩ

Lo

Drive regulator turn-on voltage for

ACDRV with respect to V_(PVCC)

V_(REGAC)

V_{(VCC, ACDRV)}, V_(VCC)> 13 V, I_(ACDRV)= 5 mA

-6.5

-7.5

V

BATTERY P-Channel MOSFET DRIVER (BATDRV )

R_{(DS_BAT)}

BATDRV off-state resistance

BATDRV on-state resistance

Driver output = HI, V_(PVCC)= 18 V

100

10

150

20

Ω

Hi

R_{(DS_BAT)}

Driver output = LO, BATDRV=V_(PVCC)-V_(REGBAT), V_(PVCC)= 18 V

kΩ

Lo

Drive regulator negative turn-on

voltage for BATDRV with respect to

V_(SYS)

V_(REGBAT)

V_{(VCC, BATDRV)}, V_(VCC)> 13 V, I_(BATDRV)= 5 mA

-5

-6.5

-7.5

V

SYSTEM POWER SELECTOR TIMING

Dead time when switching between

No load at ACDRV and BATDRV

1

µs

ACDRV and BATDRV

BYPASS SWITCH TIMING

Delay to turn-off BYPASS

(2) For the bq24721: When BAT falls below the V_(BATSHORT)threshold, the charger continues regulating at the programmed current down to

zero volts on BAT; then after 1 second deglitch time, the charge current automatically changes to 1/8 the programmed charge current.

The charge current automatically changes from 1/8 the programmed charge current to the full programmed charge current when BAT

voltage rises above (V_(BATSHORT)+ 200 mV hysteresis), after 1 second deglitch time.

9

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)

8 Vdc ≤ V_(VCC)≤ 24 Vdc, 0°C ≤ T_J≤ 125°C, all voltages with respect to AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PWM HIGH-SIDE N-Channel MOSFET DRIVER (HIDRV), bq24721

R_{(DS_HIDRV)}

High-side on-state resistance

High-side off-state resistance

HSD switch on, HIDRV = HI, V_(BOOST,PH)= 5.5 V

HSD switch off, HIDRV = LO, V_(BOOST,PH)= 5.5 V

2.2

1.5

3

Ω

Hi

R_{(DS_HIDRV)}

2.5

Lo

PWM HIGH-SIDE N-Channel MOSFET DRIVER (HIDRV), bq24721C

R_{(DS_HIDRV)}

High-side on-state resistance

High-side off-state resistance

HSD switch on, HIDRV = HI, V_(BOOST,PH)= 5.5 V

HSD switch off, HIDRV = LO, V_(BOOST,PH)= 5.5 V

4.5

1.5

8.6

2.6

Ω

Hi

R_{(DS_HIDRV)}

Lo

PWM LOW-SIDE N-Channel MOSFET DRIVER (LODRV), bq24721

R_{(DS_LODRV)}

Low-side on-state resistance

Low-side off-state resistance

LSD switch on, LODRV = HI, V_(PVCC)= 7 V

LSD switch off, LODRV = LO, V_(PVCC)= 7 V

2.2

1.5

3

Ω

Hi

R_{(DS_LODRV)}

2.5

Lo

PWM LOW-SIDE N-Channel MOSFET DRIVER (LODRV), bq24721C

R_{(DS_LODRV)}

Low-side on-state resistance

Low-side off-state resistance

LSD switch on, LODRV = HI, V_(PVCC)= 7 V

LSD switch off, LODRV = LO, V_(PVCC)= 7 V

4.5

1.5

8.6

2.6

Ω

Hi

R_{(DS_LODRV)}

Lo

PWM LOW-SIDE DRIVER REGULATOR (REGN)

V(REGN) at I(REGN) = 10 mA, sourcing,

Adapter detected (V_(ACDET)> V_(ACD)), V_(PVCC)> 7 V

5.5

6

6.5

V

V_O(HREGN)

I_{O(REGN_SW)}

I_{(REGN_LIM)}

REGN output voltage

V(REGN) at I(REGN) = 10 mA, sourcing,

Adapter not detected, (V_(ACDET)< V_(ACD)), V_(PVCC)> 7 V

4.2

2 times 25 nC load, fs = 300 kHz

2 times 25 nC load, fs = 500 kHz

15

25

mA

REGN output current while charger

switching

VREGN = 5 V

Adapter detected (V_(ACDET)> V_(ACD)), V_(PVCC)> 7 V

100

13.3

15

mA

REGN Current limit

Adapter detected

VREGN = 0 V, shorted

Adapter detected (V_(ACDET)> V_(ACD)), V_(PVCC)> 7 V

REGN Current limit

Adapter not detected

VREGN = 4.2 V

Adapter not detected, (V_(ACDET)< V_(ACD)), V_(PVCC)> 7 V

PWM DRIVERS TIMING

Dead time when switching between

LSD and HSD, no load at LSD and

HSD

30

ns

PWM OSCILLATOR

PWM oscillator ramp voltage , low

value

V_(RAMPLO)

V_(RAMPHI)

0% duty cycle occurs below this threshold

0.35

V

PWM oscillator ramp voltage , high

value

near 100% duty cycle occurs above this threshold

3

V_PP(RAMP)

V_(RAMPCL)

F_S

PWM ramp peak-to-peak amplitude

PWM oscillator ramp clamp voltage

PWM oscillator frequency (300 kHz)

PWM oscillator frequency (500 kHz)

0.1×VCC

3.5

V

265

425

300

345

575

kHz

500

INTERNAL SOFT START (8 steps to Ireg)

SRSET pin voltage number of steps

Eight steps of charge current regulation to get to programmed value

(SRSET = 1 V).

8

1

step

during soft start.

Step Duration.

Eight steps of charge current regulation to get to programmed value

(SRSET = 1 V).

0.8

1.2

ms/step

CHARGER SECTION POWER-UP SEQUENCING

Time delay between power up of

charger block references (first) and

start charge (second)

1

ms

Time delay from adapter detected

until ACDRV enable and charger

block enable

500

10

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

TYPICAL CHARACTERISTICS

VREF5 LOAD REGULATION

VREF5 LINE REGULATION

VREF5 CURRENT LIMIT

vs

JUNCTION TEMPERATURE

vs

LOAD CURRENT

INPUT VOLTAGE

5

4.988

4.986

114

113

112

111

110

V = 20 V

I

V = 20 V

I

4.99

T

= 0^oC

T

= 25^oC

J

T

4.98

4.97

4.96

4.95

4.94

J

4.984

4.982

4.98

T

= 25^oC

J

T

= 85^oC

J

T

= 85^oC

J

4.978

= 125^oC

T

= 125^oC

T

J

109

108

4.976

4.974

4.93

4.92

0

5

10 15 20 25 30 35 40 45 50

7

9

11 13 15 17 19 21 23 24

0

20

40

60

80 100 110 120 125

V − Input Voltage − V

I

T

− Junction Temperature − ^o

C

I

− Load Current − mA

L

J

Figure 1.

Figure 2.

Figure 3.

REGN LOAD REGULATION

REGN LINE REGULATION

vs

REGN CURRENT LIMIT

vs

JUNCTION TEMPERATURE

vs

LOAD CURRENT

INPUT VOLTAGE

5.95

5.9

5.92

5.91

5.9

116

115.5

115

V = 20 V

I

V = 20 V

I

T

= 0^oC

J

T

= 0^oC

J

T

= 25^oC

J

T

= 25^oC

J

5.85

5.8

T

= 85^oC

114.5

114

J

5.89

T

= 85^oC

J

= 125^oC

5.88

5.87

5.75

5.7

T

= 125^oC

J

113.5

113

T

J

0

5

10 15 20 25 30 35 40 45 50

7

9

11 13 15 17 19 21 23 24

0

20

40

60

80 100 110 120 125

V − Input Voltage − V

I

T

− Junction Temperature − ^o

C

I

− Load Current − mA

L

J

Figure 4.

Figure 5.

Figure 6.

QUIESCENT CURRENT, NO

QUIESCENT CURRENT, WITH

REGN CURRENT LIMIT

vs

FORCED REGN VOLTAGE

ADAPTER

vs

ADAPTER

vs

JUNCTION TEMPERATURE

160

140

280

270

260

5.8

5.6

5.4

V

= 24 V

CC

120

100

80

V = 16.8 V

I

5.2

5

250

240

230

220

210

200

V = 16.8 V

I

V = 12.6 V

I

4.8

4.6

4.4

4.2

4

V = 12.6 V

I

60

40

20

0

1

2

3

4

5

6

0

20

40

60

80 100 110 120 125

-15

5

T

25

45

65

85

105 125

C

T

− Junction Temperature − ^o

C

− Junction Temperature − ^o

V − Forced REGN Voltage − V

I

J

Figure 7.

Figure 8.

Figure 9.

11

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

TYPICAL CHARACTERISTICS (continued)

ACDET THRESHOLD

vs

JUNCTION TEMPERATURE

ACDET HYSTERESIS

vs

JUNCTION TEMPERATURE

HIDRV, r_DS(on), PULL UP

vs

JUNCTION TEMPERATURE

1.2012

1.201

19.25

19.2

6

5.5

5

V = 20 V

I

V = 20 V

I

V = 20 V

I

19.15

19.1

1.2008

4.5

4

1.2006

1.2004

1.2002

1.2

bq24721C

19.05

19

3.5

3

18.95

18.9

2.5

2

18.85

18.8

bq24721

1.1998

1.1996

1.5

18.75

0

20

40

60

80 100 110 120 125

0

20

40

60

80 100 110 120 125

0

20

T

40

60

80

100 120 125

− Junction Temperature − ^o

C

T

− Junction Temperature − ^o

C

− Junction Temperature − ^o

C

T

J

Figure 10.

Figure 11.

Figure 12.

HIDRV, r_DS(on), PULL DOWN

vs

JUNCTION TEMPERATURE

LODRV, r_DS(on), PULL UP

vs

JUNCTION TEMPERATURE

LODRV, r_DS(on), PULL DOWN

vs

JUNCTION TEMPERATURE

1.9

1.8

1.9

1.8

6

5.5

5

V = 20 V

I

V = 20 V

I

1.7

1.6

1.5

1.4

1.3

1.2

1.7

1.6

1.5

1.4

1.3

1.2

bq24721C

4.5

4

3.5

3

2.5

2

bq24721

1.1

1

1.1

1

1.5

0

20

40

60

80 100 110 120 125

0

20

40

60

80 100 110 120 125

0

20

T

40

60

80

100 120 125

− Junction Temperature − ^o

C

T

− Junction Temperature − ^o

C

− Junction Temperature − ^o

C

T

J

Figure 13.

Figure 14.

Figure 15.

BATTERY VOLTAGE REGULATION

CHARGE CURRENT REGULATION

ACCURACY

vs

BATTERY VOLTAGE REGULATION

vs

ACCURACY

vs

BATTERY VOLTAGE

JUNCTION TEMPERATURE

SRP-SRN VOLTAGE

0.1

15

13

V = 20 V

I

V = 24 V

I

0.08

0.06

0.04

0.08

0.06

0.04

T

= 85^oC

11

9

J

T

= 125^oC

= 85^oC

J

V = 12.6 V

I

0.02

0

0.02

0

7

5

T

J

V = 16.8 V

I

-0.02

-0.04

-0.06

-0.08

-0.1

-0.02

-0.04

-0.06

-0.08

-0.1

T

= 25^oC

J

T

J

= 25^oC

= 0^oC

T

= 125^oC

3

1

J

T

J

T

= 0^oC

J

-1

0

20

40

60

80 100 110 120 125

9

11

V

13

15

17

19

5

15

25

35

45

55

65

− Junction Temperature − ^o

C

V − SPR-SRN Voltage − mV

I

T

− Battery Voltage − V

J

(BAT)

Figure 16.

Figure 17.

Figure 18.

12

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

TYPICAL CHARACTERISTICS (continued)

INPUT CURRENT REGULATION

(DPM) ACCURACY

vs

I_O= DPM CURRENT SENSE

AMPLIFIER ACCURACY

vs

(DPM) ACCURACY

vs

ACP-ACN VOLTAGE

INPUT VOLTAGE

ACP-ACN VOLTAGE

13

11

9

5

4

0.28

0.26

V = 20 V

I

V = 20 V

I

V = 20 V

I

T

= 0^oC

J

0.24

0.22

0.2

5.12 mV

T

= 125^oC

= 85^oC

J

3

T

= 85^oC

J

7

5

2

1

T

J

0.18

0.16

10.24 mV

T

J

= 25^oC

T

= 25^oC

3

T

= 125^oC

J

40.96 mV

20.48 mV

0.14

T

= 0^oC

J

0

1

0.12

0.1

-1

5

9

13 17 21 25 29 33 37 41

14

16

18

20

22

24

0

10 20 30 40 50 60 70 80 90 100

V − ACP-ACN Voltage − mV

I

V − Voltage − mV

I

V − ACP-ACN Voltage − mV

I

Figure 19.

Figure 20.

Figure 21.

I_O= DPM CURRENT SENSE

AMPLIFIER OFFSET

vs

I_O= ADAPTER OUTPUT CURRENT

I_O= CHARGE SENSE AMPLIFIER

LIMIT

ACCURACY

vs

JUNCTION TEMPERATURE

SRP-SRN VOLTAGE

1

0.9

0.8

0.7

6

0.2

0

5.95

5.9

V = 20 V

I

-0.2

-0.4

-0.6

-0.8

-1

T

= 125^oC

J

5.85

5.8

0.6

0.5

0.4

0.3

0.2

T

= 85^oC

J

5.75

5.7

T

= 25^oC

= 0^oC

J

V = 20 V

I

J

5.65

5.6

-1.2

-1.4

0.1

0

20

40

60

80 100 110 120 125

0

20

40

60

80 100 110 120 125

0

10 20 30 40 50 60 70 80 90 100

− Junction Temperature − ^o

C

T

− Junction Temperature − ^o

C

V − SRP-SRN Voltage − mV

I

T

J

Figure 22.

Figure 23.

Figure 24.

I_O= CHARGE CURRENT LIMIT

vs

JUNCTION TEMPERATURE

300-kHz SWITCHING FREQUENCY

vs

INPUT VOLTAGE

JUNCTION TEMPERATURE

5.75

5.7

311

T

= 85^oC

V = 20 V

I

J

V = 20 V

I

310.5

310

310.5

310

T

= 125^oC

J

5.65

5.6

309.5

309

T

= 25^oC

5.55

5.5

J

309.5

309

308.5

308

5.45

5.4

T

= 0^oC

J

308.5

0

20

40

60

80 100 110 120 125

0

20

40

60

80 100 110 120 125

14

16

18

20

22

24

− Junction Temperature − ^o

C

T

− Junction Temperature − ^o

C

V − Input Voltage − V

I

T

J

Figure 25.

Figure 26.

Figure 27.

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

TYPICAL CHARACTERISTICS (continued)

500-kHz SWITCHING FREQUENCY

vs

THERMISTOR LTF THRESHOLD

vs

JUNCTION TEMPERATURE

vs

INPUT VOLTAGE

JUNCTION TEMPERATURE

498.5

498

498.5

73.65

T

= 85^oC

J

V = 20 V

I

V = 20 V

I

498

497.5

497

T

= 125^oC

73.6

J

497.5

73.55

497

496.5

496

496.5

496

73.5

73.45

73.4

T

J

= 25^oC

T

= 0^oC

J

495.5

495

494.5

73.35

14

16

18

20

22

24

0

20

40

60

80 100 110 120 125

0

20

40

60

80 100 110 120 125

− Junction Temperature − ^o

C

T

− Junction Temperature − ^o

C

V − Input Voltage − V

I

T

J

Figure 28.

Figure 29.

Figure 30.

THERMISTOR LTF THRESHOLD

vs

JUNCTION TEMPERATURE

THERMISTOR TCO THRESHOLD

vs

THERMISTOR TSDET THRESHOLD

vs

JUNCTION TEMPERATURE

34.4

29.3

84.8

V = 20 V

I

34.395

V = 20 V

I

84.79

84.78

84.77

84.76

84.75

V = 20 V

I

29.28

34.39

34.385

34.38

34.375

34.37

29.26

29.24

84.74

84.73

34.365

34.36

29.22

29.2

84.72

84.71

34.355

34.35

84.7

0

20

40

60

80 100 110 120 125

0

20

40

60

80 100 110 120 125

0

20

40

60

80 100 110 120 125

T

− Junction Temperature − ^o

C

T

− Junction Temperature − ^o

C

T

J

− Junction Temperature − ^o

C

J

Figure 31.

Figure 32.

Figure 33.

14

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

TYPICAL CHARACTERISTICS (continued)

EFFICIENCY

vs

BATTERY CHARGE CURRENT

REGULATION CURRENT

vs

SYSTEM CURRENT

4500

4000

3500

3000

2500

2000

1500

1000

500

100

95

IDPM

V

= 16.8 V

(BAT)

V

= 12 V

(BAT)

= 20 V

CC

90

R

= 10 mW

V

= 12.6 V

(sns)

(BAT)

ICHG

85

DPM Active

V = 19.5 V

= 20^oC

I

80

T

A

ILOOP Active

75

0

1

2

3

4

5

6

7

8

0

500 1 k 1.5 k 2 k 2.5 k 3 k 3.5 k 4 k 4.5 k

System Current − mA

Battery Charge Current − A

Figure 34.

Figure 35.

TRANSIENT SYSTEM LOAD

SYSTEM SELECTOR GATE DRIVES AFTER ACDET

Adapter plugged in (ACDET goes above 1.2 V)

ACDRV has a 500-ms delay before turning on

Power Loop Verification (DPM) Transient Response

Constant Current Regulation, Then (DPM) Regulation

Ch1

20 V

BYPASS

ACDRV

Ch4 = System Current

Ch2

20 V

Ch4

0 A

Ch4

20 V

Ch1 = Input Current

BATDRV

Ch1

Ch3

0 A

Ch3 = Battery Current

ACDET

Ch1

0 V

t − Time = 100 ms/div

t − Time = 1 ms/div

Figure 36.

Figure 37.

15

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

TYPICAL CHARACTERISTICS (continued)

SYSTEM SELECTOR ADAPTER INSERTION

SYSTEM SELECTOR ADAPTER REMOVAL

System Power Selection

Adapter is unplugged in, System switches over to battery once the adapter

voltage drops below VAIRLINE.

Adapter is plugged in, then 500 ms later the system switches over.

System Voltage

Adapter Voltage

1-A System Load

Battery Voltage

System Voltage

Battery Voltage

Ch1

Ch2

Ch4

0 V

1-A System Load

Adapter Voltage

Ch1

Ch2

Ch4

0 V

t − Time = 200 ms/div

t − Time = 1 s/div

Figure 38.

Figure 39.

REGN VREF5 POWER UP

SOFTSTART CHARGE CURRENT

VREF5 and REGN Power-Up

Softstart Operation

Inductor Current

Ch4

0 V

REGN

0 A

VREF5

Ch2

0 V

AVCC/PVCC

Ch1

0 V

t − Time = 1 ms/div

t − Time = 2 ms/div

Figure 40.

Figure 41.

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

TYPICAL CHARACTERISTICS (continued)

NONSYNCHRONOUS TO SYNCHRONOUS TRANSITION

SYNCHRONOUS TO NONSYNCHRONOUS TRANSITION

Transition from Non-Synchronous to Synchronous

Inductor Current

Transition from Non-Synchronous to Synchronous

Inductor Current

Ch3

0 A

Ch3

0 A

Ch4

0 V

Ch4

0 V

Low side NMOS gate voltage

Ch1

0 V

Ch1

0 V

PH

t − Time = 10 ms/div

Figure 42.

Figure 43.

NEAR 100% DUTY CYCLE BTST RECHARGE PULSE

BATTERY SHORT RESPONSE

Bootstrap Refresh Comparator Operation

BATSHORT Functionality

Inductor Current

Trefresh = 250 ms

BAT

Ch3

0 A

Ch2

0 V

BAT goes from 13 V to 3 V, 1 sec deglitch, charge turns off

BAT goes back to 13 V, 1 sec deglitch, charge turns back on

Ch2

0 V

Low side NMOS gate

Inductor Current

PH

Ch3

0 A

Ch1

0 V

t − Time = 400 ms/div

t − Time = 40 ms/div

Figure 44.

Figure 45.

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

TYPICAL CHARACTERISTICS (continued)

CHARGE OVERCURRENT

ACOC ACDRV TURN OFF (32-µs DEGLITCH)

Charge Overcurrent Comparator Functionality

ACOC Rising Edge (32 ms deglitch)

ACN decreases below ACOC threshold

Regulating 4 A, then add 1 W in parallel

to reduce VBAT

VBAT

Ch1

20 V

ADCRV

Ch2

0 V

ACN (ACP fixed)

Ch2

20 V

Ch3

4 A

Inductor Current

t − Time = 20 ms/div

Figure 46.

Figure 47.

ACOC ACDRV TURN ON (500-µs DEGLITCH)

SWITCHING CONTINUOUS CURRENT MODE (CCM)

Steady State Operation

ACOC Falling Edge (500 ms deglitch)

ACN increases above ACOC threshold

Ch2 = VPH

Ch1

20 V

ADCRV

Ch1

12 V

Ch1 = VOUTCAPS

Ch2

0 V

Ch3 = Inductor Current

Ch3

4 A

Ch4

12 V

Ch2

20 V

ACN (ACP fixed)

Ch4 = VOUTCAPS_AC Ripple

Max (C1) 10.4 V

Min (C1) 8.0 V

Min (C2) -1.2 V

Min (C3) 3.12 A

Min (C4) 32.0 mV

Max (C2) 20.4 V

Max (C3) 5.04 A

Max (C4) 42.0 mV

t − Time = 1 ms/div

t − Time = 200 ms/div

Figure 48.

Figure 49.

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TYPICAL CHARACTERISTICS (continued)

SWITCHING DISCONTINUOUS CURRENT MODE

vs

(DCM)

Steady State Operation

Ch2 = VPH

Ch1

12.6 V

Ch1 = VOUTCAPS

Ch2

0 V

Ch4 = VOUTCAPS_AC Ripple

Ch4

12.6 V

Ch3

4 A

Min (C1) 11.6 V

Min (C2) -1.2 V

Min (C3) 320.0 mA

Min (C4) 22.0 mV

Max (C1) 14.0 V

Ch3 = Inductor

Current

Max (C2) 20.8 V

Max (C3) 1.12 A

Max (C4) 30.0 mV

t − Time = 1 ms/div

Figure 50.

19

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

SIMPLIFIED BLOCK DIAGRAM

IOUT

BYPASS

ACDRV

BATDRV

AGND

VCC

VREF5

20X

REFERENCE SYSTEM

Select Adaptor current

or Charge current

Always on

AC SW AND BAT SW DRIVERS

− break−before−make LOGIC

Always on

BYPASS SW

DRIVER

−

5v ldo when ACPRES

Power−on reset

UVLO

Always on

Voltage references

Internal timebase

SRP

SRN

Always on

SYNCHRONOUS SWITCHING

PWM CONVERTER

BYPON

ACON

ACOC

CHGOC

LOGIC

ACP

ACN

−

current loop

dpm loop

− Power up/down sequencing

− Charge enable logic

CLK, POR

voltage loop

sync/nonsync comparator

charge overcurrent

comparator

− Charge enable sequencing

− System power selector logic

− System selector bbm logic

− Deglitch times

EAO

EAI

POWERON

BDEP, ACCHG, THDET,

TCOLD, THOT ,VSHI, TERMDET,

ADPSRC, VCCGTBAT, TCMP

FBO

SYSTEM STATUS

COMPARATORS

charge current reference

dpm current reference

break−before−make logic

CHARGERON

SYNP

ACGOOD

Always on

−

Battery depleted (1)

AC detection (1)

SYNN

− duty−cycle limited, 0% to near

100% (99.5%)

−

ISYNSET

*Thermistor inserted (1)

*Thermistor cold (2)

−

NMOS/NMOS drivers

ACDET

BAT

Internal soft start

*Thermistor hot (2)

PWM oscillator 300 kHz/500 kHz

BTST

System voltage / pack voltage (2)

VCC above pack voltage (2)

SYS

TS

HIDRV

PH

(1) always on

Enabled only when AC is

(2) enabled when AC is detected

REGN

LODRV

PVCC

detected and CHGEN is low

TTL INPUT

BUFFER

ALARM

VREG DAC

DECODER

1BIT Select Cells

7BIT (6.25mV/bit)

SBS [b1−b14] to

bq24721 [7bit +1bit]

SMBUS INTERFACE

Always on

MEMORY

SCL

SDA

SR IREG DAC

7BIT (1.28mV/bit)

Always on

AC IREG DAC

7BIT (1.28mV/bit)

CHGEN

PGND

Figure 51. bq24721 SBS-Like SMBus Controlled Simplified Block Diagram

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

TYPICAL APPLICATION bq24721

Q2

SI4435

Q1

SI4435

R1

0.010

SYSTEM

ADAPTER+

bq24721

PACK+

C1

10 uF

C2

10 uF

C6

1 uF

ADAPTER-

ACDRV

VCC

SYC

D1

BAT54C

C7

0.1 uF

ACN

ACP

BATDRV

PVCC

R3

464 k

C8

C9

0.1uF

1%

0.1uF

C3

4x10uF

BYPASS

ACDET

Q5

SI4435

Q3

FDS6670A

HIDRV

PH

L1

10 uH

R2

0.010

PACK+

PACK-

R4

33.2 k

1%

C12

VREF5

, 0.1uF

VREF5

AGND

BTST

R5

5.6 k

1%

PACK

THERMISTOR

SENSE

D2

BAT54

C10

1 uF

C13, 1uF

REGN

C4

2x10 uF

TS

Q4

FDS6670A

C14

0.1uF

C5

2x10 uF

C17

0.1 uF

OPTIONAL

LODRV

PGND

SYNP

SYNN

SRP

R13

118 k

1%

C18

0.1 uF

OPTIONAL

C15

0.1uF

C16

0.1 uF

SRN

ACGOOD

BAT

C19

0.1 uF

CHGEN

EAO

VREF5

C20

51pF

R10

20k

R9

7.5k

EMBEDDED

CONTROLLER

HOST

C22

130pF

EAI

FBO

R6

10 k

R7

10 k

R8

10 k

R11

200k

C21

2000pF

SCL

SDA

SMBus

IRQ

ISYNSET

R12

33k

ALARM

PowerPAD

A/D

IOUT

C11

0.1uF

Short PowerPAD to

PGND and AGND

Figure 52. bq24721 SBS-Like SMBus Host Control With System Power Selector

(bq24721 With TS Thermistor Sense Input Pin)

BOM Key Components (For Figure 52, bq24721 Typical Application Circuit)

Reference Designator

Qty

1

Description⁽¹⁾

Q3

Q4

N-channel MOSFET, 30V, 12.5A, SO-8, FDS6680A

N-channel MOSFET, 30V, 13A, SO-8, FDS6670A

1

Q1, Q2, Q5

3

P-channel MOSFET, -30V,-6A, SO-8, Vishay-Siliconix, Si4435

Diode, Dual Schottky, 30V, 200mA, SOT23, Fairchild, BAT54C

Diode, Single Schottky, 30V, 200mA, SOT23, Fairchild, BAT54

Inductor, 10µH, 7A, 31mΩ, Vishay-Dale, IHLP5050FD-01

D1

1

D2

1

L1

1

R1, R2

2

Sense Resistor, 10 mΩ, 1%, 1W, 2010, Vishay-Dale, WSL2010R0100F

C1, C2, C3, C4, C5

10

Capacitor, Ceramic, 10µF, 35V, 20%, X5R, 1206, Panasonic,

ECJ-3YB1E106M

C6, C10, C13

3

Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E105K

C7, C8, C9, C12, C14, C15, C16,

C19, (C17 and C18 optional)

10

Capacitor, Ceramic, 0.1µF, 50V, 10%, X7R, 0805, Kemet,

C0805C104K5RACTU

C20

1

Capacitor, Ceramic, 51pF, 50V, 5%, NPO, 0603

(1) The manufacturer's part number are used for test purposes only.

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

BOM Key Components (For Figure 52, bq24721 Typical Application Circuit) (continued)

Reference Designator

Qty

1

Description⁽¹⁾

Capacitor, Ceramic, 2000pF, 50V, 5%, X7R, 0805

Capacitor, Ceramic, 130pF, 50V, 5%, NPO, 0603

Resistor, Chip, 464kΩ, 1/16W, 1%, 0402

Resistor, Chip, 33.2kΩ, 1/16W, 1%, 0402

Resistor, Chip, 33kΩ, 1/16W, 5%, 0402

Resistor, Chip, 7.54kΩ, 1/16W, 1%, 0402

Resistor, Chip, 20kΩ, 1/16W, 1%, 0402

Resistor, Chip, 200kΩ, 1/16W, 1%, 0402

Resistor, Chip, 10kΩ, 1/16W, 5%, 0402

Resistor, Chip, 5.6kΩ, 1/16W, 1%, 0402

Resistor, Chip, 118kΩ, 1/16W, 1%, 0402

C21

C22

R3

1

R4

1

R12

R9

1

R10

R11

1

R6, R7, R8

R5

3

1

R13

1

Typical bq24721 Narrow VDC (NVDC) Application (2 sense resistors)

Q1

SI4435

SYSTEM

ADAPTER +

bq24721

C1

10uF

PACK+

C2

10 uF

C6

1u

ACDRV

SYC

ADAPTER -

F

VCC

D1

BAT54C

C7

0.1uF

ACN

ACP

BATDRV

PVCC

R3

464k

1%

C8

0.1uF

C9

0.1uF

C3

4x10uF

BYPASS

Q3

FDS6670A

HIDRV

PH

ACDET

VREF5

AGND

R2

0.010

R13

0.010

L1

10uH

PACK+

PACK-

R4

33.2k

1%

VREF5

C12, 0.1uF

PACK

THERMISTOR

SENSE

C10

1uF

BTST

R5

5.6 k

1%

D2

BAT54

C13, 1uF

Q4

FDS6670A

C4

REGN

2x10uF

TS

C14

0.1uF

C5

2x10uF

R1

118k

1%

LODRV

C17

0.1uF

PGND

SYNP

SYNN

C18

0.1uF

C15

0.1uF

C16

SRP

SRN

BAT

0.1uF

ACGOOD

C19

0.1uF

CHGEN

EAO

VREF5

C20

51pF

R10

20k

R9

7.5k

C22

130 pF

EMBEDDED

CONTROLLER

HOST

EAI

FBO

R6

10k

R7

10k

R8

10k

R11

200 k

C21

2000 pF

SCL

SDA

SMBus

IRQ

ISYNSET

R12

33k

ALARM

A/D

PowerPAD

IOUT

C11

0.1uF

Short PowerPAD to

PGND and AGND

Figure 53. bq24721 SBS-Like SMBus Host Control, NVDC (no system power selector) With 2 Sense

Resistors. ACP and ACN Regulating Converter Current Instead of Input Current

22

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

Typical bq24721 Narrow VDC (NVDC) Application (3 sense resistors)

Q1

R1

SYSTEM

SI4435

0.010

ADAPTER+

bq24721

C1

10 uF

PACK+

C2

10 uF

C6

1 uF

C7

0.1 uF

ACDRV

SYC

ADAPTER-

VCC

D1

BAT54C

ACN

ACP

BATDRV

PVCC

R3

464 k

1%

C8

0.1 uF

C9

0.1 uF

C3

4x10uF

BYPASS

Q3

FDS6670A

HIDRV

PH

ACDET

VREF5

AGND

L1

10 uH

R2

0.010

R13

0.010

PACK+

PACK-

R4

33.2 k

1%

C12

VREF5

0.1 uF

BTST

R5

5.6 k

1%

PACK

THERMISTOR

SENSE

D2

BAT54

C10

1 uF

C13, 1 uF

Q4

FDS6670A

C4

REGN

2x10 uF

TS

C14

0.1 uF

C5

2x10 uF

LODRV

R13

118 k

1%

C17

0.1 uF

PGND

SYNP

SYNN

C18

0.1 uF

C15

0.1 uF

C16

0.1 uF

SRP

SRN

BAT

ACGOOD

C19

0.1 uF

CHGEN

EAO

VREF5

R7

R10

20 k

C20

51 pF

R9

7.5 k

EMBEDDED

CONTROLLER

HOST

C22

130 pF

EAI

FBO

R6

R8

R11

200 k

C21

2000 pF

10 k

10 k 10 k

SCL

SDA

SMBus

IRQ

ISYNSET

R12

33 k

ALARM

A/D

PowerPAD

IOUT

C11

0.1uF

Short PowerPAD to

PGND and AGND

Figure 54. bq24721 SBS-Like SMBus Host Control, NVDC (no system power selector)

With 3 Sense Resistors

23

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

5-V LDO

ENA

VREF5

VCC

ADAPTER

DETECTED

ACDET

CHGEN

EAO

+

-

1.2 V

SYS-BAT

SYS

250 mV

BAT

-

BATDEP

-

PVCC

PVCC-6V

SRP-BAT

ACOC

PVCC-6V

LDO

PVCC

SMBUS

+

BATDEPSET

BAT + 250 mV

BYPASS

ACDRV

SYS

PVCC-6V

SYSTEM

POWER

SELECTOR

LOGIC

EAI

PVCC-6V

SYS-6V

SYS

SYS 6-V

LDO

FBO

ACOC_SET

V(ACP-ACN)

+

-

ACOC

BATDRV

BTST

ACP

ACN

+

-

ICH_ER

SYS-6V

-

SMBUS

CHGEN

COMP

ERROR

AMPLIFIER

IIN

DAC

+

CHGEN

ACP-BAT

-

250 mV

+

1 V

BAT + 250 mV

4 mA

LEVEL

SHIFTER

BAT_ER

HIDRV

BAT

SRP

-

VBAT

DAC

+

20 mA

OVP

+

-

OVP

OCP

110% x BAT_DAC

PH

SYNCH

DC-DC

CONVERTER

PWM LOGIC

+

-

V(SRP-SRN)

ICH_ER

-

ACP-BAT

IBAT

DAC

+

VCC

REGN

LODRV

PGND

IOUT

SRN

6-V LDO

20 mA

SUSPEND

TSDET

500 kHz 300 kHz

2 x IBAT_DAC

V(SYNP-N)

REFRESH

CBTST

SYNP

BTST

4.5 V

-

OCP

+

-

+

SW FREQ

SELECT

+

_

PH

+

-

SYNCH

SYNN

ISYNSET

ACP

ACN

+

-

ISYNSET x 500

V(IADAPT)

V(IBAT)

20x

IC T_J

145^oC

TSHUT

+

-

SELECT

VREF5

1 V

SRP

SRN

+

-

+

_

+

TSDET

LTF

ALARM

SDA

-

CHARGE STATUS

REGISTER

-

CHARGE MODE

REGISTER

+

TS

VBAT

DAC

+

-

HTF

SUSPEND

SMBus LOGIC

IBAT

DAC

SCL

AGND

+

-

TCO

IIN (DPM)

DAC

Figure 55. bq24721 Functional Block Diagram

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ADAPTER

POWER

external

SYSTEM&CHARGEPOWER

SELECTOR

SYSTEM

Chrg

Dischrg

Chrg

Vin

Bat

bq24721

BATTERY

CHARGER

CONTROLLER

IC

BATTERY

Primary

BATTERY

Secondary

&

CONVERTER

PSID

I/O

SMBus

I/O

SMBus

HOST - Embedded Controller (EC)

Figure 56. Host Controller

BLOCK DESCRIPTION

Detail Block Diagram

The bq24721 charge controller can be used to charge Li-Ion, NiMH, or NiCd batteries. The high efficiency

synchronous buck controller uses n-channel power MOSFETs for both the high-side control device and the

low-side synchronous device. The controller offers high regulation accuracy of the charge current, battery

voltage, and input current limits. The low offset of the current loops allow using sense resistors with low-value,

such as 10 mΩ.

An embedded controller host programs the battery voltage, charge current, and input current regulation limit

thresholds through an SMBus interface using SBS-like DAC registers. The embedded host can control the

operation of the charger through a Charge Control (0x12) register, and monitor the status of the charger through

a Charger Status (0x13) register.

The voltage loop regulates the battery voltage to the programmed value, and prevents the voltage from

exceeding that value when the battery is connected. The charge current loop regulates the battery charge

current to the programmed value, and prevents the charge current from exceeding that value. Through the use

of dynamic power management (DPM), the input current loop regulates the battery charge current to the

programmed value, and prevents the input current from exceeding that value. The three regulation loops operate

independently, yet only require a single loop compensation network.

The system power selector function selects the appropriate power source for the system load. If the adapter is

detected, then the adapter is connected to the system load. When the adapter is removed, the battery is

selected to power the system load. A battery learn cycle is performed when the adapter is present by setting the

CONTROL(0x12) register into Learn Mode via SMBus by the embedded host. This disconnects the adapter from

the system; and instead, connect the battery to the system. This is typically done for Ni-based batteries.

SMBus Interface

The bq24721 uses all the SMBus communications protocol, except for packet error correction (PEC). The

charger IC address is (0x12), although it is not 100% SBS compliant. In most applications, the extra functionality

provided by the differing SBS-Like interface enhances the control of the charger application, while simplifying the

interface block, using only the pertinent functions. Five 16-bit registers are used to interface between the

embedded host and the charge control IC. The Charging Voltage (0x15) register is used to set the battery

regulation voltage. The Charging Current (0x14) register is used to set the battery charge regulation current. The

Input Current (0x3F) register is used to set the input regulation current. The Charger Mode (0x12) control

register is used to set the charger operating modes. Finally, the Charger Status (0x13) register is used to

monitor the operating status of the charger.

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BLOCK DESCRIPTION (continued)

ADDRESS

0x15

REGISTER

DESCRIPTION

Charging voltage

Charging current

Input current

Used to set the battery regulation voltage.

Used to set the battery charge regulation current.

Used to set the input regulation current.

Used to set the charger operating modes.

Used to monitor the operating status of the charger.

0x14

0x3F

0x12

Charger mode

Charger status

0x13

The SMBus communications requires only two pins besides the analog ground pin—through the SDA (data) and

SCL (clock) pins. The open-drain SCL and SDA pins require pull-up resistors on the board pulling up to the host

digital output voltage rail. The pins can be pulled up to any rail between 3 V to 5 V.

An alarm is sent to the host through the ALARM open drain pin. This is used to trigger an interrupt request

(IRQ). A low on the ALARM pin indicates there was a change on the Charger Status (0x13) register. The

ALARM pin stays low until the host reads the Charger Status (0x13) register, then the ALARM pin clears and

returns to the HI state. The open-drain ALARM pin requires a pull-up resistor that pulls up to the host digital

input voltage rail. The pin can be pulled up to any rail between 3 V to 5 V. The charge controller continues to

operate whether the host chooses to read or not to read the Charger Status (0x13) register. There is no

communications watchdog timer, so there is no need to continuously poll the Charger Status (0x13) register or

have to continuously reprogram any of the other registers.

Setting Charge Voltage (VBAT DAC register)

The charge voltage can be programmed by setting Charging Voltage(0x15) register. The SBS specification asks

for 16 bits to set the regulation voltage with a 1-mV LSB—giving a maximum possible voltage of 65.535 V. The

bq24721 uses bits 1 through 14 only, and maps them into the closest value of an internal 7-bit DAC on a per cell

basis using a 6.25-mV per cell LSB for three ranges: 9-V precharge voltage; 3 cells Li+ battery pack range; or 4

cells Li+ battery pack range. The 3 cell portion has an LSB of 18.75 mV and a range from 12 V-14.4 V; while the

4 cell portion has an LSB of 25 mV and a range from 16 V-19.2 V. Intermediate programmed voltages between

the internal 7-bit DAC values are truncated to the lower value to avoid an overvoltage on the battery.

Programmed voltages above 19.2 V are automatically set to the maximum 19.2-V limit. The charger is disabled

for programmed voltages below 12 V (except for 9 V), and for programmed voltages between 14.4 V – 16 V.

This triggers a voltage-out-of-range condition and the VOR bit of the Charger Status (0x13) register is set, and

an alarm (ALARM pin pulled low) is sent to the host. The default power-up-reset voltage value is 0 V, charger

disabled.

Setting Charge Current (IBAT DAC register)

The charge current can be programmed using the Charging Current (0x14) register. The SBS specification asks

for 16 bits to set the charge current with a 1-mA LSB—giving a maximum possible current of 65.535 A using a

10-mΩ sense resistor. The bq24721 uses bits 7 – 14 only to limit the range within a practical operating range.

The current range is 0 mA to 16.384 A with an LSB of 128 mA using a 10-mΩ sense resistor. The charger is

disabled when the programmed input current is 0 A. The default power-up-reset current value is 0 A, charger

disabled. Other sense resistors can be used to set the charge current—the user needs to transform the DAC

current table values to the new current values by dividing the current by 10 mΩ, then multiplying by the new

sense resistor value used.

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Setting Input (DPM) Current (IDPM DAC register)

The input current can be similarly programmed using the Input Current (0x3F) register. The SBS specification

asks for 16 bits to set the input current with a 1-mA LSB—giving a maximum possible current of 65.535 A using

a 10-mΩ sense resistor. The bq24721 uses bits 7 – 14 only to limit the range within a practical operating range.

The current range is 0 mA to 16.384 A with an LSB of 128 mA using a 10-mΩ sense resistor. The charger is

disabled when the programmed input current is 0 A. The default power-up-reset current value is 0 A, charger

disabled. Other sense resistors can be used to set the input current—the user needs to transform the DAC

current table values to the new current values by dividing the current by 10 mΩ, then multiplying by the new

sense resistor value used.

Power Up

When the adapter is not detected, the REGN output voltage is 4.6 V and the VREF5 LDO regulator is off, to

lower the power consumption from the battery. The VREF5 LDO is pulled-down to AGND when the adapter is

not detected. The REGN LDO regulator begins to regulate at 4.6 V when the input VCC voltage is greater than

6 V. The REGN output voltage is then 6 V when the adapter is detected, and the VCC is greater than 7 V. If

adapter is detected, but VCC is less than 7 V, then the REGN is in dropout, and REGN output voltage depends

on the VCC voltage and REGN load current. The VREF5 LDO is allowed to turn-on and regulate to 5 V, 5 ms

after REGN is 6 V and the adapter is detected. There is a 500-ms delay from the time the adapter is detected,

until the ACFET from the system power selector is allowed to turn-on, and until the charger is allowed to turn-on.

The battery continues to be connected to the system during this 500-ms delay.

Adapter Detect

The adapter detect threshold is programmed by an external voltage divider resistor from the adapter to the

ACDET pin. The internal ACDET comparator has a 1.2-V rising-edge threshold and a 15-mV falling-edge

hysteresis. The adapter detect value is typically programmed to a value greater than the maximum battery

voltage, and lower than the minimum allowed adapter voltage. The ACDETECT divider is placed before the

BYPASS FET in order to sense the true adapter input voltage whether the BYPASS is on or off.

The VREF5 LDO output is also used to indicate when the adapter is detected, for both the bq24721 and the

bq24721, since the VREF5 LDO only comes up when the adapter is detected.

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System Power Selector

The bq24721 can automatically switch between adapter power or battery power to the system load. The battery

is connected to the system when there is no adapter detected. The adapter is connected to the system when the

adapter is detected. An automatic break-before-make logic prevents shoot-through currents when the selector

switches.

When no adapter is detected the ACDRV pin is pulled to the PVCC pin to keep the external ACFET p-channel

power MOSFET off, disconnecting the adapter from system. The break-before-make logic waits until the ACFET

is off and the System to battery voltage comparator indicates the system voltage is within 250 mV of the Battery

(SYS voltage falling-edge, with a 50-mV hysteresis SYS voltage rising-edge). This prevents shoot-through

currents or large discharge currents from going into the battery. The BATDRV pin is then set to the SYS pin

voltage minus 6 V by an internal regulator in order to turn on the external BATFET p-channel power MOSFET,

connecting the battery pack to the system.

When adapter is detected there is a 500-ms delay; then, the BATDRV is set to the SYS pin voltage to turn off

the external BATFET p-channel power MOSFET, in order to disconnect the battery. The break-before-make

logic waits until the BATFET is off to prevent shoot-through currents. The ACDRV pin is then set to the PVCC

pin voltage minus 6 V by an internal regulator in order to turn on the external ACFET p-channel power MOSFET,

connecting the adapter to the system.

The host can override the adapter to system connection when adapter is present, by setting the charger into

Learn Mode. The host can then induce a learn cycle in which the battery is allowed to discharge. A learn cycle is

used to recalibrate the fuel gauge for Ni-based batteries, or for clearing the memory effect of a Ni-cd battery.

After discharging the battery, Learn Mode can be disabled allowing the adapter to be reconnected to the system,

then resuming a normal charge cycle.

Whenever the battery is connected to the system (whether in learn cycle with adapter present, or no adapter

present), there is a Low Battery comparator that monitors the battery voltage, and alerts the host and charge

controller that the battery has been depleted. The BAT_DEP threshold can be programmed through the Charger

Mode control (0x12) register through bits b9-b11. The three bits can program the threshold between 2.2-V per

cell to 2.9-V per cell, in 100-mV increments. The number of cells is determined by the programmed battery

regulation voltage (0x15) register. If the battery voltage falls below the BAT_DEP threshold, then the battery is

disconnected from the system and the adapter is connected to the system. The Battery Voltage Low bit (b11) is

set in the Charger Status (0x13) register, and the ALARM pin is pulled low to alert the host. There is a 1 second

deglitch time to prevent false triggering.

The Charger Status (0x13) register bits b6 and b7 also always indicate whether the battery is connected to the

system (b6), or the adapter is connected to the system (b7). An alarm is triggered whenever these states

change.

Asymmetrical gate drives (100 Ω turn-off; 10 kΩ turn-on) for the ACDRV and BATDRV drivers provide fast

turn-off and slow turn-on of the ACFET and BATFET to help the break-before-make logic and to allow a

soft-start at turn-on of either FET. The soft-start time is further increased by putting a capacitor from gate to

source of the p-channel power MOSFETs.

Input Overcurrent Protection (ACOC)

For solutions using the selector functions, an input overcurrent protection function (ACOC) is provided which

disconnects the ACFET by turning off the ACDRV pin, whenever the sensed input current exceeds the

programmed ACOC threshold. The ACOC threshold is programmed through the SMBus Charge Mode (0x12)

control register, bits b6, b7, b8. The ACOC function is automatically disabled upon power-on-reset. The host

needs to enable it by setting the ACOC bit (b6) HI. The ACOC threshold is set by the SET_ACOC bits (b7, b8),

to thresholds of 130%, 150%, 170%, or 190% of the input current (DPM) regulation limit threshold from the Input

Current (0x3F) register.

The ACFET turns off when the sensed current exceeds the threshold after a 200-µs deglitch time. The ACFET

automatically turns on after 2 ms, to limit the on-time duty cycle, and limit the power dissipation on the ACFET.

Care must be taken to ensure the system load power does not exceed the power-up allowable power when the

ACOC function is used.

The function is not intended for system short-circuits, as usually the adapter self protects. Instead, the function is

intended for long-term overcurrent protection of the selector power devices, and to limit start-up peak current.

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Bypass FET

The BYPASS pin is used to control an input FET that is off to prevent reverse discharge from the battery to the

adapter, and is on during input current draw to the system or battery, to minimize the power dissipation, as

compared to using a Schottky diode. If no adapter is detected, the BYPASS FET is off, by setting the BYPASS

pin to the PVCC pin. When the adapter is detected there is a 500-ms delay, then an ACP-to-BAT voltage

comparator is used to control the BYPASS pin. The BYPASS driver is set to the PVCC pin voltage when the

adapter voltage (ACP pin) is not more than 250 mV (ACP voltage falling-edge) above the battery voltage (BAT

pin), in order to turn off the external BYPASS p-channel power MOSFET. There is a 50 mV (ACP voltage

rising-edge) hysteresis, to protect from noise and prevent chatter. When adapter is detected and the ACP pin

voltage is greater than 300 mV above the BAT pin voltage, the BYPASS pin voltage is set to PVCC pin voltage

minus 6 V, in order to turn on the external BYPASS p-channel power MOSFET.

The ACP-to-BAT comparator also prevents the battery voltage from holding-up the ACDET sensed value and

falsely detecting ACDET when the adapter is removed, this prevents the system power selector from getting

stuck in an adapter always detected state. When ACP gets near to BAT, the external BYPASS p-channel power

MOSFET is turned off. This isolates the ACDET network from the battery, and allows the adapter input node to

discharge to PGND.

The BYPASS driver has a symmetrical gate drive of 1 kΩ turn-on and turn-off and does not need to be slowed

down.

Enabling Charge

Charge is only enabled 500 ms after adapter is detected. To initiate charge the CHGEN pin must be low, and

the Charger Mode (0x12) register END CHARGE bit (b0) must be set LO. The power-on-reset default for the

END CHARGE bit is HI, disabling charge.

The Charger Status (0x13) register NOT READY TO CHARGE bit (b0) indicates whether the charger is ready to

charge. A HI indicates the charger is not ready to charge, while a LO indicates the charger is ready to charge.

The NOT READY TO CHARGE bit (b0) must be LO in order for the charger to be enabled. The conditions that

make the charger not ready to charge are: adapter not detected, 500-ms delay after adapter detected not over,

REGN voltage not up, or VREF5 voltage not up.

The Charger Status (0x13) register CHARGER NOT ON bit (b1) indicates whether the charger is not on (HI), or

the charger is on (LO). For charger to be on, the CHGEN pin must be low, the Charger Mode (0x13) register

END CHARGE bit (b0) must be LO, the, IC junction temperature must be below the TSHUT threshold,

overcurrent detected, or Thermistor Sense (TS) indicates battery pack is out of programmed permissible charge

temperature range (bq24721 only).

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ACP

+

-

VCC

I

REG

1 kW

(adapter)

+

-

ACN

1 V

+

-

ACSET

Adapter Current

DAC 6BIT

3.2 mV - 200 mV

CHARGE_ENZ

I_ACSET

VCC

SRP

SRN

I ( VCC/10)

RAMP

+

-

VCC

I

REG

1 kW

(BAT)

(V

PP

= VCC/10)

+

-

1 V

+

-

PWM

OSC

SRSET

Q

S

R

To Gate

DriveLogic

Charge Current

DAC 6BIT

3.2 mV - 200 mV

RAMP

CHARGE_ENZ

I_SRSET

BAT

Compensation

EAI

FBO

EAO

-

+

CLAMP

BAT

VCC

V

REG

VCC

(BAT)

+

-

SMBus

Cells

Select

Divider

1 V

Voltage

DAC 7BIT

2 V - 2.4 V

20 mA

CHARGE_EN_DG

Figure 57. PWM Control Logic

Converter Operation

The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme.

A type III compensation network allows using ceramic output capacitors. The compensation input stage is

connected between the feedback output (FBO) pin and the error amplifier input (EAI) pin. The feedback

compensation stage is connected between the error amplifier input (EAI) pin and error amplifier output (EAO)

pin.

An internal saw-tooth ramp is compared to the EAO pin error control signal to vary the duty-cycle of the

converter. The ramp height is one-tenth of the input adapter voltage making it always directly proportional to the

input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies

the loop compensation. The ramp is offset by 300 mV in order to allow zero percent duty-cycle, when the EAO

signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a

100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the

N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below

4.5 V for more than 3 cycles, then the high-set n-channel power MOSFET is turned off and the low-side

n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the

high-side driver returns to 100% duty-cycle operation until the voltage is detected to fall low again due to

leakage current discharging the BTST capacitor below the 4.5 V, and the reset pulse is reissued.

The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,

battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible

noise region. The switching frequency can be changed from 300 kHz to 500 kHz by the Charger Mode (0x12)

register PWM FS bit (b5) – a HI is 500 kHz, a LO is 300 kHz. The switching frequency is 300 kHs by default

after power-on-reset. Typical chargers use 300 kHz, but 500 kHz allows a smaller inductance value

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The charge current sense resistor should be placed with at least half or more of the total output capacitance

placed before the sense resistor contacting both sense resistor and the output inductor; and the other half or

remaining capacitance placed after the sense resistor. The output capacitance should be divided and placed

onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives the best performance; but the

node in which the output inductor and sense resistor connect should have a minimum of 50% of the total

capacitance. This capacitance provides sufficient filtering to remove the switching noise and give better sense

accuracy. The type III compensation is already providing phase boost near the cross-over frequency, giving

sufficient phase margin.

ISYNSET

The ISYNSET pin is used to program the charge current threshold at which the charger changes from

nonsynchronous operation into synchronous operation. This prevents negative inductor current. Negative

inductor current may cause a boost effect in which the input voltage increases as power is transferred from the

battery to the input capacitors—this can lead to an overvoltage on the PVCC node and potentially cause some

damage to the system.

This programmable value allows setting the current threshold for any inductor current ripple, and avoiding

negative inductor current. The SYNP and SYNN pins are used to sense across the charge current sense

resistor.

To program the threshold, a resistor is connected from the ISYNSET pin to AGND. The minimum synchronous

threshold should be set from the inductor current ripple to the full ripple current, where the inductor current ripple

is given by.

I

(RIPPLE_MAX)

£ I

(RIPPLE_MAX)

(SYN)

2

(1)

where

V

(

(BAT_MIN)

1

(

x

V

- V

(

(IN_MAX)

(BAT_MIN)

(

V

¦

(IN_MAX)

S

R

=

(RIPPLE_MAX)

L

(MIN)

(2)

V_{(IN_MAX)}is the maximum adapter voltage, V_{(BAT_MIN)}is the minimum battery voltage, f_Sis the switching

frequency, and LMIN is the minimum output inductor value.

The ISYNSET pin is internally regulated to 1 V. When the R_(SYNSET)resistor is connected to AGND, it sets an

ISYNSET current equal to 1 V/R_(SYNSET). The ISYNSET current internally flows through a 500 Ω creating a

voltage at which the voltage across R_(SENSE)is compared. The ISYN charge current threshold is the voltage

divided by the R_(SENSE)sense resistor value. The R_(SYNSET)resistor value is calculated by:

1 V x 500 W

R

=

(SYNSET)

I

x R

(SENSE)

(SYN)

(3)

where ISYN is the charge current threshold at which the converter changes to synchronous operation.

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SYNP

SYNN

ISYNC FET -

Charger Undercurrent

Comparator

+

−

500W

ISYNC_LOWD

−

+

t_bo

40ns

1V

+

−

ISYNSET

R_ISYNSET

CHARGE_ENZ

NOTE: Patent Pending

Figure 58. Synchronous to Nonsynchronous threshold, ISYNSET, Block – Charger Undercurrent

(prevents negative inductor current)

Synchronous versus Nonsynchronous Operation

The charger operates in nonsynchronous mode when the sensed charge current is below the ISYNSET

programmed value. When above the ISYNSET programmed value, the charger operates in synchronous mode.

During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel power

MOSFET is off. The internal gate drive logic ensures there is break-before-make switching to prevent

shoot-through currents. During the dead-time where both FETs are off, the back-diode of the low-side power

MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low, and

allows safely charging at high currents. During Synchronous mode the inductor current is always flowing and

operates in Continuous Conduction Mode (CCM) creating a fixed two-pole system. During nonsynchronous

operation: after the high-side n-channel power MOSFET turns off, and after the break-before-make dead-time,

the low-side n-channel power MOSFET turns on for around 80 ns, then the low-side power MOSFET turns off

and stays off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. The

80 ns low-side MOSFET on-time is done to ensure the bootstrap capacitor is always recharged and able to keep

the high-side power MOSFET on during the next cycle. This is important for battery chargers, where unlike

regular dc-dc converters, there is a battery load that maintains a voltage and can both source and sink current.

The 80 ns low-side pulse pulls the PH node (connection between high and low-side MOSFET) down, allowing

the bootstrap capacitor to recharge up to the REGN LDO value. After the 80 ns, the low-side MOSFET is kept

off to prevent negative inductor current from occurring. The inductor current is blocked by the off low-side

MOSFET, and the inductor current becomes discontinuous. This mode is called Discontinuous Conduction Mode

(DCM).

During the DCM mode the loop response automatically changes and has a single pole system at which the pole

is proportional to the load current, because the converter does not sink current, and only the load provides a

current sink. This means at very low currents the loop response is slower, as there is less sinking current

available to discharge the output voltage.

At very low currents during nonsynchronous operation, there may be a small amount of negative inductor current

during the 80 ns recharge pulse. The charge should be low enough to be absorbed by the input capacitance.

Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn-on, and the

low-side MOSFET does not turn-on (no 80 ns recharge pulse), so there is no discharge from the battery.

Battery Voltage Regulation Loop

The BAT pin is used to sense the battery voltage and should be connected as close to the battery as possible,

or directly to the output capacitor. A 0.1-µF ceramic capacitor from BAT to AGND is recommended—added as

close to the BAT pin as possible to decouple high frequency noise.

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The voltage regulation feedback is through the BAT pin. This input is tied directly to the positive side of the

battery pack. The bq24721 monitors the battery-pack voltage between the BAT and VSS pins. The regulation

voltage is programmed through the SBS-like SMBus interface.

The voltage regulation DAC register input is decoded into an internal 7-bit DAC that programs the voltage on a

per-cell basis, then is multiplied by the number of cells. There are a total of 128 voltage steps with a 6.25 mV

step, giving a per cell range of [4 V – (4.8 V–6.25 mV)]. There are 128 steps in the 3-cell voltage range of

[12 V – (14.4 V–18.75 mV)]. There are 128 steps in the 4-cell voltage range of [16 V – (19.2 V–25 mV)].

Valid voltage values are 9 V, 12 V–14.381 V, and 16 V–19.175 V. The internal voltage DAC allows programming

to 9 V which is used for waking-up or closing the battery pack. A 9 V programmed voltage is interpreted as a

2-cell voltage by the BATDEP and BATSHORT thresholds. Step size for 3-cell battery programming voltage is

18.75 mV. The Charger interprets a 3-cell battery for any voltage between 12 V–14.4 V. Step size for 4-cell

battery programming voltage is 25 mV. The charger interprets a 4-cell battery for any voltage programmed

between 16 V–19.2 V.

Invalid DAC voltages are indicated by the VOR (voltage out of range) bit of the status register. Voltages below

12 V (except for 9 V) are out of range and keep the converter disabled. Voltages between 14.4 V–16 V

(including 14.4 V, but not including 16 V) are out of range and keep the converter disabled. Voltages above 19.2

V (including 19.2 V) are out of range and allow the converter to charge, but the voltage is always set to the

maximum allowable voltage of 19.175 V = (19.2 V–25 mV).

Battery Charge Current Regulation Loop

The battery charge current DAC is set for a 10-mΩ sense resistor; however, resistors of other values can also

be used. The larger the sense resistance, the larger the sensed voltage, and the higher the regulation accuracy,

but at the expense of higher conduction losses. The SRP and SRN pins are used to sense across the sense

resistor.

The battery charge current, I_O(CHARGE), is established by setting the external sense resistor, R_{(SNS_CHG)}, and the

SMBus charge current DAC (0 × 14). In order to set the current, first R_{(SNS_CHG)}should be chosen based on the

regulation threshold V_{(IREG_CHG)}, across this resistor. The listed SBS current corresponds to a 10-mΩ sense

resistor.

R_{(SNS_CHG)}= V_{(IREG_CHG)}/ I_O(CHARGE)

Input Current Regulation Loop (DPM)

The ACP and ACN pins are used to sense across the sense resistor. The input current DAC is set for a 10-mΩ

sense resistor; however, resistors of other values can also be used. The larger the sense resistance, the larger

the sensed voltage, and the higher the regulation accuracy, but at the expense of higher conduction losses.

The input current, I_I(DPM), is established by setting the external sense resistor, R_{(SNS_DPM)}, and the SMBus input

current DAC (0 × 3F). In order to set the current, first R_{(SNS_DPM)}is chosen based on the regulation threshold

V_{(IREG_DPM)}, across this resistor. The listed SBS current corresponds to a 10-mΩ sense resistor.

R_{(SNS_DPM)}= V_{(IREG_DPM)}/ I_O(CHARGE)

Automatic Internal Soft-Start Charger Current

The charger automatically soft-starts the charger regulation current every time the charger is enabled, in order to

ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of

stepping-up the charge regulation current into eight evenly divided steps up to the programmed charge current

of register (0x14). Duration of each step is around 1 ms, for a typical rise time of 8 ms. No external components

are needed for this function.

The bq24721 current regulation loop reference steps-up whenever charge is enabled, and when returning from

fault/suspend mode into charge where the current regulator is turned on. The loop should take control within a

few hundred micro-seconds with very little overshoot due to the LC output filter and the high compensation loop

bandwidth with 300 kHz or 500 kHz operating frequency; therefore, the reference could ramp up from precharge

to fast-charge within 50 µs to 500 ms. Going into fault/suspend mode, short circuit (V_(BAT)< V_(UVT)), Sleepmode

(V_(ACP)< V_(BAT)), or UVLO (VCC < 3.7 V) initiates an immediate shut-off of the high-side PWM FET by setting its

gate to V_(PH). The output inductor and battery load determines the ramp-down rate as it freewheels through the

Schottky diode.

33

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SLUS683C–NOVEMBER 2005–REVISED DECEMBER 2006

High Accuracy Current Sense Amplifiers (CSA), IOUT pin, for Input Current and Charge Current

Industry standard, high accuracy current sense amplifiers (CSA) can be used to monitor the input current or the

charge current by the host or some discrete logic through the analog voltage output of the IOUT pin. The current

sense amplifier from the input current and the current sense amplifier of the charge current (voltage across

SRP-SRN pins) amplifies the input sensed voltage by 20x, through the Iout pin. The IOUT output is selectable

between the input current or the charge current, through a multiplexor that is controlled by the Charge Mode

(0x12) control register, IOUT Select bit (b3). The default setting is LO selecting the input current CSA.

Programming a HI selects the charger current CSA.

The IOUT output is a voltage source 20 times the input differential voltage. If the user wants to lower the

voltage, use a sense resistor from IOUT to AGND, and still achieve accuracy overtemperature as the resistors

match their thermal coefficients.

A 0.1-µF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional

RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response

delay.

Charger Overcurrent Protection

The charger has a secondary overcurrent protection function that monitors the charge current, and prevents it

from exceeding 200% of the programmed charge current. The high-side gate drive turns off and automatically

resume when the current falls below the overcurrent threshold

Current Regulation Down to Zero Battery Voltage

The bq24721 charger regulates charge current and input current down to zero volts on the battery BAT voltage.

If there is a drop below 2 V, then the converter immediately turns off both high-side and low-side FETs to stop

current flow, then resumes regulating the current. This ensures there is no overcurrent surge that could cause

damage to the battery, charger, or system.

Thermal Shutdown Protection

The QFN package has low thermal impedance which provides good thermal conduction from the silicon to the

ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and

self-protects whenever the junction temperature exceeds the T_(SHUT)threshold of 145°C. The charger stays off

until the junction temperature falls below 130°C.

Battery Short-Circuit or Low Condition

The number of cells determines the value for the BATDEP threshold and for the BATSHORT threshold, as these

values are programmed on a per-cell basis. The programmed regulation voltage determines the number of cells.

The battery depleted (BATDEP) threshold is programmed by the control register bits b9-b11. The three bit dac

sets the voltage between 2.2 V to 2.9 V per cell at 100 mV increments. The BATSHORT threshold is 1.7 V/Cell

falling entering a shorted condition, and 1.9 V/Cell rising leaving shorted condition, and entering normal

condition. BATSHORT has a 1 second deglitch on both edge directions to protect from transient conditions, and

to allow closing deeply discharge battery packs.

The PWM duty-cycle immediately resets to zero percent when the battery voltage is sensed to drop below 2 V,

then the regulation loop allows the duty-cycle to settle in the current regulation value, C. After a 1 second

deglitch, the converter regulates battery current to C/8 when the battery voltage falls below 1.7 V/cell. The

converter regulates back at C after a 1 second deglitch from the time the battery voltage rises above 1.9 V/cell.

Charge Termination for Li-Ion or Li-Polymer

The primary termination method for Li-Ion and Li-Polymer is minimum current. Secondary temperature

termination methods is also provided for additional safety. The host controls the charge initiation and the

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