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产品型号BQ76925RGER的概述

BQ76925RGER芯片概述 BQ76925RGER芯片是由德州仪器（Texas Instruments）公司推出的一款集成电池监控与保护功能的IC。该芯片专为多节锂离子或锂聚合物电池组开发，广泛应用于电动车、电池储能系统、便携式设备及其他需要高能量密度的应用领域。BQ76925RGER支持高电压和智能电池管理系统，具备较高的集成度，能够有效地管理电池的安全性和使用寿命。该芯片主要功能包括电池电压测量、温度监测、过压和欠压保护、短路保护等。BQ76925RGER以其高精度的电压测量和灵敏的保护机制，为锂电池组提供了强大的安全保障。 BQ76925RGER详细参数 ### 基本参数 - 电源电压范围：5V到32V - 工作温度范围：-40°C到85°C - 最大直流电流：6A - 电池节数支持：最多可支持25节锂离子电池 - 电压测量精度：±10mV - 电流测量精度：±1% ...

产品型号BQ76925RGER的Datasheet PDF文件预览

bq76925

www.ti.com

SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

Host Controlled Analog Front End for 3-Series to 6-Series Cell Li-Ion/Li-Polymer Battery

Protection and Gas Gauging Applications

Check for Samples: bq76925

FEATURES

DESCRIPTION

The bq76925 Host controlled analog front end (AFE)

is part of a complete pack monitoring, balancing and

protection system for 3-, 4-, 5-, or 6-series cell Li-Ion

and Li-Polymer batteries. The bq76925 allows a Host

controller to easily monitor individual cell voltages,

pack current and temperature. This information may

be used by the Host to determine unsafe or faulty

•

Analog Interface for Host cell Measurement

–

Cell Input MUX, Level Shifter, and Scaler

1.5-/ 3.0-V Low-Drift, Calibrated Reference

Allows Accurate Analog to Digital

Conversions

•

Analog Interface for Host Current

Measurement

operating

conditions

such

overvoltage,

undervoltage, over-temperature and overcurrent, as

well as cell imbalance, state of charge and state of

health conditions.

–

Variable Gain Current Sense Amplifier

Capable of Operation with 1-mΩ Sense

Resistor

Cell input voltages are level-shifted, multiplexed,

scaled, and output for measurement by a Host ADC.

A low-drift calibrated reference voltage is provided on

a dedicated pin to enable accurate measurements.

•

Switchable Thermistor Bias output for Host

Temperature Measurements

Overcurrent Comparator with Dynamically

Adjustable Threshold

The voltage across an external sense resistor is

amplified and output to a Host ADC for both charge

and discharge current measurements. Two gain

settings enable operation with a variety of sense

resistor values over a wide range of pack currents.

–

Alerts Host to Potential Overcurrent Faults

May be used to Wake up Host on Load

Connect

•

Integrated Cell Balancing FETs

To enable temperature measurements by the Host,

the AFE provides a separate output pin for biasing an

external thermistor network. This output can be

switched on and off under Host control to minimize

power consumption.

–

Individual Host Control

50 mA per-cell Balancing Current

•

Supports Cell Sense-line Open Wire Detection

Integrated 3.3-V Regulator for Powering

Micro-controller and/or LEDs

I²C Interface for Host Communications

The bq76925 includes

comparator with

dynamically selectable threshold for monitoring

current. The comparator result is driven through an

open-drain output to alert the host when the threshold

is exceeded. This feature can be used to wake up the

Host on connection of the load, or to alert the Host to

a potential fault condition.

•

–

Optional Packet CRC for Robust Operation

•

Supply Voltage Range From 4.2 to 26.4 V

Low Power Consumption

–

40 µA Typical in Normal Mode

1.5 µA Maximum in Sleep Mode

The bq76925 integrates cell balancing FETs that are

fully controlled by the Host. The balancing current is

set by external resistors up to a maximum value of 50

mA. These same FETs may be utilized in conjunction

with cell voltage measurements to detect an open

wire on a cell sense-line.

•

20-pin TSSOP or 24-pin QFN Package

APPLICATIONS

•

Primary Protection in Li-Ion Battery Packs

The Host communicates with the AFE via an I²C

interface. A packet CRC may optionally be used to

ensure robust operation. The device may be put into

a low-current sleep mode via the I²C interface and

awakened by pulling up the ALERT pin.

–

Cordless Power Tools

Light Electric Vehicles (E-Bike, Scooter,

etc.)

–

UPS Systems

Medical Equipment

Portable Test Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq76925

SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PIN DIAGRAMS

PW PACKAGE

(TOP VIEW)

RGE PACKAGE

(TOP VIEW)

VCTL

BAT

VC6

VC5

VC4

VC3

VC2

VC1

VC0

VSS

V3P3

24 23 22 21 20 19

SCL

VC6

VC5

VC4

VC3

VC2

VC1

SDA

VREF

VTB

VREF

VTB

bq76925

VCOUT

VIOUT

ALERT

VCOUT

VIOUT

ALERT

SENSEP

SENSEN

10 11 12

PIN FUNCTIONS

PIN NO.

NAME

TYPE

DESCRIPTION

TSSOP

QFN

VCTL

BAT

Output

Power

Input

Power

3.3-V Regulator control voltage⁽¹⁾

Supply voltage, tied to most positive cell

Sense voltage for most positive cell

Sense voltage for second most positive cell

Sense voltage for third most positive cell

Sense voltage for fourth most positive cell

Sense voltage for fifth most positive cell

Sense voltage for least positive cell

Sense voltage for negative end of cell stack

Ground

VC6

VC5

VC4

VC3

VC2

VC1

VC0

VSS

No Connection (leave open)

SENSEN

SENSEP

ALERT

VIOUT

VCOUT

VTB

Input

Output

Negative current sense

Positive current sense

Overcurrent alert (open drain)

Current measurement voltage

Cell measurement voltage

Bias voltage for thermistor network

Reference voltage for ADC

VREF

SDA

Input / Output I²C Data (open drain)

SCL

Input

Output

I²C Clock (open drain)

V3P3

3.3-V Regulator

No Connection (leave open)

(1) When a bypass FET is used to supply the regulated 3.3-V load current, VCTL automatically adjusts to keep V3P3 = 3.3 V. If VCTL is

tied to BAT, the load current is supplied through V3P3.

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bq76925

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SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

FUNCTIONAL BLOCK DIAGRAM

PACK+

Bypass FET (optional)

Hold-up

circuit

(optiona)l

3.3 V

µC / LED

Supply

R_VCTL

D_BAT

R_BAT

BAT

VCTL

VREG

Z_BAT

C_BAT

POR

V3P3

VC6

C_V3P3

R_IN

C_IN

Cell Select

Bal Select

VC5

VC4

VC3

VC2

VC1

SCL

I2C

R_IN

I2C

Interface

SDA

REGS

Cell MUX

Ref Select

Level Shift

VREF

ADC

Reference

1.5 / 3.0 V

REF

Balance

Control

C_REF

REF×0.5

VTB

REF×0.85

ADC Ch 1

Temp

R_TH

R_NTC

C_TH

VCOUT

Amp

–

ADC Ch 2

Cell Voltage

C_IN

C_OUT

Gain = 0.3, 0.6

C_IN

VC0

VIOUT

ADC Ch 3

Pack Current

Shunt Select

VSS

C_OUT

Gain Select

Amp

–

SENSEN

Wakeup

Detect

Overcurrent

Alert

R_SENSE

R_SENSEN

ALERT

Gain = 4, 8

Output Range = 1 V, 2 V

C_SENSE

SENSEP

Amp

–

R_SENSEP

Comp

–

I_THRESH

Gain = 1

25,50,75,100,…,400 mV

Polarity Select

bq76925

PACK–

ORDERING INFORMATION⁽¹⁾

PACKAGE

T_A

PART NUMBER⁽²⁾

bq76925PW

20-Pin PW

–25°C to 85°C

24-Pin RGE

bq76925RGE

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) The PW and RGE package options are also available taped and reeled. Add an R suffix to the device type (e.g., bq76925PWR for 2000

units per reel). See applications section of data sheet for layout information.

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bq76925

SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

RANGE⁽²⁾

MAX

MIN

UNITS

Supply

V_BAT

voltage

range

BAT

–0.3

Cell input differential, VCn to VCn+1, n = 0 to 5

Cell input, VCn, n = 1 to 6

–0.3

–10

–3

(6 × n)

Input

BAT to VC6 differential

V_I

voltage

range

(3)

VC0

SENSEP, SENSEN

SCL, SDA

–3

–0.3

VCOUT, VIOUT, VREF

VTB, V3P3

3.6

Output

voltage

range

V_O

ALERT

150

VCTL

I_CB

Cell balancing current

Cell input current

°C

I_IN

–25

–65

T_STG

Storage temperature range

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only. Functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating

Conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltages are relative to VSS, except “Cell input differential.”

(3) Negative voltage swings on VC0 in the absolute maximum range can cause unwanted circuit behavior and should be avoided.

THERMAL INFORMATION

bq76925

TSSOP

(PW PACKAGE)

QFN

(RGE PACKAGE)

THERMAL METRIC⁽¹⁾

UNITS

(20) PINS

97.5

31.7

48.4

1.5

(24) PINS

36.0

38.6

14.0

0.6

θ_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

θ_{JC (top)}

θ_JB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

47.9

n/a

14.0

4.6

θ_{JC (bottom)}Junction-to-case (bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

RECOMMENDED OPERATING CONDITIONS⁽¹⁾

MIN

4.2

TYP

MAX

26.4

4.4

UNIT

Supply voltage range

BAT

Cell input differential, VCn to VCn+1, n = 0 to 5

Cell input, VCn, n = 1 to 6

BAT to VC6 differential

VC0, SENSEN

1.4

4.4 × n

–8

V_IN

Input voltage range

SENSEP

–125

375

5.5

SCL, SDA

V3P3

Backfeeding⁽²⁾

5.5

ALERT

Wakeup function

26.4

V3P3 +

0.2

VCOUT, VIOUT

REFSEL = 0

1.5

3.0

VREF

REFSEL = 1

V_OUT

Output voltage range

VTB

5.5

V3P3

VCTL

ALERT

Regulating

3.3

0.8

26.4

5.5

Alert function

I_CB

Cell balancing current

R_BAT

C_BAT

R_IN

BAT filter resistance

100

⁽³⁾100

BAT filter capacitance

µF

Ω

External cell input resistance

External cell input capacitance

C_IN

0.1

µF

R_SENSEN

R_SENSEP

Current sense input filter resistance

Current sense input filter capacitance

Ω

C_SENSE

0.1

µF

Without external bypass transistor

With external bypass transistor

Without external bypass transistor

With external bypass transistor

R_VCTL

VCTL pullup resistance

Ω

200K

4.7

1.0

C_V3P3

C_REF

C_OUT

V3P3 output capacitance

µF

VREF output capacitance

ADC channel output capacitance

1.0

0.1

µF

°C

VCOUT

VIOUT

470

–25

–40

2000

T_OPR

Operating free-air temperature

Functional free-air temperature

T_FUNC

100

(1) All voltages are relative to VSS, except “Cell input differential.”

(2) Internal 3.3-V regulator may be overridden (i.e. backfed) by applying an external voltage larger than the regulator voltage.

(3) R_IN,MIN= 0.5 × (VCn_MAX/ 50 mA) if cell balancing used so that maximum recommended cell balancing current is not exceeded.

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SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

www.ti.com

ELECTRICAL CHARACTERISTICS

BAT = 4.2 to 26.4 V, VCn = 1.4 to 4.4, T_A= –25°C to 85°C

Typical values stated where T_A= 25°C and BAT= 21.6 V (unless otherwise noted)

Supply Current

PARAMETER

TEST CONDITION

All device functions enabled

MIN

TYP

MAX

UNIT

I_DD1

Normal mode supply current

All pins unloaded

µA

SDA and SCL high

V3P3 and overcurrent monitor enabled

All pins unloaded

All other device functions disabled

SDA and SCL high

I_DD2

Standby mode 1 supply current

Standby mode 2 supply current

Sleep mode supply current

µA

V3P3 enabled

All pins unloaded

All device functions disabled

SDA and SCL high

I_DD3

I_DD4

I_VCn

V3P3 disabled

All pins unloaded

All device functions disabled

SDA and SCL low

1.0

2.4

1.5

µA

All cell voltages equal

Cell balancing disabled

Open cell detection disabled

during cell voltage monitoring

n = 6

2.7

Input current for selected cell

µA

n = 1 – 5

< 0.5

All cell voltages equal

∆I_VCnCell to cell input current difference Cell balancing disabled

< 0.2

Open cell detection disabled

Internal Power Control (Startup and Shutdown)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Initial BAT < 1.4

4.3

4.5

4.7

VBAT rising⁽¹⁾

V_POR

Power on reset voltage

Shutdown voltage⁽²⁾

Measured at BAT pin

Initial BAT > 1.4

6.5

7.0

7.5

3.6

VBAT rising⁽¹⁾

V_SHUT

t_POR

Measured at BAT pin, BAT falling

Time delay after POR before I2C

comms allowed

CV3P3 = 4.7 µF

V_WAKE

Wakeup voltage

Measured at ALERT pin

0.8

t_{WAKE_PLS}Wakeup signal pulse width

μs

Time delay after wakeup before

t_{WAKE_DLY}

CV3P3 = 4.7 µF

I2C comms allowed

(1) Initial power up will start with BAT < 1.4 V, however if BAT falls below V_SHUTafter rising above V_POR, the power on threshold depends

on the minimum level reached by BAT after falling below V_SHUT

(2) Following POR, the device will operate down to this voltage.

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SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

3.3 V Voltage Regulator

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

3.3 V VOLTAGE REGULATOR

(1)(2)

V_CTL

Regulator control voltage

Regulator output

Measured at VCTL, V3P3 regulating

3.3

3.2

26.4

3.4

V_V3P3

Measured at V3P3, I_REG= 0 to 4 mA,

BAT = 4.2 to 26.4 V

3.3

I_REG

I_SC

V3P3 output current

4.0

V3P3 short circuit current limit

Thermistor bias voltage

Thermistor bias current

V3P3 = 0.0 V

10.0

17.0

V_TB

I_TB

Measured at VTB, I_TB= 0

V_V3P3

1.0

Ω

R_TB

Thermistor bias internal resistance R_DS,ONfor internal FET switch, I_TB= 1.0 mA

130

(1) When a bypass FET is used to supply the regulated 3.3V load current, VCTL automatically adjusts to keep V3P3 = 3.3 V. Note that

V_CTL,MINand the FET V_GSwill determine the minimum BAT voltage at which the bypass FET will operate.

(2) If VCTL is tied to BAT, the load current is supplied through V3P3.

Voltage Reference

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

VOLTAGE REFERENCE

Before gain correction, T_A= 25°C

REF_SEL = 0

REF_SEL = 1

REF_SEL = 0

REF_SEL = 1

VCOUT_SEL = 2

1.44

2.88

1.56

3.12

V_REF

Voltage reference output

After gain correction, ⁽¹⁾T_A= 25°C

–0.1%

1.5

3.0

+0.1%

–0.9% 0.5 × +0.9%

V_REF

Reference calibration

voltage

VCOUT_SEL = 3

–0.5% 0.85 × +0.5%

V_{REF_CAL}

Measured at VCOUT

V_REF

(0.85 × V_REF) – (0.5 –0.3% 0.35 × +0.3%

× V_REFV_REF

)

∆V_REF

Voltage reference tolerance T_A= 0 – 50°C

–40

ppm/

°C

I_REF

VREF output current

µA

(1) Gain correction factor determined at final test and stored in non-volatile storage. Gain correction is applied by Host controller.

Cell Voltage Amplifier

PARAMETER

TEST CONDITION

REF_SEL = 0

MIN

–1.6%

–16

TYP

0.3

MAX

1.5%

UNIT

G_VCOUTCell voltage amplifier gain

O_VCOUTCell voltage amplifier offset

Measured from VCn to VCOUT

Measured at VCOUT, VCn = 5.0 V

REF_SEL = 1

0.6

REF_SEL = 0

REF_SEL = 1

1.47

1.5

3.0

0.0

1.53

3.06

(1)

V_COUT

Cell voltage amp output range

2.94

Measured at VCOUT, VCn = 0.0 V

VCn = 1.4 V to 4.4 V, After

T_A= 25°C

–3

–5

–8

(2)

correction,

T_A= 0°C to 50°C

∆V_COUTCell voltage amplifier accuracy

(3)

Measured at VCOUT

REF_SEL = 1⁽⁴⁾

T_A= –25°C to 85°C

I_VCOUT

t_VCOUT

(1) For VCn values greater than 5.0 V, VCOUT clamps at approximately V3P3.

VCOUT output current⁽⁵⁾

Delay from VCn select to VCOUT Output step of 200 mV. C_OUT= 0.1 µF

100

µA

µs

(2) Correction factor determined at final test and stored in non-volatile storage. Correction is applied by Host controller.

(3) Output referred. Input referred accuracy is calculated as ∆V_COUT/ G_VCOUT(e.g. 3 / 0.6 = 5).

(4) Correction factors are calibrated for gain of 0.6. Tolerance at gain of 0.3 is approximately doubled. Contact TI for information on devices

calibrated to a gain of 0.3.

(5) Max DC load for specified accuracy.

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SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

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UNIT

Current Sense Amplifier

PARAMETER

TEST CONDITION

I_GAIN = 0

MIN

TYP

MAX

Measured from SENSEN,

SENSEP to VIOUT

G_VIOUTCurrent sense amplifier gain

I_GAIN = 1

Measured from SENSEN,

SENSEP to VSS

V_IIN

Current sense amp input range

Current sense amp output range

–125

375

REF_SEL = 0

REF_SEL = 1

REF_SEL = 0

REF_SEL = 1

0.25

0.5

1.25

2.5

Measured at VIOUT

V_IOUT

1.0

2.0

Measured at VIOUT

SENSEP = SENSEN

Zero current output

∆V_IOUTCurrent amplifier accuracy

–1%

(1)

IV_IOUT

VIOUT output current

µA

(1) Max DC load for specified accuracy

Over Current Comparator

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

V_{BAT_COMP}

G_VCOMP

V_ITRIP

Minimum VBAT for comparator operation⁽¹⁾

Measured from SENSEP to comparator

input

Comparator amplifier gain

Current comparator trip threshold⁽²⁾

–6

400

V_ITRIP= 25 mV

∆V_ITRIP

Current comparator accuracy

ALERT Output Low Logic

V_ITRIP> 25 mV

–10%

10%

0.4

V_{OL_ALERT}

V_{OH_ALERT}

I_ALERT

I_ALERT= 1 mA

(3)

ALERT Output High Logic

ALERT Pulldown current

ALERT Leakage current

Comparator response time

ALERT = 0.4 V, Output driving low

ALERT = 5.0 V, Output high-Z

μA

µs

I_{ALERT_LKG}

t_OC

< 1

100

(1) The Over Current Comparator is not guaranteed to work when VBAT is below this voltage.

(2) Trip threshold selectable from 25, 50, 75, 100, 125, 150, 175, 200, 225, 250, 275, 300, 325, 350, 375 or 400 mV

(3) This parameter NA because output is open drain.

Internal Temperature Measurement

PARAMETER

TEST CONDITION

MIN

TYP

1.2

MAX UNIT

V_{TEMP_INT}

Internal temperature voltage

Internal temperature voltage sensitivity

Measured at VCOUT, T_INT= 25°C

1.15

1.25

∆V_{TEMP_INT}

–4.4

mV /

ºC

Cell Balancing and Open Cell Detection

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

R_DS,ONfor VC1 internal FET switch,

VCn = 3.6 V

R_BAL

Cell balancing internal resistance⁽¹⁾

Ω

R_DS,ONfor internal VC2 to VC6 FET switch,

VCn = 3.6 V

5.5

(1) Balancing current is not internally limited. The cell balancing operation is completely controlled by the Host processor, no automatic

function or time-out is included in the part. Care must be used to ensure that balancing current through the part is below the maximum

power dissipation limit. The Host algorithm is responsible for limiting thermal dissipation to package ratings.

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SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

I²C Compatible Interface

DC PARAMETERS

MIN

TYP

MAX UNIT

V_IL

Input Low Logic Threshold

Input High Logic Threshold

Output Low Logic Drive

0.6

V_IH

V_OL

2.8

I_OL= 1 mA

0.20

0.40

I_OL= 2.5 mA

V_OH

I_LKG

Output High Logic Drive (Not applicable due to open-drain outputs)

I²C Pin Leakage

Pin = 5.0 V, Output in high-Z

N/A

< 1

µA

AC PARAMETERS

t_r

SCL, SDAꢀRise Time

1000

300

µs

kHz

t_f

SCL, SDAꢀFall Time

t_w(H)

SCL Pulse Width High

4.0

4.7

4.0

250

0⁽¹⁾

4.0

4.7

t_w(L)

SCL Pulse Width Low

t_su(STA)

t_h(STA)

t_su(DAT)

t_h(DAT)

t_su(STOP)

t_su(BUF)

t _V

Setup time for START condition

START condition hold time after which first clock pulse is generated

Data setup time

Data hold time

Setup time for STOP condition

Time the bus must be free before new transmission can start

Clock Low to Data Out Valid

900

t_h(CH)

f_SCL

Data Out Hold Time After Clock Low

Clock Frequency

100

2.5

t_WAKE

I2C ready after transition to Wake Mode

(1) Devices must provide internal hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.

SCL

SDA

SCL

SDA

SCL

SDA

Figure 1. I²C Timing

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OPERATIONAL OVERVIEW

INTRODUCTION

The bq76925 Host controlled analog front end (AFE) is part of a complete pack monitoring, balancing and

protection system for 3 to 6 series cell Lithium batteries. The bq76925 allows a Host controller to easily monitor

individual cell voltages, pack current and temperature. This information can be used by the Host to detect and

act on a fault condition caused when one or more of these parameters exceed the limits of the application. In

addition, this information may be used by the Host to determine end-of-charge, end-of-discharge and other

gas-gauging and state of health conditions.

PACK+

VCTL

V3P3

AVCC

DVCC

BAT

VC6

VC5

VC4

VC3

VC2

VC1

SCL

SDA

SCL

SDA

P1.5

COMM

µController

VREF

VTB

VeREF+

Example:

bq76925

MSP430x20x2

equivalent

R_TH

R_NTC

VCOUT

VIOUT

ALERT

VeREF-

VC0

AVSS

DVSS

VSS

R_SENSE

NMI

SENSEN

SENSEP

Note: Some components

omitted for clarity.

FET Driver Circuits

PACK-

Example only. Not required.

Figure 2. Example of bq76925 With Host Controller

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POWER MODES

Power On Reset (POR)

When initially powering up the bq76925, the voltage on the BAT pin must exceed V_POR(4.7 V max) before the

device will turn on. Following this, the device will remain operational as long as the voltage on BAT remains

above V_SHUT(3.6 V max). If the BAT voltage falls below V_SHUTthe device will shut down. Recovery from

shutdown occurs when BAT rises back above the V_PORthreshold and is equivalent to a POR. The V_PORthreshold

following a shutdown depends on the minimum level reached by BAT after crossing below V_SHUT. If BAT does

not fall below ~1.4 V, a higher V_POR(7.5 V max) applies. This is illustrated in Figure 3.

V_BAT

V_POR

Initial BAT > 1.4 V

V_POR

Initial BAT < 1.4 V

V_SHUT

1.4 V

OFF

Figure 3. Power On State vs V_BAT

Following a power on reset, all volatile registers assume their default state. Therefore, care must be taken that

transients on the BAT pin during normal operation do not fall below V_SHUT. To avoid this condition in systems

subject to extreme transients or brown-outs, a hold-up circuit such as the one shown in the functional diagram is

recommended. When a hold-up circuit is used, care must be taken to observe the BAT to VC6 maximum ratings.

Standby

Individual device functions such as cell translator, current amplifier, reference and current comparator can be

enabled and disabled under Host control by writing to the POWER_CTL register. This feature can be used to

save power by disabling functions that are unused. In the minimum power standby mode, all device functions can

be turned off leaving only the 3.3 V regulator active.

Sleep

In addition to standby, a sleep mode is provided by which the Host can order the bq76925 to shutdown all

internal circuitry including the LDO regulator. In this mode the device will consume a minimal amount of current

(< 1.5 μA) due only to leakage and powering of the wake-up detection circuitry.

Sleep mode is entered by writing a ‘1’ to the SLEEP bit in the POWER_CTL register. In sleep mode, all functions

including the LDO are disabled. Wake-up is achieved by pulling up the ALERT pin; however the wake-up circuitry

is not armed until the voltage at V3P3 drops to ~0 V. To facilitate the discharge of V3P3, an internal 3-kΩ

pull-down is connected from V3P3 to VSS during the time that sleep mode is active. Once V3P3 is discharged,

the bq76925 may be awakened by pulling the ALERT pin above V_WAKE(2 V max).

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The SLEEP_DIS bit in the POWER_CTL register acts as an override to the sleep function. When SLEEP_DIS is

set to ‘1’, writing the SLEEP bit has no effect (i.e. sleep mode cannot be entered). If SLEEP_DIS is set after

sleep mode has been entered, the device will immediately exit sleep mode. This scenario can arise if

SLEEP_DIS is set after SLEEP is set, but before V3P3 has discharged below a valid operating voltage. This

scenario can also occur if the V3P3 pin is held up by external circuitry and not allowed to fully discharge.

If the over-current alert function is not used, the ALERT pin can function as a dedicated wake-up pin. Otherwise,

the ALERT pin will normally be pulled up to the LDO voltage, so care must be taken in the system design so that

the wake-up signal does not interfere with proper operation of the regulator.

Internal LDO Voltage Regulator

The bq76925 provides a regulated 3.3 V supply voltage on the V3P3 pin for operating the device’s internal logic

and interface circuitry. This regulator may also be used to directly power an external microcontroller or other

external circuitry up to a limit of 4 mA load current. In this configuration, the VCTL pin is tied directly to the BAT

pin. For applications requiring more than 4 mA, an external bypass transistor may be used to supply the load

current. In this configuration the VCTL pin is tied to the gate of the bypass FET. These two configurations are

show in Figure 4.

PACK+

3.3 V

R_VCTL

BAT

R_BAT

C_BAT

R_BAT

BAT

VCTL

V3P3

VCTL

V3P3

VREG

C_BAT

C_V3P3

bq76925

a) Regulator load supplied through bq76925

b) Regulator load supplied through external

pass device

Figure 4. LDO Regulator Configurations

For the configuration of Figure 4B), a high gain bypass device should be used to ensure stability. A bipolar PNP

or p-channel FET bypass device may be used. Contact TI for recommendations.

The LDO regulator may be overridden (i.e., back-fed) by an external supply voltage greater than the regulated

voltage on V3P3. In this configuration the bq76925 internal logic and interface circuitry will operate from the

external supply and the internal 3.3 V regulator will supply no load current.

ADC Interface

The bq76925 is designed to interface to a multi-channel analog-to-digital converter (ADC) located in an external

Host controller, such as an MSP430 Microcontroller or equivalent. Three outputs provide voltage, current and

temperature information for measurement by the Host. In addition, the bq76925 includes a low-drift calibrated 1.5

/ 3 V reference that is output on a dedicated pin for use as the reference input to the ADC.

The gain and offset characteristics of the bq76925 are measured during factory test and stored in non-volatile

memory as correction factors. The Host reads these correction factors and applies them to the ADC conversion

results in order to achieve high measurement accuracy. In addition, the precise voltage reference of the bq76925

can be used to calibrate out the gain and offset of the Host ADC.

Reference Voltage

The bq76925 outputs a stable reference voltage for use by the Host ADC. A nominal voltage of 1.5 V or 3 V is

selected via the REF_SEL bit in the CONFIG_2 register. The reference voltage is very stable across

temperature, but the initial voltage may vary by ±4%. The variation from nominal is manifested as a gain error in

the ADC conversion result. To correct for this error, offset and gain correction factors are determined at final test

and stored in the non-volatile registers VREF_CAL and VREF_CAL_EXT. The Host reads the correction factors

and applies them to the nominal reference voltage to arrive at the actual reference voltage as described under

Cell Voltage Monitoring. After gain correction, the tolerance of the reference will be within ±0.1%.

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Host ADC Calibration

All analog to digital converters have inherent gain and offset errors which adversely affect measurement

accuracy. Some microcontrollers may be characterized by the manufacturer and shipped with ADC gain and

offset information stored on-chip. It is also possible for such characterization to be done by the end-user on loose

devices prior to PCB assembly, or as a part of the assembled PCB test.

For applications where such ADC characterization is not provided or is not practical, the bq76925 provides a

means for in-situ calibration of the Host ADC. Through setting of the VCOUT_SEL bits in the CELL_CTL register

two scaled versions of the reference voltage, 0.5 × V_REFand 0.85 × V_REF, can be selected for output on the

VCOUT pin for measurement by the Host ADC. Measuring both scaled voltages enables the Host to do a

two-point calibration of the ADC and compensate for the ADC offset and gain in all subsequent ADC

measurement results as shown in Figure 5.

Note that the calibration accuracy will be limited by the tolerance of the scaled reference voltage output so that

use of this method may not be effective. For these cases, it is recommended to use a higher accuracy source for

the two-point calibration shown in Figure 5.

V_OUT

Actual transfer curve:

V_ADC,ACT= G’ × V_IN+ V_OFFSET

Slope =

Actual gain = G’

Ideal transfer curve:

V_ADC,IDEAL= V_IN

Corrected result:

V_ADC,COR= (V_ADC,ACT– V_OFFSET) ÷ G’

Slope =

Ideal gain = 1

V_OFFSET

V_IN

VREF × 0.5

VREF × 0.85

Figure 5. Host ADC Calibration Using V_REF

Cell Voltage Monitoring

The cell voltage monitoring circuits include an input level-shifter, multiplexer (MUX) and scaling amplifier. The

Host selects one VCn cell input for measurement by setting the VCOUT_SEL and CELL_SEL bits in the

CELL_CTL register. The scaling factor is set by the REF_SEL bit in the CONFIG_2 register. The selected cell

input is level shifted to VSS reference, scaled by a nominal gain G_VCOUT= 0.3 (REF_SEL = 0) or 0.6 (REF_SEL

= 1) and output on the VCOUT pin for measurement by the Host ADC.

Similar to the reference voltage, gain and offset correction factors are determined at final test for each individual

cell input and stored in non-volatile registers VCn_CAL (n = 1-6) and VC_CAL_EXT_m (m = 1-2). These factors

are read by the Host and applied to the ADC voltage measurement results in order to obtain the specified

accuracy.

The cell voltage offset and gain correction factors are stored as 5-bit signed integers in 2’s complement format.

The most significant bits (VCn_OC_4, VCn_GC_4) are stored separately and must be concatenated with the

least significant bits (VCn_OFFSET_CORR, VCn_GAIN_CORR).

The reference voltage offset and gain correction factors are stored respectively as a 6-bit and 5-bit signed integer

in 2’s complement format. As with the cell voltage correction factors, the most significant bits (VREF_OC_5,

VREF_OC_4, VREF_GC_4) are stored separately and must be concatenated with the least significant bits

(VREF_OFFSET_CORR, VREF_GAIN_CORR).

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The actual cell voltage (VCn) is calculated from the measured voltage (VCOUT) as shown in the following

equations:

ADC Count

VCOUT =

× VREF_NOMINAL

Full Scale Count

VCOUT ´ GC_VREF+ OC_VCOUT

VCn =

× (1 + GC_VCOUT)

G_VCOUT

(1)

spacer

GC_VCOUT

VCn_GC_4 << 4 + VCn_GAIN_CORR ´ 0.001,

)

(

OC_VCOUT

VCn_OC_4 << 4 + VCn_OFFSET_CORR ´ 0.001,

)

(

GC_VREF= (1 + VREF_GC_4 << 4 + VREF_GAIN_CORR ´ 0.001)

( )

(^{VREF_OC_5 << 5})⁺(^{VREF_OC_4 << 4})^{+ VREF_OFFSET_CORR}

´ 0.001

VREF_NOMINAL

(2)

Cell Amplifier Headroom Under Extreme Cell Imbalance

For cell voltages across (VC1 – VC0) that are less than ~2.64 V, extreme cell voltage imbalances between

(VC1 – VC0) and (VC2 – VC1) can lead to a loss of gain in the (VC2 – VC1) amplifier. The cell imbalance at

which the loss of gain occurs is determined by the following equation:

(VC2 - VC1) ´ 0.6 > (VC1 - VSS)

(3)

Assuming VC0 = VSS, it can be seen that when (VC1 – VC0) > 2.64 volts, the voltage across (VC2 – VC1) can

range up to the limit of 4.4 V without any loss of gain. At the minimum value of (VC1 – VC0) = 1.4 V, an

imbalance of more than 900 mV is tolerated before any loss of gain in the (VC2 – VC1) amplifier. For higher

values of (VC1 – VC0), increasingly large imbalances are tolerated. For example, when (VC1 – VC0) = 2.0 V, an

imbalance up to 1.33 V (i.e. (VC2 – VC1) = 3.33 V) results in no degradation of amplifier performance.

Normally, cell imbalances greater than 900 mV will signal a faulty condition of the battery pack and its use should

be discontinued. The loss of gain on the second cell input does not affect the ability of the system to detect this

condition. The gain fall-off is gradual so that the measured imbalance will never be less than the critical

imbalance set by Equation 3.

Therefore if the measured (VC2 – VC1) is greater than (VC1 – VSS) / 0.6, a severe imbalance is detected and

the pack should enter a fault state which prevents further use. In this severe cell imbalance condition

comparisons of the measured (VC2 – VC1) to any over-voltage limits will be optimistic due to the reduced gain in

the amplifier, further emphasizing the need to enter a fault state.

Cell Amplifier Headroom Under BAT Voltage Drop

Voltage differences between BAT and the top cell potential come from two sources as shown in Figure 6: V3P3

regulator current that flows through the R_BATfilter resistor, and the voltage drop in the series diode D_BATof the

hold-up circuit. These effects cause BAT to be less than the top cell voltage measured by the cell amplifier.

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D_BAT

BAT

R_BAT

VCTL

VREG

Z_BAT

C_BAT

V3P3

C_V3P3

VC6

bq76925

Figure 6. Sources of Voltage Drop Affecting the BAT Pin

The top cell amplifier (VC6 – VC5) is designed to measure an input voltage down to 1.4 V with a difference

between the BAT and VC6 pin up to 1.2 V (i.e. BAT can be 1.2 V lower than VC6). However, in applications with

fewer than 6 cells, the upper cell inputs are typically shorted to the top cell input. For example, in a 5-cell

application VC6 and VC5 would be shorted together and the (VC5 – VC4) amplifier would measure the top cell

voltage. The case is similar for 4- and 3-cell applications.

For these cases when using the (VC5 – VC4), (VC4 –VC3) or (VC3 – VC2) amplifier to measure the top cell, the

difference between BAT and the top cell amplifier must be less than 240 mV in order to measure cell voltages

down to 1.4 V. Note that at higher cell input voltages the top amplifier tolerates a greater difference. For example,

in a 5-cell configuration (VC6 and VC5 tied together) the (VC5 – VC4) amplifier is able to measure down to a 1.7

V input with a 600 mV difference between VC5 and BAT.

Accordingly, in systems with fewer than 6 cells it is important in system design to minimize R_BATand to use a

Schottky type diode for D_BATwith a low forward voltage. If it is not possible to reduce the drop at BAT to an

acceptable level, then for 4 and 5 cell configurations the (VC6 – VC5) amplifier may be used as the top cell

amplifier as show in Table 1, which allows up to a 1.2 V difference between BAT and top cell.

Table 1. Alternate Connections for 4 and 5 Cells

Configuration

5-cell

Cell 5

Cell 4

Cell 3

Cell 2

Cell 1

Unused Cell Inputs

Short VC5 to VC4

VC6 – VC5

VC4 – VC3

VC6 – VC5

VC3 – VC2

VC2 – VC1

VC1 – VC0

4-cell

Short VC5 to VC4 to VC3

Current Monitoring

Current is measured by converting current to voltage via a sense resistor connected between SENSEN and

SENSEP. A positive voltage at SENSEP with respect to SENSEN indicates a discharge current is flowing, and a

negative voltage indicates a charge current. The small voltage developed across the sense resistor is amplified

by gain G_VIOUTand output on the VIOUT pin for conversion by the Host ADC. The voltage on VIOUT is always

positive and for zero current is set to 3/4 of the output range. The current sense amplifier is inverting; discharge

current causes VIOUT to decrease and charge current causes VIOUT to increase. Therefore, the measurement

range for discharge currents is 3 times the measurement range for charge currents.

The current sense amplifier is preceded by a multiplexer that allows measurement of either the SENSEN or

SENSEP input with respect to VSS. The Host selects the pin for measurement by writing the I_AMP_CAL bit in

the CONFIG_1 register. The Host then calculates the voltage across the sense resistor by subtracting the

measured voltage at SENSEN from the measured voltage at SENSEP. If the SENSEN and VSS connections are

such that charge and discharge currents do not flow through the connection between them, i.e. there is no

voltage drop between SENSEN and VSS due to the current being measured, then the measurement of the

SENSEN voltage can be regarded as a calibration step and stored by the Host for use as a pseudo-constant in

the V_SENSEcalculation. The SENSEN voltage measurement would then only need updating when changing

environmental conditions warrant.

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The Host sets G_VIOUTby writing the I_GAIN bit in the CONFIG_1 register. The available gains of 4 and 8 enable

operation with a variety of sense resistor values over a broad range of pack currents. The gain may be changed

at any time allowing for dynamic range and resolution adjustment. The input and output ranges of the amplifier

are determined by the value of the REF_SEL bit in the CONFIG_2 register. These values are shown in Table 2.

Because the current amplifier is inverting, the Min column under Output Range corresponds to the Max column

under Input Range. Likewise, the Max column under Output Range corresponds to the Min column under Input

Range.

The actual current is calculated from the measured voltage (VIOUT) as follows. Note that V_SENSEis positive when

discharge current is flowing. In keeping with battery pack conventions, the sign of I_SENSEis inverted so that

discharge current is negative.

-(VIOUT(SENSEP) - VIOUT(SENSEN))

V_SENSE

G_VIOUT

V_SENSE

I_SENSE= -

R_SENSE

(4)

Table 2. Current Amplifier Configurations

Input Range⁽¹⁾(mV)

Output Range (V)⁽²⁾

I_SENSE

Resolution

(mA)w/10-bit

ADC⁽³⁾

VIOUT (V) at

I_SENSE= 0

(typical)

I_SENSERange (A)

at R_SENSE= 1

mΩ

REF_SEL

I_GAIN

Gain

Min

Max

Min

Max

1.0

2.0

–62.5

–14

187.5

0.25

0.27

0.5

1.25

1.11

2.5

–62.5 – 187.5

–14 – 91

366

183

732

366

–125

–62.5

375

–125 – 375

–62.5 – 187.5

187.5

0.5

2.5

(1) SENSEN or SENSEP measured with respect to VSS.

(2) Output range assumes typical value of VIOUT at I_SENSE= 0. For non-typical values, the output range will shift accordingly.

(3) Assumes 1 mΩ R_SENSEand ADC reference voltage of 1.5 V and 3.0 V when REF_SEL = 0 and 1, respectively.

Over Current Monitoring

The bq76925 also includes a comparator for monitoring the current sense resistor and alerting the Host when the

voltage across the sense resistor exceeds a selected threshold. The available thresholds range from 25 mV to

400 mV and are set by writing the I_THRESH bits in the CONFIG_1 register. Positive (discharge) or negative

(charge) current may be monitored by setting the I_COMP_POL bit in the CONFIG_1 register. By the choice of

sense resistor and threshold a variety of trip points are possible to support a wide range of applications.

The comparator result is driven through the open-drain ALERT output to signal the host when the threshold is

exceeded. This feature can be used to wake up the Host on connection of a load, or to alert the Host to a

potential fault condition. The ALERT pin state is also available by reading the ALERT bit in the STATUS register.

Temperature Monitoring

To enable temperature measurements by the Host, the bq76925 provides the LDO regulator voltage on a

separate output pin (VTB) for biasing an external thermistor network. In order to minimize power consumption,

the Host may switch the VTB output on and off by writing to the VTB_EN bit in the POWER_CTL register. Note

that if the LDO is back-fed by an external source, the VTB bias will be switched to the external source.

In a typical application, the thermistor network will consist of a resistor in series with an NTC thermistor, forming

a resistor divider where the output is proportional to temperature. This output may be measured by the Host ADC

to determine temperature.

Internal Temperature Monitoring

The internal temperature (T_INT) of the bq76925 can be measured by setting VCOUT_SEL = ‘01’ and CELL_SEL

= ‘110’ in the CELL_CTL register. In this configuration, a voltage proportional to temperature (V_{TEMP_INT}) is output

on the VCOUT pin. This voltage is related to the internal temperature as follows:

V_{TEMP_INT}(mV) = V_{TEMP_INT}(T_INT= 25°C) – T_INT(°C) × ΔV_{TEMP_INT}

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Cell Balancing and Open Cell Detection

The bq76925 integrates cell balancing FETs that are individually controlled by the Host. The balancing method is

resistive bleed balancing, where the balancing current is set by the external cell input resistors. The maximum

allowed balancing current is 50 mA per cell.

The Host may activate one or more cell balancing FETs by writing the BAL_n bits in the BAL_CTL register. To

allow the greatest flexibility, the Host has complete control over the balancing FETs. However, in order to avoid

exceeding the maximum cell input voltage, the bq76925 will prevent two adjacent balancing FETs from being

turned on simultaneously. If two adjacent bits in the balance control register are set to 1, neither balancing

transistor will be turned on. The Host based balancing algorithm must also limit the power dissipation to the

maximum ratings of the device.

In a normal system, closing a cell balancing FET will cause 2 cell voltages to appear across one cell input. This

fact can be utilized to detect a cell sense-line open condition, i.e. a broken wire from the cell sense point to the

bq76925 VCn input. Table 3 shows how this can be accomplished. Note that the normal cell voltage

measurements may represent a saturated or full scale reading. However, these will normally be distinguishable

from the open cell measurement.

Table 3. Open Cell Detection Method

Method 1

Method 2

Kelvin

input to

test

Result

Turn On

Measure

Turn On

Measure

Normal

Open

CELL2

CELL3

CELL4

CELL5

CELL6

Normal

Open

VC0

VC1

VC2

VC3

VC4

VC5

VC6

BAL_1

BAL_2

BAL_3

BAL_4

BAL_5

CELL2

CELL3

CELL4

CELL5

CELL6

CELL2 + 0.5 × CELL1

CELL3 + 0.5 × CELL2

CELL4 + 0.5 × CELL3

CELL5 + 0.5 × CELL4

CELL6 + 0.5 × CELL5

BAL_2

BAL_3

BAL_4

BAL_5

BAL_6

CELL1

CELL2

CELL3

CELL4

CELL5

CELL1 + 0.5 × CELL2

CELL2 + 0.5 × CELL3

CELL3 + 0.5 × CELL4

CELL4 + 0.5 × CELL5

CELL5 + 0.5 × CELL6

CELL1

CELL2

CELL3

CELL4

CELL5

It should be noted that the cell amplifier headroom limits discussed above apply to the open cell detection

method because by virtue of closing a switch between 2 cell inputs, internally to the device this appears as an

extreme cell imbalance. Therefore, when testing for an open on CELL2 by closing the CELL1 balancing FET, the

CELL2 measurement will be less than the expected normal result due to gain loss caused by the imbalance.

However, the CELL2 measurement will still increase under this condition so that a difference between open (no

change) and normal (measured voltage increases) can be detected.

Host Interface

The Host communicates with the AFE via an I2C interface. A CRC byte may optionally be used to ensure robust

operation. The CRC is calculated over all bytes in the message according to the polynomial x⁸+ x²+ x + 1.

I²C Addressing

In order to reduce communications overhead, the addressing scheme for the I2C interface combines the slave

device address and device register addresses into a single 7-bit address as shown below.

ADDRESS[6:0] = (I2C_GROUP_ADDR[3:0] << 3) + REG_ADDR[4:0]

The I2C_GROUP_ADDR is a 4-bit value stored in the EEPROM. REG_ADDR is the 5-bit register address being

accessed, and can range from 0x00 – 0x1F. The factory programmed value of the group address is ‘0100’.

Contact TI if an alternative group address is required.

For the default I2C_GROUP_ADDR, the combined address can be formed as shown in Table 4.

Table 4. Combined I2C Address for Default Group

Address

ADDRESS[6:0]

4:0

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Bus Write Command to bq76925

The Host writes to the registers of the bq76925 as shown in Figure 7. The bq76925 acknowledges each received

byte by pulling the SDA line low during the acknowledge period.

The Host may optionally send a CRC after the Data byte as shown. The CRC for write commands is enabled by

writing the CRC_EN bit in the CONFIG_2 register. If the CRC is not used, then the Host generates the Stop

condition immediately after the bq76925 acknowledges receipt of the Data byte.

When the CRC is disabled, the bq76925 will act on the command on the first rising edge of SCL following the

ACK of the Data byte. This occurs as part of the normal bus setup prior to a Stop. If a CRC byte is sent while the

CRC is disabled, the first rising edge of the SCL following the ACK will be the clocking of the first bit of the CRC.

The bq76925 does not distinguish these two cases. In both cases, the command will complete normally, and in

the latter case the CRC will be ignored.

SCL

...

R/W ACK

ACK

A6 A5

D7 D6

C7 C6

SDA

CRC

(optional)

Start

Address

Stop

Data

Figure 7. I²C Write Command

Bus Read Command from bq76925

The Host reads from the registers of the bq76925 as shown in Figure 8. This protocol is similar to the write

protocol, except that the slave now drives data back to the Host. The bq76925 acknowledges each received byte

by pulling the SDA line low during the acknowledge period. When the bq76925 sends data back to the Host, the

Host drives the acknowledge.

The Host may optionally request a CRC byte following the Data byte as shown. The CRC for read commands is

always enabled, but not required. If the CRC is not used, then the Host simply NACK’s the Data byte and then

generates the Stop condition.

SCL

...

NACK

R/W ACK

ACK

A6 A5

D7 D6

C7 C6

SDA

Slave

Drives Data

Slave

Drives CRC

(optional)

Start

Address

Stop

Master

Drives NACK

Figure 8. I²C Read Command

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Address

SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

Name

Access

R/W

0x00

0x01

STATUS

CELL_CTL

BAL_CTL

ALERT

CRC_ERR

CELL_SEL

BAL_2

POR

R/W

VCOUT_SEL

0x02

R/W

BAL_6

I_THRESH

BAL_5

BAL_4

BAL_3

BAL_1

I_GAIN

0x03

CONFIG_1

CONFIG_2

POWER_CTL

Reserved

R/W

I_COMP_POL

I_AMP_CAL

0x04

R/W

CRC_EN

SLEEP

REF_SEL

REF_EN

0x05

R/W

SLEEP_DIS

I_COMP_EN

I_AMP_EN

VC_AMP_EN

VTB_EN

0x06

R/W

0x07

CHIP_ID

0x08 – 0x0F

0x10

Reserved

R/W

VREF_CAL

VC1_CAL

EEPROM

VREF_OFFSET_CORR

VC1_OFFSET_CORR

VC2_OFFSET_CORR

VC3_OFFSET_CORR

VC4_OFFSET_CORR

VC5_OFFSET_CORR

VC6_OFFSET_CORR

VREF_GAIN_CORR

0x11

VC1_GAIN_CORR

VC2_GAIN_CORR

VC3_GAIN_CORR

VC4_GAIN_CORR

VC5_GAIN_CORR

VC6_GAIN_CORR

0x12

VC2_CAL

0x13

VC3_CAL

0x14

VC4_CAL

0x15

VC5_CAL

0x16

VC6_CAL

0x17

VC_CAL_EXT_1

VC_CAL_EXT_2

Reserved

VC1_OC_4

VC3_OC_4

VC1_GC_4

VC3_GC_4

VC2_OC_4

VC4_OC_4

VC2_GC_4

VC4_GC_4

0x18

VC5_OC_4

VC5_GC_4

VC6_OC_4

VC6_GC_4

0x10 – 0x1A

0x1B

VREF_CAL_EXT

Reserved

VREF_OC_5

VREF_OC_4

VREF_GC_4

0x1C – 0x1F

STATUS

Address

Name

Type

ALERT

CRC_ERR

POR

0x00

STATUS

R/W

Defaults:

ALERT: Over-current alert. Reflects state of the over-current comparator. ‘1’ = over-current.

CRC_ERR: CRC error status. Updated on every I²C write packet when CRC_EN = ‘1’. ‘1’ = CRC error.

POR: Power on reset flag. Set on each power-up and wake-up from sleep. May be cleared by writing with ‘0’.

CELL_CTL

Address

Name

Type

D7⁽¹⁾

CELL_SEL

0x01

CELL_CTL

R/W

VCOUT_SEL

Defaults:

(1) This bit must be kept = 0

VCOUT_SEL: VCOUT MUX select. Selects the VCOUT pin function as follows.

VCOUT_SEL

VCOUT

VSS

0 0

0 1

1 0

1 1

VCn (n determined by CELL_SEL)

VREF × 0.5

VREF × 0.85

CELL_SEL: Cell select. Selects the VCn input for output on VCOUT when VCOUT_SEL = ‘01’.

VCOUT_SEL

CELL_SEL

0 0 0

VCOUT

VC1

0 1

0 0 1

VC2

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VCOUT_SEL

CELL_SEL

0 1 0

VCOUT

VC3

0 1

0 1 1

VC4

1 0 0

VC5

1 0 1

VC6

1 1 0

V_TEMP,INT

Hi-Z

1 1 1

BAL_CTL

Address

Name

Type

BAL_6

BAL_5

BAL_4

BAL_3

BAL_2

BAL_1

0x02

BAL_CTL

R/W

Defaults:

BAL_n: Balance control for cell n. When set, turns on balancing transistor for cell n. Setting of two adjacent

balance controls is not permitted. If two adjacent balance controls are set, neither cell balancing transistor will be

turned on. However, the BAL_n bits will retain their values.

CONFIG_1

Address

Name

Type

I_THRESH

I_AMP_CAL

I_GAIN

0x03

CONFIG_1

R/W

I_COMP_POL

Defaults:

I_THRESH: Current comparator threshold. Sets the threshold of the current comparator as follows:

I_THRESH

0x0

Comparator threshold

25 mV

0x1

50 mV

0x2

75 mV

0x3

100 mV

125 mV

150 mV

175 mV

200 mV

225 mV

250 mV

275 mV

300 mV

325 mV

350 mV

375 mV

400 mV

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

I_COMP_POL: Current comparator polarity select. When ‘0’, trips on discharge current (SENSEP > SENSEN).

When ‘1’, trips on charge current (SENSEP < SENSEN).

I_AMP_CAL: Current amplifier calibration. When ‘0’, current amplifier reports SENSEN with respect to VSS.

When ‘1’, current amplifier reports SENSEP with respect to VSS. This bit can be used for offset cancellation as

described under OPERATIONAL OVERVIEW.

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I_GAIN: Current amplifier gain. Sets the nominal gain of the current amplifier as follows.

I_GAIN

Current amp gain

CONFIG_2

Address

Name

Type

CRC_EN

REF_SEL

0x04

CONFIG_2

R/W

Defaults:

CRC_EN: CRC enable. Enables CRC comparison on write. When ‘1’, CRC is enabled. CRC on read is always

enabled but is optional for Host.

REF_SEL: Reference voltage selection. Sets reference voltage output on VREF pin, cell voltage amplifier gain

and VIOUT output range.

REF_SEL

VREF (V)

1.5

VCOUT Gain

VIOUT Output Range (V)

0.25 – 1.25

0.3

0.6

3.0

0.5 – 2.5

POWER_CTL

Address

Name

Type

SLEEP_DIS

I_AMP_EN

VTB_EN

REF_EN

0x05

POWER_CTL

R/W

SLEEP

I_COMP_EN

VC_AMP_EN

Defaults:

SLEEP: Sleep control. Set to ‘1’ to put device to sleep

SLEEP_DIS: Sleep mode disable. When ‘1’, disables the sleep mode.

I_COMP_EN: Current comparator enable. When ‘1’, comparator is enabled. Disable to save power.

I_AMP_EN: Current amplifier enable. When ‘1’, current amplifier is enabled. Disable to save power.

VC_AMP_EN: Cell amplifier enable. When ‘1’, cell amplifier is enabled. Disable to save power.

VTB_EN: Thermistor bias enable. When ‘1’, the VTB pin is internally switched to the V3P3 voltage.

REF_EN: Voltage reference enable. When ‘1’, the 1.5 / 3.0 V reference is enabled. Disable to save power

CHIP_ID

Address

Name

Type

0x07

CHIP_ID

0x10

Defaults:

CHIP_ID: Silicon version identifier.

VREF_CAL

Address

Name

Type

0x10

VREF_CAL

EEPROM

VREF_OFFSET_CORR

VREF_GAIN_CORR

VREF_OFFSET_CORR: Lower 4 bits of offset correction factor for reference output. The complete offset

correction factor is obtained by concatenating this value with the the two most significant bits VREF_OC_5 and

VREF_OC_4, which are stored in the VREF_CAL_EXT register. The final value is a 6-bit signed 2’s complement

number in the range -32 to +31 with a value of 1 mV per lsb. See description of usage in OPERATIONAL

OVERVIEW.

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VREF_GAIN_CORR: Lower 4 bits of gain correction factor for reference output. The complete gain correction

factor is obtained by concatenating this value with the most significant bit VREF_GC_4, which is stored in the

VREF_CAL_EXT register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a

value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC1_CAL

Address

Name

Type

0x11

VC1_CAL

EEPROM

VC1_OFFSET_CORR

VC1_GAIN_CORR

VC1_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 1 translation. The complete offset

correction factor is obtained by concatenating this value with the most significant bit VC1_OC_4, which is stored

in the VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15

with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC1_GAIN_CORR: Lower 4 bits of gain correction factor for cell 1 translation. The complete gain correction

factor is obtained by concatenating this value with the most significant bit VC1_GC_4, which is stored in the

VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a

value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC2_CAL

Address

Name

Type

0x12

VC2_CAL

EEPROM

VC2_OFFSET_CORR

VC2_GAIN_CORR

VC2_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 2 translation. The complete offset

correction factor is obtained by concatenating this value with the most significant bit VC2_OC_4, which is stored

in the VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15

with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC2_GAIN_CORR: Lower 4 bits of gain correction factor for cell 2 translation. The complete gain correction

factor is obtained by concatenating this value with the most significant bit VC2_GC_4, which is stored in the

VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a

value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC3_CAL

Address

Name

Type

0x13

VC3_CAL

EEPROM

VC3_OFFSET_CORR

VC3_GAIN_CORR

VC3_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 3 translation. The complete offset

correction factor is obtained by concatenating this value with the most significant bit VC3_OC_4, which is stored

in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15

with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC3_GAIN_CORR: Lower 4 bits of gain correction factor for cell 3 translation. The complete gain correction

factor is obtained by concatenating this value with the most significant bit VC3_GC_4, which is stored in the

VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a

value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.

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VC4_CAL

Address

Name

Type

0x14

VC4_CAL

EEPROM

VC4_OFFSET_CORR

VC4_GAIN_CORR

VC4_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 4 translation. The complete offset

correction factor is obtained by concatenating this value with the most significant bit VC4_OC_4, which is stored

in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15

with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC4_GAIN_CORR: Lower 4 bits of gain correction factor for cell 4 translation. The complete gain correction

factor is obtained by concatenating this value with the most significant bit VC4_GC_4, which is stored in the

VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a

value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC5_CAL

Address

Name

Type

0x15

VC5_CAL

EEPROM

VC5_OFFSET_CORR

VC5_GAIN_CORR

VC5_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 5 translation. The complete offset

correction factor is obtained by concatenating this value with the most significant bit VC5_OC_4, which is stored

in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15

with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC5_GAIN_CORR: Lower 4 bits of gain correction factor for cell 5 translation. The complete gain correction

factor is obtained by concatenating this value with the most significant bit VC5_GC_4, which is stored in the

VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a

value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC6_CAL

Address

Name

Type

0x16

VC6_CAL

EEPROM

VC6_OFFSET_CORR

VC6_GAIN_CORR

VC6_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 6 translation. The complete offset

correction factor is obtained by concatenating this value with the most significant bit VC6_OC_4, which is stored

in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15

with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC6_GAIN_CORR: Lower 4 bits of gain correction factor for cell 6 translation. The complete gain correction

factor is obtained by concatenating this value with the most significant bit VC6_GC_4, which is stored in the

VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a

value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.

VC_CAL_EXT_1

Address

Name

Type

0x17

VC_CAL_EXT_1

EEPROM

VC1_OC_4

VC1_GC_4

VC2_OC_4

VC2_GC_4

VC1_OC_4: Most significant bit of offset correction factor for cell 1 translation. See VC1_CAL register description

for details.

VC1_GC_4: Most significant bit of gain correction factor for cell 1 translation. See VC1_CAL register description

for details.

VC2_OC_4: Most significant bit of offset correction factor for cell 2 translation. See VC2_CAL register description

for details.

VC2_GC_4: Most significant bit of gain correction factor for cell 2 translation. See VC2_CAL register description

for details.

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VC_CAL_EXT_2

Address

Name

Type

0x18

VC_CAL_EXT_2

EEPROM

VC3_OC_4

VC3_GC_4

VC4_OC_4

VC4_GC_4

VC5_OC_4

VC5_GC_4

VC6_OC_4

VC6_GC4

VC3_OC_4: Most significant bit of offset correction factor for cell 3 translation. See VC3_CAL register description

for details.

VC3_GC_4: Most significant bit of gain correction factor for cell 3 translation. See VC3_CAL register description

for details.

VC4_OC_4: Most significant bit of offset correction factor for cell 4 translation. See VC4_CAL register description

for details.

VC4_GC_4: Most significant bit of gain correction factor for cell 4 translation. See VC4_CAL register description

for details.

VC5_OC_4: Most significant bit of offset correction factor for cell 5 translation. See VC5_CAL register description

for details.

VC5_GC_4: Most significant bit of gain correction factor for cell 5 translation. See VC5_CAL register description

for details.

VC6_OC_4: Most significant bit of offset correction factor for cell 6 translation. See VC6_CAL register description

for details.

VC6_GC_4: Most significant bit of gain correction factor for cell 6 translation. See VC6_CAL register description

for details.

VREF_CAL_EXT

Address

Name

Type

0x1B

VREF_CAL_EXT

EEPROM

VREF_OC_5

VCREF_OC_4

VREF_GC4

VREF_OC_5: Most significant bit of offset correction factor for reference output. See VREF_CAL register

description for details.

VREF_OC_4: Next most significant bit of offset correction factor for reference output. See VREF_CAL register

description for details.

VREF_GC_4: Most significant bit of gain correction factor for reference output. See VREF_CAL register

description for details.

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SLUSAM9B –JULY 2011–REVISED DECEMBER 2011

Page

www.ti.com

Changes from Original (July 2011) to Revision A

•

Changed literature number to Rev A for ProductMix release ............................................................................................... 3

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Changes from Revision A (July 2011) to Revision B

Page

•

Added 24-pin QFN (RGE) Package to Production Data ....................................................................................................... 2

Added 24-pin QFN (RGE) Package to Production Data ....................................................................................................... 3

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PACKAGE OPTION ADDENDUM

www.ti.com

6-Jan-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

BQ76925PW

BQ76925PWR

BQ76925RGER

BQ76925RGET

ACTIVE

TSSOP

VQFN

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

2000

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAUAGLevel-2-260C-1 YEAR

RGE

Green (RoHS

& no Sb/Br)

VQFN

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ76925PWR

BQ76925RGER

BQ76925RGET

TSSOP

VQFN

RGE

2000

3000

250

330.0

180.0

16.4

12.4

6.95

4.25

7.1

1.6

8.0

16.0

12.0

4.25

1.15

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ76925PWR

BQ76925RGER

BQ76925RGET

TSSOP

VQFN

RGE

2000

3000

250

367.0

210.0

367.0

185.0

38.0

35.0

Pack Materials-Page 2

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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BQ76925RGER产品参数

型号:	BQ76925RGER
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	QFN
包装说明：	HVQCCN, LCC24,.16SQ,20
针数：	24
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	1.62
可调阈值：	YES
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	S-PQCC-N24
JESD-609代码：	e4
长度：	4 mm
湿度敏感等级：	2
信道数量：	1
功能数量：	1
端子数量：	24
最高工作温度：	85 °C
最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN
封装等效代码：	LCC24,.16SQ,20
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260
电源：	4.2/26.4 V
认证状态：	Not Qualified
座面最大高度：	1 mm
子类别：	Power Management Circuits
最大供电电流 (Isup)：	0.048 mA
最大供电电压 (Vsup)：	26.4 V
最小供电电压 (Vsup)：	4.2 V
标称供电电压 (Vsup)：	21.6 V
表面贴装：	YES
温度等级：	OTHER
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4 mm
Base Number Matches：	1

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