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MULTILAYER CERAMIC CAPACITORS/AXIAL

& RADIAL LEADED

Multilayer ceramic capacitors are available in a

edges of the laminated structure. The entire structure is

fired at high temperature to produce a monolithic

block which provides high capacitance values in a

small physical volume. After firing, conductive

terminations are applied to opposite ends of the chip to

make contact with the exposed electrodes.

Termination materials and methods vary depending on

the intended use.

variety of physical sizes and configurations, including

leaded devices and surface mounted chips. Leaded

styles include molded and conformally coated parts

with axial and radial leads. However, the basic

capacitor element is similar for all styles. It is called a

chip and consists of formulated dielectric materials

which have been cast into thin layers, interspersed

with metal electrodes alternately exposed on opposite

TEMPERATURE CHARACTERISTICS

Ceramic dielectric materials can be formulated with

a wide range of characteristics. The EIA standard for

ceramic dielectric capacitors (RS-198) divides ceramic

dielectrics into the following classes:

Class III: General purpose capacitors, suitable

for by-pass coupling or other applications in which

dielectric losses, high insulation resistance and

stability of capacitance characteristics are of little or

no importance. Class III capacitors are similar to Class

II capacitors except for temperature characteristics,

Class I: Temperature compensating capacitors,

suitable for resonant circuit application or other appli-

cations where high Q and stability of capacitance char-

acteristics are required. Class I capacitors have

predictable temperature coefficients and are not

affected by voltage, frequency or time. They are made

from materials which are not ferro-electric, yielding

superior stability but low volumetric efficiency. Class I

capacitors are the most stable type available, but have

the lowest volumetric efficiency.

which are greater than

15%. Class III capacitors

have the highest volumetric efficiency and poorest

stability of any type.

KEMET leaded ceramic capacitors are offered in

the three most popular temperature characteristics:

C0G: Class I, with a temperature coefficient of 0

30 ppm per degree C over an operating

temperature range of - 55°C to + 125°C (Also

known as “NP0”).

Class II: Stable capacitors, suitable for bypass

or coupling applications or frequency discriminating

circuits where Q and stability of capacitance char-

acteristics are not of major importance. Class II

capacitors have temperature characteristics of 15%

or less. They are made from materials which are

ferro-electric, yielding higher volumetric efficiency but

less stability. Class II capacitors are affected by

temperature, voltage, frequency and time.

X7R: Class II, with a maximum capacitance

change of 15% over an operating temperature

range of - 55°C to + 125°C.

Z5U: Class III, with a maximum capacitance

change of + 22% - 56% over an operating tem-

perature range of + 10°C to + 85°C.

Specified electrical limits for these three temperature

characteristics are shown in Table 1.

SPECIFIED ELECTRICAL LIMITS

Temperature Characteristics

X7R

Parameter

C0G

Z5U

Dissipation Factor: Measured at following conditions.

C0G – 1 kHz and 1 vrms if capacitance >1000pF

1 MHz and 1 vrms if capacitance 1000 pF

X7R – 1 kHz and 1 vrms* or if extended cap range 0.5 vrms

Z5U – 1 kHz and 0.5 vrms

2.5%

(3.5% @ 25V)

0.10%

4.0%

Dielectric Stength: 2.5 times rated DC voltage.

Pass Subsequent IR Test

1,000 M

or 100 G

F

1,000 M

or 100 G

F

1,000 M

or 10 G

F

Insulation Resistance (IR): At rated DC voltage,

whichever of the two is smaller

Temperature Characteristics: Range, °C

Capacitance Change without

DC voltage

-55 to +125

30 ppm/°C

-55 to +125

15%

+ 10 to +85

+22%,-56%

0

* MHz and 1 vrms if capacitance 100 pF on military product.

Table I

4

APPLICATION NOTES FOR MULTILAYER

CERAMIC CAPACITORS

The variation of a capacitor’s impedance with frequency

determines its effectiveness in many applications.

ELECTRICAL CHARACTERISTICS

The fundamental electrical properties of multilayer

ceramic capacitors are as follows:

Dissipation Factor: Dissipation Factor (DF) is a mea-

sure of the losses in a capacitor under AC application. It is the

ratio of the equivalent series resistance to the capacitive reac-

tance, and is usually expressed in percent. It is usually mea-

sured simultaneously with capacitance, and under the same

conditions. The vector diagram in Figure 2 illustrates the rela-

tionship between DF, ESR, and impedance. The reciprocal of

the dissipation factor is called the “Q”, or quality factor. For

convenience, the “Q” factor is often used for very low values

of dissipation factor. DF is sometimes called the “loss tangent”

or “tangent ␦”, as derived from this diagram.

Polarity: Multilayer ceramic capacitors are not polar,

and may be used with DC voltage applied in either direction.

Rated Voltage: This term refers to the maximum con-

tinuous DC working voltage permissible across the entire

operating temperature range. Multilayer ceramic capacitors

are not extremely sensitive to voltage, and brief applications

of voltage above rated will not result in immediate failure.

However, reliability will be reduced by exposure to sustained

voltages above rated.

Capacitance: The standard unit of capacitance is the

farad. For practical capacitors, it is usually expressed in

ESR

Figure 2

-6

-9

microfarads (10 farad), nanofarads (10 farad), or picofarads

-12

(10 farad). Standard measurement conditions are as

O

ESR

follows:

DF =

X

c

Class I (up to 1,000 pF):

1MHz and 1.2 VRMS

maximum.

δ

X

Ζ

c

Class I (over 1,000 pF):

1kHz and 1.2 VRMS

maximum.

1

2πfC

=

X

Class II:

Class III:

1 kHz and 1.0 0.2 VRMS.

1 kHz and 0.5 0.1 VRMS.

c

Like all other practical capacitors, multilayer ceramic

capacitors also have resistance and inductance. A simplified

schematic for the equivalent circuit is shown in Figure 1.

Other significant electrical characteristics resulting from

these additional properties are as follows:

Insulation Resistance: Insulation Resistance (IR) is the

DC resistance measured across the terminals of a capacitor,

represented by the parallel resistance (Rp) shown in Figure 1.

For a given dielectric type, electrode area increases with

capacitance, resulting in a decrease in the insulation resis-

tance. Consequently, insulation resistance is usually specified

as the “RC” (IR x C) product, in terms of ohm-farads or

megohm-microfarads. The insulation resistance for a specific

capacitance value is determined by dividing this product by

the capacitance. However, as the nominal capacitance values

become small, the insulation resistance calculated from the

RC product reaches values which are impractical.

Consequently, IR specifications usually include both a mini-

mum RC product and a maximum limit on the IR calculated

from that value. For example, a typical IR specification might

read “1,000 megohm-microfarads or 100 gigohms, whichever

is less.”

R

Figure 1

P

R

L

S

C

C = Capacitance

L = Inductance

R

= Equivalent Series Resistance (ESR)

= Insulation Resistance (IR)

S

P

Impedance: Since the parallel resistance (Rp) is nor-

mally very high, the total impedance of the capacitor is:

Insulation Resistance is the measure of a capacitor to

resist the flow of DC leakage current. It is sometimes referred

to as “leakage resistance.” The DC leakage current may be

calculated by dividing the applied voltage by the insulation

resistance (Ohm’s Law).

2

R_S+ (X_C- X_L)²

Z =

Dielectric Withstanding Voltage: Dielectric withstand-

ing voltage (DWV) is the peak voltage which a capacitor is

designed to withstand for short periods of time without dam-

age. All KEMET multilayer ceramic capacitors will withstand a

test voltage of 2.5 x the rated voltage for 60 seconds.

Where Z =Total Impedance

RS = Equivalent Series Resistance

1

X_C= Capacitive Reactance =

2πfC

KEMET specification limits for these characteristics at

standard measurement conditions are shown in Table 1 on

page 4. Variations in these properties caused by changing

conditions of temperature, voltage, frequency, and time are

covered in the following sections.

X_L= Inductive Reactance = 2πfL

5

APPLICATION NOTES FOR MULTILAYER

CERAMIC CAPACITORS

TABLE 1

EIA TEMPERATURE CHARACTERISTIC CODES

FOR CLASS I DIELECTRICS

Significant Figure

of Temperature

Coefficient

Multiplier Applied

to Temperature

Coefficient

Tolerance of

Temperature

Coefficient *

PPM per

Degree C

Letter

Symbol

Multi-

plier

Number

Symbol

PPM per

Degree C

Letter

Symbol

0.0

0.3

0.9

1.0

1.5

2.2

3.3

4.7

7.5

C

B

A

M

P

R

S

T

-1

-10

-100

-1000

-100000

+1

0

1

2

3

4

5

6

7

8

9

30

60

G

H

J

K

L

120

250

500

1000

2500

M

N

+10

+100

+1000

+10000

U

* These symetrical tolerances apply to a two-point measurement of

temperature coefficient: one at 25°C and one at 85°C. Some deviation

is permitted at lower temperatures. For example, the PPM tolerance

for C0G at -55°C is +30 / -72 PPM.

TABLE 2

EIA TEMPERATURE CHARACTERISTIC CODES

FOR CLASS II & III DIELECTRICS

Low Temperature

Rating

High Temperature Maximum Capacitance

Rating Shift

Degree

Celcius

Letter

Symbol Celcius

Degree

Number

Symbol

Letter

Symbol

Percent

+10C

-30C

-55C

Z

Y

X

+45C

+65C

+85C

+105C

+125C

+150C

+200C

2

4

5

6

7

8

9

1.0%

1.5%

2.2%

3.3%

4.7%

7.5%

10.0%

15.0%

22.0%

A

B

C

D

E

F

P

R

S

T

+10

+20

+30

+40

+50

+60

+70

+80

+22/-33%

+22/-56%

+22/-82%

U

V

6

APPLICATION NOTES FOR MULTILAYER

CERAMIC CAPACITORS

At higher AC voltages, both capacitance and dissipation factor

begin to decrease.

Typical curves showing the effect of applied AC and DC

voltage are shown in Figure 6 for KEMET X7R capacitors and

Figure 7 for KEMET Z5U capacitors.

Effect of Frequency: Frequency affects both capaci-

tance and dissipation factor. Typical curves for KEMET multi-

layer ceramic capacitors are shown in Figures 8 and 9.

The variation of impedance with frequency is an impor-

tant consideration in the application of multilayer ceramic

capacitors. Total impedance of the capacitor is the vector of the

capacitive reactance, the inductive reactance, and the ESR, as

illustrated in Figure 2. As frequency increases, the capacitive

reactance decreases. However, the series inductance (L)

shown in Figure 1 produces inductive reactance, which

increases with frequency. At some frequency, the impedance

ceases to be capacitive and becomes inductive. This point, at

the bottom of the V-shaped impedance versus frequency

curves, is the self-resonant frequency. At the self-resonant fre-

quency, the reactance is zero, and the impedance consists of

the ESR only.

Typical impedance versus frequency curves for KEMET

multilayer ceramic capacitors are shown in Figures 10, 11, and

12. These curves apply to KEMET capacitors in chip form, with-

out leads. Lead configuration and lead length have a significant

impact on the series inductance. The lead inductance is

approximately 10nH/inch, which is large compared to the

inductance of the chip. The effect of this additional inductance

is a decrease in the self-resonant frequency, and an increase

in impedance in the inductive region above the self-resonant

frequency.

Effect of Time: The capacitance of Class II and III

dielectrics change with time as well as with temperature, volt-

age and frequency. This change with time is known as “aging.”

It is caused by gradual realignment of the crystalline structure

of the ceramic dielectric material as it is cooled below its Curie

temperature, which produces a loss of capacitance with time.

The aging process is predictable and follows a logarithmic

decay. Typical aging rates for C0G, X7R, and Z5U dielectrics

are as follows:

C0G

X7R

Z5U

None

2.0% per decade of time

5.0% per decade of time

Typical aging curves for X7R and Z5U dielectrics are

shown in Figure 13.

Effect of Temperature: Both capacitance and dissipa-

tion factor are affected by variations in temperature. The max-

imum capacitance change with temperature is defined by the

temperature characteristic. However, this only defines a “box”

bounded by the upper and lower operating temperatures and

the minimum and maximum capacitance values. Within this

“box”, the variation with temperature depends upon the spe-

cific dielectric formulation. Typical curves for KEMET capaci-

tors are shown in Figures 3, 4, and 5. These figures also

include the typical change in dissipation factor for KEMET

capacitors.

The aging process is reversible. If the capacitor is heat-

ed to a temperature above its Curie point for some period of

time, de-aging will occur and the capacitor will regain the

capacitance lost during the aging process. The amount of de-

aging depends on both the elevated temperature and the

length of time at that temperature. Exposure to 150°C for one-

half hour or 125°C for two hours is usually sufficient to return

the capacitor to its initial value.

Because the capacitance changes rapidly immediately

after de-aging, capacitance measurements are usually delayed

for at least 10 hours after the de-aging process, which is often

referred to as the “last heat.” In addition, manufacturers utilize

the aging rates to set factory test limits which will bring the

capacitance within the specified tolerance at some future time,

to allow for customer receipt and use. Typically, the test limits

are adjusted so that the capacitance will be within the specified

tolerance after either 1,000 hours or 100 days, depending on

the manufacturer and the product type.

Insulation resistance decreases with temperature.

Typically, the insulation resistance at maximum rated temper-

ature is 10% of the 25°C value.

Effect of Voltage: Class I ceramic capacitors are not

affected by variations in applied AC or DC voltages. For Class

II and III ceramic capacitors, variations in voltage affect only

the capacitance and dissipation factor. The application of DC

voltage higher than 5 vdc reduces both the capacitance and

dissipation factor. The application of AC voltages up to 10-20

Vac tends to increase both capacitance and dissipation factor.

7

APPLICATION NOTES FOR MULTILAYER

CERAMIC CAPACITORS

capacitors may be operated with AC voltage applied without

need for DC bias.

POWER DISSIPATION

Power dissipation has been empirically determined for

two representative KEMET series: C052 and C062. Power dis-

sipation capability for various mounting configurations is shown

in Table 3. This table was extracted from Engineering Bulletin

F-2013, which provides a more detailed treatment of this sub-

ject.

Note that no significant difference was detected between

the two sizes in spite of a 2 to 1 surface area ratio. Due to the

materials used in the construction of multilayer ceramic capac-

itors, the power dissipation capability does not depend greatly

on the surface area of the capacitor body, but rather on how

well heat is conducted out of the capacitor lead wires.

Consequently, this power dissipation capability is applicable to

other leaded multilayer styles and sizes.

RELIABILITY

A well constructed multilayer ceramic capacitor is

extremely reliable and, for all practical purposes, has an infi-

nite life span when used within the maximum voltage and

temperature ratings. Capacitor failure may be induced by sus-

tained operation at voltages that exceed the rated DC voltage,

voltage spikes or transients that exceed the dielectric with-

standing voltage, sustained operation at temperatures above

the maximum rated temperature, or the excessive tempera-

ture rise due to power dissipation.

Failure rate is usually expressed in terms of percent per

1,000 hours or in FITS (failure per billion hours). Some

KEMET series are qualified under U.S. military established

reliability specifications MIL-PRF-20, MIL-PRF-123, MIL-

PRF-39014, and MIL-PRF-55681. Failure rates as low as

0.001% per 1,000 hours are available for all capacitance /

voltage ratings covered by these specifications. These spec-

ifications and accompanying Qualified Products List should

be consulted for details.

TABLE 3

POWER DISSIPATION CAPABILITY

(Rise in Celsius degrees per Watt)

Power

Dissipation

Mounting Configuration

For series not covered by these military specifications,

an internal testing program is maintained by KEMET Quality

Assurance. Samples from each week’s production are sub-

jected to a 2,000 hour accelerated life test at 2 x rated voltage

and maximum rated temperature. Based on the results of

these tests, the average failure rate for all non-military series

covered by this test program is currently 0.06% per 1,000

hours at maximum rated conditions. The failure rate would be

much lower at typical use conditions. For example, using MIL-

HDBK-217D this failure rate translates to 0.9 FITS at 50%

rated voltage and 50°C.

of C052 & C062

1.00" leadwires attached to binding post

of GR-1615 bridge (excellent heat sink)

90 Celsius degrees

rise per Watt 10%

0.25" leadwires attached to binding post

of GR-1615 bridge

55 Celsius degrees

rise per Watt 10%

Capacitor mounted flush to 0.062" glass-

epoxy circuit board with small copper traces

77 Celsius degrees

rise per Watt 10%

Capacitor mounted flush to 0.062" glass-

epoxy circuit board with four square inches

of copper land area as a heat sink

53 Celsius degrees

rise per Watt 10%

Current failure rate details for specific KEMET multilay-

er ceramic capacitor series are available on request.

As shown in Table 3, the power dissipation capability of

the capacitor is very sensitive to the details of its use environ-

ment. The temperature rise due to power dissipation should not

exceed 20°C. Using that constraint, the maximum permissible

power dissipation may be calculated from the data provided in

Table 3.

It is often convenient to translate power dissipation capa-

bility into a permissible AC voltage rating. Assuming a sinu-

soidal wave form, the RMS “ripple voltage” may be calculated

from the following formula:

MISAPPLICATION

Ceramic capacitors, like any other capacitors, may fail

if they are misapplied. Typical misapplications include expo-

sure to excessive voltage, current or temperature. If the

dielectric layer of the capacitor is damaged by misapplication

the electrical energy of the circuit can be released as heat,

which may damage the circuit board and other components

as well.

If potential for misapplication exists, it is recommended

that precautions be taken to protect personnel and equipment

during initial application of voltage. Commonly used precau-

tions include shielding of personnel and sensing for excessive

power drain during board testing.

P_MAX

E = Z x

R

Where E = RMS Ripple Voltage (volts)

P = Power Dissipation (watts)

Z = Impedance

STORAGE AND HANDLING

Ceramic chip capacitors should be stored in normal

working environments. While the chips themselves are quite

robust in other environments, solderability will be degraded

by exposure to high temperatures, high humidity, corrosive

atmospheres, and long term storage. In addition, packaging

materials will be degraded by high temperature – reels may

soften or warp, and tape peel force may increase. KEMET

recommends that maximum storage temperature not exceed

40˚ C, and maximum storage humidity not exceed 70% rela-

tive humidity. In addition, temperature fluctuations should be

minimized to avoid condensation on the parts, and atmos-

pheres should be free of chlorine and sulfur bearing com-

pounds. For optimized solderability, chip stock should be

used promptly, preferably within 1.5 years of receipt.

R = ESR

The data necessary to make this calculation is included in

Engineering Bulletin F-2013. However, the following criteria

must be observed:

1. The temperature rise due to power dissipation

should be limited to 20°C.

2. The peak AC voltage plus the DC voltage must not

exceed the maximum working voltage of the

capacitor.

Provided that these criteria are met, multilayer ceramic

8

APPLICATION NOTES FOR MULTILAYER

CERAMIC CAPACITORS

EFFECT OF FREQUENCY

IMPEDANCE VS FREQUENCY

+0.2

+0.1

0

0.20

0.10

0.0

100

.001μF

.01μF

%ΔC

100

10

-0.1

-0.2

%DF

10

1

100

1K

10K

100K

1M

10M

0.001µF

1

Figure 8.

Frequency - Hertz

Capacitance & DF vs Frequency - C0G

0.01µF

0.1

0⁰.0^.01¹_0.1

1

0

100

1000

Frequency - MHz

Figure 10. Impedance vs Frequency

+5

0

10.0

7.5

5.0

2.5

0.0

0.001

for C0G Dielectric

0.1

1

10

100

1,000

%DF

Figure 10.

Frequency - MHz

%ΔC

-5

Impedance vs Frequency for C0G Dielectric

-10

-15

100

1K

10K

100K

1M

10M

0.1μF ^0.01µF

.01μF

Figure 9.

Frequency - Hertz

10

Capacitance & DF vs Frequency - X7R & Z5U

0.1µ

F

1

1.0 μF

1.0µF

1

0.1

0.01

0.1

1

1 0

100

1000

Frequency -MHz

Figure 11. Impedance vs Frequency

(hours)

EFFECT OF TIME

0.01

for X7R Dielectric

100%

98%

X7R

96%

0.001

94%

0.1

1

10

100

1,000

94%

92%

Figure 11.

Frequency - MHz

90%

88%

100

Impedance vs Frequency for X7R Dielectric

86%

84%

Z5U

10

Z5U

82%

80%

100

0.1µF

1

78%

0.1μF

1.0µF

78%

76%

10

0.1

74%

1

0

1

0

1

0

1

0

K

100K0K

10

1.0 μF

0.01

Figure 13. Typical Aging Rates for X7R & Z5U

0.1

1

0

100

1000

1

Frequency -MHz

Figure 12. Impedance vs Frequency

for Z5U Dielectric

0.1

0.01

0.001

0.1

1

10

100

1,000

Figure 12.

Frequency - MHz

Impedance vs Frequency for Z5U Dielectric

9

CERAMIC CONFORMALLY COATED/AXIAL

“AXIMAX”

ENVIRONMENTAL

GENERAL SPECIFICATIONS

Working Voltage:

Vibration:

EIA RS-198, Method 304, Condition D (10-2000Hz; 20g)

Shock:

EIA RS-198, Method 305, Condition I (100g)

Axial (WVDC)

C0G

X7R

Z5U

50, 100, 200

25, 50, 100, 200, 250

50, 100

Life Test:

Radial (WVDC)

EIA RS-198, Method 201, Condition D.

C0G

X7R

Z5U

50, 100, 200, 500, 1k, 1.5k, 2k, 2.5k, 3k

25, 50, 100, 200, 250, 500, 1k, 1.5k, 2k, 2.5k, 3k

50, 100

<200V

C0G – 200% of rated voltage @ +125°C

X7R – 200% of rated voltage @ +125°C

Z5U – 200% of rated voltage @ +85°C

>500V

Temperature Characteristics:

C0G

X7R

Z5U

0

30 PPM / °C from -55°C to +125°C (1)

15% from -55°C to +125°C

C0G – rated voltage @ +125°C

X7R – rated voltage @ +125°C

+ 22%, -56% from +10°C to +85°C

Post Test Limits @ 25°C are:

Capacitance Change:

Capacitance Tolerance:

C0G

X7R

Z5U

0.5pF, 1%, 2%, 5%, 10%, 20%

C0G ( 200V) – 3% or 0.25pF, whichever is greater.

C0G ( 500V) – 3% or 0.50pF, whichever is greater.

X7R – 20% of initial value (2)

Z5U – 30% of initial value (2)

Dissipation Factor:

10%, 20%, +80% / -20%

20%, 80% / -20%

Construction:

Epoxy encapsulated – meets flame test requirements

of UL Standard 94V-0.

C0G – 0.10% maximum

X7R – 2.5% maximum (3.5% for 25V)

Z5U – 4.0% maximum

High-temperature solder – meets EIA RS-198, Method 302,

Condition B (260°C for 10 seconds)

Insulation Resistance:

C0G – 10 G or 100 M

–

F, whichever is less.

Lead Material:

Standard: 100% matte tin (Sn) with nickel (Ni) underplate

and steel core ( “TA” designation).

>1kV tested @ 500V.

X7R – 10 G or 100 M

–

F, whichever is less.

Alternative 1: 60% Tin (Sn)/40% Lead (Pb) finish with copper-

clad steel core ( “HA” designation).

>1kV tested @ 500V.

Z5U – 1 G or 100 M

– F, whichever is less.

Alternative 2: 60% Tin (Sn)/40% Lead (Pb) finish with 100%

copper core (available with “HA” termination code with c-spec)

Moisture Resistance:

EIA RS-198, Method 204, Condition A (10 cycles

without applied voltage).

Solderability:

EIA RS-198, Method 301, Solder Temperature: 230°C 5°C.

Post Test Limits @ 25°C are:

Capacitance Change:

Dwell time in solder = 7

seconds.

C0G ( 200V) – 3% or 0.25pF, whichever is greater.

C0G ( 500V) – 3% or 0.50pF, whichever is greater.

X7R – 20% of initial value (2)

Z5U – 30% of initial value (2)

Dissipation Factor:

Terminal Strength:

EIA RS-198, Method 303, Condition A (2.2kg)

ELECTRICAL

Capacitance @ 25°C:

C0G – 0.10% maximum

Within specified tolerance and following test conditions.

C0G – >1000pF with 1.0 vrms @ 1 kHz

1000pF with 1.0 vrms @ 1 MHz

X7R – 2.5% maximum (3.5% for 25V)

Z5U – 4.0% maximum

Insulation Resistance:

C0G – 10 G or 100 M

– Fwhichever is less.

X7R – with 1.0 vrms @ 1 kHz (Referee Time: 1,000 hours)

Z5U – with 1.0 vrms @ 1 kHz

500V test @ rated voltage, >500V test @ 500V.

X7R – 10 G or 100 M F, whichever is less.

500V test @ rated voltage, >500V test @ 500V.

–

Dissipation Factor @25°C:

Same test conditions as capacitance.

C0G – 0.10% maximum

X7R – 2.5% maximum (3.5% for 25V)

Z5U – 4.0% maximum

Z5U – 1k M or 100 M

– F, whichever is less.

Thermal Shock:

EIA RS-198, Method 202, Condition B (C0G & X7R:

-55°C to 125°C); Condition A (Z5U: -55°C to 85°C)

Insulation Resistance @25°C:

EIA RS-198, Method 104, Condition A <1kV

C0G – 100 G or 1000 M

– F, whichever is less.

(1) +53 PPM -30 PPM/ °C from +25°C to -55°C, + 60 PPM below 10pF.

(2) X7R and Z5U dielectrics exhibit aging characteristics; therefore, it is highly

recommended that capacitors be deaged for 2 hours at 150°C and stabilized

at room temperature for 48 hours before capacitance measurements are made.

500V test @ rated voltage, >500V test @ 500V

X7R – 100 G or 1000 M

F, whichever is less.

500V test @ rated voltage, >500V test @ 500V

Z5U – 10 G or 1000 M F, whichever is less.

–

Dielectric Withstanding Voltage:

EIA RS-198, Method 103

250V test @ 250% of rated voltage for 5 seconds

with current limited to 50mA.

500V test @ 150% of rated voltage for 5 seconds

with current limited to 50mA.

1000V test @ 120% of rated voltage for 5 seconds

with current limited to 50mA.

10

CERAMIC CONFORMALLY COATED/AXIAL

“AXIMAX”

CAPACITOR OUTLINE DRAWING

MAXIMUM DIMENSIONS — INCHES (MILLIMETERS)

LD (Nominal)

L

Max

D

Max

LL

Min

+.001,-.003

Style

(+.025,-.076)

C410

C412

C420

C430

C440

.170 (4.32)

.260 (6.60)

.290 (7.37)

.400 (10.16)

.100 (2.54)

.120 (3.05)

.100 (2.54)

.150 (3.81)

.020 (.51)

1.0 (25.4)

ORDERING INFORMATION

C 410 C 104 K

5

R

5

T

A

FAILURE RATE

CERAMIC

CASE SIZE

A – Not Applicable

LEAD MATERIAL

See Table Above

T – 100ꢃ Tin (Sn)

SPECIFICATION

H – 60/40ꢃ Tin/Lead (SnPb)

INTERNAL CONSTRUCTION

ꢀ – %ultilayer

C – Standard

CAPACITANCE PICOFARAD CODE

Expressed in picofarads (pF). First two

digits represent significant figures. Third

digit specifies number of zeros. Use 9 for

1.0 through 9.9pF. Example 2.2pF = 229

DIELECTRIC

EIA ꢂesignation

G – C0G (NP0) - Ultra Stable

R – X7R - Stable

U – ZꢀU - General Purpose

CAPACITANCE TOLERANCE

C – 0.2ꢀpFꢁ ꢂ – 0.ꢀpFꢁ F – 1.0ꢃꢁ

G – 2.0ꢃꢁ ꢄ – ꢀꢃꢁ ; – 10ꢃꢁ % – 20ꢃꢁ

Z – -20ꢃ +80ꢃ

RATED VOLTAGE (DC)

A – 2ꢀ0Vꢁ 2 – 200Vꢁ 1 – 100Vꢁ ꢀ – ꢀ0Vꢁ 3 – 2ꢀV

MARKING INFORMATION

Manufacturer

(KEMET)

Rated Voltage

Dielectric

K5R

104K

AB

0814

Capacitance

Code

Capacitance

Tolerance

Lot

Date

Code

11

CERAMIC CONFORMALLY COATED/AXIAL

“AXIMAX”

RATINGS & PART NUMBER REFERENCE

ULTRA-STABLE TEMPERATURE CHARACTERISTIC — C0G/NP0

Style

C410

WVDC

100

C412

WVDC

100

C420

WVDC

100

C430

WVDC

100

C440

WVDC

100

Cap

Code

Cap

Tol

Cap

50

200

50

200

50

200

50

200

50

200

1.0pF

1.5

109

159

189

229

279

339

399

479

569

689

829

100

120

150

180

220

270

330

390

470

560

680

820

101

121

151

181

221

271

331

391

471

561

681

821

102

122

152

182

222

272

332

392

472

562

682

822

103

123

153

C,D

1.8

C,D

2.2

C,D

2.7

C,D

3.3

C,D

3.9

C,D

4.7

C,D

5.6

C,D

6.8

C,D

8.2

C,D

10

J,K,M

12

15

18

22

27

33

39

47

56

68

82

100

120

150

180

220

270

330

390

470

560

680

820

1000

1200

1500

1800

2200

2700

3300

3900

4700

5600

6800

8200

.010uF

.012

.015

For packaging information, see pages 46 and 48.

12

CERAMIC CONFORMALLY COATED/AXIAL

“AXIMAX”

RATINGS & PART NUMBER REFERENCE

STABLE TEMPERATURE CHARACTERISTIC — X7R

Style

Cap

Code

C410

WVDC

100

C412

WVDC

100

C420

WVDC

100

C430

WVDC

100

C440

WVDC

100

Cap

Tol

25

50

200

250

25

50

200

250

25

50

200

250

25

50

200

250

25

50

200

250

Cap

10

12

15

18

22

27

33

39

47

56

68

82

100

120

150

180

220

270

330

390

470

560

680

820

101

121

151

181

221

271

331

391

471

561

681

821

102

122

152

182

222

272

332

392

472

562

682

822

103

123

153

183

223

273

333

393

473

563

683

823

104

124

154

184

224

274

334

394

474

564

684

824

105

125

155

185

225

275

335

395

475

565

685

J, K,M

100

120

150

180

220

270

330

390

470

560

680

820

1000

1200

1500

1800

2200

2700

3300

3900

4700

5600

6800

8200

.010uF

.012

.015

.018

.022

.027

.033

.039

.047

.056

.068

.082

.10

.12

.15

.18

.22

.27

.33

.39

.47

.56

.68

.82

1.0

1.2

1.5

1.8

2.2

2.7

3.3

3.9

4.7

5.6

6.8

For packaging information, see pages 46 and 48.

13

CERAMIC CONFORMALLY COATED/AXIAL

“AXIMAX”

RATINGS & PART NUMBER REFERENCE

GENERAL PURPOSE TEMPERATURE CHARACTERISTIC — Z5U

Style

C410

WVDC

100

C412

WVDC

100

C420

WVDC

100

C430

WVDC

100

C440

WVDC

100

Cap

Code

Cap

Tol

Cap

50

200

50

200

50

200

50

200

50

200

1000pF

1200

1500

1800

2200

2700

3300

3900

4700

5600

6800

8200

.010uF

.012

.015

.018

.022

.027

.033

.039

.047

.056

.068

.082

.10

102

122

152

182

222

272

332

392

472

562

682

822

103

123

153

183

223

273

333

393

473

563

683

823

104

124

154

184

224

274

334

394

474

564

684

824

105

125

155

185

225

M,Z

M.Z

.12

.15

.18

.22

.27

.33

.39

.47

.56

.68

.82

1.0

1.2

1.5

1.8

2.2

For packaging information, see pages 46 and 48.

14

CERAMIC LEADED

PACKAGING INFORMATION

Ceramic Axial

Lead Tape and Reel Packaging

KEMET offers standard reeling of Molded and Conformally

Coated Axial Leaded Ceramic Capacitors for automatic insertion

or lead forming machines per EIA specification RS-296. KEMET’s

internal specification four-digit suffix, 7200, is placed at the end of

the part number to designate tape and reel packaging, ie:

C410C104Z5U5CA7200.

Paper (50 lb.) test minimum is inserted between the layers of

capacitors wound on reels for component pitch ≤ 0.400”.

Capacitor lead length may extend only a maximum of .0625”

(1.59mm) beyond the tapes’ edges. Capacitors are centered in a

row between the two tapes and will deviate only

0.031

(0.79mm) from the row center. A minimum of 36” (91.5 cm) leader

tape is provided at each end of the reel capacitors. Universal

splicing clips are used to connect the tape. Standard reel

quantities are shown on page 48.

46

CERAMIC LEADED

PACKAGING INFORMATION

47

CERAMIC LEADED

PACKAGING INFORMATION

CERAMIC PACKAGING

Standard (1)

Bulk

Quantity

Ammo Pack

Maximum

Reel

Quantity

KEMET

Series

Military

Style

Military

Specification

Reel

Size

Quantity

Maximum

C114C-K-G

C124C-K-G

C192C-K-G

C202C-K

C222C-K

C052C-K-G

C062C-K-G

C114G

C124G

C192G

C202G

C222G

C052/56G

C062/66G

C512G

C522G

C114T

C124T

C192T

C202T

C222T

C052/56T

C062/66T

C31X

C32X

C33X

C340

C350

C410

C412

C420

C430

C440

C512

C522

C617

CK12, CC75

CK13, CC76

CK14, CC77

CK15

MIL-C-11015/

MIL-PRF-20

200/Box

100/Box

25/Box

5000

3000

500

12"

N/A

12"

CK16

10/Tray

300

CK05, CC05

CK06, CC06

CCR75

CCR76

CCR77

CC78-CCR78

CC79-CCR79

CCR05

100/Bag

200/Box

100/Box

25/Box

2000

1500

2000

1500

5000

3000

500

MIL-PRF-20

10/Tray

300

100/Bag

Footnote (2)

200/Box

100/Box

25/Box

1700

1500

N/A

CCR06

CC07-CCR07

CC08-CCR08

CKR11

CKR12

CKR14

CKR15

CKR16

CKR05

CKR06

N/A

MIL-PRF-39014

5000

3000

500

10/Tray

300

100/Bag

500/Bag

250/Bag

100/Bag

50/Bag

300/Box

200/Box

300/Box

200/Box

Footnote (2)

250/Bag

100/Bag

50/Bag

1700

1500

2500

1500

1000

500

5000

2500

N/A

1000

500

2500

1500

1000

N/A

4000

2000

12"

N/A

12"

N/A

C622/C623

C627/C628

C630/C631

C637/C638

C640/C641

C642/C643

C647/C648

C657/C658

C667/C668

50/Bag

500

50/Bag

NOTE: (1) Standard packaging refers to number of pieces per bag, tray or vial.

(2) Quantity varies. For further details, please consult the factory.

48

型号:	C410C150F1G5TA91707200
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	KEMET ELECTRONICS CORP
Reach Compliance Code：	compliant
风险等级：	5.78
电容：	0.000015 µF
电容器类型：	CERAMIC CAPACITOR
直径：	2.41 mm
介电材料：	CERAMIC
JESD-609代码：	e3
长度：	4.32 mm
安装特点：	THROUGH HOLE MOUNT
多层：	Yes
负容差：	1%
端子数量：	2
最高工作温度：	125 °C
最低工作温度：	-55 °C
封装形式：	Axial
包装方法：	TR, 12 INCH
正容差：	1%
额定（直流）电压（URdc）：	100 V
参考标准：	AEC-Q200
表面贴装：	NO
温度特性代码：	C0G
温度系数：	-/+30ppm/Cel ppm/ °C
端子面层：	Matte Tin (Sn)
端子形状：	WIRE

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