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产品型号CA3086的概述

芯片CA3086的概述 CA3086是一种常用的半导体集成电路，属于运算放大器和音频信号处理器类别。它广泛应用于音频、视频和其他信号处理应用中。该芯片由西屋电气（Westinghouse）公司首次推出，凭借其高增益、低失真和宽频带特性，CA3086迅速成为设计工程师的首选。此外，CA3086内部集成了多种功能，包括可配置的增益和独特的电流反馈机制，使其在复杂的信号处理环境中表现出色。芯片CA3086的详细参数 CA3086的详细技术参数如下： - 工作电压范围：±4V至±15V - 增益带宽积：约1.5MHz - 输入阻抗：约1MΩ - 输出阻抗：约75Ω - 最大输出电流：50mA - 输入失调电压：通常为1mV - 失调电流：通常为10nA - 噪声电压：低于50μV（在单位带宽下） - 频率响应：适用于20Hz至100kHz的信号处理此外，CA3086还具有较高的线性度和热稳...

产品型号CA3086的Datasheet PDF文件预览

CA3086

Data Sheet

Augus t 2003

FN483.5

General Purpos e NPN Trans is tor Array

Applications

The CA3086 consists of five general-purpose silicon NPN

transistors on a common monolithic substrate. Two of the

transistors are internally connected to form a differentially

connected pair.

• Power Applications from DC to 120MHz

• General-Purpose Use in Signal Processing Systems

Operating in the DC to 190MHz Range

• Temperature Compensated Amplifiers

The transistors of the CA3086 are well suited to a wide

variety of applications in low-power systems at frequencies

from DC to 120MHz. They may be used as discrete

transistors in conventional circuits. However, they also

provide the very significant inherent advantages unique to

integrated circuits, such as compactness, ease of physical

handling and thermal matching.

• See Application Note, AN5296 “Application of the CA3018

Integrated-Circuit Transistor Array” for Suggested

Applications

Pinout

CA3086 (PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

(BRAND)

TEMP.

RANGE ( C)

PKG.

DWG. #

PACKAGE

13 SUBSTRATE

CA3086

-55 to 125 14 Ld PDIP

E14.3

CA3086M96

(3086)

-55 to 125 14 Ld SOIC Tape M14.15

and Reel

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

CA3086

Absolute Maximum Ratings

Thermal Information

The following ratings apply for each transistor in the device:

Thermal Resistance (Typical, Note 2)

( C/W)

Collector-to-Emitter Voltage, V

. . . . . . . . . . . . . . . . . . . . .15V

CEO

. . . . . . . . . . . . . . . . . . . . . . .20V

PDIP Package . . . . . . . . . . . . . . . . . . .

SOIC Package . . . . . . . . . . . . . . . . . . .

Maximum Power Dissipation (Any one transistor). . . . . . . . .300mW

Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C

Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C

110

130

N/A

Collector-to-Base Voltage, V

CBO

Collector-to-Substrate Voltage, V

(Note 1). . . . . . . . . . . . .20V

CIO

. . . . . . . . . . . . . . . . . . . . . . . . .5V

Emitter-to-Base Voltage, V

EBO

Collector Current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C

(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. The collector of each transistor in the CA3086 is isolated from the substrate by an integral diode. The substrate (Terminal 13) must be connected

to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. To avoid

undesirable coupling between transistors, the substrate (Terminal 13) should be maintained at either DC or signal (AC) ground. A suitable

bypass capacitor can be used to establish a signal ground.

2. θ is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

= 25 C, For Equipment Design

PARAMETER

SYMBOL

TEST CONDITIONS

= 10µA, I = 0

MIN

TYP

MAX

UNITS

Collector-to-Base Breakdown Voltage

Collector-to-Emitter Breakdown Voltage

Collector-to-Substrate Breakdown Voltage

Emitter-to-Base Breakdown Voltage

Collector-Cutoff Current (Figure 1)

(BR)CBO

(BR)CEO

= 1mA, I = 0

= 10µA, I = 0

(BR)ClO

= 10µA, I = 0

100

(BR)EBO

= 10V, I = 0,

0.002

(Figure 2)

100

µA

CBO

CEO

Collector-Cutoff Current (Figure 2)

= 10V, I = 0,

DC Forward-Current Transfer Ratio (Figure 3)

= 3V, I = 1mA

Electrical Specifications

= 25 C, Typical Values Intended Only for Design Guidance

TYPICAL

PARAMETER

SYMBOL

TEST CONDITIONS

VALUES

UNITS

DC Forward-Current Transfer Ratio

(Figure 3)

= 3V

= 10mA

= 10µA

= 1 mA

= 10mA

100

Base-to-Emitter Voltage (Figure 4)

0.715

0.800

-1.9

Temperature Coefficient (Figure 5)

∆V /∆T

= 3V, l = 1 mA

mV/ C

Collector-to-Emitter

Saturation Voltage

= 1mA, I = 10mA

0.23

CE SAT

Noise Figure (Low Frequency)

f = 1kHz, V

= 3V, I = 100µA,

3.25

= 1kΩ

CA3086

Electrical Specifications

T = 25 C, Typical Values Intended Only for Design Guidance (Continued)

TYPICAL

VALUES

PARAMETER

SYMBOL

TEST CONDITIONS

f = 1kHz,V = 3V, I = 1mA

UNITS

Low-Frequency, Small-Signal Equivalent-

Circuit Characteristics:

Forward Current-Transfer Ratio

(Figure 6)

100

3.5

Short-Circuit Input Impedance

(Figure 6)

kΩ

µS

Open-Circuit Output Impedance

(Figure 6)

15.6

-4

Open-Circuit Reverse-Voltage

Transfer Ratio (Figure 6)

1.8 X 10

Admittance Characteristics:

f = 1MHz,V = 3V, l = 1mA

CE C

Forward Transfer Admittance

(Figure 7)

31 - j1.5

Input Admittance (Figure 8)

Output Admittance (Figure 9)

0.3 + j0.04

0.001 + j0.03

See Figure 10

Reverse Transfer Admittance

(Figure 10)

Gain-Bandwidth Product (Figure 11)

Emitter-to-Base Capacitance

= 3V, I = 3mA

550

0.6

MHz

C l

= 3V, I = 0

EBO

Collector-to-Base Capacitance

Collector-to-Substrate Capacitance

= 3V, I = 0

0.58

2.8

CBO

= 3V, I = 0

ClO

Typical Performance Curves

I = 0

= 0

= 15V

= 10V

= 5V

-1

-2

-3

-4

-1

-2

-3

100

125

100

125

TEMPERATURE ( C)

FIGURE 1. I

vs TEMPERATURE

FIGURE 2. I

vs TEMPERATURE

CEO

CBO

CA3086

Typical Performance Curves (Continued)

0.8

0.7

0.6

0.5

0.4

120

= 3V

= 25 C

110

100

0.1

0.01

0.1

1.0

EMITTER CURRENT (mA)

FIGURE 4. V

vs I

FIGURE 3. h vs I

100

= 3V

f = 1kHz

= 25 C

= 100

= 3.5kΩ

1mA

-4

= 1.88 x 10

= 15.6µS

0.9

0.8

0.7

0.6

0.5

0.4

= 3mA

1.0

0.1

= 1mA

= 0.5mA

-75

-50

-25

100

125

0.01

0.1

1.0

COLLECTOR CURRENT (mA)

TEMPERATURE ( C)

FIGURE 6. NORMALIZED h , h , h , h

FE IE RE OE

vs I

FIGURE 5. V

vs TEMPERATURE

COMMON EMITTER CIRCUIT, BASE INPUT

= 25 C, V

= 3V, I = 1mA

= 25 C, V

= 3V, I = 1mA

CE C

-10

-20

0.1

FREQUENCY (MHz)

100

0.1

FREQUENCY (MHz)

100

FIGURE 7. y vs FREQUENCY

FIGURE 8. y vs FREQUENCY

CA3086

Typical Performance Curves (Continued)

COMMON EMITTER CIRCUIT, BASE INPUT

= 25 C, V

= 3V, I = 1mA

= 25 C, V

= 3V, I = 1mA

CE C

IS SMALL AT FREQUENCIES

LESS THAN 500MHz

-0.5

-1.0

-1.5

-2.0

0.1

FREQUENCY (MHz)

100

FREQUENCY (MHz)

FIGURE 9. y

vs FREQUENCY

FIGURE 10. y

vs FREQUENCY

= 3V

= 25 C

1000

900

800

700

600

500

400

300

200

100

COLLECTOR CURRENT (mA)

FIGURE 11. f vs I

CA3086

Dual-In-Line Plas tic Packages (PDIP)

E14.3 (JEDEC MS-001-AA ISSUE D)

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INDEX

AREA

INCHES

MILLIMETERS

1 2

N/2

SYMBOL

MIN

MAX

0.210

MIN

MAX

5.33

NOTES

-B-

-C-

-A-

0.015

0.115

0.014

0.045

0.008

0.735

0.005

0.300

0.240

0.39

2.93

0.356

1.15

0.204

18.66

0.13

7.62

6.10

BASE

PLANE

0.195

0.022

0.070

0.014

0.775

4.95

0.558

1.77

0.355

19.68

SEATING

PLANE

e_A

e_C

e_B

0.010 (0.25) M

B S

0.325

0.280

8.25

7.11

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English

and Metric dimensions, the inch dimensions control.

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication No. 95.

0.430

0.150

10.92

3.81

0.115

2.93

4. Dimensions A, A1 and L are measured with the package seated in

JEDEC seating plane gauge GS-3.

Rev. 0 12/93

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and

dicular to datum

7. e and e are measured at the lead tips with the leads uncon-

are measured with the leads constrained to be perpen-

-C-

strained. e must be zero or greater.

8. B1maximumdimensionsdonotincludedambarprotrusions. Dambar

protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -

1.14mm).

CA3086

Small Outline Plas tic Packages (SOIC)

M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

INDEX

AREA

0.25(0.010)

B M

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

8.55

3.80

MAX

1.75

0.25

0.51

0.25

8.75

4.00

NOTES

0.0532

0.0040

0.013

0.0688

0.0098

0.020

SEATING PLANE

0.0075

0.3367

0.1497

0.0098

0.3444

0.1574

-A-

h x 45

-C-

0.050 BSC

1.27 BSC

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

0.10(0.004)

0.25(0.010) M

C A M B S

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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CA3086产品参数

型号:	CA3086
是否Rohs认证：	不符合
生命周期：	Transferred
包装说明：	IN-LINE, R-PDIP-T14
Reach Compliance Code：	unknown
ECCN代码：	EAR99
风险等级：	5.73
Is Samacsys：	N
最大集电极电流 (IC)：	0.05 A
集电极-发射极最大电压：	15 V
配置：	COMPLEX
最高频带：	VERY HIGH FREQUENCY BAND
JEDEC-95代码：	MS-001AA
JESD-30 代码：	R-PDIP-T14
JESD-609代码：	e0
元件数量：	5
端子数量：	14
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	IN-LINE
极性/信道类型：	NPN
认证状态：	Not Qualified
表面贴装：	NO
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子位置：	DUAL
晶体管应用：	AMPLIFIER
晶体管元件材料：	SILICON
标称过渡频率 (fT)：	550 MHz
Base Number Matches：	1

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