CC1050PWR应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

当前位置：IC37首页_>C字母起始型号索引_>C字母起始型号索引第670页更新时间：2024-10-24 08:30:09

产品型号CC1050PWR的概述

CC1050PWR芯片的概述 CC1050PWR是一款高性能的低功耗射频(RF)收发芯片，广泛应用于短距离无线通信。该芯片设计用于支持低数据速率的无线应用，适合如智能家居、工业自动化、遥控系统以及各种物联网设备等领域。CC1050PWR通常用于传输数据，提供稳定的通信能力，并具有较长的工作范围。 CC1050PWR具有多种功能特点，尤其是其集成的调制解调器支持多种调制方式，从而提高了数据通过率和连接的可靠性。该芯片简化了射频线路的设计，提高了产品的整体效能，并降低了生产成本。 CC1050PWR的详细参数 CC1050PWR芯片的主要技术参数包括： - 频率范围：从300MHz到440MHz，这一频段使其能够有效支持各种无线应用。 - 输出功率：可调输出功率，最大可达到+10dBm，提供良好的传输距离。 - 灵敏度：-109dBm的接收灵敏度，保证可信的接收能力。 - 数据速率：...

产品型号CC1050PWR的Datasheet PDF文件预览

Not Recommended for New Designs

CC1050

Single Chip Very Low Power RF Transmitter

Applications

• Very low power UHF wireless data

transmitters

• RKE – Remote Keyless Entry

• Home automation

• 315 / 433 / 868 and 915 MHz ISM/SRD

band systems

• Wireless alarm and security systems

• AMR – Automatic Meter Reading

• Low power telemetry

• Game Controllers and advanced toys

Product Description

CC1050 is a true single-chip UHF trans-

mitter designed for very low power and

very low voltage wireless applications. The

circuit is mainly intended for the ISM

(Industrial, Scientific and Medical) and

SRD (Short Range Device) frequency

bands at 315, 433, 868 and 915 MHz, but

can easily be programmed for operation at

other frequencies in the 300-1000 MHz

range.

CC1050 is based on Chipcon’s SmartRF^®

technology in 0.35 µm CMOS.

The main operating parameters of CC1050

can be programmed via an easy-to-

interface serial bus, thus making CC1050 a

very flexible and easy to use transmitter.

In a typical system CC1050 will be used

together with a microcontroller and a few

external passive components.

Features

•

True single chip UHF RF transmitter

Very low current consumption

Frequency range 300 – 1000 MHz

Programmable output power –20 to

12 dBm

•

Complies with EN 300 220 and FCC

CFR47 part 15

Programmable frequency in 250 Hz

steps makes crystal temperature drift

compensation possible without TCXO

•

Suitable

protocols

for

frequency

hopping

•

Small size (TSSOP-24 package)

Low supply voltage (2.1 V to 3.6 V)

Very few external components required

Single-ended antenna connection

FSK data rate up to 76.8 kBaud

•

Development Kit available

Easy-to-use software for generating the

CC1050 configuration data

SWRS044

Page 1 of 40

Not Recommended for New Designs

CC1050

Table of Contents

Absolute Maximum Ratings .......................................................................................................4

Operating Conditions .................................................................................................................4

Electrical Specifications .............................................................................................................4

Pin Assignment ..........................................................................................................................7

Application Circuit ......................................................................................................................9

Configuration Overview............................................................................................................10

Configuration Software.............................................................................................................11

3-wire Serial Configuration Interface........................................................................................12

Microcontroller Interface...........................................................................................................14

Signal interface ........................................................................................................................15

Frequency programming..........................................................................................................17

VCO .........................................................................................................................................17

VCO and PLL self-calibration...................................................................................................17

VCO current control .................................................................................................................21

Power management.................................................................................................................21

Output Matching.......................................................................................................................24

Output power programming .....................................................................................................25

Crystal oscillator.......................................................................................................................26

Optional LC Filter .....................................................................................................................27

System Considerations and Guidelines ...................................................................................28

PCB Layout Recommendations...............................................................................................29

Antenna Considerations...........................................................................................................29

Configuration registers.............................................................................................................30

Package Description (TSSOP-24) ...........................................................................................38

Soldering Information...............................................................................................................38

Plastic Tube Specification........................................................................................................38

SWRS044

Page 2 of 40

Not Recommended for New Designs

CC1050

Carrier Tape and Reel Specification ........................................................................................38

Ordering Information ................................................................................................................39

General Information .................................................................................................................39

Address Information.................................................................................................................40

SWRS044

Page 3 of 40

Not Recommended for New Designs

CC1050

Absolute Maximum Ratings

Parameter

Min.

-0.3

Max.

Units

Condition

Supply voltage, VDD

5.0

VDD+0.3,

max 5.0

Voltage on any pin

Input RF level

Storage temperature range

Reflow soldering temperature

dBm

°C

-50

150

260

T = 10 s

Under no circumstances the absolute

maximum ratings given above should be

violated. Stress exceeding one or more of

the limiting values may cause permanent

damage to the device.

Caution! ESD sensitive device.

Precaution should be used when handling

the device in order to prevent permanent

damage.

Operating Conditions

Parameter

Min.

Typ.

Max.

Unit

Condition / Note

RF Frequency Range

300

-40

1000

MHz

Programmable in steps of 250 Hz

Operating ambient temperature range

Supply voltage

°C

2.1

3.0

3.6

Note: The same supply voltage

should be used for digital (DVDD)

and analogue (AVDD) power.

Electrical Specifications

Tc = 25°C, VDD = 3.0 V if nothing else stated

Parameter

Min.

Typ.

Max.

Unit Condition / Note

Transmit Section

Transmit data rate

0.6

76.8

kBaud NRZ or Manchester encoding.

76.8 kBaud equals 76.8 kbit/s

using NRZ coding. See page 15.

Binary FSK frequency separation

kHz

The frequency separation is

programmable in 250 Hz steps.

65 kHz is the maximum

guaranteed separation at 1 MHz

reference frequency. Larger

separations can be achieved at

higher reference frequencies.

Output power

433 MHz

868 MHz

Delivered to 50 Ω load.

The output power is

programmable.

-20

dBm

RF output impedance

433/868 MHz

110 / 70

Transmit mode. For matching

details see p.24.

Ω

SWRS044

Page 4 of 40

Not Recommended for New Designs

CC1050

Parameter

Min.

Typ.

Max.

Unit Condition / Note

Spurious emission

-36

dBm

Complies with EN 300 220

Harmonics

-20

dBc

An external LC should be used to

reduce harmonics emission to

comply with SRD requirements.

See p.27.

Frequency Synthesiser

Section

Crystal Oscillator Frequency

MHz

ppm

Crystal frequency can be 3-4, 6-8

or 9-16 MHz. Recommended

frequencies are 3.6864, 7.3728,

11.0592 and 14.7456. See page

26 for details.

Crystal frequency accuracy

requirement

433 MHz

868 MHz

± 50

± 25

The crystal frequency accuracy

and drift (ageing and

temperature dependency) will

determine the frequency accuracy

of the transmitted signal.

Crystal operation

Parallel

C3 and C4 are loading

capacitors, see page 26

Crystal load capacitance

3-8 MHz, 22 pF recommended

6-8 MHz, 16 pF recommended

9-16 MHz, 16 pF recommended

Crystal oscillator start-up time

1.5

3.6864 MHz, 16 pF load

7.3728 MHz, 16 pF load

16 MHz, 16 pF load

Output signal phase noise

PLL lock time

-80

dBc/Hz At 100 kHz offset from carrier

200

Up to 1 MHz frequency step

Crystal oscillator running

µs

PLL turn-on time, crystal oscillator

on in power down mode

250

Digital Inputs/Outputs

Logic "0" input voltage

Logic "1" input voltage

Logic "0" output voltage

0.7*VDD

0.3*VDD

VDD

0.4

Output current -2.5 mA,

3.0 V supply voltage

Logic "1" output voltage

2.5

VDD

Output current 2.5 mA,

3.0 V supply voltage

Logic "0" input current

Logic "1" input current

DI setup time

-1

Input signal equals GND

Input signal equals VDD

µA

TX mode, minimum time DI must

be ready before the positive edge

of DCLK

DI hold time

TX mode, minimum time DI must

be held after the positive edge of

DCLK

SWRS044

Page 5 of 40

Not Recommended for New Designs

CC1050

Parameter

Min.

Typ.

Max.

Unit Condition / Note

Serial interface (PCLK, PDATA and

PALE) timing specification

See Table 2 page 13

Current Consumption

Power Down mode

0.2

Oscillator core off

µA

Current Consumption,

transmit mode 433/868 MHz:

P=0.01mW (-20dBm)

P=0.3mW (-5dBm)

P=1mW (0dBm)

5.5/8.0

7.3/10.0

9.1/14.2

13.3/17.7

15.9/24.9

23.3/NA

The output power is delivered to a

50Ω load

P=3mW (5dBm)

P=6mW (8dBm)

P=16mW (12dBm)

Current Consumption, crystal osc.

105

3-8 MHz, 16 pF load

9-14 MHz, 12 pF load

14-16 MHz, 16 pF load

µA

Current Consumption, crystal osc.

and bias

400

µA

Current Consumption, crystal osc.,

bias and synthesiser

4.0

5.5

< 500 MHz

> 500 MHz

SWRS044

Page 6 of 40

Not Recommended for New Designs

CC1050

Pin Assignment

Pin no.

Pin name

AVDD

AGND

Pin type

Power (A)

Description

Power supply (3 V) for analog modules (PA)

Ground connection (0 V) for analog modules (PA)

Ground connection (0 V) for analog modules (VCO and prescaler)

Connection no 1 for external VCO tank inductor

Connection no 2 for external VCO tank inductor

Power supply (3 V) for analog modules (VCO and prescaler)

Charge pump current output when external loop filter is used

The pin can also be used as PLL Lock indicator. Output is high

when PLL is in lock.

Ground (A)

Analog input

Power (A)

AVDD

CHP_OUT

Analog output

R_BIAS

AGND

AVDD

Analog output

Ground (A)

Power (A)

Connection for external precision bias resistor (82 kΩ, ± 1%)

Ground connection (0 V) for analog modules (backplane)

Power supply (3 V) for analog modules (general)

Ground connection (0 V) for analog modules (general)

Crystal, pin 2

AGND

XOSC_Q2

XOSC_Q1

AGND

DGND

DVDD

DGND

Ground (A)

Analog output

Analog input

Ground (A)

Ground (D)

Power (D)

Ground (D)

Digital input

Digital output

Digital input

Digital

Crystal, pin 1, or external clock input

Ground connection (0 V) for analog modules (guard)

Ground connection (0 V) for digital modules (substrate)

Power supply (3 V) for digital modules

Ground connection (0 V) for digital modules

Data input in transmit mode

Clock for data in transmit mode

Programming clock for 3-wire bus

Programming data for 3-wire bus. Programming data input for

write operation, programming data output for read operation

Programming address latch enable for 3-wire bus

RF signal output to antenna

DCLK

PCLK

PDATA

input/output

Digital input

RF output

PALE

RF_OUT

A=Analog, D=Digital

(Top View)

AVDD

RF_OUT

AGND

PALE

AGND

PDATA

AGND

PCLK

DCLK

1C50

AVDD

DGND

CHP_OUT

DVDD

R_BIAS

DGND

AGND

AVDD

XOSC_Q1

AGND

XOSC_Q2

SWRS044

Page 7 of 40

Not Recommended for New Designs

CC1050

Circuit Description

CONTROL

DCLK

PDATA, PCLK, PALE

RF_OUT

BIAS

OSC

R_BIAS

XOSC_Q2

XOSC_Q1

CHARGE

PUMP

VCO

LPF

L1 L2

CHP_OUT

Figure 1. Simplified block diagram

The frequency synthesiser generates the

local oscillator signal which is fed to the

PA in transmit mode. The frequency

synthesiser consists of a crystal oscillator

(OSC), phase detector (PD), charge pump

(CHARGE PUMP), VCO, and frequency

dividers (/R and /N). An external crystal

must be connected to XOSC, and only an

external inductor is required for the VCO.

A simplified block diagram of CC1050 is

shown in Figure 1. Only signal pins are

shown.

The voltage controlled oscillator (VCO)

output signal is fed directly to the power

amplifier (PA). The RF output is frequency

shift keyed (FSK) by the digital bit stream

fed to the pin DI. The single ended PA

makes the antenna interface and matching

very easy.

The 3-wire digital serial interface

(CONTROL) is used for configuration.

SWRS044

Page 8 of 40

Not Recommended for New Designs

CC1050

Application Circuit

Very few external components are

required for the operation of CC1050. A

typical application circuit is shown Figure

2. Component values are shown in Table

Crystal oscillator

C3 and C4 are the loading capacitors for

the crystal. See page 26 for details.

Additional filtering

Additional filtering (e.g. a low pass LC-

filter) may be used in order to reduce the

harmonic emission. See also Optional LC

Filter p.27 for further information.

Output matching

C1, C2 and L2 are used to match the

transmitter to 50 Ω. See Output Matching

p.24 for details.

Power supply decoupling and filtering

must be used (not shown in the

application circuit). The placement and

size of the decoupling capacitors and the

power supply filtering are very important to

achieve the optimum performance.

Chipcon provides a reference design

(CC1050EB) that should be followed very

closely.

VCO inductor

The VCO is completely integrated except

for the inductor L1. For further details see

p. 17.

Component values for the matching

network and VCO inductor are easily

calculated using the SmartRF® Studio

software.

AVDD=3V

Antenna

(50 Ohm)

AVDD=3V

LC filter

AVDD

RF_OUT

Optional

AGND

PALE

AGND

PDATA

PCLK

AGND

DCLK

AVDD

CHP_OUT

R_BIAS

AGND

DGND

DVDD

DGND

AGND

DVDD=3V

AVDD

XOSC_Q1

XOSC_Q2

AGND

XTAL

Figure 2. Typical CC1050 application circuit

SWRS044

Page 9 of 40

Not Recommended for New Designs

CC1050

Item

C3*

C4*

315 MHz

433 MHz

868 MHz

915 MHz

5.6 pF, 5%, C0G, 0603

8.2 pF, 5%, C0G, 0603

15 pF, 5%, C0G, 0603

56 nH, 5%, 0603

12 pF, 5%, C0G, 0603

6.8 pF, 5%, C0G, 0603

15 pF, 5%, C0G, 0603

33 nH, 5%, 0603

4.7 pF, 5%, C0G, 0603

5.6 pF, 5%, C0G, 0603

15 pF, 5%, C0G, 0603

5.6 nH, 5%, 0603

4.7 pF, 5%, C0G, 0603

5.6 pF, 5%, C0G, 0603

15 pF, 5%, C0G, 0603

5.6 nH, 5%, 0603

20 nH, 10%, 0805

6.2 nH, 10%, 0805

2.5 nH, 10%, 0805

XTAL

82 kΩ, 1%, 0603

14.7456 MHz crystal,

16 pF load

82 kΩ, 1%, 0603

14.7456 MHz crystal,

16 pF load

82 kΩ, 1%, 0603

14.7456 MHz crystal,

16 pF load

82 kΩ, 1%, 0603

14.7456 MHz crystal,

16 pF load

Notes:

Items shaded are different for different frequencies.

Component values for 868 and 915 MHz are equal.

*) C3 and C4 will depend on the crystal load capacitance, see page 26.

Table 1. Bill of materials for the application circuit

Configuration Overview

frequency

separation

(deviation),

CC1050 can be configured to achieve the

best performance for different

applications. Through the programmable

configuration registers the following key

parameters can be programmed:

crystal oscillator reference frequency

Crystal oscillator power-up / power

down

Data rate and data format (NRZ,

Manchester coded or UART interface)

Synthesiser lock indicator mode

Modulation spectrum shaping

•

Transmit mode / power-down / power-

up mode

•

RF output power

Frequency

parameters: RF output frequency, FSK

synthesiser

key

SWRS044

Page 10 of 40

Not Recommended for New Designs

CC1050

Configuration Software

Chipcon provides users of CC1050 with a

software program, SmartRF® Studio

(Windows interface) that generates all

necessary CC1050 configuration data

based on the user's selections of various

parameters. These hexadecimal numbers

will then be the necessary input to the

microcontroller for the configuration of

CC1050. In addition the program will

provide the user with the component

values needed for the output matching

circuit and the VCO inductor.

Figure 3 shows the user interface of the

CC1050 configuration software.

Figure 3. SmartRF® Studio user interface

SWRS044

Page 11 of 40

Not Recommended for New Designs

CC1050

3-wire Serial Configuration Interface

The timing for the programming is also

shown in Figure 4 with reference to Table

2. The clocking of the data on PDATA is

done on the negative edge of PCLK.

When the last bit, D0, of the 8 data-bits

has been loaded, the data word is loaded

in the internal configuration register.

CC1050 is configured via a simple 3-wire

interface (PDATA, PCLK and PALE).

There are 19 8-bit configuration registers,

each addressed by a 7-bit address. A

Read/Write bit initiates a read or write

operation. A full configuration of CC1050

requires sending 19 data frames of 16 bits

each (7 address bits, R/W bit and 8 data

The configuration data is stored in internal

RAM and is valid after power-down mode,

but not when the power-supply is turned

off. The registers can be programmed in

any order.

bits). The time needed for

full

configuration depend on the PCLK

frequency. With a PCLK frequency of 10

MHz the full configuration is done in less

than 30 µs. Setting the device in power

down mode requires sending one frame

only and will in this case take less than 2

µs. All registers are also readable.

The configuration registers can also be

read by the microcontroller via the same

configuration interface. The seven address

bits are sent first, then the R/W bit set low

to initiate the data read-back. CC1050 then

returns the data from the addressed

output and must be tri-stated (or set high n

the case of an open collector pin) by the

microcontroller during the data read-back

(D7:0). The read operation is illustrated in

Figure 5.

In each write-cycle 16 bits are sent on the

PDATA-line. The seven most significant

bits of each data frame (A6:0) are the

address-bits. A6 is the MSB (Most

Significant Bit) of the address and is sent

as the first bit. The next bit is the R/W bit

(high for write, low for read). During

address and R/W bit transfer the PALE

(Program Address Latch Enable) must be

kept low. The

8 data-bits are then

transferred (D7:0). See Figure 4.

T_SA

T_HA

T_SA

T_CH,min

T_CL,min

T_HD

T_SD

PCLK

Address

Write mode

Data byte

PDATA

PALE

Figure 4. Configuration registers write operation

SWRS044

Page 12 of 40

Not Recommended for New Designs

CC1050

PCLK

PDATA

PALE

Address

Read mode

Data byte

Figure 5. Configuration registers read operation

Parameter Symbol

Min

Max

Units

Conditions

PCLK, clock

frequency

F_CLOCK

MHz

PCLK low

pulse

duration

T_CL,min

The minimum time PCLK must be low.

The minimum time PCLK must be high.

PCLK high

pulse

T_CH,min

duration

PALE setup

time

T_SA

T_HA

T_SD

T_HD

The minimum time PALE must be low before

negative edge of PCLK.

PALE hold

time

The minimum time PALE must be held low after

the positive edge of PCLK.

PDATA setup

time

The minimum time data on PDATA must be ready

before the negative edge of PCLK.

PDATA hold

time

The minimum time data must be held at PDATA,

after the negative edge of PCLK.

Rise time

Fall time

T_rise

T_fall

100

The maximum rise time for PCLK and PALE

The maximum fall time for PCLK and PALE

Note: The set-up- and hold-times refer to 50% of VDD.

Table 2. Serial interface, timing specification

SWRS044

Page 13 of 40

Not Recommended for New Designs

CC1050

Microcontroller Interface

Used in a typical system, CC1050 will

interface to microcontroller. This

microcontroller must be able to:

•

Optionally the microcontroller can do

data encoding / decoding.

Optionally the microcontroller can

monitor the frequency lock status from

pin CHP_OUT (LOCK).

•

Program CC1050 into different modes

via the 3-wire serial configuration

interface (PDATA, PCLK and PALE).

Interface to the synchronous data

signal interface (DI and DCLK).

Connecting the microcontroller

The microcontroller uses 3 output pins for

the configuration interface (PDATA, PCLK

and PALE). PDATA should be a bi-

directional pin for data read-back. The DI

pin is used for data to be transmitted.

DCLK providing the data timing should be

The microcontroller pins connected to

PDATA and PCLK can be used for other

purposes when the configuration interface

is not used. PDATA and PCLK are high

impedance inputs as long as PALE high.

connected to

microcontroller input.

PALE has an internal pull-up resistor and

should be left open (tri-stated by the

microcontroller) or set to a high level

during power down mode in order to

prevent a trickle current flowing in the pull-

up.

Optionally another pin can be used to

monitor the LOCK signal (available at the

CHP_OUT pin). This signal is logic level

high when the PLL is in lock. See

Figure 6.

PDATA

PCLK

Micro-

PALE

controller

CC1050

DCLK

(Optional)

CHP_OUT

(LOCK)

Figure 6. Microcontroller interface

SWRS044

Page 14 of 40

Not Recommended for New Designs

CC1050

Signal interface

The signal interface consists of DI and

DCLK and is used for the data to be

transmitted. DI is the data input line and

the data rates 0.3, 0.6, 1.2, 2.4, 4.8, 9.6,

19.2 or 38.4 kbit/s. The 38.4 kbit/s rate

corresponds to the maximum 76.8 kBaud

due to the Manchester encoding. See

Figure 8.

DCLK provides

a synchronous clock

during data transmission.

Transparent Asynchronous UART mode.

In transmit mode DI is used as data input.

The data is modulated at RF without

synchronisation or encoding. Data rates in

the range from 0.6 to 76.8 kBaud can be

used. See Figure 9.

The CC1050 can be used with NRZ (Non-

Return-to-Zero) data or Manchester (also

known as bi-phase-level) encoded data.

CC1050 can be configured for three

different data formats:

Manchester encoding

In the Synchronous Manchester encoded

Synchronous NRZ mode. CC1050 provides

the data clock at DCLK, and DI is used as

data input. Data is clocked into CC1050 at

the rising edge of DCLK. The data is

modulated at RF without encoding. CC1050

can be configured for the data rates 0.6,

1.2, 2.4, 4.8, 9.6, 19.2, 38.4 or 76.8 kbit/s.

See Figure 7.

mode CC1050 uses Manchester coding

when

Manchester code is based on transitions;

“0” is encoded as low-to-high

modulating

the

data.

The

transition, a “1” is encoded as a high-to-

low transition. See Figure 10.

The Manchester code ensures that the

signal has a constant DC component,

which is necessary in some FSK

demodulators. Using this mode also

ensures compatibility with CC400/CC900

designs.

Synchronous Manchester encoded mode.

CC1050 provides the data clock at DCLK,

and DI is used as data input. Data is

clocked into CC1050 at the rising edge of

DCLK and should be in NRZ format. The

data is modulated at RF with Manchester

code. The encoding is done by CC1050. In

this mode CC1050 can be configured for

DCLK

Clock provided by CC1050

Data provided by microcontroller

“RF”

FSK modulating signal (NRZ),

internal in CC1050

Figure 7. Synchronous NRZ mode

SWRS044

Page 15 of 40

Not Recommended for New Designs

CC1050

DCLK

Clock provided by CC1050

Data provided by microcontroller (NRZ)

“RF”

FSK modulating signal (Manchester encoded),

internal in CC1050

Figure 8. Synchronous Manchester encoded mode

DCLK

DCLK is not used

Data provided by UART (TXD)

“RF”

FSK modulating signal,

internal in CC1050

Figure 9. Transparent Asynchronous UART mode

1 0 1 1 0 0 0 1 1 0 1

data

Time

Figure 10. Manchester encoding

SWRS044

Page 16 of 40

Not Recommended for New Designs

CC1050

Frequency programming

The operation frequency is set by

programming the frequency word in the

configuration registers. There are two

frequency words registers, termed A and

B, which can be programmed to two

different frequencies in order to switch fast

FREQ + 8192

f_VCO= f_ref

⋅

16384

where the reference frequency is the

crystal oscillator clock divided by REFDIV

(4 bits in the PLL register), a number

between 2 and 15:

between

two

different

channels.

f_xosc

Frequency word A or B is selected by the

F_REG bit in the MAIN register.

f_ref

REFDIV

The equation above gives the VCO

frequency, that is, f_VCOis the f₀frequency

for transmit mode (lower FSK frequency).

The frequency word is 24 bits (3 bytes)

located in FREQ_2A:FREQ_1A:FREQ_0A

and FREQ_2B:FREQ_1B:FREQ_0B for

the A and B word respectively.

The upper FSK frequency is given by:

f₁= f₀+ f_sep

where f_sepis set by the separation word:

The FSK

programmed in the FSEP1:FSEP0

frequency separation is

registers (11 bits).

FSEP

f_sep= f_ref

⋅

The frequency word FREQ is calculated

by:

16384

VCO

Only one external inductor (L1) is required

for the VCO. The inductor will determine

the operating frequency range of the

circuit. It is important to place the inductor

as close to the pins as possible in order to

Typical tuning range for the integrated

varactor is 20-25%.

Component values for various frequencies

are given in Table 1. Component values

for other frequencies can be found using

the SmartRF® Studio software.

reduce

stray

inductance.

recommended to use a high Q, low

tolerance inductor for best performance.

VCO and PLL self-calibration

To compensate for supply voltage,

temperature and process variations the

VCO and PLL must be calibrated. The

calibration is done automatically and sets

maximum VCO tuning range and optimum

charge pump current for PLL stability.

After setting up the device at the operating

frequency, the self-calibration can be

initiated by setting the CAL_START bit.

The calibration result is stored internally in

the chip, and is valid as long as power is

not turned off. If large supply voltage

variations (more than 0.5 V) or

temperature variations (more than 40

degrees) occur after calibration, a new

calibration should be performed.

The self-calibration is controlled through

the CAL register (see configuration

registers description p. 30). The

CAL_COMPLETE bit indicates complete

calibration. The user can poll this bit, or

simply wait for 26 ms (calibration wait time

when CAL_WAIT = 1). The wait time is

proportional to the internal PLL reference

frequency. The lowest permitted reference

frequency (1 MHz) gives 26 ms wait time,

which is therefore the worst case.

Reference

Calibration time

frequency [MHz]

[ms]

2.4

2.0

1.5

1.0

SWRS044

Page 17 of 40

Not Recommended for New Designs

CC1050

The CAL_COMPLETE bit can also be

monitored at the CHP_OUT (LOCK) pin

(configured by LOCK_SELECT[3:0]) and

used as an interrupt input to the

microcontroller.

MHz, or different VCO currents are used

(VCO_CURRENT[3:0] in the CURRENT

separately. The CAL_DUAL bit in the CAL

calibration.

The CAL_START bit must be set to 0 by

the microcontroller after the calibration is

done.

The single calibration algorithm using

separate calibration for two frequencies is

illustrated in Figure 11.

There are separate calibration values for

the two frequency registers. If the two

frequencies, A and B, differ more than 1

In Figure 12 the dual calibration algorithm

is shown.

SWRS044

Page 18 of 40

Not Recommended for New Designs

CC1050

Start single calibration

Write FREQ_A, FREQ_B

If DR>=38kBd then {write TEST4: L2KIO=3Fh,

PRESCALER = 04h}

Write CAL: CAL_DUAL = 0

Frequency register A and B are used for

two different channels

Frequency register A is calibrated first

Write MAIN:

F_REG = 0; TX_PD = 0; FS_PD = 0

CORE_PD = 0; BIAS_PD = 0; RESET_N=1

‘Current’ is the VCO current to be used

for both frequencies

PA is turned off to prevent spurious emission

Write CURRENT:

VCO_CURRENT = Current

Write PA_POW = 00h

The result of the calibration is stored for

frequency FREQ_A and can be read from

the status registers TEST0 and TEST2

when F_REG = 0

Write CAL:

CAL_START=1

Calibration time depend on the reference

frequency, see text.

Wait for maximum 26 ms, or

Read CAL and wait until

CAL_COMPLETE=1

Write CAL:

CAL_START=0

Frequency register B is calibrated second

Write MAIN: F_REG = 1

The result of the calibration is stored for

frequency FREQ_B and can be read from

the status registers TEST0 and TEST2

when F_REG = 1

Write CAL:

CAL_START=1

Wait for 26 ms, or

Read CAL and wait until

CAL_COMPLETE=1

Write CAL:

CAL_START=0

End of calibration

Figure 11. Single calibration algorithm for two different frequencies

SWRS044

Page 19 of 40

Not Recommended for New Designs

CC1050

Start dual calibration

Write FREQ_A, FREQ_B

If DR>=38kBd then {write TEST4: L2KIO=3Fh,

PRESCALER = 04h}

Frequency registers A and B are both used

Write CAL: CAL_DUAL = 1

Either frequency register A or B is selected

Write MAIN:

F_REG = 0

TX_PD = 0; FS_PD = 0

CORE_PD = 0; BIAS_PD = 0; RESET_N=1

Write CURRENT:

VCO_CURRENT = Current

Write PA_POW = 00h

‘Current’ is the VCO current to be

used for both frequencies

The result of the calibration is stored for

Both frequency FREQ_A and FREQ_B, and

can be read from the status registers TEST0

and TEST2

Write CAL:

CAL_START=1

Wait for maximum 26 ms, or

Read CAL and wait until

CAL_COMPLETE=1

Calibration time depend on the reference

frequency, see text.

Write CAL:

CAL_START=0

End of calibration

Figure 12. Dual calibration algorithm

SWRS044

Page 20 of 40

Not Recommended for New Designs

CC1050

VCO current control

The VCO current is programmable and

should be set according to operating

The bias current for the PA buffers are

also programmable. Recommended

frequency

Recommended

VCO_CURRENT bits in the CURRENT

32.

and

output

settings

power.

for the

settings for the PA_DRIVE bits in the

CURRENT register are shown in the

tables on page 32.

Power management

typical power-on and initialising

CC1050 offers great flexibility for power

management in order to meet strict power

consumption requirements in battery

operated applications. Power Down mode

is controlled through the MAIN register.

There are separate bits to control the TX

part, the frequency synthesiser and the

crystal oscillator. This individual control

can be used to optimise for lowest

possible current consumption in a certain

application.

sequence for minimum power

consumption is shown in Figure 13 and

Figure 14.

PALE should be tri-stated or set to a high

level during power down mode in order to

prevent a trickle current from flowing in the

internal pull-up resistor.

PA_POW should be set to 00h during

power down mode to ensure lowest

possible

leakage

current.

SWRS044

Page 21 of 40

Not Recommended for New Designs

CC1050

Power Off

Power turned on

Initialise and reset:

MAIN:

F_REG = 0

Reset and turn on the

crystal oscillator core

TX_PD = 1

FS_PD = 1

CORE_PD = 0

BIAS_PD = 1

RESET_N = 0

*Time to wait depends on the crystal frequency

and the load capacitance

MAIN: RESET_N = 1

Wait 2 ms*

Program all registers except MAIN

Calibrate VCO and PLL

Calibration is performed according

to calibration algorithm

PA_POW = 00h

MAIN: TX_PD = 1, FS_PD = 1,

CORE_PD = 1, BIAS_PD = 1

Power Down

Figure 13. Initializing sequence

SWRS044

Page 22 of 40

Not Recommended for New Designs

CC1050

Power Down

Turn on crystal oscillator core

MAIN: CORE_PD = 0

Wait 2 ms*

*Time to wait depends on the crystal frequency

and the load capacitance

Turn on bias generator

BIAS_PD = 0

Wait 200 µs

Turn on TX:

PA_POW = 00h

MAIN: F_REG = 1

FS_PD = 0

Waiting for the PLL to lock

Waiting for the PA to ramp up

Wait 250 µs

TX_PD = 0

PA_POW = ‘Output power’

Wait 20 µs

TX mode

Turn off TX:

PA_POW = 00h

MAIN: TX_PD = 1, FS_PD = 1,

CORE_PD=1, BIAS_PD=1

Power Down

Figure 14. Sequence for activating TX mode

SWRS044

Page 23 of 40

Not Recommended for New Designs

CC1050

Output Matching

few passive external components

are given in Table 1. Component values

for other frequencies can be found using

the configuration software.

ensures match in TX mode. The matching

network is shown in Figure 15.

Component values for various frequencies

TO ANTENNA

RF_OUT

CC1050

AVDD=3V

Figure 15. Output matching network

SWRS044

Page 24 of 40

Not Recommended for New Designs

CC1050

Output power programming

The RF output power is programmable

and controlled by the PA_POW register.

In power down mode the PA_POW should

be set to 00h for minimum leakage

current.

Table 3 shows the closest programmable

value for output powers in steps of 1 dB.

The typical current consumption is also

shown.

Output power

[dBm]

RF frequency 433 MHz

RF frequency 868 MHz

PA_POW

[hex]

Current consumption,

typ. [mA]

PA_POW

[hex]

Current consumption,

typ. [mA]

-20

-19

-18

-17

-16

-15

-14

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

5.5

5.7

6.0

6.2

6.5

6.8

7.0

7.3

7.5

8.0

8.3

8.5

8.7

8.9

9.1

9.4

9.6

9.8

10.0

10.4

10.6

10.9

13.4

14.2

15.0

15.7

16.3

17.0

17.7

19.1

20.0

24.9

7.8

8.3

8.5

9.1

10.5

11.5

12.4

13.3

14.7

15.1

15.9

17.6

19.2

20.0

23.3

Table 3. Output power settings and typical current consumption

SWRS044

Page 25 of 40

Not Recommended for New Designs

CC1050

Crystal oscillator

CC1050 has an advanced amplitude

regulated crystal oscillator. A high current

is used to start up the oscillations. When

the amplitude builds up, the current is

reduced to what is necessary to maintain

a 600 mVpp amplitude. This ensures a

DR_new

f_{xtal _ new}= f_xtal

Using the internal crystal oscillator, the

crystal must be connected between

XOSC_Q1 and XOSC_Q2. The oscillator

is designed for parallel mode operation of

the crystal. In addition loading capacitors

(C3 and C4) for the crystal are required.

The loading capacitor values depend on

the total load capacitance, C_L, specified for

the crystal. The total load capacitance

seen between the crystal terminals should

equal C_Lfor the crystal to oscillate at the

specified frequency.

fast

start-up,

keeps

the

current

consumption as well as the drive level to a

minimum and makes the oscillator

insensitive to ESR variations.

An external clock signal or the internal

crystal oscillator can be used as main

frequency reference. An external clock

signal should be connected to XOSC_Q1,

while XOSC_Q2 should be left open. The

XOSC_BYPASS bit in the XOSC register

should be set when an external clock

signal is used.

C_L=

+ C_parasitic

C₃C₄

The crystal frequency should be in the

range 3-4, 6-8 or 9-16 MHz. Because the

crystal frequency is used as reference for

the data rate (as well as other internal

functions), the following frequencies are

recommended: 3.6864, 7.3728, 11.0592

or 14.7456 MHz. These frequencies will

give accurate data rates. The crystal

The parasitic capacitance is constituted by

pin input capacitance and PCB stray

capacitance. Typically the total parasitic

capacitance is 8 pF. A trimming capacitor

may be placed across C4 for initial tuning

if necessary.

frequency

range

selected

The crystal oscillator circuit is shown in

Figure 16. Typical component values for

different values of C_Lare given in Table 4.

XOSC_FREQ1:0 in the MODEM0 register.

To operate in synchronous mode at data

rates different from the standards at 1.2,

2.4, 4.8 kBaud and so on, the crystal

frequency can be scaled. The data rate

(DR) will change proportionally to the new

crystal frequency (f). To calculate the new

crystal frequency:

The initial tolerance, temperature drift,

ageing and load pulling should be carefully

specified in order to meet the required

frequency

accuracy

certain

application.

XOSC_Q1

XOSC_Q2

XTAL

Figure 16. Crystal oscillator circuit

Item

C_L= 12 pF

6.8 pF

C_L= 16 pF

15 pF

C_L= 22 pF

27 pF

6.8 pF

15 pF

27 pF

Table 4. Crystal oscillator component values

SWRS044

Page 26 of 40

Not Recommended for New Designs

CC1050

Optional LC Filter

An optional LC filter may be added

between the antenna and the matching

network in certain applications. The filter

will reduce the emission of harmonics.

A T-Type LC filter can be used to further

attenuate harmonics if the Pi-type filter is

not sufficient. A T-type filter provides much

better stop-band attenuation than a Pi-

type filter due to improved insulation

between input and output. For more

details refer to Application Note AN028 LC

Filter with Improved High-Frequency

Attenuation available from the Chipcon

A Pi-type filter topology is shown in Figure

17. Component values are given in Table

5. The filter is designed for 50

Ω

terminations. The component values may

have to be tuned to compensate for layout

parasitics.

web

site.

L71

C71

C72

Figure 17. LC filter

Item

C71

C72

L71

315 MHz

30 pF

433 MHz

20 pF

868 MHz

915 MHz

10 pF

5.6 nH

15 nH

12 nH

4.7 nH

Table 5. LC filter component values

SWRS044

Page 27 of 40

Not Recommended for New Designs

CC1050

System Considerations and Guidelines

compensation of the crystal if the

temperature drift curve is known and a

temperature sensor is included in the

system. Even initial adjustment can be

done using the frequency programmability.

This eliminates the need for an expensive

TCXO and trimming in some applications.

In less demanding applications a crystal

with low temperature drift and low ageing

SRD regulations

International regulations and national laws

regulate the use of radio receivers and

transmitters. SRDs (Short Range Devices)

for licence free operation are allowed to

operate in the 433 and 868-870 MHz

bands in most European countries. In the

United States such devices operate in the

260–470 and 902-928 MHz bands. CC1050

is designed to meet the requirements for

operation in all these bands. A summary

of the most important aspects of these

regulations can be found in Application

Note AN001 SRD regulations for licence

free transceiver operation, available from

Chipcon’s web site.

could

used

without

further

compensation. A trimmer capacitor in the

crystal oscillator circuit (in parallel with C4)

could be used to set the initial frequency

accurately.

High output power systems

The CHP_OUT (LOCK) pin can be

configured to control an power amplifier.

This is controlled by LOCK_SELECT in

the LOCK register.

Low cost systems

In systems where low cost is of great

importance the CC1050 is the ideal choice.

Very few external components keep the

total cost at a minimum. The oscillator

crystal can then be a low cost crystal with

50 ppm frequency tolerance.

Frequency hopping spread spectrum

systems

Due to the very fast frequency shift

properties of the PLL, the CC1050 is also

suitable for frequency hopping systems.

Hop rates of 1-100 hops/s are usually

used depending on the bit rate and the

amount of data to be sent during each

transmission. The two frequency registers

(FREQ_A and FREQ_B) are designed

such that the ‘next’ frequency can be

programmed while the ‘present’ frequency

is used. The switching between the two

frequencies is done through the MAIN

Battery operated systems

In low power applications the power down

mode should be used when not being

active. Depending on the start-up time

requirement, the oscillator core can be

powered during power down. See page 21

for information on how effective power

management can be implemented.

Crystal drift compensation

A unique feature in CC1050 is the very fine

frequency resolution of 250 Hz. This can

be used to do the temperature

SWRS044

Page 28 of 40

Not Recommended for New Designs

CC1050

PCB Layout Recommendations

A two layer PCB is highly recommended.

The bottom layer of the PCB should be the

“ground-layer”. Chipcon provide reference

designs that should be followed in order to

achieve the best performance.

Precaution should be used when placing

the microcontroller in order to avoid

interference with the RF circuitry.

In certain applications where the ground

plane for the digital circuitry is expected to

be noisy, the ground plane may be split in

an analogue and a digital part. All AGND

pins and AVDD de-coupling capacitors

should be connected to the analogue

ground plane. All DGND pins and DVDD

The top layer should be used for signal

routing, and the open areas should be

filled with metallisation connected to

ground using several vias.

The ground pins should be connected to

ground as close as possible to the

package pin using individual vias. The de-

coupling capacitors should also be placed

as close as possible to the supply pins

and connected to the ground plane by

separate vias.

de-coupling

capacitors

should

connected to the digital ground. The

connection between the two ground

planes should be implemented as a star

connection with the power supply ground.

A development kit with a fully assembled

PCB is available, and can be used as a

guideline for layout.

The external components should be as

small as possible and surface mount

devices should be used.

Antenna Considerations

difficult impedance matching because of

their very low radiation resistance.

CC1050 can be used together with various

types of antennas. The most common

antennas for short range communication

are monopole, helical and loop antennas.

For low power applications the λ/4-

monopole antenna is recommended giving

the best range and because of its

simplicity.

Monopole

antennas

are

resonant

antennas with a length corresponding to

one quarter of the electrical wavelength

(λ/4). They are very easy to design and

can be implemented simply as a “piece of

wire” or even integrated into the PCB.

The length of the λ/4-monopole antenna is

given by:

L = 7125 / f

Non-resonant monopole antennas shorter

than λ/4 can also be used, but at the

expense of range. In size and cost critical

applications such an antenna may very

well be integrated into the PCB.

where f is in MHz, giving the length in cm.

An antenna for 869 MHz should be 8.2

cm, and 16.4 cm for 434 MHz.

The antenna should be connected as

close as possible to the IC. If the antenna

is located away from the input pin the

antenna should be matched to the feeding

transmission line (50 Ω).

Helical antennas can be thought of as a

combination of a monopole and a loop

antenna. They are a good compromise in

size critical applications. But helical

antennas tend to be more difficult to

optimise than the simple monopole.

For a more thorough primer on antennas,

please refer to Application Note AN003

SRD Antennas available from Chipcon’s

web site.

Loop antennas are easy to integrate into

the PCB, but are less effective due to

SWRS044

Page 29 of 40

Not Recommended for New Designs

CC1050

Configuration registers

Studio software. A complete description of

the registers are given in the following

tables. After a RESET is programmed all

the registers have default values.

The configuration of CC1050 is done by

programming the 19 8-bit configuration

registers. The configuration data based on

selected system parameters are most

easily found by using the SmartRF®

ADDRESS

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

40h

41h

42h

43h

44h

45h

46h

Byte Name

MAIN

Description

MAIN Register

FREQ_2A

FREQ_1A

FREQ_0A

FREQ_2B

FREQ_1B

FREQ_0B

FSEP1

FSEP0

CURRENT

XOSC

Frequency Register 2A

Frequency Register 1A

Frequency Register 0A

Frequency Register 2B

Frequency Register 1B

Frequency Register 0B

Frequency Separation Register 1

Frequency Separation Register 0

Current Consumption Control Register

Crystal Oscillator Control Register

PA Output Power Control Register

PLL Control Register

LOCK Status Register and signal select to CHP_OUT (LOCK) pin

VCO Calibration Control and Status Register

Not used

Modem Control Register

Not used

PA_POW

PLL

LOCK

CAL

Not used

MODEM0

Not used

FSCTRL

Frequency Synthesiser Control Register

Reserved

PRESCALER Prescaler Control Register

TEST6

TEST5

TEST4

TEST3

TEST2

TEST1

TEST0

Test register for PLL LOOP

Test register for PLL LOOP (must be updated as specified)

Test register for VCO

Test register for Calibration

SWRS044

Page 30 of 40

Not Recommended for New Designs

CC1050

MAIN Register (00h)

NAME

Default Active Description

value

MAIN[7]

MAIN[6]

Not used

F_REG

Selection of Frequency Register, 0 : Register A, 1 :

MAIN[5]

MAIN[4]

MAIN[3]

MAIN[2]

MAIN[1]

Not used

TX_PD

FS_PD

CORE_PD

BIAS_PD

Power Down of Signal Interface and PA

Power Down of Frequency Synthesiser

Power Down of Crystal Oscillator Core

Power Down of BIAS (Global_Current_Generator)

and Crystal Oscillator Buffer

MAIN[0]

RESET_N

Reset, active low. Writing RESET_N low will write default

values to all other registers than MAIN. Bits in MAIN do

not have a default value, and will be written directly

through the configurations interface. Must be set high to

complete reset.

FREQ_2A Register (01h)

NAME

Default

Active Description

value

FREQ_2A[7:0]

FREQ_A[23:16]

01110101

8 MSB of frequency control word A

FREQ_1A Register (02h)

NAME

Default

value

Active Description

FREQ_1A[7:0]

FREQ_A[15:8]

10100000

Bit 15 to 8 of frequency control word A

FREQ_0A Register (03h)

NAME

Default

value

Active Description

FREQ_0A[7:0]

FREQ_A[7:0]

11001011

8 LSB of frequency control word A

FREQ_2B Register (04h)

NAME

Default

value

Active Description

FREQ_2B[7:0]

FREQ_B[23:16]

01110101

8 MSB of frequency control word B

FREQ_1B Register (05h)

NAME

Default

value

Active Description

FREQ_1B[7:0]

FREQ_B[15:8]

10100101

Bit 15 to 8 of frequency control word B

FREQ_0B Register (06h)

NAME

Default

value

Active Description

FREQ_0B[7:0]

FREQ_B[7:0]

01001110

8 LSB of frequency control word B

FSEP1 Register (07h)

NAME

Default

value

Active Description

FSEP1[7:3]

Not used

FSEP1[2:0]

FSEP_MSB[2:0]

000

3 MSB of frequency separation control

FSEP0 Register (08h)

NAME

FSEP_LSB[7:0]

Default

value

01011001

Active Description

8 LSB of frequency separation control

FSEP0[7:0]

SWRS044

Page 31 of 40

Not Recommended for New Designs

CC1050

CURRENT Register (09h)

NAME

Default Active Description

value

CURRENT[7:4]

VCO_CURRENT[3:0]

1100

Control of current in VCO core

0000 : 160µA

0001 : 320µA

0010 : 480µA

0011 : 630µA

0100 : 790µA

0101 : 950µA

0110 : 1100µA

0111 : 1250µA

1000 : 1560µA, use for f< 500 MHz

1001 : 1720µA

1010 : 1870µA

1011 : 2030µA

1100 : 2180µA

1101 : 2340µA

1110 : 2490µA

1111 : 2640µA, use for f>500 MHz

CURRENT[3:2]

CURRENT[1:0]

Not used

PA_DRIVE[1:0]

Control of current in VCO buffer for PA

00 : 1mA

01 : 2mA, use for TX, f<500 MHz

10 : 3mA

11 : 4mA, use for TX, f>500 MHz

XOSC Register (0Ah)

NAME

Default Active Description

value

XOSC[7:1]

XOSC[0]

Not used

XOSC_BYPASS

0 : Internal XOSC enabled

1 : Power-Down of XOSC, external CLK used

SWRS044

Page 32 of 40

Not Recommended for New Designs

CC1050

PA_POW Register (0Bh)

NAME

Default

value

0000

Active Description

PA_POW[7:4]

PA_HIGHPOWER[3:0]

Control of output power in high power array.

Should be 0000 in PD mode . See

Table 3 page 25 for details.

PA_POW[3:0]

PA_LOWPOWER[3:0]

1111

Control of output power in low power array

Should be 0000 in PD mode. See

Table 3 page 25 for details.

PLL Register (0Ch)

NAME

Default

value

Active Description

PLL[7]

EXT_FILTER

1 : External loop filter

0 : Internal loop filter

1-to-0 transition samples F_COMP

comparator when BREAK_LOOP=1

(TEST3)

PLL[6:3]

REFDIV[3:0]

0010

Reference divider

0000 : Not allowed

0001 : Not allowed

0010 : Divide by 2

0011 : Divide by 3

...........

1111 : Divide by 15

PLL[2]

PLL[1]

PLL[0]

ALARM_DISABLE

ALARM_H

0 : Alarm function enabled

1 : Alarm function disabled

Status bit for tuning voltage out of range

(too close to VDD)

Status bit for tuning voltage out of range

(too close to GND)

ALARM_L

SWRS044

Page 33 of 40

Not Recommended for New Designs

CC1050

LOCK Register (0Dh)

NAME

Default

value

0000

Active

Description

LOCK[7:4]

LOCK_SELECT[3:0]

Selection of signals to CHP_OUT (LOCK) pin

0000 : Normal, pin can be used as CHP_OUT

0001 : LOCK_CONTINUOUS (active high)

0010 : LOCK_INSTANT (active high)

0011 : ALARM_H (active high)

0100 : ALARM_L (active high)

0101 : CAL_COMPLETE (active high)

0110 : Not used

0111 : REFERENCE_DIVIDER Output

1000 : TX_PDB (active high, activates external

PA when TX_PD=0)

1001 : Not used

1010 : Not used

1011 : Not used

1100 : Not used

1101 : Not used

1110 : N_DIVIDER Output

1111 : F_COMP

LOCK[3]

LOCK[2]

PLL_LOCK_

ACCURACY

0 : Sets Lock Threshold = 127, Reset Lock

Threshold = 111. Corresponds to a worst case

accuracy of 0.7%

1 : Sets Lock Threshold = 31, Reset Lock

Threshold =15. Corresponds to a worst case

accuracy of 2.8%

0 : Normal PLL lock window

1 : Not used

PLL_LOCK_

LENGTH

LOCK[1]

LOCK[0]

LOCK_INSTANT

LOCK_CONTINUOUS

Status bit from Lock Detector

CAL Register (0Eh)

NAME

Default

Active Description

value

CAL[7]

CAL_START

↑

↑ 1 : Calibration started

0 : Calibration inactive

CAL_START must be set to 0 after

calibration is done

CAL[6]

CAL[5]

CAL_DUAL

CAL_WAIT

1 : Store calibration in both A and B

0 : Store calibration in A or B defined by

MAIN[6]

1 : Normal Calibration Wait Time

0 : Half Calibration Wait Time

The calibration time is proportional to the

internal reference frequency. 2 MHz

reference frequency gives 14 ms wait time.

1 : Calibration Current Doubled

0 : Normal Calibration Current

Status bit defining that calibration is

complete

CAL[4]

CAL[3]

CAL_CURRENT

CAL_COMPLETE

CAL_ITERATE

CAL[2:0]

101

Iteration start value for calibration DAC

000 - 101: Not used

110 : Normal start value

111 : Not used

SWRS044

Page 34 of 40

Not Recommended for New Designs

CC1050

MODEM0 Register (11h)

NAME

Default Active Description

value

MODEM0[7]

MODEM0[6:4]

Not used

BAUDRATE[2:0]

010

000 : 0.6 kBaud

001 : 1.2 kBaud

010 : 2.4 kBaud

011 : 4.8 kBaud

100 : 9.6 kBaud

101 : 19.2 kBaud

110 : 38.4 kBaud

111 : 76.8 kBaud

00 : NRZ operation.

01 : Manchester operation

10 : Transparent Asyncronous UART operation

11 : Not used

Selection of XTAL frequency range

00 : 3MHz - 4MHz crystal, 3.6864MHz

recommended

MODEM0[3:2] DATA_FORMAT[1:0]

MODEM0[1:0]

XOSC_FREQ[1:0]

01 : 6MHz - 8MHz crystal, 7.3728MHz

recommended

10 : 9MHz - 12MHz crystal, 11.0592 MHz

recommended

11 : 12MHz - 16MHz crystal, 14.7456MHz

recommended

FSCTRL Register (13h)

NAME

Default Active Description

value

FSCTRL[7:4]

FSCTRL[3:1]

Not used

Reserved

FSCTRL[0]

FS_RESET_N

Separate reset of frequency synthesizer

PRESCALER Register (1Ch)

NAME

Default Active Description

value

PRESCALER[7:6]

PRE_SWING[1:0]

Prescaler swing. Fractions for

PRE_CURRENT[1:0] = 00

00 : 1 * Nominal Swing

01 : 2/3 * Nominal Swing

10 : 7/3 * Nominal Swing

11 : 5/3 * Nominal Swing

Prescaler current scaling

PRESCALER[5:4]

PRE_CURRENT

[1:0]

00 : 1 * Nominal Current

01 : 2/3 * Nominal Current

10 : 1/2 * Nominal Current

11 : 2/5 * Nominal Current

Bypass the resistor in the PLL loop filter

0 : Not bypassed

1 : Bypassed

Disconnect the capacitor in the PLL loop filter

0 : Capacitor connected

PRESCALER[3]

PRESCALER[2]

BYPASS_R

DISCONNECT_C

1 : Capacitor disconnected. Use for data rate

38.4 and 76.8 kBaud only.

Not used

PRESCALER[1:0]

SWRS044

Page 35 of 40

Not Recommended for New Designs

CC1050

TEST6 Register (for test only, 40h)

NAME

Default

value

Active Description

TEST6[7]

LOOPFILTER_TP1

LOOPFILTER_TP2

CHP_OVERRIDE

CHP_CO[4:0]

1 : Select testpoint 1 to CHP_OUT

0 : CHP_OUT tied to GND

1 : Select testpoint 2 to CHP_OUT

0 : CHP_OUT tied to GND

1 : use CHP_CO[4:0] value

0 : use calibrated value

TEST6 [6]

TEST6 [5]

TEST6[4:0]

10000

Charge_Pump Current DAC override value

TEST5 Register (for test only, 41h)

NAME

Default

Active Description

value

TEST5[7:6]

TEST5[5]

Not used

CHP_DISABLE

1 : CHP up and down pulses disabled

0 : normal operation

TEST5[4]

VCO_OVERRIDE

VCO_AO[3:0]

1 : use VCO_AO[3:0] value

0 : use calibrated value

VCO_ARRAY override value

TEST5[3:0]

1000

TEST4 Register (for test only, 42h)

NAME

Default

value

Active Description

TEST4[7:6]

TEST4[5:0]

Not used

L2KIO[5:0]

100101

Constant setting charge pump current

scaling/rounding factor. Sets Bandwidth of

PLL. Use 3Fh for 38.4 and 76.8 kBaud

TEST3 Register (for test only, 43h)

NAME

Default

Active Description

value

TEST3[7:5]

TEST3[4]

Not used

1 : PLL loop open

BREAK_LOOP

0 : PLL loop closed

TEST3[3:0]

CAL_DAC_OPEN

0100

Calibration DAC override value, active when

BREAK_LOOP =1

TEST2 Register (for test only, 44h)

NAME

Default

Active Description

value

TEST2[7:5]

TEST2[4:0]

Not used

Status vector defining applied

CHP_CURRENT value

CHP_CURRENT

[4:0]

TEST1 Register (for test only, 45h)

NAME

Default

Active Description

value

TEST1[7:4]

TEST1[3:0]

Not used

CAL_DAC[3:0]

Status vector defining applied Calibration

DAC value

TEST0 Register (for test only, 46h)

NAME

Default

Active Description

value

TEST0[7:4]

TEST0[3:0]

Not used

VCO_ARRAY[3:0]

Status vector defining applied VCO_ARRAY

value

SWRS044

Page 36 of 40

Not Recommended for New Designs

CC1050

SWRS044

Page 37 of 40

Not Recommended for New Designs

CC1050

Package Description (TSSOP-24)

Note: The figure is an illustration only.

Thin Shrink Small Outline Package (TSSOP)

7.7

4.30

0.05

0.19

0.45

Copl.

0.10

0°

TSSOP 24

Min

6.40

0.65

Max

7.9

4.50

1.20

0.15

0.30

0.75

8°

All dimensions in mm

Soldering Information

Recommended soldering profile is according to IPC/JEDEC J-STD-020B, July 2002.

Plastic Tube Specification

TSSOP 4.4mm (.173”) antistatic tube.

Tube Specification

Package

Tube Width

268 mil

Tube Height

Tube

Length

20”

Units per Tube

TSSOP 24

80 mil

Carrier Tape and Reel Specification

Carrier tape and reel is in accordance with EIA Specification 481.

Tape and Reel Specification

Package

Tape Width

16 mm

Component

Pitch

8 mm

Hole

Pitch

4 mm

Reel

Diameter

13”

Units per Reel

2500

TSSOP 24

SWRS044

Page 38 of 40

Not Recommended for New Designs

CC1050

Ordering Information

Ordering part number Description

MOQ

CC1050

Single Chip RF Transceiver

62 (tube)

CC1050/T&R

CC1050DK-433

CC1050DK-868

CC1050SK

Single Chip RF Transceiver

2500 (tape and reel)

CC1050 Development Kit, 433 MHz

CC1050 Development Kit, 868/915 MHz

CC1050 Sample Kit (5 pcs)

MOQ = Minimum Order Quantity

General Information

Document Revision History

Revision

Date

April 2004

Description/Changes

Shaping feature removed

L1 changed to 0603 size

1.1

Crystal oscillator information added

Preliminary version removed

Minor corrections and editorial changes

Application circuit and BOM simplified

Description in the FSCTRL register changed

KOA inductor removed in BOM

1.2

August 2004

Additional information on LC-filter

Disclaimer

Chipcon AS believes the information contained herein is correct and accurate at the time of this printing. However,

Chipcon AS reserves the right to make changes to this product without notice. Chipcon AS does not assume any

responsibility for the use of the described product; neither does it convey any license under its patent rights, or the

rights of others. The latest updates are available at the Chipcon website or by contacting Chipcon directly.

To the extent possible, major changes of product specifications and functionality will be stated in product specific

Errata Notes published at the Chipcon website. Customers are encouraged to sign up for the Developer’s Newsletter

for the most recent updates on products and support tools.

When a product is discontinued this will be done according to Chipcon’s procedure for obsolete products as

described in Chipcon’s Quality Manual. This includes informing about last-time-buy options. The Quality Manual can

be downloaded from Chipcon’s website.

Trademarks

SmartRF^®is a registered trademark of Chipcon AS. SmartRF^®is Chipcon's RF technology platform with RF library

cells, modules and design expertise. Based on SmartRF^®technology Chipcon develops standard component RF

circuits as well as full custom ASICs based on customer requirements and this technology.

All other trademarks, registered trademarks and product names are the sole property of their respective owners.

Life Support Policy

This Chipcon product is not designed for use in life support appliances, devices, or other systems where malfunction

can reasonably be expected to result in significant personal injury to the user, or as a critical component in any life

support device or system whose failure to perform can be reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness. Chipcon AS customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting

from any improper use or sale.

SWRS044

Page 39 of 40

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CC1050PWR相关文章

配单直通车

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

柒号芯城电子商务（深圳）有限公司服务专线: 0755-83209937 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

CC1050PWR产品参数

型号:	CC1050PWR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Not Recommended
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	TSSOP
包装说明：	TSSOP-24
针数：	24
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
Factory Lead Time：	12 weeks
风险等级：	6.79
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	1338032
Samacsys Pin Count：	24
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	tssop-24-
Samacsys Released Date：	2019-11-29 05:15:51
Is Samacsys：	N
JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e4
长度：	7.8 mm
湿度敏感等级：	3
功能数量：	1
端子数量：	24
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP24,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	2.5/3.3 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
子类别：	Other Telecom ICs
标称供电电压：	3 V
表面贴装：	YES
技术：	CMOS
电信集成电路类型：	RF AND BASEBAND CIRCUIT
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
Base Number Matches：	1

电子百科

产品导航

产品型号CC1050PWR的概述

产品型号CC1050PWR的Datasheet PDF文件预览

CC1050PWR相关产品

CC1050PWR相关文章

IC37:专业IC行业平台