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  • CD4053BPWR图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • CD4053BPWR 现货库存
  • 数量172 
  • 厂家TI(德州仪器) 
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  • 原装特价可提供13点
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  • 集好芯城

     该会员已使用本站13年以上
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  • 数量24503 
  • 厂家TI(德州仪器) 
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  • 深圳市芯球通科技有限公司

     该会员已使用本站8年以上
  • CD4053BPWR 现货库存
  • 数量2000 
  • 厂家TI/德州仪器 
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  • 深圳市正信鑫科技有限公司

     该会员已使用本站12年以上
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  • 数量8685 
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  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
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  • 深圳市勤思达科技有限公司

     该会员已使用本站14年以上
  • CD4053BPWR 现货库存
  • 数量30000 
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  • 深圳市正纳电子有限公司

     该会员已使用本站2年以上
  • CD4053BPWR 现货库存
  • 数量10000 
  • 厂家TI/德州仪器 
  • 封装TSSOP-16 
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  • 只做原装 欢迎询价???
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • CD4053BPWR 现货库存
  • 数量2000 
  • 厂家TI 
  • 封装TSSOP (PW) 
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  • 新到现货、一手货源、当天发货、bom配单
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  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • CD4053BPWR 优势库存
  • 数量8800 
  • 厂家TI 
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  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • CD4053BPWR
  • 数量5300 
  • 厂家TI(德州仪器) 
  • 封装TSSOP-16 
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  • CD4053BPWR图
  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
  • CD4053BPWR
  • 数量7536 
  • 厂家Texas Instruments 
  • 封装16-TSSOP 
  • 批号23+ 
  • 模拟开关IC原装现货
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  • 0755-82777852 QQ:892152356
  • CD4053BPWR图
  • 深圳市正纳电子有限公司

     该会员已使用本站15年以上
  • CD4053BPWR
  • 数量2000 
  • 厂家TI 
  • 封装TSSOP-16 
  • 批号21+ 
  • ■原装长期供应支持小批量秒发货
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  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • CD4053BPWR
  • 数量5000 
  • 厂家TI/德州仪器 
  • 封装TSSOP 
  • 批号21+ 
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • CD4053BPWR
  • 数量3000 
  • 厂家TI 
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  • 深圳市美思瑞电子科技有限公司

     该会员已使用本站12年以上
  • CD4053BPWR
  • 数量46662 
  • 厂家TI/德州仪器 
  • 封装TSSOP 
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  • 现货,原厂原装假一罚十!
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  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • CD4053BPWR
  • 数量8500 
  • 厂家原厂品牌 
  • 封装原厂封装 
  • 批号新年份 
  • 羿芯诚只做原装长期供,支持实单
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  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • CD4053BPWR
  • 数量5600 
  • 厂家TI 
  • 封装TSSOP 
  • 批号23+ 
  • 100%深圳原装现货库存
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • CD4053BPWR
  • 数量14 
  • 厂家TI/德州仪器 
  • 封装NA/ 
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  • 优势代理渠道,原装正品,可全系列订货开增值税票
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • CD4053BPWR
  • 数量68000 
  • 厂家TI/德州仪器 
  • 封装TSSOP16 
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  • 假一罚十,原装进口正品现货供应,价格优势。
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  • 北京耐芯威科技有限公司

     该会员已使用本站13年以上
  • CD4053BPWR
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装16-TSSOP 
  • 批号21+ 
  • 全新原装、现货库存,欢迎询价
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  • CD4053BPWR图
  • 集好芯城

     该会员已使用本站13年以上
  • CD4053BPWR
  • 数量17686 
  • 厂家TI/德州仪器 
  • 封装TSSOP 
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  • 原装原厂 现货现卖
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  • CD4053BPWR图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • CD4053BPWR
  • 数量12736 
  • 厂家TI 
  • 封装TSSOP 
  • 批号23+ 
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  • CD4053BPWRG4图
  • 深圳市华科泰电子商行

     该会员已使用本站13年以上
  • CD4053BPWRG4
  • 数量155 
  • 厂家TI 
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  • 批号08+ 
  • 绝对原装现货特价
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  • CD4053BPWR图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • CD4053BPWR
  • 数量13048 
  • 厂家TI(德州仪器) 
  • 封装TSSOP-16 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
  • QQ:3007947087QQ:3007947087 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-83061789 QQ:3007947087QQ:3007947087
  • CD4053BPWR图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • CD4053BPWR
  • 数量30000 
  • 厂家TI/德州仪器 
  • 封装TSSOP-16 
  • 批号23+ 
  • 代理全新原装现货,价格优势
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  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • CD4053BPWR
  • 数量72282 
  • 厂家TI/德州仪器 
  • 封装N/A 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CD4053BPWR
  • 数量39296 
  • 厂家 
  • 封装 
  • 批号2023+ 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CD4053BPWR
  • 数量12500 
  • 厂家TI/德州仪器 
  • 封装TSSOP-16 
  • 批号2023+ 
  • 绝对原装正品全新深圳进口现货,优质渠道供应商!
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  • 深圳市西源信息科技有限公司

     该会员已使用本站9年以上
  • CD4053BPWR
  • 数量8800 
  • 厂家TI 
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  • 批号最新批号 
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  • 深圳市昌和盛利电子有限公司

     该会员已使用本站11年以上
  • CD4053BPWR
  • 数量12764 
  • 厂家TI 
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  • 深圳市集创讯科技有限公司

     该会员已使用本站5年以上
  • CD4053BPWR
  • 数量13500 
  • 厂家TI/德州仪器 
  • 封装TSSOP-16 
  • 批号24+ 
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  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • CD4053BPWR
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装16-TSSOP 
  • 批号2024+ 
  • 全新原装、现货库存,欢迎询价
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产品型号CD4053BPWR的概述

CD4053BPWR芯片概述及详细参数 CD4053BPWR是一款多路开关芯片,属于CMOS系列,通常用于音频信号、视频信号或数据选择等应用。其专为选择电路和信号切换设计,能够在多个信号之间进行选择和切换,具有低功耗和高稳定性等特点。该芯片实现了四个独立的多路选择功能,并可用于构建复杂的信号路由系统。 CD4053BPWR的详细参数 CD4053BPWR的关键参数包括: - 工作电压:至多为15V,最低可降至3V,以适应不同的应用场景。 - 输入/输出电流(I_D):可承受的输入和输出电流为最大20mA,适合大多数音频和控制信号应用。 - 功耗:该芯片在静态时功耗非常低,约为10µA,这使得其在续航受限的设备中表现优异。 - 带宽:在标准应用中,CD4053可提供高达10MHz的带宽,能够满足大多数音频和视频信号的需求。 - 切换时间:信号在开关切换时的延迟约为100ns,确保快速响应...

产品型号CD4053BPWR的Datasheet PDF文件预览

CD4051B, CD4052B, CD4053B  
Data sheet acquired from Harris Semiconductor  
SCHS047G  
August 1998 - Revised October 2003  
The CD4051B is a single 8-Channel multiplexer having three  
binary control inputs, A, B, and C, and an inhibit input. The  
three binary signals select 1 of 8 channels to be turned on,  
and connect one of the 8 inputs to the output.  
Features  
• Wide Range of Digital and Analog Signal Levels  
- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V  
- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V  
P-P  
The CD4052B is a differential 4-Channel multiplexer having  
two binary control inputs, A and B, and an inhibit input. The  
two binary input signals select 1 of 4 pairs of channels to be  
turned on and connect the analog inputs to the outputs.  
• Low ON Resistance, 125(Typ) Over 15V  
Range for V -V = 18V  
Signal Input  
[ /Title  
(CD405  
1B,  
CD4052  
B,  
CD4053  
B)  
/Sub-  
P-P  
DD EE  
• High OFF Resistance, Channel Leakage of ±100pA (Typ)  
at V -V = 18V  
DD EE  
The CD4053B is a triple 2-Channel multiplexer having three  
separate digital control inputs, A, B, and C, and an inhibit  
input. Each control input selects one of a pair of channels  
which are connected in a single-pole, double-throw  
configuration.  
• Logic-Level Conversion for Digital Addressing Signals of  
3V to 20V (V -V = 3V to 20V) to Switch Analog  
DD SS  
Signals to 20V  
(V -V = 20V)  
P-P DD EE  
• Matched Switch Characteristics, r  
ON  
= 5(Typ) for  
V
-V = 15V  
DD EE  
When these devices are used as demultiplexers, the  
“CHANNEL IN/OUT” terminals are the outputs and the  
“COMMON OUT/IN” terminals are the inputs.  
ject  
• Very Low Quiescent Power Dissipation Under All Digital-  
Control Input and Supply Conditions, 0.2µW (Typ) at  
(CMOS  
Analog  
Multi-  
plex-  
ers/Dem  
ultiplex-  
ers with  
Logic  
Level  
Conver-  
sion)  
V
-V = V -V = 10V  
DD SS DD EE  
Ordering Information  
• Binary Address Decoding on Chip  
TEMP. RANGE  
o
• 5V, 10V, and 15V Parametric Ratings  
PART NUMBER  
( C)  
PACKAGE  
• 100% Tested for Quiescent Current at 20V  
CD4051BF3A, CD4052BF3A,  
CD4053BF3A  
-55 to 125  
16 Ld CERAMIC  
DIP  
• Maximum Input Current of 1µA at 18V Over Full Package  
Temperature Range, 100nA at 18V and 25 C  
o
CD4051BE, CD4052BE,  
CD4053BE  
-55 to 125  
-55 to 125  
16 Ld PDIP  
• Break-Before-Make Switching Eliminates Channel  
Overlap  
CD4051BM, CD4051BMT,  
CD4051BM96  
16 Ld SOIC  
CD4052BM, CD4052BMT,  
CD4052BM96  
CD4053BM, CD4053BMT,  
CD4053BM96  
Applications  
/Author  
()  
• Analog and Digital Multiplexing and Demultiplexing  
• A/D and D/A Conversion  
• Signal Gating  
/Key-  
words  
(Harris  
Semi-  
conduc-  
tor,  
CD4051BNSR, CD4052BNSR,  
CD4053BNSR  
-55 to 125  
-55 to 125  
16 Ld SOP  
CD4051BPW, CD4051BPWR,  
CD4052BPW, CD4052BPWR  
CD4053BPW, CD4053BPWR  
16 Ld TSSOP  
CMOS Analog Multiplexers/Demultiplexers  
with Logic Level Conversion  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
The CD4051B, CD4052B, and CD4053B analog multiplexers  
CD4000 are digitally-controlled analog switches having low ON  
impedance and very low OFF leakage current. Control of  
analog signals up to 20V  
can be achieved by digital  
P-P  
signal amplitudes of 4.5V to 20V (if V -V  
= 3V, a  
DD SS  
V
-V of up to 13V can be controlled; for V -V level  
DD EE DD EE  
differences above 13V, a V -V  
of at least 4.5V is  
DD SS  
required). For example, if V = +4.5V, V  
= 0V, and  
SS  
DD  
= -13.5V, analog signals from -13.5V to +4.5V can be  
V
EE  
controlled by digital inputs of 0V to 5V. These multiplexer  
circuits dissipate extremely low quiescent power over the  
full V -V  
DD SS  
and V -V supply-voltage ranges,  
DD EE  
independent of the logic state of the control signals. When  
a logic “1” is present at the inhibit input terminal, all  
channels are off.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD4051B, CD4052B, CD4053B  
Pinouts  
CD4051B (PDIP, CDIP, SOIC, SOP, TSSOP)  
TOP VIEW  
CD4052B (PDIP, CDIP, SOP, TSSOP)  
TOP VIEW  
4
6
1
2
3
4
5
6
7
8
16 V  
15 2  
14 1  
13 0  
12 3  
11 A  
10 B  
0
2
1
2
3
4
5
6
7
8
16 V  
15 2  
14 1  
DD  
Y CHANNELS  
IN/OUT  
DD  
CHANNELS  
IN/OUT  
X CHANNELS  
IN/OUT  
COM OUT/IN  
7
COMMON “Y” OUT/IN  
CHANNELS IN/OUT  
3
1
13 COMMON “X” OUT/IN  
Y CHANNELS  
IN/OUT  
CHANNELS  
IN/OUT  
5
12 0  
X CHANNELS  
IN/OUT  
INH  
INH  
11 3  
10 A  
V
V
V
V
EE  
SS  
EE  
SS  
9
C
9 B  
CD4053B (PDIP, CDIP, SOP, TSSOP)  
TOP VIEW  
by  
bx  
cy  
1
2
3
4
5
6
7
8
16 V  
DD  
15 OUT/IN bx OR by  
14 OUT/IN ax OR ay  
13 ay  
IN/OUT  
OUT/IN CX OR CY  
IN/OUT CX  
INH  
IN/OUT  
12 ax  
11 A  
10 B  
V
V
EE  
SS  
9
C
Functional Block Diagrams  
CD4051B  
CHANNEL IN/OUT  
7
4
6
2
5
5
4
1
3
2
1
0
V
16  
12 15 14 13  
DD  
TG  
TG  
TG  
TG  
TG  
TG  
TG  
TG  
11  
A †  
COMMON  
OUT/IN  
10  
B †  
BINARY  
TO  
1 OF 8  
DECODER  
WITH  
3
LOGIC  
LEVEL  
CONVERSION  
9
C †  
INHIBIT  
6
INH †  
V
7
8
V
EE  
SS  
All inputs are protected by standard CMOS protection network.  
2
CD4051B, CD4052B, CD4053B  
Functional Block Diagrams (Continued)  
CD4052B  
X CHANNELS IN/OUT  
3
2
1
0
11  
15  
14  
12  
TG  
TG  
TG  
TG  
TG  
TG  
TG  
TG  
V
16  
DD  
COMMON X  
OUT/IN  
13  
10  
9
A †  
B †  
BINARY  
TO  
1 OF 4  
3
LOGIC  
LEVEL  
COMMON Y  
OUT/IN  
DECODER  
WITH  
CONVERSION  
6
INHIBIT  
INH †  
1
0
5
1
2
2
4
3
8
7
V
V
EE  
SS  
Y CHANNELS IN/OUT  
CD4053B  
BINARY TO  
1 OF 2  
DECODERS  
WITH  
IN/OUT  
by bx  
LOGIC  
LEVEL  
CONVERSION  
V
16  
DD  
cy  
3
cx  
5
ay  
13  
ax  
12  
INHIBIT  
1
2
COMMON  
OUT/IN  
ax OR ay  
TG  
TG  
TG  
TG  
TG  
TG  
14  
11  
A †  
COMMON  
OUT/IN  
bx OR by  
15  
10  
9
B †  
C †  
COMMON  
OUT/IN  
cx OR cy  
4
6
INH †  
V
DD  
8
V
V
EE  
7
SS  
All inputs are protected by standard CMOS protection network.  
3
CD4051B, CD4052B, CD4053B  
TRUTH TABLES  
INPUT STATES  
INHIBIT  
C
B
A
“ON” CHANNEL(S)  
CD4051B  
0
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0
0
1
0
2
0
3
0
4
0
5
6
0
0
7
1
None  
CD4052B  
INHIBIT  
B
0
0
1
1
X
A
0
1
0
1
X
0
0x, 0y  
1x, 1y  
2x, 2y  
3x, 3y  
None  
0
0
0
1
CD4053B  
INHIBIT  
A OR B OR C  
0
0
1
X
ax or bx or cx  
ay or by or cy  
None  
0
1
X = Don’t Care  
4
CD4051B, CD4052B, CD4053B  
Absolute Maximum Ratings  
Supply Voltage (V+ to V-)  
Voltages Referenced to V Terminal . . . . . . . . . . . -0.5V to 20V  
DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to V  
DD  
Thermal Information  
Package Thermal Impedance, θ (see Note 1):  
JA  
E (PDIP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 C/W  
M (SOIC) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 C/W  
NS (SOP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C/W  
PW (TSSOP) package . . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W  
Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C  
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C  
o
SS  
o
+0.5V  
o
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA  
o
o
Operating Conditions  
o
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
o
o
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265 C  
(SOIC - Lead Tips Only)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, V  
= ±5V, A = +1,  
SUPPLY  
V
R
= 100, Unless Otherwise Specified (Note 3)  
L
o
CONDITIONS  
LIMITS AT INDICATED TEMPERATURES ( C)  
25  
PARAMETER  
V
(V)  
V
(V)  
V
(V)  
V
(V)  
-55  
-40  
85  
125  
MIN  
TYP  
MAX  
UNITS  
IS  
EE  
SS  
DD  
SIGNAL INPUTS (V ) AND OUTPUTS (V  
)
IS  
OS  
Quiescent Device  
Current, I Max  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
5
10  
20  
100  
800  
310  
200  
-
5
10  
20  
100  
850  
330  
210  
-
150  
300  
600  
3000  
1200  
520  
300  
-
150  
300  
600  
3000  
1300  
550  
320  
-
-
-
-
-
-
-
-
-
-
-
-
0.04  
0.04  
0.04  
0.08  
470  
180  
125  
15  
5
10  
20  
100  
1050  
400  
240  
-
µA  
µA  
µA  
µA  
DD  
-
10  
-
-
15  
20  
5
-
-
Drain to Source ON  
Resistance r Max  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ON  
10  
15  
5
0 V V  
IS DD  
Change in ON  
Resistance (Between  
Any Two Channels),  
10  
15  
18  
-
-
-
-
10  
-
r  
ON  
-
-
-
-
5
-
OFF Channel Leakage  
Current: Any Channel  
OFF (Max) or ALL  
±100 (Note 2) ±1000 (Note 2)  
±0.01  
±100  
(Note 2)  
nA  
Channels OFF (Common  
OUT/IN) (Max)  
Capacitance:  
-
-5  
5-  
5
Input, C  
-
-
-
-
-
5
-
pF  
IS  
Output, C  
OS  
CD4051  
CD4052  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30  
18  
9
-
-
-
pF  
pF  
pF  
CD4053  
Feedthrough  
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.2  
30  
15  
10  
-
pF  
ns  
ns  
ns  
IOS  
Propagation Delay Time  
(Signal Input to Output  
V
R
C
= 200k,  
= 50pF,  
5
60  
30  
20  
DD  
L
L
10  
15  
t , t = 20ns  
r
f
5
CD4051B, CD4052B, CD4053B  
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, V  
= ±5V, A = +1,  
SUPPLY  
V
R
= 100, Unless Otherwise Specified (Continued) (Note 3)  
L
o
CONDITIONS  
LIMITS AT INDICATED TEMPERATURES ( C)  
25  
PARAMETER  
V
(V)  
V
C
(V)  
V
(V)  
V
(V)  
-55  
-40  
85  
125  
MIN  
TYP  
MAX  
UNITS  
IS  
EE  
SS  
DD  
CONTROL (ADDRESS OR INHIBIT), V  
Input Low Voltage, V  
Max  
,
V
= V  
V
R
= V ,  
SS  
= 1kto V ,  
< 2µA on All  
5
1.5  
3
1.5  
3
1.5  
3
1.5  
3
-
-
-
-
-
-
-
-
1.5  
V
V
IL  
IL  
DD  
EE  
through  
1k;  
V
L
SS  
10  
3
I
IS  
= V  
OFF Channels  
IH  
DD  
15  
5
4
4
4
4
-
4
V
through  
Input High Voltage, V  
Min  
,
3.5  
7
3.5  
7
3.5  
7
3.5  
7
3.5  
7
-
V
IH 1kΩ  
10  
15  
18  
-
-
V
11  
±0.1  
11  
±0.1  
11  
±1  
11  
±1  
11  
-
V
-5  
Input Current, I (Max)  
IN  
V
= 0, 18  
±10  
±0.1  
µA  
IN  
Propagation Delay Time:  
Address-to-Signal  
OUT (Channels ON or  
OFF) See Figures 10,  
11, 14  
t , t = 20ns,  
0
0
0
5
10  
15  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
450  
160  
120  
225  
720  
320  
240  
450  
ns  
ns  
ns  
ns  
r
f
C
= 50pF,  
L
L
0
0
0
R
= 10kΩ  
0
-5  
Propagation Delay Time:  
Inhibit-to-Signal OUT t , t = 20ns,  
0
0
0
0
0
0
5
10  
15  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400  
160  
120  
200  
720  
320  
240  
400  
ns  
ns  
ns  
ns  
r
f
(Channel Turning ON)  
See Figure 11  
C
R
= 50pF,  
= 1kΩ  
L
L
0
-10  
Propagation Delay Time:  
Inhibit-to-Signal OUT t , t = 20ns,  
0
0
0
0
0
0
5
10  
15  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200  
90  
450  
210  
160  
300  
7.5  
ns  
ns  
ns  
ns  
pF  
r
f
(Channel Turning  
OFF) See Figure 15  
C
R
= 50pF,  
= 10kΩ  
L
L
0
70  
-10  
130  
5
Input Capacitance, C  
IN  
(Any Address or Inhibit  
Input)  
NOTE:  
2. Determined by minimum feasible leakage measurement for automatic testing.  
Electrical Specifications  
TEST CONDITIONS  
LIMITS  
PARAMETER  
V
(V)  
V
(V)  
R
(k)  
L
TYP  
30  
UNITS  
IS  
DD  
Cutoff (-3dB) Frequency Chan- 5 (Note 3)  
nel ON (Sine Wave Input)  
10  
1
V
at Common OUT/IN  
at Any Channel  
CD4053  
CD4052  
CD4051  
MHz  
MHz  
MHz  
MHz  
OS  
V
= V  
,
25  
EE  
SS  
V
20  
OS  
-----------  
20Log  
= –3dB  
V
IS  
V
60  
OS  
6
CD4051B, CD4052B, CD4053B  
Electrical Specifications  
TEST CONDITIONS  
LIMITS  
TYP  
0.3  
PARAMETER  
V
(V)  
V
(V)  
R (k)  
L
UNITS  
%
IS  
DD  
Total Harmonic Distortion, THD 2 (Note 3)  
5
10  
3 (Note 3)  
5 (Note 3)  
10  
15  
0.2  
%
0.12  
%
V
= V , f = 1kHz Sine Wave  
SS IS  
%
EE  
-40dB Feedthrough Frequency 5 (Note 3)  
(All Channels OFF)  
10  
1
V
at Common OUT/IN  
at Any Channel  
CD4053  
CD4052  
CD4051  
8
10  
12  
8
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
OS  
V
= V  
,
EE  
SS  
V
OS  
-----------  
20Log  
= –40dB  
V
IS  
V
OS  
-40dB Signal Crosstalk  
Frequency  
5 (Note 3)  
V = V  
10  
1
Between Any 2 Channels  
3
,
SS  
Between Sections,  
CD4052 Only  
Measured on Common  
6
EE  
V
OS  
-----------  
Measured on Any Chan-  
nel  
10  
20Log  
= –40dB  
V
IS  
Between Any Two  
Sections, CD4053  
Only  
In Pin 2, Out Pin 14  
In Pin 15, Out Pin 14  
2.5  
6
MHz  
MHz  
Address-or-Inhibit-to-Signal  
Crosstalk  
-
10  
10  
(Note 4)  
65  
65  
mV  
PEAK  
PEAK  
V
EE  
= 0, V = 0, t , t = 20ns, V  
SS  
mV  
r
f
CC  
= V  
- V (Square Wave)  
DD  
SS  
NOTES:  
V
V  
EE  
2
3. Peak-to-Peak voltage symmetrical about  
DD  
-----------------------------  
4. Both ends of channel.  
Typical Performance Curves  
300  
250  
200  
150  
100  
50  
600  
V
- V = 10V  
EE  
DD  
V
- V = 5V  
EE  
DD  
500  
400  
o
T
= 125 C  
A
o
T
= 125 C  
A
300  
200  
100  
0
o
T
= 25 C  
A
o
T
= 25 C  
A
o
T
= -55 C  
A
o
T
= -55 C  
A
0
-10  
-4  
-3  
-2  
-1  
0
1
2
3
4
5
-7.5  
-5  
-2.5  
0
2.5  
5
7.5  
10  
V
, INPUT SIGNAL VOLTAGE (V)  
V , INPUT SIGNAL VOLTAGE (V)  
IS  
IS  
FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL  
VOLTAGE (ALL TYPES)  
FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL  
VOLTAGE (ALL TYPES)  
7
CD4051B, CD4052B, CD4053B  
Typical Performance Curves (Continued)  
600  
500  
400  
300  
200  
100  
0
250  
o
T
= 25 C  
V
- V = 15V  
EE  
A
DD  
V
- V = 5V  
EE  
DD  
200  
150  
100  
50  
o
T
= 125 C  
A
o
T
= 25 C  
A
o
T
= -55 C  
A
10V  
15V  
0
-10  
-7.5  
-5  
-2.5  
V , INPUT SIGNAL VOLTAGE (V)  
IS  
0
2.5  
5
7.5  
10  
-10  
-7.5  
-5  
-2.5  
0
2.5  
5
7.5  
10  
V
, INPUT SIGNAL VOLTAGE (V)  
IS  
FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL  
VOLTAGE (ALL TYPES)  
FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL  
VOLTAGE (ALL TYPES)  
5
6
10  
o
TEST CIRCUIT  
V
V
V
= 5V  
= 0V  
= -5V  
o
T
= 25 C  
DD  
SS  
EE  
A
R
= 100k, R = 10kΩ  
L
L
V
DD  
ALTERNATING “O”  
AND “I” PATTERN  
= 50pF  
1kΩ  
B/D  
CD4029  
4
2
0
500Ω  
f
C
T
= 25 C  
L
A
4
3
2
10  
10  
10  
100Ω  
A B C  
V
DD  
V
= 15V  
DD  
1110 9  
100Ω  
13  
14  
15  
12  
1
CD4051  
V
= 10V  
-2  
-4  
-6  
5
DD  
3
2
4
8 7  
6
C
V
= 5V  
DD  
L
100Ω  
Ι
C
= 15pF  
L
10  
2
3
4
5
-6  
-4  
-2  
0
2
4
6
1
10  
10  
10  
10  
10  
V
, INPUT SIGNAL VOLTAGE (V)  
SWITCHING FREQUENCY (kHz)  
IS  
FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS  
(CD4051B)  
FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING  
FREQUENCY (CD4051B)  
5
5
o
10  
10  
10  
o
V
= 15V  
T
= 25 C  
DD  
A
T
= 25 C  
A
ALTERNATING “O”  
AND “I” PATTERN  
= 50pF  
ALTERNATING “O”  
AND “I” PATTERN  
V
= 10V  
DD  
TEST CIRCUIT  
C
V
L
C
= 50pF  
DD  
L
4
3
2
f
4
10  
10  
CD4029  
B/D  
A B  
TEST CIRCUIT  
V
V
DD  
f
V
= 15V  
DD  
DD  
9
3
5
4
100Ω  
1
C
L
100Ω  
10 9  
12  
3
C
L
10  
10  
3
5
2
4
13  
13  
2
1
15  
14  
100Ω  
12  
CD4053  
14  
15  
11  
V
= 10V  
10  
11  
6
CD4052  
DD  
V
= 5V  
6
7
DD  
2
V
= 5V  
10  
DD  
7
8
8
C
= 15pF  
L
C
= 15pF  
Ι
L
Ι
10  
10  
2
10  
3
4
5
2
3
4
5
1
10  
10  
10  
10  
1
10  
10  
10  
10  
10  
SWITCHING FREQUENCY (kHz)  
SWITCHING FREQUENCY (kHz)  
FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING  
FREQUENCY (CD4052B)  
FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING  
FREQUENCY (CD4053B)  
8
CD4051B, CD4052B, CD4053B  
Test Circuits and Waveforms  
V
= 15V  
V
= 7.5V  
V
DD  
= 5V  
V
= 5V  
DD  
DD  
DD  
5V  
5V  
7.5V  
16  
16  
16  
16  
V
= 0V  
V
= 0V  
SS  
SS  
V
= 0V  
SS  
V
= 0V  
= 0V  
EE  
7
8
7
8
7
8
7
8
V
= -10V  
V
= -5V  
V
= -7.5V  
EE  
EE  
EE  
V
SS  
(D)  
(C)  
(B)  
(A)  
NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels  
are: “0” = V and “1” = V . The analog signal (through the TG) may  
SS DD  
swing from V to V  
.
EE  
DD  
FIGURE 9. TYPICAL BIAS VOLTAGES  
t = 20ns  
r
t = 20ns  
r
t = 20ns  
f
t = 20ns  
f
90%  
90%  
50%  
90%  
50%  
90%  
50%  
50%  
10%  
10%  
10%  
10%  
10%  
TURN-ON TIME  
90%  
50%  
90%  
10%  
10%  
TURN-OFF TIME  
TURN-ON  
TIME  
TURN-OFF TIME  
t
PHZ  
FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON  
(R = 1k)  
FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF  
(R = 1k)  
L
L
V
V
V
DD  
DD  
DD  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
I
I
DD  
DD  
I
DD  
CD4053  
CD4051  
CD4052  
FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF  
9
CD4051B, CD4052B, CD4053B  
Test Circuits and Waveforms (Continued)  
V
V
V
DD  
DD  
DD  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
I
DD  
I
I
DD  
DD  
CD4052  
CD4051  
CD4053  
FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF  
V
DD  
V
DD  
OUTPUT  
OUTPUT  
OUTPUT  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
DD  
R
C
L
R
V
C
L
L
DD  
L
R
C
L
L
V
V
DD  
EE  
V
EE  
V
V
DD  
DD  
V
EE  
V
V
V
EE  
EE  
V
V
V
DD  
EE  
V
V
SS  
SS  
CLOCK  
IN  
CLOCK  
IN  
V
SS  
CLOCK  
IN  
V
SS  
SS  
SS  
V
V
CD4051  
V
CD4053  
SS  
SS  
CD4052  
SS  
FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT  
V
V
DD  
DD  
OUTPUT  
OUTPUT  
OUTPUT  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
V
DD  
R
50pF  
V
R
50pF  
L
L
R
L
50pF  
14  
13  
12  
11  
10  
9
V
EE  
EE  
V
V
EE  
V
V
DD  
V
DD  
DD  
DD  
V
V
V
DD  
SS  
DD  
V
SS  
CLOCK  
IN  
V
V
V
V
V
CLOCK  
IN  
V
V
EE  
EE  
SS  
CLOCK  
IN  
EE  
SS  
SS  
SS  
V
V
V
SS  
SS  
SS  
t
AND t  
PLH  
t
AND t  
PLH  
t
AND t  
PHL  
PHL  
PHL PLH  
CD4052  
CD4051  
CD4053  
FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT  
V
DD  
V
DD  
V
DD  
µA  
1K  
V
IH  
1
2
3
4
5
6
7
8
16  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
1K  
1K  
15  
14  
13  
12  
11  
10  
9
µA  
µA  
15  
14  
13  
12  
11  
10  
9
1K  
1K  
V
V
IH  
IH  
V
1K  
IH  
V
IH  
V
IL  
V
IL  
V
V
IL  
IL  
V
IH  
CD4053B  
CD4052B  
CD4051B  
V
IL  
V
IL  
MEASURE < 2µA ON ALL  
“OFF” CHANNELS (e.g., CHANNEL 6)  
MEASURE < 2µA ON ALL  
“OFF” CHANNELS (e.g., CHANNEL 2x)  
MEASURE < 2µA ON ALL  
“OFF” CHANNELS (e.g., CHANNEL by)  
FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)  
10  
CD4051B, CD4052B, CD4053B  
Test Circuits and Waveforms (Continued)  
V
DD  
V
KEITHLEY  
160 DIGITAL  
MULTIMETER  
DD  
V
DD  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
TG  
“ON”  
10kΩ  
1kΩ  
RANGE  
Y
X
X-Y  
PLOTTER  
V
SS  
H.P.  
MOSELEY  
7030A  
CD4052  
Ι
CD4051  
CD4053  
Ι
FIGURE 17. QUIESCENT DEVICE CURRENT  
FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT  
CIRCUIT  
V
V
DD  
DD  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
V
DD  
DD  
Ι
Ι
V
V
SS  
SS  
CD4051  
CD4053  
CD4052  
V
V
SS  
SS  
NOTE: Measureinputssequentially,  
to both V and V connect all  
NOTE: Measureinputssequentially,  
to both V and V connect all  
DD  
SS  
DD  
SS  
unused inputs to either V  
or V  
SS  
.
unused inputs to either V  
or V .  
SS  
DD  
DD  
FIGURE 19. INPUT CURRENT  
5V  
P-P  
CHANNEL  
OFF  
CHANNEL  
ON  
RF  
VM  
COMMON  
RF  
VM  
R
5V  
P-P  
L
OFF  
CHANNEL  
1K  
R
V
L
DD  
CHANNEL  
ON  
RF  
VM  
CHANNEL  
OFF  
6
7
8
R
R
L
L
FIGURE 20. FEEDTHROUGH (ALL TYPES)  
FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS  
(ALL TYPES)  
5V  
P-P  
CHANNEL IN Y  
ON OR OFF  
CHANNEL IN X  
ON OR OFF  
RF  
VM  
R
R
L
L
FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)  
11  
CD4051B, CD4052B, CD4053B  
Test Circuits and Waveforms (Continued)  
DIFFERENTIAL  
SIGNALS  
CD4052  
CD4052  
COMMUNICATIONS  
LINK  
DIFF.  
AMPLIFIER/  
LINE DRIVER  
DIFF.  
RECEIVER  
DIFF.  
MULTIPLEXING  
DEMULTIPLEXING  
FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B  
Special Considerations  
In applications where separate power sources are used to  
drive V and the signal inputs, the V current capability  
DD  
DD  
should exceed V /R (R = effective external load). This  
DD  
provision avoids permanent current flow or clamp action on  
the V supply when power is applied or removed from the  
L
L
DD  
CD4051B, CD4052B or CD4053B.  
A
B
C
A
B
CD4051B  
CD4051B  
CD4051B  
C
INH  
Q
0
COMMON  
OUTPUT  
A
A
B
E
D
E
Q
Q
1
2
1/2  
CD4556  
B
C
INH  
A
B
C
INH  
FIGURE 24. 24-TO-1 MUX ADDRESSING  
12  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Feb-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
PDIP  
Drawing  
7901502EA  
8101801EA  
CD4051BE  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
16  
16  
16  
1
1
None  
None  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD4051BF  
CD4051BF3A  
CD4051BM  
ACTIVE  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
SOIC  
J
J
16  
16  
16  
1
1
None  
None  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
D
40  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-250C-1 YEAR  
CU NIPDAU Level-2-250C-1 YEAR  
CU NIPDAU Level-2-250C-1 YEAR  
CD4051BM96  
CD4051BMT  
CD4051BNSR  
CD4051BPW  
CD4051BPWR  
CD4052BE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SO  
D
D
16  
16  
16  
16  
16  
16  
2500  
250  
2000  
90  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
NS  
PW  
PW  
N
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
TSSOP  
TSSOP  
PDIP  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
2000  
25  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
CD4052BF  
CD4052BF3A  
CD4052BM  
ACTIVE  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
SOIC  
J
J
16  
16  
16  
1
1
None  
None  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
D
40  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
CD4052BM96  
CD4052BMT  
CD4052BNSR  
CD4052BPW  
CD4052BPWR  
CD4053BE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SO  
D
D
16  
16  
16  
16  
16  
16  
2500  
250  
2000  
90  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
NS  
PW  
PW  
N
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
TSSOP  
TSSOP  
PDIP  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
2000  
25  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
CD4053BF  
CD4053BF3A  
CD4053BM  
ACTIVE  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
SOIC  
J
J
16  
16  
16  
1
1
None  
None  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
D
40  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
CD4053BM96  
CD4053BMT  
CD4053BNSR  
CD4053BPW  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SO  
D
D
16  
16  
16  
16  
2500  
250  
2000  
90  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
NS  
PW  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
TSSOP  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-250C-UNLIM  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Feb-2005  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
CD4053BPWR  
ACTIVE  
TSSOP  
PW  
16  
2000  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-250C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional  
product content details.  
None: Not yet available Lead (Pb-Free).  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,  
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
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Use of such information may require a license from a third party under the patents or other intellectual property  
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
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Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2005, Texas Instruments Incorporated  
配单直通车
CD4053BPWR产品参数
型号:CD4053BPWR
Brand Name:Texas Instruments
是否无铅:不含铅
是否Rohs认证:符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:TSSOP
包装说明:TSSOP-16
针数:16
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:6 weeks
风险等级:0.68
Is Samacsys:N
模拟集成电路 - 其他类型:SINGLE-ENDED MULTIPLEXER
标称带宽:30 MHz
最大输入电压:20.5 V
最小输入电压:-0.5 V
JESD-30 代码:R-PDSO-G16
JESD-609代码:e3
长度:5 mm
湿度敏感等级:1
标称负供电电压 (Vsup):-5 V
正常位置:NC
信道数量:2
功能数量:3
端子数量:16
标称断态隔离度:40 dB
通态电阻匹配规范:15 Ω
最大通态电阻 (Ron):1050 Ω
最高工作温度:125 °C
最低工作温度:-55 °C
输出:SEPARATE OUTPUT
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260
电源:5/15 V
认证状态:Not Qualified
座面最大高度:1.2 mm
最大信号电流:0.01 A
子类别:Multiplexer or Switches
最大供电电流 (Isup):3 mA
最大供电电压 (Vsup):20 V
最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V
表面贴装:YES
最长断开时间:720 ns
最长接通时间:720 ns
切换:BREAK-BEFORE-MAKE
技术:CMOS
温度等级:MILITARY
端子面层:Matte Tin (Sn)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm
Base Number Matches:1
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