CD4553芯片引脚定义引脚图及功能IC贸易商引脚图技术参数-中国IC网-芯三七

CD4555BMS

CD4556BMS

CMOS Dual Binary to 1 of 4

Decoder/Demultiplexers

December 1992

CD4556BMS

TOP VIEW

Features

Pinouts

• High Voltage Type (20V Rating)

E

A

1

2

3

4

5

6

7

8

16 VDD

• CD4555BMS: Outputs High on Select

• CD4556BMS: Outputs Low on Select

• Expandable with Multiple Packages

• 100% Tested for Quiescent Current at 20V

• Standardized, Symmetrical Output Characteristics

15

14

13

E

A

B

Q0

Q1

Q2

Q3

VSS

1/2 OF DUAL

12 Q0

11 Q1

10 Q2

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

9

Q3

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

CD4555BMS

TOP VIEW

- 2V at VDD = 10V

E

A

1

2

3

4

5

6

7

8

16 VDD

- 2.5V at VDD = 15V

15

14

13

E

A

B

• 5V, 10V and 15V Parametric Ratings

B

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Q0

Q1

Q2

Q3

VSS

1/2 OF DUAL

12 Q0

11 Q1

10 Q2

Applications

• Decoding

9

Q3

• Code Conversion

• Demultiplexing (Using Enable Input as a Data Input

• Memory Chip-Enable Selection

• Function Selection

Functional Diagrams

VDD

16

4

2

Q0

A

3

5

6

7

Q1

Q2

Q3

B

E

1

Description

CD4555BMS and CD4556BMS are dual one-of-four decod-

ers/demultiplexers. Each decoder has two select inputs (A

and B), an Enable input (E), and four mutually exclusive out-

puts. On the CD4555BMS the outputs are high on select; on

the CD4556BMS the outputs are low on select.

12

11

10

9

Q0

Q1

Q2

Q3

14

A

13

B

15

E

8

VSS

When the Enable input is high, the outputs of the

CD4555BMS remain low and the outputs of the

CD4556BMS remain high regardless of the state of the

select inputs A and B. The CD4555BMS and CD4556BMS

are similar to types MC14555 and MC14556, respectively.

CD4555BMS

VDD

16

4

5

6

7

2

3

1

Q0

Q1

Q2

Q3

A

B

E

The CD4555BMS and CD4556BMS are supplied in these

16-lead outline packages:

12

11

10

9

Q0

Q1

Q2

Q3

14

13

15

A

B

E

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

*CD4555B Only

*H46

H1E

H6W

†H4T

8

VSS

†CD4556B Only

CD4556BMS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3346

7-1249

Speciﬁcations CD4555BMS, CD4556BMS

Absolute Maximum Ratings

Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Thermal Resistance . . . . . . . . . . . . . . . .

Ceramic DIP and FRIT Package . . . . . 80 C/W

Flatpack Package . . . . . . . . . . . . . . . . 70 C/W

θ

jc

ja

o

20 C/W

o

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

20 C/W

o

Maximum Package Power Dissipation (PD) at +125 C

o

Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C

Package Types D, F, K, H

For T = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW

A

o

For T = +100 C to +125 C (Package Type D, F, K). . . . . .Derate

A

o

Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C

Linearity at 12mW/ C to 200mW

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

o

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

For T = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C

A

o

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

MIN MAX UNITS

GROUP A

SUBGROUPS

PARAMETER

Supply Current

SYMBOL

CONDITIONS (NOTE 1)

TEMPERATURE

o

IDD

VDD = 20V, VIN = VDD or GND

1

+25 C

-

10

1000

10

µA

nA

mV

V

o

2

+125 C

-

o

VDD = 18V, VIN = VDD or GND

3

-55 C

-

o

Input Leakage Current

IIL

VIN = VDD or GND

VDD = 20

1

+25 C

-100

-

o

2

+125 C

-1000

-

o

VDD = 18V

VDD = 20

3

-55 C

-100

-

o

IIH

VIN = VDD or GND

1

+25 C

-

100

1000

100

50

o

2

+125 C

o

VDD = 18V

3

-55 C

o

Output Voltage

VOL15 VDD = 15V, No Load

VOH15 VDD = 15V, No Load (Note 3)

1, 2, 3

+25 C, +125 C, -55 C

o

Output Voltage

1, 2, 3

+25 C, +125 C, -55 C 14.95

-

o

Output Current (Sink)

IOL5

IOL10

IOL15

VDD = 5V, VOUT = 0.4V

VDD = 10V, VOUT = 0.5V

VDD = 15V, VOUT = 1.5V

1

+25 C

0.53

1.4

3.5

-

mA

V

o

1

+25 C

-

o

1

+25 C

-

o

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V

Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V

1

+25 C

-0.53

-1.8

-1.4

-3.5

-0.7

2.8

o

1

+25 C

-

o

1

+25 C

-

o

1

+25 C

-

o

N Threshold Voltage

P Threshold Voltage

Functional

VNTH

VPTH

F

VDD = 10V, ISS = -10µA

+25 C

-2.8

0.7

o

VSS = 0V, IDD = 10µA

1

+25 C

V

o

VDD = 2.8V, VIN = VDD or GND

VDD = 20V, VIN = VDD or GND

VDD = 18V, VIN = VDD or GND

VDD = 3V, VIN = VDD or GND

VDD = 5V, VOH > 4.5V, VOL < 0.5V

7

+25 C

VOH > VOL <

VDD/2 VDD/2

V

o

7

+25 C

o

8A

8B

1, 2, 3

+125 C

o

-55 C

o

Input Voltage Low

(Note 2)

VIL

VIH

VIL

VIH

+25 C, +125 C, -55 C

-

1.5

V

o

Input Voltage High

(Note 2)

VDD = 5V, VOH > 4.5V, VOL < 0.5V

1, 2, 3

+25 C, +125 C, -55 C 3.5

-

4

-

o

Input Voltage Low

(Note 2)

VDD = 15V, VOH > 13.5V,

VOL < 1.5V

+25 C, +125 C, -55 C

-

o

Input Voltage High

(Note 2)

VDD = 15V, VOH > 13.5V,

VOL < 1.5V

+25 C, +125 C, -55 C

11

NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit

implemented.

is 0.050V max.

2. Go/No Go test with limits applied to inputs.

7-1250

Speciﬁcations CD4555BMS, CD4556BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

MIN

GROUP A

SUBGROUPS TEMPERATURE

PARAMETER

SYMBOL

CONDITIONS (NOTE 1, 2)

MAX

440

594

400

540

200

270

UNITS

ns

o

Propagation Delay

A or B Input to any Output TPLH1

TPHL1 VDD = 5V, VIN = VDD or GND

9

+25 C

-

o

10, 11

9

+125 C, -55 C

ns

o

Propagation Delay

E to any Output

TPHL2 VDD = 5V, VIN = VDD or GND

TPLH2

+25 C

ns

o

10, 11

9

+125 C, -55 C

ns

o

Transition Time

NOTES:

TTHL

TTLH

VDD = 5V, VIN = VDD or GND

+25 C

ns

o

10, 11

+125 C, -55 C

ns

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

o

2. -55 C and +125 C limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER

Supply Current

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

5

UNITS

µA

o

IDD

VDD = 5V, VIN = VDD or GND

1, 2

-55 C, +25 C

-

o

+125 C

150

10

µA

o

VDD = 10V, VIN = VDD or GND

VDD = 15V, VIN = VDD or GND

1, 2

-55 C, +25 C

µA

o

+125 C

300

10

µA

o

-55 C, +25 C

µA

o

+125 C

600

50

µA

o

Output Voltage

Output Current (Sink)

VOL

VOH

IOL5

VDD = 5V, No Load

VDD = 10V, No Load

VDD = 5V, No Load

VDD = 10V, No Load

VDD = 5V, VOUT = 0.4V

1, 2

+25 C, +125 C,

mV

o

-55 C

o

+25 C, +125 C,

-

50

-

mV

V

o

-55 C

o

+25 C, +125 C,

4.95

9.95

o

-55 C

o

+25 C, +125 C,

-

V

o

-55 C

o

+125 C

0.36

-

mA

V

o

-55 C

0.64

o

Output Current (Sink)

Output Current (Source)

IOL10

IOL15

VDD = 10V, VOUT = 0.5V

VDD = 15V, VOUT = 1.5V

1, 2

+125 C

0.9

-

o

-55 C

1.6

-

o

+125 C

2.4

-

o

-55 C

4.2

-

o

IOH5A VDD = 5V, VOUT = 4.6V

IOH5B VDD = 5V, VOUT = 2.5V

+125 C

-

-0.36

-0.64

-1.15

-2.0

-0.9

-1.6

-2.4

-4.2

3

o

-55 C

o

+125 C

o

-55 C

o

IOH10

IOH15

VDD = 10V, VOUT = 9.5V

VDD =15V, VOUT = 13.5V

+125 C

o

-55 C

o

+125 C

o

-55 C

o

Input Voltage Low

Input Voltage High

VIL

VDD = 10V, VOH > 9V, VOL < 1V

1, 2

+25 C, +125 C,

o

-55 C

o

VIH

+25 C, +125 C,

7

-

V

o

-55 C

7-1251

Speciﬁcations CD4555BMS, CD4556BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

MIN

PARAMETER

SYMBOL

CONDITIONS

NOTES

1, 2, 3

1, 2

TEMPERATURE

MAX

190

140

170

130

100

80

UNITS

ns

o

Propagation Delay

A or B Input to any Output TPLH1

TPHL1 VDD = 10V

+25 C

-

o

VDD = 15V

+25 C

ns

o

Propagation Delay

E to any Output

TPHL2 VDD = 10V

TPLH2

+25 C

ns

o

VDD = 15V

+25 C

ns

o

Transition Time

TTHL

TTLH

VDD = 10V

VDD = 15V

Any Input

+25 C

ns

o

+25 C

ns

o

Input Capacitance

NOTES:

CIN

+25 C

7.5

pF

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized

on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER

Supply Current

SYMBOL

IDD

CONDITIONS

NOTES

1, 4

TEMPERATURE

MIN

MAX

25

UNITS

o

VDD = 20V, VIN = VDD or GND

VDD = 10V, ISS = -10µA

+25 C

-

-2.8

-

µA

V

o

N Threshold Voltage

VNTH

∆VTN

1, 4

+25 C

-0.2

±1

o

N Threshold Voltage

Delta

1, 4

+25 C

V

o

P Threshold Voltage

VTP

VSS = 0V, IDD = 10µA

1, 4

+25 C

0.2

-

2.8

V

o

P Threshold Voltage

Delta

∆VTP

+25 C

±1

o

Functional

F

VDD = 18V, VIN = VDD or GND

VDD = 3V, VIN = VDD or GND

VDD = 5V

1

+25 C

VOH >

VDD/2

VOL <

VDD/2

V

o

Propagation Delay Time

TPHL

TPLH

1, 2, 3, 4

+25 C

-

1.35 x

ns

o

+25 C

Limit

o

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

3. See Table 2 for +25 C limit.

4. Read and Record

o

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C

PARAMETER

Supply Current - MSI-2

Output Current (Sink)

Output Current (Source)

SYMBOL

IDD

DELTA LIMIT

± 1.0µA

IOL5

± 20% x Pre-Test Reading

IOH5A

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In)

Interim Test 1 (Post Burn-In)

Interim Test 2 (Post Burn-In)

PDA (Note 1)

METHOD

100% 5004

GROUP A SUBGROUPS

READ AND RECORD

IDD, IOL5, IOH5A

1, 7, 9

IDD, IOL5, IOH5A

1, 7, 9

1, 7, 9, Deltas

1, 7, 9

Interim Test 3 (Post Burn-In)

PDA (Note 1)

IDD, IOL5, IOH5A

1, 7, 9, Deltas

7-1252

Speciﬁcations CD4555BMS, CD4556BMS

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Final Test

METHOD

GROUP A SUBGROUPS

READ AND RECORD

100% 5004

2, 3, 8A, 8B, 10, 11

Group A

Group B

Sample 5005

1, 2, 3, 7, 8A, 8B, 9, 10, 11

1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas

1, 7, 9

Subgroup B-5

Subgroup B-6

Subgroups 1, 2, 3, 9, 10, 11

Subgroups 1, 2 3

Group D

1, 2, 3, 8A, 8B, 9

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST

READ AND RECORD

MIL-STD-883

METHOD

CONFORMANCE GROUPS

PRE-IRRAD

POST-IRRAD

PRE-IRRAD

POST-IRRAD

Group E Subgroup 2

5005

1, 7, 9

Table 4

1, 9

Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION

OPEN

GROUND

VDD

9V ± -0.5V

50kHz

25kHz

PART NUMBER CD4555BMS & CD4556BMS

Static Burn-In 1

Note 1

4 - 7, 9 - 12

-

1 - 3, 8, 13 - 15

16

1 - 3, 13 - 16

16

Static Burn-In 2

Note 1

8

Dynamic Burn-

In Note 1

1, 8, 15

4 - 7, 9 - 12

2, 14

3, 13

Irradiation

Note 2

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

VDD = 10V ± 0.5V

Logic Diagrams

4(12)

5(11)

6(10)

7(9)

4(12)

5(11)

6(10)

7(9)

2(14)

Q0

Q1

Q2

Q3

Q0

Q1

Q2

Q3

A

B

E

A

B

E

*

3(13)

*

1(15)

VDD

*

*ALL INPUTS PROTECTED BY CMOS

PROTECTION NETWORK

*ALL INPUTS PROTECTED BY CMOS

PROTECTION NETWORK

VSS

FIGURE 1. CD455RBMS LOGIC DIAGRAM (1 OF 2 IDENTICAL

CIRCUITS)

FIGURE 2. CD4556BMS LOGIC DIAGRAM (1 OF 2 IDENTICAL

CIRCUITS)

7-1253

CD4555BMS, CD4556BMS

TRUTH TABLE

INPUTS ENABLE SELECT

OUTPUTS CD4555BMS

OUTPUTS CD4556BMS

E

B

0

1

X

A

0

1

0

1

X

Q3

0

Q2

0

Q1

0

Q0

1

Q3

1

Q2

1

Q1

1

Q0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X = Don’t Care

Logic 1 ≡ High

Logic 0 ≡ Low

Typical Performance Characteristics

AMBIENT TEMPERATURE (T_A) = +25^oC

15.0

12.5

10.0

7.5

30

25

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

20

15

10V

10

5

5.0

2.5

5V

0

5

10

15

0

5

10

15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15

-10

-5

0

-15

-10

-5

0

AMBIENT TEMPERATURE (T_A) = +25^oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-5

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10

-15

-20

-25

-30

-5

-10V

-10

-15

-15V

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

7-1254

CD4555BMS, CD4556BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (T_A) = +25^oC

SUPPLY VOLTAGE (VDD) = 5V

250

200

150

250

200

150

100

50

SUPPLY VOLTAGE (VDD) = 5V

10V

15V

100

50

10V

15V

0

20

40

60

80

100

0

20

40

60

80

100

LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD

CAPACITANCE (A OR B INPUT TO ANY OUTPUT)

FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD

CAPACITANCE (E INPUTS TO ANY OUTPUT)

AMBIENT TEMPERATURE (T_A) = +25^oC

300

250

200

SUPPLY VOLTAGE (VDD) = 5V

150

ANY INPUT

150

100

E INPUT

10V

15V

50

0

5

10

15

20

0

20

40

60

80

100

SUPPLY VOLTAGE (VDD) = 5V

LOAD CAPACITANCE (CL) (pF)

FIGURE 9. TYPICAL PROPAGATION DELAY TIME vs SUPPLY

VOLTAGE

FIGURE 10. TYPICAL TRANSITION TIME vs LOAD CPACI-

TANCE

10⁶

AMBIENT TEMPERATURE (T_A) = +25^oC

10⁵

10⁴

10³

SUPPLY VOLTAGE (VDD) = 15V

LOAD CAPACITANCE (CL) = 50pF

VDD = 10V

CL = 50pF

10²

VDD = 10V

CL = 15pF

10

1

VDD = 5V

CL = 50pF

2

4

6 8

2

4

6 8

2

4

6 8

2

4

6 8

2 4 6 8

10^-1

1

10

10²

10³

10⁴

INPUT FREQUENCY (f) (kHz)

FIGURE 11. TYPICAL DYNAMIC POWER DISSIPATION vs FREQUENCY

7-1255

CD4555BMS, CD4556BMS

20ns

VDD

90%

50%

10%

90%

50%

10%

INPUT B

VSS

INPUT B

VSS

tPHL

tPLH

tPHL

VDD

90%

50%

10%

90%

50%

10%

OUTPUT Q3

VSS

OUTPUT Q3

VSS

tTHL

tTLH

tTHL

fI = 1MHz, 50% DUTY CYCLE

FIGURE 12. CD4555BMS B INPUT TO Q3 OUTPUT DYNAMIC

SIGNAL WAVEFORMS

FIGURE 13. CD4556BMS B INPUT TO Q3 OUTPUT DYNAMIC

SIGNAL WAVEFORMS

20ns

VDD

90%

50%

10%

90%

50%

10%

INPUT E

VSS

INPUT E

VSS

tPHL

tPLH

tPHL

tPLH

VDD

90%

50%

10%

90%

50%

OUTPUT Q3

VSS

OUTPUT Q3

VSS

10%

tTLH

tTHL

tTLH

tTHL

fI = 1MHz, 50% DUTY CYCLE

FIGURE 14. CD4555BMS E INPUT TO Q3 OUTPUT DYNAMIC

SIGNAL WAVEFORMS

FIGURE 15. CD4556BMS E INPUT TO Q3 OUTPUT DYNAMIC

SIGNAL WAVEFORMS

Applications

TRUTH TABLE

1/6 CD4555BMS

SELECT INPUTS

OUTPUTS

A

Q0

Q1

Q2

Q3

A

B

Q0

Q1

Q2

Q3

B

0

1

A

0

1

0

1

Q0

Q1

Q2

Q3

DATA

0

DATA

0

B

E

OUTPUTS

0

DATA

0

DATA

0

DATA

1/6 CD4069BMS

FIGURE 16. 1 OF 4 LINE DATA DEMULTIPLEXER USING

CD4555BMS

7-1256

CD4555BMS, CD4556BMS

Applications (Continued)

CD4555BMS

TRUTH TABLE

Q OUTPUTS

A

B

E

Q0

Q1

Q2

Q3

INPUTS

Q0

A

B

C

0

1

B

0

1

0

1

A

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

0

1

0

3

0

1

0

4

0

1

0

5

0

1

0

6

0

1

0

7

0

1

Q1

Q2

Q3

OUTPUTS

A

B

E

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

C

1/6 CD4069BMS

OR EQUIV

FIGURE 17. 1 OF 8 DECODER USING CD4555BMS

CD4555BMS

A

B

E

Q0

Q1

Q2

Q3

A

B

Q0

Q1

Q2

Q3

A

B

E

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

A

B

E

Q0

Q1

Q2

Q3

C

D

E

OUTPUTS

A

B

E

Q0

Q1

Q2

Q3

Q8

Q9

Q10

Q11

1/2 CD4556BMS

A

B

E

Q0

Q1

Q2

Q3

Q12

Q13

Q14

Q15

FIGURE 18. 1 OF 16 DECODER USING CD4555BMS AND CD4556BMS

7-1257

CD4555BMS, CD4556BMS

TRUTH TABLE

INPUTS

Q OUTPUTS

E

0

1

D

0

1

X

C

0

1

0

1

X

B

0

1

0

1

0

1

0

1

X

A

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

0

1

0

3

0

1

0

4

0

1

0

5

0

1

0

6

0

1

0

7

0

1

0

8

0

1

0

9

0

1

0

10

0

1

0

11

0

1

0

12

0

1

0

13

0

1

0

14

0

1

0

15

0

1

0

X = Don’t Care

Chip Dimensions and Pad Layouts

CD4555BMSH

CD4556BMSH

Dimensions in parenthesis are in millimeters and are

derived from the basic inch dimensions as indicated.

Grid graduations are in mils (10-3 inch).

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches

7-1258

CD4555BMS, CD4556BMS

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

EUROPE

ASIA

Intersil Corporation

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

Intersil (Taiwan) Ltd.

Taiwan Limited

7F-6, No. 101 Fu Hsing North Road

Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (321) 724-7000

FAX: (321) 724-7240

1259

型号:	CD4555BD
生命周期：	Transferred
IHS 制造商：	GENERAL ELECTRIC SOLID STATE
包装说明：	,
Reach Compliance Code：	unknown
风险等级：	5.75
Base Number Matches：	1

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