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产品型号CD54HCT244F3A的概述

CD54HCT244F3A芯片概述 CD54HCT244F3A是一款高性能的八路缓冲器/驱动器，属于HCT（高电平 CMOS）系列，主要用于数字逻辑电路中。该芯片能在较高的逻辑电平下工作，适用于各种高速应用。它在标准74系列TTL逻辑芯片和CMOS技术之间架起了一座桥梁，展现出较好的兼容性，能够与TTL及CMOS设备顺利交互。 CD54HCT244F3A的外形结构为DIP封装，便于在各类应用中的插装或焊接。其工作电压范围为4.5V至5.5V，非常适合于5V的微控制器和其他数字电路。此芯片广泛应用于数据缓冲、总线驱动、状态指示灯驱动等场合。 CD54HCT244F3A的详细参数以下是CD54HCT244F3A的一些重要参数： - 工作电压：4.5V至5.5V - 逻辑高电平输入：2.0V（最小值） - 逻辑低电平输入：0.8V（最大值） - 输入电流：±1 µA（典型值） - 输出电流...

产品型号CD54HCT244F3A的Datasheet PDF文件预览

CD54/74HC240, CD54/74HCT240,

CD74HC241, CD54/74HCT241,

CD54/74HC244, CD54/74HCT244

High-Speed CMOS Logic

Data sheet acquired from Harris Semiconductor

SCHS167E

November 1997 - Revised October 2004

Octal Buffer/Line Drivers, Three-State

Features

Ordering Information

• HC/HCT240 Inverting

TEMP. RANGE

PART NUMBER

CD54HC240F3A

CD54HC244F3A

CD54HCT240F3A

CD54HCT241F3A

CD54HCT244F3A

CD74HC240E

( C)

PACKAGE

20 Ld CERDIP

20 Ld PDIP

20 Ld SOIC

20 Ld PDIP

20 Ld SOIC

20 Ld PDIP

20 Ld SOIC

20 Ld PDIP

20 Ld SOIC

20 Ld TSSOP

20 Ld PDIP

20 Ld SOIC

20 Ld PDIP

20 Ld SOIC

• HC/HCT241 Non-Inverting

• HC/HCT244 Non-Inverting

[ /Title

(CD74

HC240

CD74

HCT24

CD74

HC241

CD74

HCT24

-55 to 125

• Typical Propagation Delay = 8ns at V

= 5V,

C = 15pF, T = 25 C for HC240

• Three-State Outputs

• Buffered Inputs

• High-Current Bus Driver Outputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

CD74HC240M

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

CD74HC240M96

CD74HC241E

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

CD74HC241M

CD74

HC244

CD74HC241M96

CD74HC244E

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74

CD74HC244M

at V

= 5V

• HCT Types

CD74HC244M96

CD74HCT240E

CD74HCT240M

CD74HCT240M96

CD74HCT240PW

CD74HCT240PWR

CD74HCT240PWT

CD74HCT241E

CD74HCT241M

CD74HCT241M96

CD74HCT244E

CD74HCT244M

CD74HCT244M96

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

Description

The ’HC240 and ’HCT240 are inverting three-state buffers

having two active-low output enables. The CD74HC241,

’HCT241, ’HC244 and ’HCT244 are non-inverting three-

state buffers that differ only in that the 241 has one active-

high and one active-low output enable, and the 244 has two

active-low output enables. All three types have identical

pinouts.

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

Pinout

CD54HC240, CD54HCT240, CD54HCT241,

CD54HC244, CD54HCT244

(CERDIP)

CD74HC240, CD74HC241, CD74HCT241,

CD74HC244, CD74HCT244

(PDIP, SOIC)

CD74HCT240,

(PDIP, SOIC, TSSOP)

TOP VIEW

241

244

241

244

240

1OE

1A0

2Y3

1A1

2Y2

1A2

2Y1

1A3

2Y0

1OE

1A0

2Y3

1A1

2Y2

1A2

2Y1

1A3

2Y0

2OE (241) 2OE (240, 244)

18 1Y0

17 2A3

16 1Y1

1Y0

2A3

1Y1

2A2

1Y2

2A1

2A2

1Y2

13 2A1

1Y3

11 2A0

1Y3

2A0

GND GND 10

Functional Diagram

241

AND

244

240

1A0

1Y0 1Y0

1Y1 1Y1

1Y2 1Y2

1Y3 1Y3

2Y0 2Y0

2Y1 2Y1

2Y2 2Y2

2Y3 2Y3

1A1

1A2

1A3

2A0

2A1

2A2

240

AND

244

2A3

241

= 20

GND = 10

1OE 1OE

2OE 2OE

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

Thermal Resistance (Typical, Note 1)

DC Input Diode Current, I

For V < -0.5V or V > V

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . .

M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . .

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . .

69 C/W

+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

For V < -0.5V or V > V

58 C/W

DC Output Diode Current, I

83 C/W

+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C

Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C

(SOIC - Lead Tips Only)

DC Drain Current, per Output, I

For -0.5V < V < V

+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . ±35mA

DC Output Source or Sink Current per Output Pin, I

For V > -0.5V or V < V

+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC V

or Ground Current, I

. . . . . . . . . . . . . . . . . . . . . . . . .±70mA

Operating Conditions

Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance wIth JESD 51-7.

DC Electrical Speciﬁcations

TEST

CONDITIONS

25 C

-40 C TO 85 C

-55 C TO 125 C

PARAMETER

HC TYPES

SYMBOL V (V)

(mA)

(V) MIN TYP MAX

MIN

MAX

MIN

MAX

UNITS

High Level Input

Voltage

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

4.5

Low Level Input

Voltage

0.5

4.5

1.35

1.8

High Level Output

Voltage

CMOS Loads

-0.02

1.9

4.4

5.9

3.98

5.48

1.9

4.4

5.9

3.84

5.34

1.9

4.4

5.9

3.7

5.2

-0.02

-6

4.5

High Level Output

Voltage

TTL Loads

4.5

-7.8

Low Level Output

Voltage

CMOS Loads

0.02

4.5

0.1

0.4

0.1

Low Level Output

Voltage

TTL Loads

4.5

0.26

0.33

7.8

Input Leakage

Current

±0.1

±1

µA

GND

Quiescent Device

Current

160

GND

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

DC Electrical Speciﬁcations

(Continued)

TEST

CONDITIONS

25 C

-40 C TO 85 C

-55 C TO 125 C

PARAMETER

SYMBOL V (V)

(mA)

(V) MIN TYP MAX

MIN

MAX

MIN

MAX

UNITS

Three-State Leakage

Current

±0.5

±10

µA

HCT TYPES

High Level Input

Voltage

4.5 to

5.5

0.8

Low Level Input

Voltage

4.5 to

5.5

High Level Output

Voltage

CMOS Loads

-0.02

4.5

4.4

High Level Output

Voltage

TTL Loads

-6

3.98

3.84

3.7

Low Level Output

Voltage

CMOS Loads

0.02

0.1

0.26

0.1

0.33

0.1

0.4

Low Level Output

Voltage

TTL Loads

Input Leakage

Current

5.5

±0.1

±1

µA

GND

Quiescent Device

Current

160

490

GND

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆I

(Note 2)

4.5 to

5.5

100

360

450

-2.1

Three-State Leakage

Current

5.5

±0.5

±5

±10

µA

NOTE:

2. For dual-supply systems theoretical worst case (V = 2.4V, V

= 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT

UNIT LOADS

HCT240

HCT241

HCT244

nA0-A3

1OE

1.5

0.7

2OE

nA0-A3

1OE

0.7

1.5

2OE

nA0-A3

1OE

0.7

2OE

NOTE: Unit Load is ∆I

Speciﬁcations table, e.g., 360µA max at 25 C.

limit speciﬁed in DC Electrical

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

Switching Speciﬁcations C = 50pF, Input t , t = 6ns

r f

TEST

CONDI-

TIONS

25 C

-40 C TO 85 C

-55 C TO 125 C

(V)

PARAMETER

HC TYPES

SYMBOL

MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

Propagation Delay

, t

= 50pF

PLH PHL

Data to Outputs

HC240

4.5

100

125

150

= 15pF

= 50pF

110

140

165

Data to Outputs

HC241

, t

PLH PHL

4.5

= 15pF

= 50pF

110

140

165

Data to Outputs

HC244

t , t

PLH PHL

4.5

= 15pF

= 50pF

150

190

225

Output Enable and Disable

Time

, t

THL TLH

4.5

Output Transition Time

Input Capacitance

, t

TLH THL

= 50pF

4.5

= 50pF

Three-State Output

Capacitance

Power Dissipation Capacitance

(Notes 3, 4)

= 15pF

HC240

HC241

HC244

HCT TYPES

Propagation Delay

Data to Outputs

HCT240

= 50pF

= 15pF

= 50pF

= 15pF

= 50pF

= 15pF

4.5

PHL, PLH

Data to Outputs

HCT241

4.5

PHL, PLH

Data to Outputs

HCT244

4.5

PHL, PLH

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

Switching Speciﬁcations C = 50pF, Input t , t = 6ns (Continued)

r f

TEST

CONDI-

TIONS

25 C

-40 C TO 85 C

-55 C TO 125 C

(V)

PARAMETER

SYMBOL

MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

Output Enable and Disable

Times

= 50pF

4.5

TLH, THL

Output Transition Time

Input Capacitance

, t

THL TLH

= 50pF

4.5

Power Dissipation Capacitance

(Notes 3, 4)

HCT240

HCT241

HCT244

NOTES:

3. C

is used to determine the dynamic power consumption, per channel.

4. P = V

f (C

+ C ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V

= Supply Voltage.

Test Circuits and Waveforms

t = 6ns

90%

50%

10%

2.7V

1.3V

0.3V

INPUT

GND

THL

TLH

THL

TLH

90%

1.3V

90%

50%

10%

INVERTING

OUTPUT

INVERTING

OUTPUT

10%

PLH

PHL

PLH

PHL

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6ns

OUTPUT

DISABLE

OUTPUT

DISABLE

90%

2.7

50%

1.3

10%

0.3

GND

PZL

PLZ

OUTPUT LOW

TO OFF

OUTPUT LOW

TO OFF

50%

1.3V

10%

90%

10%

90%

PZH

PHZ

PZH

OUTPUT HIGH

TO OFF

OUTPUT HIGH

TO OFF

1.3V

OUTPUTS

ENABLED

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

FIGURE 3. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

Test Circuits and Waveforms (Continued)

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

= 1kΩ

IC WITH

THREE-

STATE

FOR t AND t

PLZ

GND FOR t

PZL

AND t

PHZ

PZH

OUTPUT

50pF

OUTPUT

DISABLE

NOTE: Open drain waveforms t

and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to

PZL L

PLZ

, C = 50pF.

FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

0,10

0,65

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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Use of such information may require a license from a third party under the patents or other intellectual property

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Products

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Amplifiers

amplifier.ti.com

www.ti.com/audio

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dataconverter.ti.com

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www.ti.com/automotive

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dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

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Microcontrollers

power.ti.com

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Security

www.ti.com/opticalnetwork

www.ti.com/security

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www.ti.com/video

microcontroller.ti.com

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Wireless

www.ti.com/wireless

Mailing Address:

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CD54HCT244F3A相关文章

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CD54HCT244F3A产品参数

型号:	CD54HCT244F3A
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	HARRIS SEMICONDUCTOR
Reach Compliance Code：	unknown
风险等级：	5.6
Is Samacsys：	N
控制类型：	ENABLE LOW
系列：	HCT
JESD-30 代码：	R-GDIP-T20
JESD-609代码：	e0
负载电容（CL）：	50 pF
逻辑集成电路类型：	BUS DRIVER
最大I（ol）：	0.006 A
位数：	4
功能数量：	2
端口数量：	2
端子数量：	20
最高工作温度：	125 °C
最低工作温度：	-55 °C
输出特性：	3-STATE
输出极性：	TRUE
封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP
封装等效代码：	DIP20,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
Prop。Delay @ Nom-Sup：	38 ns
认证状态：	Not Qualified
筛选级别：	38535Q/M;38534H;883B
子类别：	Bus Driver/Transceivers
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

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