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  • 北京元坤伟业科技有限公司

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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
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  • 数量25 
  • 厂家TI 
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  • 深圳市广百利电子有限公司

     该会员已使用本站6年以上
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  • 数量18500 
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  • 深圳市恒嘉威智能科技有限公司

     该会员已使用本站7年以上
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  • 数量30000 
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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
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  • 数量25 
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  • 深圳市科庆电子有限公司

     该会员已使用本站16年以上
  • CD74HC4046AE
  • 数量8560 
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  • 深圳市西昂特科技有限公司

     该会员已使用本站13年以上
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  • 数量6000 
  • 厂家Texas Instru 
  • 封装16-DIP(300 m 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
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  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
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  • 深圳市正信鑫科技有限公司

     该会员已使用本站12年以上
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  • 数量7887 
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  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
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  • 数量5000 
  • 厂家Texas Instruments 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
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     该会员已使用本站17年以上
  • CD74HC4046AE
  • 数量10000 
  • 厂家TI/德州仪器 
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
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  • 数量15735 
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  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • CD74HC4046AE
  • 数量5000 
  • 厂家Texas Instruments 
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  • 绿盛电子(香港)有限公司

     该会员已使用本站12年以上
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  • 数量2015 
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  • 深圳市惊羽科技有限公司

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  • 数量9328 
  • 厂家TI-德州仪器 
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  • 深圳市华来深电子有限公司

     该会员已使用本站13年以上
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  • 数量8560 
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  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
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  • 数量7536 
  • 厂家Texas Instruments 
  • 封装16-PDIP 
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  • 深圳市创芯联科技有限公司

     该会员已使用本站9年以上
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  • 数量15000 
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  • 深圳市宇川湘科技有限公司

     该会员已使用本站6年以上
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  • 数量23000 
  • 厂家HARRIS 
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  • 批号23+ 
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  • 深圳市赛尔通科技有限公司

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  • 数量85600 
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  • 深圳市得捷芯城科技有限公司

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  • 数量5755 
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  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
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  • 数量5000 
  • 厂家Texas Instruments 
  • 封装16-PDIP 
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  • 深圳市欧瑞芯科技有限公司

     该会员已使用本站11年以上
  • CD74HC4046AE
  • 数量9500 
  • 厂家TI(德州仪器) 
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  • 绝对原装正品,可开13%专票,欢迎采购!!!
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  • 上海金庆电子技术有限公司

     该会员已使用本站15年以上
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  • 数量25 
  • 厂家HARRIS 
  • 封装 
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  • 深圳市珩瑞科技有限公司

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  • 数量800 
  • 厂家TI 
  • 封装DIP8 
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
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  • 数量2400 
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  • 深圳市芯福林电子有限公司

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  • 数量65000 
  • 厂家TI 
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  • 深圳市恒意法科技有限公司

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  • 数量6697 
  • 厂家Texas Instruments 
  • 封装16-DIP(0.300,7.62mm) 
  • 批号21+ 
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  • 深圳市捷兴胜微电子科技有限公司

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  • 数量1200 
  • 厂家HARRIS 
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  • 深圳市鹏睿康科技有限公司

     该会员已使用本站16年以上
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  • 数量1200 
  • 厂家TI 
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  • 批号23+ 
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  • 北京力通科信电子有限公司

     该会员已使用本站10年以上
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  • 数量1000 
  • 厂家TI 
  • 封装 16-Dip  
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  • 深圳市赛科世纪电子有限公司

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  • 数量63618 
  • 厂家HAIRRIS 
  • 封装DIP16 
  • 批号22+ 
  • 代理新到原装现货,特价,13006691066
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  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
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  • 数量6500000 
  • 厂家TI 
  • 封装原厂原装 
  • 批号22+ 
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  • 深圳市鹏和科技有限公司

     该会员已使用本站16年以上
  • CD74HC4046AE
  • 数量59013 
  • 厂家TI 
  • 封装PDIP 
  • 批号23+ 
  • 原装正品 代理渠道
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  • 北京云中青城科技有限公司

     该会员已使用本站8年以上
  • CD74HC4046AE
  • 数量9000 
  • 厂家Texas Instruments 
  • 封装DIP-16 
  • 批号20+ 
  • 只做原装.诚信经营
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  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
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  • 数量20000 
  • 厂家TI 
  • 封装原厂封装 
  • 批号23+ 
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  • 北京耐芯威科技有限公司

     该会员已使用本站13年以上
  • CD74HC4046AE
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装16-PDIP 
  • 批号21+ 
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产品型号CD74HC4046AE的概述

CD74HC4046AE 芯片概述及详细参数 一、芯片概述 CD74HC4046AE是一种广泛应用于频率合成、相位锁定环(PLL)和调制解调等领域的高性能集成电路。该芯片属于74HC系列,具有高速度、低功耗和较强的抗干扰能力等优点,使其在各种电子设计中得到广泛应用。CD74HC4046AE可以用于各种时钟和频率生成任务,以及对信号调制和解调的应用。 CD74HC4046AE集成了多个重要模块,包括相位比较器、VCO(电压控制振荡器)、分频器等。其设计充分考虑了用户的多样需求,支持多个工作模式,能够在复杂的电子系统中灵活设置。 二、详细参数 1. 电源电压范围: CD74HC4046AE对电源电压的要求为2V到6V,适合于多种设计要求。 2. 输入电压范围: CD74HC4046AE支持逻辑电平输入,典型的高电平为2/3 Vcc,低电平为1/3 Vcc。 3. 工作温度范围: ...

产品型号CD74HC4046AE的Datasheet PDF文件预览

CD54HC4046A, CD74HC4046A,  
CD54HCT4046A, CD74HCT4046A  
Data sheet acquired from Harris Semiconductor  
SCHS204J  
High-Speed CMOS Logic  
February 1998 - Revised December 2003  
Phase-Locked Loop with VCO  
Features  
Description  
• Operating Frequency Range  
The ’HC4046A and ’HCT4046A are high-speed silicon-gate  
CMOS devices that are pin compatible with the CD4046B of  
the “4000B” series. They are specified in compliance with  
- Up to 18MHz (Typ) at V  
CC  
= 5V  
[ /Title  
(CD74  
HC404  
6A,  
CD74  
HCT40  
46A)  
/Sub-  
ject  
(High-  
Speed  
CMOS  
- Minimum Center Frequency of 12MHz at V  
= 4.5V  
CC  
JEDEC standard number 7.  
• Choice of Three Phase Comparators  
- EXCLUSIVE-OR  
The ’HC4046A and ’HCT4046A are phase-locked-loop  
circuits that contain a linear voltage-controlled oscillator  
(VCO) and three different phase comparators (PC1, PC2 and  
PC3). A signal input and a comparator input are common to  
each comparator.  
- Edge-Triggered JK Flip-Flop  
- Edge-Triggered RS Flip-Flop  
• Excellent VCO Frequency Linearity  
The signal input can be directly coupled to large voltage  
signals, or indirectly coupled (with a series capacitor) to small  
voltage signals. A self-bias input circuit keeps small voltage  
signals within the linear region of the input amplifiers. With a  
passive low-pass filter, the 4046A forms a second-order loop  
PLL. The excellent VCO linearity is achieved by the use of  
linear op-amp techniques.  
• VCO-Inhibit Control for ON/OFF Keying and for Low  
Standby Power Consumption  
• Minimal Frequency Drift  
• Operating Power Supply Voltage Range  
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V  
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V  
Ordering Information  
• Fanout (Over Temperature Range)  
TEMP. RANGE  
o
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
PART NUMBER  
CD54HC4046AF3A  
CD54HCT4046AF3A  
CD74HC4046AE  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
CD74HC4046AM  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
CD74HC4046AMT  
CD74HC4046AM96  
CD74HC4046ANSR  
CD74HC4046APWR  
CD74HC4046APWT  
CD74HCT4046AE  
CD74HCT4046AM  
CD74HCT4046AMT  
CD74HCT4046AM96  
• HC Types  
- 2V to 6V Operation  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at VOL, VOH  
l
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
Applications  
• FM Modulation and Demodulation  
• Frequency Synthesis and Multiplication  
• Frequency Discrimination  
• Tone Decoding  
• Data Synchronization and Conditioning  
• Voltage-to-Frequency Conversion  
• Motor-Speed Control  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
Pinout  
CD54HC4046A, CD54HCT4046A (CERDIP)  
CD74HC4046A (PDIP, SOIC, SOP, TSSOP)  
CD74HCT4046A (PDIP, SOIC)  
TOP VIEW  
PCP  
PC1  
1
2
3
4
5
6
7
8
16 V  
OUT  
CC  
15 PC3  
OUT  
OUT  
IN  
COMP  
14 SIG  
13 PC2  
IN  
VCO  
OUT  
INH  
OUT  
12 R  
11 R  
2
1
C1  
C1  
A
B
10 DEM  
OUT  
9
VCO  
GND  
IN  
Functional Diagram  
2
PC1  
3
OUT  
OUT  
OUT  
COMP  
SIG  
15  
13  
1
IN  
PC3  
PC2  
φ
14  
IN  
PCP  
OUT  
6
7
C1  
C1  
A
4
B
11  
12  
9
VCO  
DEM  
OUT  
R
1
2
VCO  
10  
R
OUT  
VCO  
IN  
5
INH  
Pin Descriptions  
PIN NUMBER  
SYMBOL  
NAME AND FUNCTION  
1
2
PCP  
Phase Comparator Pulse Output  
Phase Comparator 1 Output  
Comparator Input  
OUT  
OUT  
PC1  
3
COMP  
IN  
4
VCO  
VCO Output  
OUT  
5
INH  
Inhibit Input  
6
C1  
C1  
Capacitor C1 Connection A  
Capacitor C1 Connection B  
Ground (0V)  
A
7
B
8
GND  
9
VCO  
VCO Input  
IN  
OUT  
1
10  
11  
12  
13  
14  
15  
16  
DEM  
Demodulator Output  
Resistor R1 Connection  
Resistor R2 Connection  
Phase Comparator 2 Output  
Signal Input  
R
R
2
PC2  
OUT  
SIG  
IN  
PC3  
Phase Comparator 3 Output  
Positive Supply Voltage  
OUT  
V
CC  
2
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
C1  
6
7
4
3
14  
SIG  
COMP  
C1  
C1  
B
IN  
IN  
A
PC1  
PC3  
OUT  
OUT  
2
V
REF  
R2  
R1  
S
12  
11  
D
D
15  
Q
Q
-
VCO  
R2  
R1  
R
-
+
V
CC  
UP  
Q
Q
D
p
10  
CP  
R
R3  
C2  
13  
DEM  
PC2  
OUT  
D
OUT  
-
R5  
+
n
Q
Q
V
CC  
D
GND  
DOWN  
CP  
R
1
D
PCP  
OUT  
INH  
5
VCO  
9
IN  
FIGURE 1. LOGIC DIAGRAM  
General Description  
VCO  
Phase Comparators  
The signal input (SIG ) can be directly coupled to the self-  
IN  
The VCO requires one external capacitor C1 (between C1  
A
biasing amplifier at pin 14, provided that the signal swing is  
between the standard HC family input logic levels.  
Capacitive coupling is required for signals with smaller  
swings.  
and C1 ) and one external resistor R1 (between R and  
B
1
GND) or two external resistors R1 and R2 (between R and  
1
GND, and R and GND). Resistor R1 and capacitor C1  
2
determine the frequency range of the VCO. Resistor R2  
enables the VCO to have a frequency offset if required. See  
logic diagram, Figure 1.  
Phase Comparator 1 (PC1)  
This is an Exclusive-OR network. The signal and comparator  
The high input impedance of the VCO simplifies the design  
of low-pass filters by giving the designer a wide choice of  
resistor/capacitor ranges. In order not to load the low-pass  
filter, a demodulator output of the VCO input voltage is  
input frequencies (f ) must have a 50% duty factor to obtain  
the maximum locking range. The transfer characteristic of  
i
PC1, assuming ripple (f = 2f ) is suppressed, is:  
r
i
V
= (V /π) (φSIG - φCOMP ) where V  
DEMOUT  
CC  
IN  
IN  
DEMOUT  
= V  
provided at pin 10 (DEM  
). In contrast to conventional  
OUT  
techniques where the DEM  
is the demodulator output at pin 10; V  
(via low-pass filter).  
DEMOUT  
PC1OUT  
voltage is one threshold  
OUT  
voltage lower than the VCO input voltage, here the DEM  
OUT  
voltage equals that of the VCO input. If DEM  
is used, a The average output voltage from PC1, fed to the VCO input  
OUT  
load resistor (R ) should be connected from DEM  
to via the low-pass filter and seen at the demodulator output at  
S
OUT  
should be left open. The VCO pin 10 (V  
GND; if unused, DEM  
), is the resultant of the phase differences  
OUT  
DEMOUT  
output (VCO  
)
can be connected directly to the of signals (SIG ) and the comparator input (COMP ) as  
OUT  
IN  
IN  
comparator input (COMP ), or connected via a frequency- shown in Figure 2. The average of V  
is equal to 1/2  
IN  
divider. The VCO output signal has a specified duty factor of  
50%. A LOW level at the inhibit input (INH) enables the VCO input the VCO oscillates at the center frequency (f ).  
DEM  
V
when there is no signal or noise at SIG , and with this  
CC  
IN  
o
and demodulator, while a HIGH level turns both off to Typical waveforms for the PC1 loop locked at f are shown  
o
minimize standby power consumption.  
in Figure 3.  
3
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
The frequency capture range (2f ) is defined as the  
C
frequency range of input signals on which the PLL will lock if  
V
V
V
=
(V /4π) (φSIG  
CC  
-
φCOMP )  
IN  
where  
DEMOUT  
DEMOUT  
DEMOUT  
IN  
is the demodulator output at pin 10;  
= V (via low-pass filter).  
PC2OUT  
it was initially out-of-lock. The frequency lock range (2f ) is  
L
defined as the frequency range of input signals on which the  
loop will stay locked if it was initially in lock. The capture  
range is smaller or equal to the lock range.  
The average output voltage from PC2, fed to the VCO via the  
low-pass filter and seen at the demodulator output at pin 10  
(V  
), is the resultant of the phase differences of  
DEMOUT  
With PC1, the capture range depends on the low-pass filter SIG and COMP as shown in Figure 4. Typical waveforms  
IN IN  
characteristics and can be made as large as the lock range. for the PC2 loop locked at f are shown in Figure 5.  
o
This configuration retains lock behavior even with very noisy  
V
CC  
input signals. Typical of this type of phase comparator is that  
it can lock to input frequencies close to the harmonics of the  
VCO center frequency.  
V
DEMOUT (AV)  
V
CC  
1/2 V  
CC  
V
DEMOUT (AV)  
1/2 V  
CC  
0
o
o
o
φDEMOUT  
-360  
0
360  
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT  
VOLTAGE vs INPUT PHASE DIFFERENCE:  
0
o
o
o
φDEMOUT  
0
90  
180  
V
= V  
DEMOUT  
PC2OUT  
= (V /4π) (φSIG - φCOMP );  
CC IN IN  
φ
= (φSIG - φCOMP )  
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT  
VOLTAGE vs INPUT PHASE DIFFERENCE:  
DEMOUT IN IN  
V
= V  
= (V /π) (φSIG  
= (φSIG - φCOMP  
IN  
-
)
IN  
DEMOUT  
PC1OUT  
DEMOUT  
CC  
IN  
φCOMP ); φ  
IN  
SIG  
IN  
COMP  
IN  
VCO  
OUT  
V
CC  
PC2  
OUT  
SIG  
GND  
IN  
HIGH IMPEDANCE OFF - STATE  
COMP  
IN  
VCO  
IN  
VCO  
OUT  
PCP  
OUT  
PC1  
OUT  
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE  
COMPARATOR 2, LOOP LOCKED AT f  
V
CC  
o
VCO  
IN  
GND  
When the frequencies of SIG and COMP are equal but  
IN IN  
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE  
the phase of SIG leads that of COMP , the p-type output  
IN IN  
COMPARATOR 1, LOOP LOCKED AT f  
o
driver at PC2  
is held “ON” for a time corresponding to  
OUT  
the phase difference (φ  
). When the phase of SIG  
DEMOUT  
lags that of COMP , the n-type driver is held “ON”.  
IN  
Phase Comparator 2 (PC2)  
IN  
When the frequency of SIG  
is higher than that of  
This is a positive edge-triggered phase and frequency  
detector. When the PLL is using this comparator, the loop  
is controlled by positive signal transitions and the duty  
IN  
COMP , the p-type output driver is held “ON” for most of  
IN  
the input signal cycle time, and for the remainder of the  
cycle both n- and p-type drivers are “OFF” (three-state). If  
the SIG frequency is lower than the COMP frequency,  
factors of SIG and COMP are not important. PC2  
IN IN  
comprises two D-type flip-flops, control-gating and a three-  
state output stage. The circuit functions as an up-down  
IN  
IN  
then it is the n-type driver that is held “ON” for most of the  
cycle. Subsequently, the voltage at the capacitor (C2) of  
counter (Figure 1) where SIG causes an up-count and  
IN  
the low-pass filter connected to PC2  
varies until the  
COMP  
a down-count. The transfer function of PC2,  
OUT  
signal and comparator inputs are equal in both phase and  
IN  
assuming ripple (f = f ) is suppressed, is:  
r
i
4
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
frequency. At this stable point the voltage on C2 remains  
constant as the PC2 output is in three-state and the VCO  
input at pin 9 is a high impedance. Also in this condition,  
V
CC  
the signal at the phase comparator pulse output (PCP  
)
OUT  
V
is a HIGH level and so can be used for indicating a locked  
DEMOUT (AV)  
condition.  
Thus, for PC2, no phase difference exists between SIG  
IN  
1/2 V  
CC  
and COMP over the full frequency range of the VCO.  
IN  
Moreover, the power dissipation due to the low-pass filter is  
reduced because both p- and n-type drivers are “OFF” for  
most of the signal input cycle. It should be noted that the  
PLL lock range for this type of phase comparator is equal to  
the capture range and is independent of the low-pass filter.  
0
o
o
o
With no signal present at SIG , the VCO adjusts, via PC2,  
φDEMOUT  
0
180  
360  
IN  
to its lowest frequency.  
FIGURE 6. PHASE COMPARATOR 3: AVERAGE OUTPUT  
VOLTAGE vs INPUT PHASE DIFFERENCE:  
Phase Comparator 3 (PC3)  
V
= V  
DEMOUT  
PC3OUT  
This is  
a positive edge-triggered sequential phase  
= (V /2π) (φSIG - φCOMP );  
CC IN IN  
detector using an RS-type flip-flop. When the PLL is using  
this comparator, the loop is controlled by positive signal  
φ
= (φSIG - φCOMP )  
DEMOUT IN IN  
transitions and the duty factors of SIG and COMP are  
IN IN  
not important. The transfer characteristic of PC3,  
assuming ripple (f = f ) is suppressed, is:  
r
i
SIG  
V
V
= V  
=
(V /2p) (fSIG  
CC  
-
fCOMP )  
IN  
where  
IN  
DEMOUT  
DEMOUT  
PC3OUT  
IN  
is the demodulator output at pin 10; V  
(via low-pass filter).  
DEMOUT  
COMP  
IN  
VCO  
OUT  
The average output from PC3, fed to the VCO via the low-  
pass filter and seen at the demodulator at pin 10  
PC3  
OUT  
(V  
), is the resultant of the phase differences of  
DEMOUT  
SIG and COMP  
as shown in Figure 6. Typical  
V
IN  
IN  
CC  
VCO  
IN  
waveforms for the PC3 loop locked at f are shown in  
o
GND  
Figure 7.  
FIGURE 7. TYPICAL WAVEFORMS FOR PLL USING PHASE  
The phase-to-output response characteristic of PC3  
(Figure 6) differs from that of PC2 in that the phase angle  
COMPARATOR 3, LOOP LOCKED AT f  
o
o
o
between SIG and COMP varies between 0 and 360  
IN IN  
o
and is 180 at the center frequency. Also PC3 gives a  
greater voltage swing than PC2 for input phase differences  
but as aconsequence the ripple content of the VCO input  
signal is higher. With no signal present at SIG , the VCO  
IN  
adjusts, via PC3, to its highest frequency.  
The only difference between the HC and HCT versions is the  
input level specification of the INH input. This input disables  
the VCO section. The comparator’s sections are identical, so  
that there is no difference in the SIG (pin 14) or COMP  
IN  
IN  
(pin 3) inputs between the HC and the HCT versions.  
5
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
Absolute Maximum Ratings  
Thermal Information  
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Package Thermal Impedance, θ (see Note 1):  
JA  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W  
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C/W  
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
o
IK  
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
o
DC Output Diode Current, I  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Drain Current, per Output, I  
O
o
o
For -0.5V < V < V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA  
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
O
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
(SOIC - Lead Tips Only)  
O
O
CC  
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA  
CC  
CC  
Operating Conditions  
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
VCO SECTION  
INH High Level Input  
Voltage  
V
-
-
-
-
3
4.5  
6
2.1  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.1  
-
2.1  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH  
3.15  
-
-
3.15  
-
-
3.15  
4.2  
4.2  
4.2  
-
INH Low Level Input  
Voltage  
V
3
-
0.9  
1.35  
1.8  
-
-
0.9  
1.35  
1.8  
-
-
0.9  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
VCO  
High Level  
V
V
V
V
or V  
IL  
-0.02  
3
2.9  
2.9  
2.9  
OUT  
OH  
IH  
IH  
IL  
Output Voltage  
CMOS Loads  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
VCO  
High Level  
-
-
-
-
-
-
-
OUT  
Output Voltage  
TTL Loads  
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
VCO  
Low Level  
V
or V  
IL  
2
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OUT  
OL  
Output Voltage  
CMOS Loads  
4.5  
6
VCO  
Low Level  
-
OUT  
Output Voltage  
TTL Loads  
4
4.5  
6
0.26  
0.26  
0.40  
0.40  
0.33  
0.33  
0.47  
0.47  
0.4  
0.4  
0.54  
0.54  
5.2  
4
C1A, C1B Low Level  
Output Voltage  
(Test Purposes Only)  
V
or V  
4.5  
6
OL  
IH  
5.2  
6
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
SYMBOL  
V (V)  
I
(mA)  
O
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
INH VCO Input  
IN  
I
V
GND  
or  
-
6
-
-
±0.1  
-
±1  
-
±1  
µA  
I
CC  
Leakage Current  
R1 Range (Note 2)  
R2 Range (Note 2)  
-
-
-
-
-
-
-
4.5  
4.5  
3
3
3
-
-
-
-
-
-
-
-
300  
300  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
kΩ  
kΩ  
pF  
pF  
pF  
V
-
-
C1 Capacitance  
Range  
-
No  
Limit  
4.5  
6
-
-
VCO Operating  
IN  
Voltage Range  
-
Over the range  
specified for R1 for  
LinearitySeeFigure  
10, and 34 - 37  
(Note 3)  
3
1.1  
1.1  
1.1  
1.9  
3.2  
4.6  
4.5  
6
V
V
PHASE COMPARATOR SECTION  
SIG , COMP  
IN  
DC Coupled  
High-Level Input  
Voltage  
V
-
-
-
2
4.5  
6
1.5  
3.15  
4.2  
-
-
-
-
-
-
1.5  
3.15  
4.2  
-
-
-
1.5  
3.15  
4.2  
-
-
-
V
V
V
IN  
IH  
SIG , COMP  
IN  
DC Coupled  
Low-Level Input  
Voltage  
V
-
2
4.5  
6
-
-
-
-
-
-
0.5  
1.35  
1.8  
-
-
-
0.5  
1.35  
1.8  
-
-
-
0.5  
1.35  
1.8  
V
V
V
IN  
IL  
PCP  
High-Level Output  
Voltage  
CMOS Loads  
, PCn OUT  
V
V
V
V
V
or V  
or V  
or V  
or V  
-0.02  
2
4.5  
6
1.9  
4.4  
5.9  
-
-
-
-
-
-
1.9  
4.4  
5.9  
-
-
-
1.9  
4.4  
5.9  
-
-
-
V
V
V
OUT  
OH  
IL  
IL  
IL  
IL  
IH  
IH  
IH  
IH  
PCP  
High-Level Output  
Voltage  
TTL Loads  
, PCn OUT  
V
-4  
4.5  
6
3.98  
5.48  
-
-
-
-
3.84  
5.34  
-
-
3.7  
5.2  
-
-
V
V
OUT  
OH  
-5.2  
PCP  
Low-Level Output  
Voltage  
CMOS Loads  
, PCn OUT  
V
0.02  
2
4.5  
6
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
0.1  
0.1  
0.1  
-
-
-
0.1  
0.1  
0.1  
V
V
V
OUT  
OL  
PCP  
Low-Level Output  
Voltage  
, PCn OUT  
V
4
4.5  
6
-
-
-
-
0.26  
0.26  
-
-
0.33  
0.33  
-
-
0.4  
0.4  
V
V
OUT  
OL  
5.2  
TTL Loads  
SIG , COMP Input  
IN IN  
Leakage Current  
I
V
or  
-
-
2
3
-
-
-
-
-
-
-
-
-
-
±3  
±7  
-
-
-
-
-
±4  
±9  
-
-
-
-
-
±5  
µA  
µA  
µA  
µA  
µA  
I
CC  
GND  
±11  
±29  
±45  
±10  
4.5  
6
±18  
±30  
±0.5  
±23  
±38  
±5  
PC2  
Three-State  
Off-State Current  
I
V
or V  
6
OUT  
OZ  
IL  
IH  
SIG , COMP Input  
Resistance  
R
V at Self-Bias  
I
Operation Point:  
3
4.5  
6
-
-
-
800  
250  
150  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
kΩ  
kΩ  
kΩ  
IN  
IN  
I
V = 0.5V,  
I
See Figure 10  
DEMODULATOR SECTION  
Resistor Range  
R
at R > 300kΩ  
Leakage Current  
Can Influence  
3
4.5  
6
50  
50  
50  
-
-
-
300  
300  
300  
-
-
-
-
-
-
-
-
-
-
-
-
kΩ  
kΩ  
kΩ  
S
S
V
DEMOUT  
7
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
SYMBOL  
V (V)  
I
(mA)  
O
(V)  
MIN  
TYP  
±30  
±20  
±10  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
mV  
I
Offset Voltage VCO  
V
V = V  
VCO IN  
=
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IN  
OFF  
I
V
to V  
CC  
2
DEM  
4.5  
6
mV  
mV  
Values Taken Over  
Range  
R
S
See Figure 23  
Dynamic Output  
Resistance at  
R
V
=
3
4.5  
6
-
-
-
-
25  
25  
25  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D
DEMOUT  
V
CC  
-
-
2
DEM  
OUT  
-
-
Quiescent Device  
Current  
I
Pins 3, 5 and 14  
at V Pin 9 at  
6
8
80  
160  
µA  
CC  
CC  
GND, I at Pins 3  
1
and 14 to be  
excluded  
HCT TYPES  
VCO SECTION  
INH High Level Input  
Voltage  
V
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
INH Low Level Input  
Voltage  
V
-
4.5 to  
5.5  
IL  
VCO  
High Level  
V
V
V
V
or V  
-0.02  
4.5  
4.5  
4.5  
4.5  
4.5  
5.5  
4.4  
4.4  
4.4  
OUT  
OH  
IH  
IH  
IH  
IL  
IL  
IL  
Output Voltage  
CMOS Loads  
VCO  
High Level  
-4  
0.02  
4
3.98  
-
-
-
-
-
3.84  
-
3.7  
-
V
V
OUT  
Output Voltage  
TTL Loads  
VCO  
Low Level  
V
or V  
or V  
-
-
-
-
0.1  
-
-
-
-
0.1  
0.33  
0.47  
±1  
-
-
-
-
0.1  
0.4  
0.54  
±1  
OUT  
OL  
Output Voltage  
CMOS Loads  
VCO  
Low Level  
0.26  
0.40  
±0.1  
V
OUT  
Output Voltage  
TTL Loads  
C1A, C1B Low Level  
Output Voltage  
(Test Purposes Only)  
V
4
V
OL  
INH VCO Input  
IN  
I
Any Voltage  
µA  
I
Leakage Current  
Between V  
and  
CC  
GND  
R1 Range (Note 2)  
R2 Range (Note 2)  
-
-
-
-
-
-
-
4.5  
4.5  
4.5  
3
3
0
-
-
-
300  
300  
-
-
-
-
-
-
-
-
-
-
-
-
kΩ  
kΩ  
pF  
-
-
C1 Capacitance  
Range  
No  
Limit  
VCO Operating  
IN  
Voltage Range  
-
Over the range  
specified for R1 for  
LinearitySeeFigure  
10, and 34 - 37  
(Note 3)  
4.5  
1.1  
-
3.2  
-
-
-
-
V
PHASE COMPARATOR SECTION  
SIG , COMP  
IN  
DC Coupled  
V
-
-
4.5 to  
5.5  
2
-
-
2
-
2
-
V
IN  
IH  
High-Level Input  
Voltage  
8
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
SIG , COMP  
V
IL  
-
-
4.5 to  
5.5  
-
-
0.8  
-
0.8  
-
0.8  
V
IN  
DC Coupled  
IN  
Low-Level Input  
Voltage  
PCP  
High-Level Output  
Voltage  
CMOS Loads  
, PCn OUT  
V
V
V
V
V
or V  
or V  
or V  
or V  
-
-
-
-
-
4.5  
4.5  
4.5  
4.5  
5.5  
4.4  
-
-
-
-
-
-
4.4  
-
4.4  
3.7  
-
-
V
V
OUT  
OH  
IL  
IL  
IL  
IL  
IH  
IH  
IH  
IH  
PCP  
High-Level Output  
Voltage  
TTL Loads  
, PCn OUT  
V
3.98  
-
3.84  
-
-
OUT  
OH  
PCP  
Low-Level Output  
Voltage  
CMOS Loads  
, PCn OUT  
V
-
-
-
0.1  
0.26  
±30  
-
-
0.1  
0.33  
±38  
0.1  
0.4  
±45  
V
OUT  
OL  
PCP  
Low-Level Output  
Voltage  
, PCn OUT  
V
-
V
OUT  
OL  
TTL Loads  
SIG , COMP Input  
IN IN  
I
Any  
µA  
I
Leakage Current  
Voltage  
Between  
V
and  
CC  
GND  
PC2  
Three-State  
Off-State Current  
I
V
or V  
IH  
-
5.5  
4.5  
-
-
-
±0.5  
±5  
-
-
-
-
±10  
µA  
kΩ  
OUT  
OZ  
IL  
SIG , COMP Input  
R
V at Self-Bias  
250  
-
-
-
IN  
IN  
I
I
Resistance  
Operation Point:  
V = 0.5V,  
I
See Figure 10  
DEMODULATOR SECTION  
Resistor Range  
R
at R > 300kΩ  
Leakage Current  
Can Influence  
4.5  
4.5  
5
-
-
300  
-
-
-
-
-
-
-
-
-
kΩ  
S
S
V
DEM OUT  
V = V =  
VCO IN  
Offset Voltage VCO  
V
±20  
mV  
IN  
OFF  
I
V
to V  
CC  
2
DEM  
Values taken over  
Range  
R
S
See Figure 23  
Dynamic Output  
Resistance at  
R
V
=
4.5  
5.5  
-
25  
-
-
-
-
-
D
DEM OUT  
V
CC  
2
DEM  
OUT  
Quiescent Device  
Current  
I
V
or  
-
-
-
-
-
8
-
-
80  
-
-
160  
490  
µA  
µA  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
I  
V
4.5 to  
5.5  
100  
360  
450  
CC  
CC  
-2.1  
(Note 4)  
Excluding  
Pin 5  
NOTES:  
2. The value for R1 and R2 in parallel should exceed 2.7k.  
3. The maximum operating voltage can be as high as V -0.9V, however, this may result in an increased offset voltage.  
CC  
4. For dual-supply systems theoretical worst case (V = 2.4V, V  
= 5.5V) specification is 1.8mA.  
CC  
I
9
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
HCT Input Loading Table  
INPUT  
INH  
UNIT LOADS  
1
NOTE: Unit load is I  
Table, e.g., 360µA max. at 25 C.  
limit specific in DC Electrical Specifications  
o
CC  
Switching Specifications C = 50pF, Input t , t = 6ns  
L
r f  
o
o
-40 C TO  
-55 C TO  
o
o
o
25 C  
85 C  
125 C  
TEST  
SYMBOL CONDITIONS  
PARAMETER  
HC TYPES  
PHASE COMPARATOR SECTION  
Propagation Delay  
SIG , COMP to PCI  
V
(V) MIN  
TYP MAX MIN MAX  
MIN  
MAX  
UNITS  
CC  
t
, t  
PLH PHL  
2
-
-
-
200  
40  
34  
300  
60  
51  
245  
49  
42  
75  
15  
13  
265  
53  
45  
315  
63  
54  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
250  
50  
43  
375  
75  
64  
305  
61  
52  
95  
19  
16  
330  
66  
56  
395  
79  
67  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
300  
60  
51  
450  
90  
77  
307  
74  
63  
110  
22  
19  
400  
80  
68  
475  
95  
81  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
mV  
mV  
mV  
IN IN OUT  
4.5  
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SIG , COMP to PCP  
IN IN  
2
-
OUT  
4.5  
6
-
-
SIG , COMP to PC3  
IN IN  
2
-
OUT  
4.5  
6
-
-
Output Transition Time  
t
, t  
THL TLH  
2
-
4.5  
6
-
-
Output Enable Time, SIG  
COMP to PC2  
IN OUT  
,
t
t
, t  
PZH PZL  
2
-
IN  
4.5  
6
-
-
Output Disable Time, SIG  
,
, t  
2
-
IN  
PHZ PLZ  
COMP to PC2  
IN OUT  
4.5  
6
-
-
AC Coupled Input Sensitivity  
) at SIG or COMP  
V
3
11  
15  
33  
I(P-P)  
(
P-P  
IN  
IN  
4.5  
6
-
-
-
-
-
-
VCO SECTION  
o
Frequency Stability with  
Temperature Change  
f  
T  
R
= 100k,  
R = ∞  
2
3
4.5  
6
-
-
-
-
-
-
-
-
-
0.11  
0.11  
0.11  
24  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
%/ C  
1
o
%/ C  
o
%/ C  
Maximum Frequency  
f
C
R
= 50pF  
3
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MAX  
1
= 3.5kΩ  
1
4.5  
6
24  
R = ∞  
2
24  
C
= 0pF  
3
38  
1
R
= 9.1kΩ  
1
4.5  
6
38  
R = ∞  
2
38  
10  
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)  
L
r f  
o
o
-40 C TO  
-55 C TO  
o
o
o
25 C  
85 C  
125 C  
TEST  
SYMBOL CONDITIONS  
PARAMETER  
Center Frequency  
V
(V) MIN  
TYP MAX MIN MAX  
MIN  
MAX  
UNITS  
MHz  
CC  
C
R
= 40pF  
= 3kΩ  
3
7
10  
17  
21  
-
-
-
-
-
-
-
-
-
-
-
1
1
4.5  
6
12  
14  
-
-
-
-
MHz  
R = ∞  
2
VCO  
=
MHz  
IN  
VCC/2  
Frequency Linearity  
f  
VCO  
R
C
= 100kΩ  
3
4.5  
6
-
-
-
-
-
-
0.4  
0.4  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
%
%
1
R = ∞  
2
= 100pF  
1
0.4  
%
Offset Frequency  
R
= 220kΩ  
3
400  
400  
400  
kHz  
kHz  
kHz  
2
C
= 1nF  
1
4.5  
6
DEMODULATOR SECTION  
V
V
f
R
= 100kΩ  
1
3
4.5  
6
-
-
-
-
330  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mV/kHz  
mV/kHz  
mV/kHz  
OUT S IN  
R = ∞  
2
C
R
= 100pF  
1
= 10kΩ  
S
R
= 100kΩ  
3
C
= 100pF  
2
HCT TYPES  
PHASE COMPARATOR SECTION  
Propagation Delay  
SIG , COMP to PCI  
t
t
PHL, PLH  
C
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
4.5  
4.5  
4.5  
4.5  
4.5  
-
-
-
-
-
-
-
-
-
-
45  
68  
58  
15  
60  
-
-
-
-
-
56  
85  
73  
19  
75  
-
-
-
-
-
68  
102  
87  
ns  
ns  
ns  
ns  
pF  
IN IN OUT  
L
L
L
L
L
SIG , COMP to PCP  
IN IN  
t
t
C
C
C
C
OUT PHL, PLH  
SIG , COMP to PC3  
t
t
IN IN OUT PHL, PLH  
Output Transition Time  
Output Enable Time, SIG  
t
, t  
TLH THL  
22  
,
t
, t  
PZH PZL  
90  
IN  
COMP to PC2  
IN OUT  
Output Disable Time, SIG  
,
t
, t  
C
= 50pF  
I(P-P)  
4.5  
4.5  
-
-
-
68  
-
-
-
85  
-
-
-
102  
-
pF  
IN  
PHZ PLZ  
L
COMP to PCZ  
IN  
OUT  
AC Coupled Input Sensitivity  
) at SIG or COMP  
V
15  
mV  
(
P-P  
IN  
I
VCO SECTION  
o
Frequency Stability with  
Temperature Change  
f  
T  
R
= 100k,  
R = ∞  
2
4.5  
4.5  
-
-
0.11  
24  
-
-
-
-
-
-
-
-
-
-
%/ C  
1
Maximum Frequency  
f
C
R
= 50pF  
MHz  
MHz  
MHz  
MAX  
1
= 3.5kΩ  
1
R = ∞  
2
C
= 0pF  
4.5  
4.5  
-
38  
17  
-
-
-
-
-
-
-
-
-
-
1
R
= 9.1kΩ  
1
R = ∞  
2
Center Frequency  
Frequency Linearity  
C
R
= 40pF  
12  
1
= 3kΩ  
1
R = ∞  
2
VCO  
=
IN  
VCC/2  
f  
VCO  
R
C
= 100kΩ  
4.5  
-
0.4  
-
-
-
-
-
%
1
R = ∞  
2
= 100pF  
1
11  
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)  
L
r f  
o
o
-40 C TO  
-55 C TO  
o
o
o
25 C  
85 C  
125 C  
TEST  
SYMBOL CONDITIONS  
PARAMETER  
Offset Frequency  
V
(V) MIN  
TYP MAX MIN MAX  
MIN  
MAX  
UNITS  
CC  
R
C
= 220kΩ  
4.5  
-
400  
330  
-
-
-
-
-
kHz  
2
= 1nF  
1
DEMODULATOR SECTION  
V
V
f
R
= 100kΩ  
1
4.5  
-
-
-
-
-
-
mV/kHz  
OUT S IN  
R = ∞  
2
C
= 100pF  
1
R
= 10kΩ  
S
R
= 100kΩ  
3
C
= 100pF  
2
Test Circuits and Waveforms  
SIG  
INPUTS  
IN  
V
S
SIG COMP  
IN  
IN  
V
S
INPUTS  
t
t
COMP  
INPUTS  
PHL  
PHL  
IN  
V
S
t
PZH  
t
PCP  
PC1  
OUT  
PZL  
OUT  
t
PZL  
t
PZH  
V
S
PC3  
OUTPUTS  
OUT  
90%  
PC2  
OUT  
OUTPUT  
V
S
t
t
TLH  
TLH  
10%  
FIGURE 8. INPUT TO OUTPUT PROPAGATION DELAYS AND  
OUTPUT TRANSITION TIMES  
FIGURE 9. THREE STATE ENABLE AND DISABLE TIMES FOR  
PC2  
OUT  
Typical Performance Curves  
I
I
V  
I
SELF-BIAS OPERATING POINT  
V
I
FIGURE 10. TYPICAL INPUT RESISTANCE CURVE AT SIG  
,
IN  
COMP  
IN  
12  
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
Typical Performance Curves (Continued)  
8
7
8
7
10  
10  
R1 = 2.2K  
R1 = 22K  
R1 = 220K  
R1 = 2.2M  
R1 = 11M  
R1 =3K  
R1 = 30K  
R1 =330K  
R1 = 3M  
R1 = 15M  
10  
10  
6
5
6
5
10  
10  
10  
10  
4
3
2
4
3
2
10  
10  
10  
10  
10  
10  
VCO = 0.5 V  
IN  
CC  
VCO = 0.5 V  
IN CC  
10  
1
10  
1
V
= 6.0V  
CC  
V
= 4.5V  
CC  
2
3
4
5
6
2
3
4
5
6
1
10  
1
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
CAPACITANCE, C1 (pF)  
CAPACITANCE, C1 (pF)  
FIGURE 11. HC4046A TYPICAL CENTER FREQUENCY vs R1,  
C1 (V = 4.5V)  
FIGURE 12. HC4046A TYPICAL CENTER FREQUENCY vs R1,  
C1 (V = 6V)  
CC  
CC  
8
7
8
10  
10  
R1 = 2.2K  
R1 = 22K  
R1 = 220K  
R1 = 2.2M  
R1 = 11M  
R1 = 1.5K  
R1 = 15K  
R1 = 150K  
R1 = 1.5M  
R1 = 7.5M  
10  
7
6
5
4
3
2
10  
10  
10  
10  
10  
10  
6
5
10  
10  
4
3
2
10  
10  
10  
VCO = 0.5 V  
IN CC  
VCO = 0.5 V  
IN  
V
= 3.0V  
CC  
10  
1
CC  
10  
1
V
= 4.5V  
R2 = OPEN  
CC  
2
3
4
5
6
2
3
4
5
6
1
10  
1
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
CAPACITANCE, C1 (pF)  
CAPACITANCE, C1 (pF)  
FIGURE 13. HC4046A TYPICAL CENTER FREQUENCY vs R1,  
C1 (V = 3V, R2 = OPEN)  
FIGURE 14. HCT4046A TYPICAL CENTER FREQUENCY vs R1,  
C1 (V = 4.5V)  
CC  
CC  
8
140  
120  
100  
10  
R1 = 3K  
C1 = 50pF  
R1 = 1.5M  
V
= 6V  
CC  
R1 = 30K  
R1 = 300K  
R1 = 3M  
R1 = 15M  
7
6
5
4
3
2
10  
10  
10  
10  
10  
10  
V
= 4.5V  
CC  
80  
60  
40  
V
= 3V  
CC  
VCO = 0.5 V  
IN CC  
10  
1
V
= 5.5V  
CC  
20  
2
3
4
5
6
0
1
2
3
4
5
6
1
10  
10  
10  
10  
10  
10  
VCO (V)  
IN  
CAPACITANCE, C1 (pF)  
FIGURE 16. HC4046A TYPICAL VCO FREQUENCY vs VCO  
FIGURE 15. HCT4046A TYPICAL CENTER FREQUENCY vs R1,  
C1 (V = 5.5V)  
IN  
(R1 = 1.5M, C1 = 50pF)  
CC  
13  
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
Typical Performance Curves (Continued)  
90  
80  
800  
C1 = 0.1µF  
R1 = 150K  
C1 = 0.1µF  
R1 = 1.5M  
V
= 6V  
V
= 6V  
CC  
CC  
700  
600  
500  
70  
60  
V
= 4.5V  
CC  
V
= 4.5V  
CC  
50  
40  
400  
300  
200  
100  
V
= 3V  
CC  
V
= 3V  
CC  
30  
20  
10  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VCO (V)  
IN  
VCO (V)  
IN  
FIGURE 17. HC4046A TYPICAL VCO FREQUENCY vs VCO  
FIGURE 18. HC4046A TYPICAL VCO FREQUENCY vs VCO  
IN  
IN  
(R1 = 1.5M, C1 = 0.1µF)  
(R1 = 150k, C1 = 0.1µF)  
18  
1400  
V
= 6V  
V
= 6V  
C1 = 0.1µF  
R1 = 5.6k  
C1 = 50pF  
R1 = 150K  
CC  
CC  
16  
1200  
1000  
V
= 4.5V  
CC  
14  
12  
V
= 3V  
V
= 4.5V  
CC  
CC  
10  
8
800  
600  
V
= 3V  
CC  
6
4
2
400  
200  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VCO (V)  
IN  
VCO (V)  
IN  
FIGURE 19. HC4046A TYPICAL VCO FREQUENCY vs VCO  
FIGURE 20. HC4046A TYPICAL VCO FREQUENCY vs VCO  
IN  
IN  
(R1 = 5.6k, C1 = 0.1µF)  
(R1 = 150k, C1 = 50pF)  
24  
24  
VCO = 0.5 V  
IN CC  
V
= 6V  
C1 = 50pF  
R1 = 5.6K  
CC  
R1 = 1.5M  
20  
16  
12  
8
C1 = 50pF, V  
= 3V  
CC  
R2 = OPEN  
20  
16  
12  
R1 = 150K  
V
= 4.5V  
CC  
4
0
R1 = 3K  
V
= 3V  
CC  
-4  
8
4
-8  
R1 = 1.5K  
-12  
-16  
-75 -50  
0
1
2
3
4
5
6
-25  
0
25  
50  
75  
100 125 150  
o
VCO (V)  
IN  
AMBIENT TEMPERATURE, T ( C)  
A
FIGURE 21. HC4046A TYPICAL VCO FREQUENCY vs VCO  
FIGURE 22. HC4046A TYPICAL CHANGE IN VCO FREQUENCY  
vs AMBIENT TEMPERATURE AS A FUNCTION OF  
IN  
(R1 = 5.6k, C1 = 50pF)  
R1 (V  
= 3V)  
CC  
14  
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
Typical Performance Curves (Continued)  
VCO = 0.5 V  
IN  
20  
16  
12  
8
CC  
= 4.5V  
VCO = 0.5 V  
IN CC  
16  
12  
8
R1 = 2.2M  
C1 = 50pF, V  
R1 = 3M  
CC  
C1 = 50pF, V  
= 6.0V  
CC  
R2 = OPEN  
R2 = OPEN  
R1 = 300K  
R1 = 220K  
4
4
0
0
-4  
-8  
-12  
R1 = 3K  
-4  
-8  
-12  
R1 = 2.2K  
-75 -50  
-25  
0
25  
50  
75  
100 125 150  
-75  
-50  
-25  
0
25  
50  
75  
100 125 150  
o
AMBIENT TEMPERATURE, T ( C)  
o
A
AMBIENT TEMPERATURE, T ( C)  
A
FIGURE 23. HC4046A TYPICAL CHANGE IN VCO FREQUENCY  
vs AMBIENT TEMPERATURE AS A FUNCTION OF  
FIGURE 24. HC4046A TYPICAL CHANGE IN VCO FREQUENCY  
vs AMBIENT TEMPERATURE AS A FUNCTION OF  
R1 (V  
= 4.5V)  
R1 (V  
= 6V)  
CC  
CC  
20  
16  
12  
8
VCO = 0.5 V  
IN CC  
20  
16  
12  
8
VCO = 0.5 V  
IN  
R1 = 2.2M  
CC  
= 5.5V  
C1 = 50pF, V  
= 4.5V  
CC  
C1 = 50pF, V  
CC  
R1 = 3M  
R2 = OPEN  
R2 = OPEN  
R1 = 220K  
R1 = 300K  
4
4
0
0
R1 = 3K  
-4  
-8  
-12  
-4  
-8  
-12  
R1 = 2.2K  
-75  
-50  
-25  
0
25  
50  
75  
100 125 150  
-75  
-50  
-25  
0
25  
50  
75  
100 125 150  
o
o
AMBIENT TEMPERATURE, T ( C)  
AMBIENT TEMPERATURE, T ( C)  
A
A
FIGURE 25. HCT4046A TYPICAL CHANGE IN VCO  
FREQUENCY vs AMBIENT TEMPERATURE AS A  
FUNCTION OF R1  
FIGURE 26. HC4046A TYPICAL CHANGE IN VCO FREQUENCY  
vs AMBIENT TEMPERATURE AS A FUNCTION OF  
R1 (V  
= 4.5V)  
CC  
15  
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
Typical Performance Curves (Continued)  
8
7
6
5
4
3
2
8
7
6
5
4
3
2
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
R2 = 1.5K  
R2 = 2.2K  
R2 = 22K  
R2 = 15K  
R2 = 220K  
R2 = 2.2M  
R2 = 150K  
R2 = 1.5M  
VCO = 0.5 V  
IN CC  
CC  
VCO = 0.5 V  
IN  
CC  
10  
1
10  
1
CC  
R2 = 11M  
5
R2 = 7.5M  
5
V
= 4.5V  
V
= 3V  
2
3
4
6
2
3
4
6
10  
1
10  
1
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
CAPACITANCE, C1 (pF)  
CAPACITANCE, C1 (pF)  
FIGURE 28. HC4046A OFFSET FREQUENCY vs R2, C1  
(V = 3V)  
FIGURE 27. HC4046A OFFSET FREQUENCY vs R2, C1  
(V = 4.5V)  
CC  
CC  
8
7
6
5
4
3
2
8
7
6
5
4
3
2
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
R2 = 2.2K  
R2 = 3K  
R2 = 30K  
R2 = 22K  
R2 = 220K  
R2 = 2.2M  
R2 = 300K  
R2 = 3M  
VCO = 0.5 V  
IN  
CC  
HC V  
= 6V  
VCO = 0.5 V  
IN  
CC  
CC  
HCT V  
10  
1
10  
1
CC  
R2 = 11M  
5
R2 = 15M  
5
= 5.5V  
V
= 4.5V  
CC  
2
3
4
6
10  
2
3
4
6
10  
1
10  
1
10  
10  
10  
10  
10  
10  
10  
10  
10  
CAPACITANCE, C1 (pF)  
CAPACITANCE, C1 (pF)  
FIGURE 29. HCT4046A OFFSET FREQUENCY vs R2, C1  
(V = 4.5V)  
FIGURE 30. HC4046A AND HCT4046A OFFSET FREQUENCY  
vs R2, C1 (V  
= 6V, V  
= 5.5V)  
CC  
CC  
CC  
PIN 9 = 0.95 V  
FOR f  
MIN  
PIN 9 = 0.95 V  
PIN 9 = 0V FOR f  
FOR f  
MAX  
CC  
PIN 9 = 0V FOR f  
MAX  
CC  
2
2
MIN  
10  
10  
V
= 3V, 4.5V, 6V  
V
= 4.5V TO 5.5V  
CC  
CC  
10  
10  
0
10  
0
10  
-2  
-1  
10  
2
-2  
-1  
2
1
10  
1
10  
10  
10  
10  
R2/R1  
R2/R1  
FIGURE 31. HC4046A f  
/f  
MIN MAX  
vs R2/R1 (V  
= 3V, 4.5V, 6V)  
FIGURE 32. HCT4046A f  
/f  
vs R2/R1 (V  
= 4.5V TO 5.5V)  
CC  
MAX MIN  
CC  
16  
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
Typical Performance Curves (Continued)  
8
6
C1 = 50pF  
= 4.5V  
V
CC  
R2 = OPEN  
4
f
VCO = 2.25V ± 1V  
IN  
2
f
f
2
0
V = 0.5V OVER THE V  
FOR VCO LINEARITY  
f’ = f + f  
RANGE:  
VCO = 2.25V ± 0.45V  
CC  
0
IN  
f
0
-2  
o
1
2
f
2
1
f’ - f  
o
o
-4  
-6  
-8  
LINEARITY =  
x 100%  
f’  
o
V  
V  
MIN  
MAX  
1/2V  
CC  
1K  
10K  
100K  
R1 (OHMS)  
1M  
10M  
V
VCOIN  
FIGURE 33. DEFINITION OF VCO FREQUENCY LINEARITY  
FIGURE 34. HC4046A VCO LINEARITY vs R1 (V  
= 4.5V)  
CC  
8
8
C1 = 50pF  
C1 = 50pF  
V
= 3V  
V
= 6V  
6
4
CC  
R2 = OPEN  
6
4
CC  
R2 = OPEN  
VCO = 3V ± 1.5V  
IN  
VCO = 1.50V ± 0.4V  
IN  
2
2
0
0
VCO = 1.50V ± 0.3V  
IN  
-2  
-2  
-4  
-6  
-8  
-4  
-6  
-8  
VCO = 3V ± 0.6V  
IN  
1K  
10K  
1K  
10K  
100K  
1M  
10M  
100K  
1M  
10M  
R1 (OHMS)  
R1 (OHMS)  
FIGURE 35. HC4046A VCO LINEARITY vs R1 (V  
= 3V)  
FIGURE 36. HC4046A VCO LINEARITY vs R1 (V  
= 6V)  
CC  
CC  
8
4
10  
V
= 5.5V,  
CC  
VCO = 2.75V ±1.3V  
VCO = 0.5 V  
IN  
= 4.5V,  
IN  
CC  
6
4
V
CC  
VCO = 2.25V ±1.0V  
IN  
3
2
10  
10  
V
= 6V  
CC  
2
0
V
= 3V  
CC  
V
= 4.5V  
-2  
V
= 5.5V,  
CC  
CC  
VCO = 2.75V ±0.55V  
IN  
10  
1
V
= 4.5V,  
-4  
-6  
-8  
CC  
VCO = 2.25V ±0.45V  
IN  
C1 = 50pF  
R2 = OPEN  
1K  
10K  
1K  
10K  
100K  
1M  
10M  
100K  
1M  
R1 (OHMS)  
RS (OHMS)  
FIGURE 37. HCT4046A VCO LINEARITY vs R1 (V  
= 4.5V,  
FIGURE 38. HC4046A DEMODULATOR POWER DISSIPATION  
vs RS (TYP) (V = 3V, 4.5V, 6V)  
CC  
V
= 5.5V)  
CC  
CC  
17  
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
Typical Performance Curves (Continued)  
6
5
4
3
2
10  
10  
10  
10  
10  
4
3
2
VCO = 0.5V  
IN  
10  
10  
10  
CC  
R2 = RS = OPEN  
= 50pF  
VCO = 0.5 V  
IN CC  
R1 = R2 = OPEN  
C
L
V
= 6V  
CC  
C1 = 50pF  
V
= 6V  
CC  
V
= 6V  
V
= 4.5V  
CC  
C1 = 1µF  
CC  
C1 = 50pF  
V
= 3V  
V
= 3V  
CC  
C1 = 1µF  
CC  
V
= 4.5V  
CC  
V
= 3V  
CC  
10  
1
C1 = 50pF  
V
= 4.5V  
CC  
C1 = 1µF  
1K  
10K  
100K  
1M  
1K  
10K  
100K  
1M  
R1 (OHMS)  
RS (OHMS)  
FIGURE 39. HCT4046A DEMODULATOR POWER DISSIPATION  
vs RS (TYP) (V = 3V, 4.5V, 6V)  
FIGURE 40. HC4046A VCO POWER DISSIPATION vs R1  
(C1 = 50pF, 1µF)  
CC  
6
5
4
3
2
6
10  
10  
10  
10  
10  
10  
VCO = 0.5V  
IN  
R2 = RS = OPEN  
VCO = 0V (AT f  
)
IN  
MIN  
V
= 6V  
CC  
C1 = 50pF  
R1 = RS = OPEN  
V
= 5.5V  
CC  
C1 = 50pF  
C
= 50pF  
L
5
4
3
2
10  
10  
10  
10  
V
= 4.5V  
V
= 4.5V  
CC  
C1 = 50pF  
CC  
C1 = 50pF  
V
= 4.5V  
CC  
C1 = 1µF  
V
= 5.5V  
CC  
C1 = 1µF  
V
= 6V  
CC  
C1 = 1µF  
V
= 4.5V  
CC  
C1 = 1µF  
1K  
10K  
1K  
10K  
100K  
1M  
100K  
1M  
R2 (OHMS)  
R1 (OHMS)  
FIGURE 41. HCT4046A VCO POWER DISSIPATION vs R2  
FIGURE 42. HCT4046A VCO POWER DISSIPATION vs R1  
(C1 = 50pF, 1µF)  
(C1 = 50pF, 1µF)  
6
10  
VCO = 0V (AT f  
IN  
R1 = RS = OPEN  
)
MIN  
V
= 6V  
CC  
C1 = 50pF  
C
= 50pF  
L
5
10  
V
= 4.5V  
CC  
C1 = 50pF  
V
= 6V  
CC  
C1 = 1µF  
4
10  
V
= 3V  
CC  
C1 = 1µF  
V
= 3V  
CC  
3
10  
10  
C1 = 50pF  
V
= 4.5V  
CC  
C1 = 1µF  
2
1K  
10K  
100K  
1M  
R2 (OHMS)  
FIGURE 43. HC4046A VCO POWER DISSIPATION vs R2 (C1 = 50pF, 1µF)  
18  
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
HC/HCT4046A C  
PD  
References should be made to Figures 11 through 15 and  
Figures 27 through 32 as indicated in the table.  
CHIP SECTION  
HC  
48  
39  
61  
HCT  
50  
UNIT  
pF  
Values of the selected components should be within the  
following ranges:  
Comparator 1  
Comparators 2 and 3  
VCO  
48  
pF  
53  
pF  
R1  
Between 3kand 300kΩ  
Between 3kand 300kΩ  
Parallel Value > 2.7kΩ  
Greater Than 40pF  
R2  
Application Information  
R1 + R2  
C1  
This information is a guide for the approximation of values of  
external components to be used with the ’HC4046A and  
’HCT4046A in a phase-lock-loop system.  
PHASE  
SUBJECT  
COMPARATOR  
DESIGN CONSIDERATIONS  
VCO Frequency  
PC1, PC2 or PC3 VCO Frequency Characteristic  
Without Extra Offset  
With R2 = and R1 within the range 3k< R1 < 300k, the characteristics of the VCO  
operation will be as shown in Figures 11 - 15. (Due to R1, C1 time constant a small offset  
remains when R2 = .)  
f
MAX  
f
VCO  
f
2f  
o
L
f
MIN  
V
MIN  
1/2 V  
MAX  
VCOIN  
CC  
FIGURE 44. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITHOUT  
OFFSET: f = CENTER FREQUENCY: 2f = FREQUENCY LOCK RANGE  
o
L
PC1  
Selection of R1 and C1  
Given f , determine the values of R1 and C1 using Figures 11 - 15  
o
PC2 or PC3  
Given f  
calculate f as f  
/2 and determine the values of R1 and C1 using Figures 11 -  
- 1.8V)/(R1C1) where valid range of VCO is 1.1V < VCO  
IN  
MAX  
o
MAX  
15. To obtain 2f : 2f 1.2 (V  
L
L
CC  
IN  
< V  
- 0.9V  
CC  
VCO Frequency with PC1, PC2 or PC3 VCO Frequency Characteristic  
Extra Offset  
With R1 and R2 within the ranges 3k< R1 < 300k, 3k, < R2 < 300k, the characteristics  
of the VCO operation will be as shown in Figures 27 - 32.  
f
MAX  
f
VCO  
2f  
f
L
o
f
MIN  
V
MIN  
1/2 V  
MAX  
VCOIN  
CC  
FIGURE 45. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITH OFFSET:  
= CENTER FREQUENCY: 2f = FREQUENCY LOCK RANGE  
f
o
L
PC1, PC2 or PC3 Selection of R1, R2 and C1  
Given f and f , offset frequency, f  
, may be calculated from fMIN f - 1.6 f .  
o
L
MIN  
o
L
Obtain the values of C1 and R2 by using Figures 27 - 30.  
Calculate the values of R1 from Figures 31 - 32.  
19  
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
PHASE  
SUBJECT  
COMPARATOR  
DESIGN CONSIDERATIONS  
o
PLL Conditions with  
No Signal at the  
SIG Input  
IN  
PC1  
PC2  
PC3  
VCO adjusts to f with φDEMOUT = 90 and V  
= 1/2 V  
(see Figure 2)  
o
VCOIN  
CC  
o
VCO adjusts to f  
VCO adjusts to f  
with φDEMOUT = -360 and V  
= 0V (see Figure 4)  
MIN  
VCOIN  
VCOIN  
o
with φDEMOUT = 360 and V  
= V  
(see Figure 6)  
MAX  
CC  
PLL Frequency  
Capture Range  
PC1, PC2 or PC3 Loop Filter Component Selection  
|F  
|
)
(j  
ω
R3  
-1/  
τ
C2  
INPUT  
OUTPUT  
ω
(B) AMPLITUDE CHARACTERISTIC  
(C) POLE-ZERO DIAGRAM  
(A) τ = R3 x C2  
1/2  
A small capture range (2f ) is obtained if τ > 2f 1/π (2πf /τ.)  
c
c
L
FIGURE 46. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET  
R3  
|F  
|
)
(j  
ω
R4  
m =  
R4  
C2  
R3 + R4  
INPUT  
OUTPUT  
-1/  
-1/  
3
2
τ
τ
m
1/  
1/  
2
ω
3
τ
τ
(B) AMPLITUDE CHARACTERISTIC  
(C) POLE-ZERO DIAGRAM  
(A) τ1 = R3 x C2;  
τ2 = R4 x C2;  
τ3 = (R3 + R4) x C2  
FIGURE 47. SIMPLE LOOP FILTER FOR PLL WITH OFFSET  
PLL Locks on  
Harmonics at Center  
Frequency  
PC1 or PC3  
PC2  
Yes  
No  
Noise Rejection at  
Signal Input  
PC1  
High  
Low  
PC2 or PC3  
PC1  
o
AC Ripple Content  
when PLL is Locked  
f = 2f , large ripple content at φDEMOUT = 90  
r i  
o
PC2  
f = f , small ripple content at φDEMOUT = 0  
r i  
o
PC3  
f = fSIG , large ripple content at φDEMOUT = 180  
IN  
r
20  
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
CDIP  
CDIP  
CDIP  
PDIP  
Drawing  
5962-8875701EA  
5962-8960901EA  
CD54HC4046AF  
CD54HC4046AF3A  
CD54HCT4046AF3A  
CD74HC4046AE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
16  
16  
16  
16  
16  
16  
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
J
1
J
1
J
1
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD74HC4046AEE4  
CD74HC4046AM  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SO  
N
D
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC4046AM96  
CD74HC4046AM96E4  
CD74HC4046AME4  
CD74HC4046AMT  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC4046AMTE4  
CD74HC4046ANSR  
CD74HC4046ANSRE4  
CD74HC4046APWR  
CD74HC4046APWRE4  
CD74HC4046APWT  
CD74HC4046APWTE4  
CD74HCT4046AE  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
NS  
NS  
PW  
PW  
PW  
PW  
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD74HCT4046AEE4  
CD74HCT4046AM  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HCT4046AM96  
CD74HCT4046AM96E4  
CD74HCT4046AME4  
CD74HCT4046AMT  
CD74HCT4046AMTE4  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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