CD74HCT138原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

CD74HC138, CD74HCT138,

CD74HC238, CD74HCT238

Data sheet acquired from Harris Semiconductor

SCHS147A

High Speed CMOS Logic 3-to-8 Line Decoder/

Demultiplexer Inverting and Non-Inverting

October 1997 - Revised February 1999

Features

• Select One Of Eight Data Outputs

Active Low for 138, Active High for 238

[ /Title

(CD74

HC138

,

CD74

HCT13

8,

CD74

HC238

,

• l/O Port or Memory Selector

• Three Enable Inputs to Simplify Cascading

• Typical Propagation Delay of 13ns at V

= 5V,

CC

o

C = 15pF, T = 25 C

L

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

CD74

HCT23

8)

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

/Sub-

ject

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

(High

Speed

at V

= 5V

CC

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

l

Pinout

CD74HC138, CD74HCT138, CD74HC238, CD74HCT238

(PDIP, SOIC)

TOP VIEW

A0

A1

1

2

3

4

5

6

7

8

16 V

CC

15 Y0 (Y0)

14 Y1 (Y1)

13 Y2 (Y2)

12 Y3 (Y3)

11 Y4 (Y4)

10 Y5 (Y5)

A2

E1

E2

E3

(Y7) Y7

GND

9

Y6 (Y6)

Signal names in parentheses are for ’HC238 and ’HCT238.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

1

CD74HC138, CD74HCT138, CD74HC238, CD74HCT238

Ordering Information

Description

The Harris CD74HC138, CD74HC238 and CD74HCT138,

CD74HCT238 are high speed silicon gate CMOS decoders

well suited to memory address decoding or data routing

applications. Both circuits feature low power consumption

usually associated with CMOS circuitry, yet have speeds

comparable to low power Schottky TTL logic. Both circuits

have three binary select inputs (A0, A1 and A2). If the device

is enabled, these inputs determine which one of the eight

normally high outputs of the HC/HCT138 series will go low

or which of the normally low outputs of the HC/HCT238

series will go high.

PKG.

NO.

o

PART NUMBER TEMP. RANGE ( C) PACKAGE

CD74HCT138E

CD74HC238E

CD74HCT238E

CD74HC138M

CD74HCT138M

CD74HC238M

CD74HCT238M

CD74HC138SM

NOTES:

-55 to 125

16 Ld PDIP

E16.3

16 Ld SOIC M16.15

16 Ld SSOP M16.209

Two active low and one active high enables (E1, E2, and E3)

are provided to ease the cascading of decoders. The

decoder’s 8 outputs can drive 10 low power Schottky TTL

equivalent loads.

Ordering Information

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

PKG.

NO.

o

PART NUMBER TEMP. RANGE ( C) PACKAGE

2. Wafer and die for this part number is available which meets all

electrical specifications. Please contact your local sales office or

Harris customer service for ordering information.

CD74HC138E

-55 to 125

16 Ld PDIP

E16.3

Functional Diagram

HC/HCT HC/HCT

238

138

1

15

14

13

12

11

10

9

A0

A1

A2

Y0

2

3

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y1

Y2

Y3

Y4

Y5

Y6

Y7

4

5

6

E1

E2

E3

7

TRUTH TABLE CD74HC138, CD74HCT138

INPUTS

ENABLE

ADDRESS

OUTPUTS

Y3 Y4

E3

X

E2

X

H

L

E1

H

X

L

A2

X

L

A1

X

L

A0

X

L

Y0

H

L

Y1

H

L

Y2

H

L

Y5

H

Y6

H

Y7

H

L

H

L

H

X

H

L

H

L

H

L

H

L

H

2

CD74HC138, CD74HCT138, CD74HC238, CD74HCT238

TRUTH TABLE CD74HC138, CD74HCT138

INPUTS

ENABLE

ADDRESS

OUTPUTS

Y3 Y4

E3

H

E2

L

E1

L

A2

H

A1

L

A0

L

Y0

H

Y1

H

Y2

H

Y5

H

L

Y6

H

L

Y7

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

TRUTH TABLE CD74HC238, CD74HCT238

INPUTS

ENABLE

ADDRESS

OUTPUTS

Y3 Y4

E3

X

E2

X

H

L

E1

A2

X

L

A1

X

L

A0

X

L

Y0

L

Y1

L

Y2

L

Y5

L

Y6

L

Y7

L

H

X

L

H

L

H

L

X

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

3

CD74HC138, CD74HCT138, CD74HC238, CD74HCT238

Absolute Maximum Ratings

Thermal Information

o

DC Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)

θ

( C/W)

CC

DC Input Diode Current, I

JA

IK

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

90

For V < -0.5V or V > V

+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

OK

For V < -0.5V or V > V

I

CC

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

115

155

DC Output Diode Current, I

o

+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

O

CC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C

Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C

o

DC Output Source or Sink Current per Output Pin, I

O

o

For V > -0.5V or V < V

+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

O

CC

DC V

or Ground Current, I

I

. . . . . . . . . . . . . . . . . .±50mA

CC

CC or GND

(SOIC - Lead Tips Only)

Operating Conditions

o

Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C

A

Supply Voltage Range, V

CC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V

I

O

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. θ is measured with the component mounted on an evaluation PC board in free air.

JA

DC Electrical Speciﬁcations

TEST

CONDITIONS

o

25 C

TYP

-40 C TO 85 C -55 C TO 125 C

V

(V)

CC

PARAMETER

HC TYPES

SYMBOL

V (V)

I

(mA)

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

O

High Level Input

Voltage

V

-

2

4.5

6

1.5

-

1.5

-

1.5

-

V

µA

IH

3.15

-

3.15

-

3.15

4.2

-

Low Level Input

Voltage

V

-

2

-

0.5

1.35

1.8

-

0.5

1.35

1.8

-

0.5

1.35

1.8

-

IL

4.5

6

-

High Level Output

Voltage

CMOS Loads

V

or V

IH IL

-0.02

2

1.9

OH

-0.02

-

4.5

6

4.4

-

4.4

-

4.4

-

5.9

-

5.9

-

5.9

-

High Level Output

Voltage

TTL Loads

-

-4

4.5

6

3.98

-

3.84

-

3.7

-

-5.2

0.02

-

5.48

-

5.34

-

5.2

-

Low Level Output

Voltage

CMOS Loads

V

or V

IH IL

2

-

0.1

-

0.1

-

0.1

-

OL

4.5

6

Low Level Output

Voltage

TTL Loads

-

4

4.5

6

0.26

±0.1

0.33

±1

0.4

±1

5.2

-

Input Leakage

Current

I

V

or

6

I

CC

GND

Quiescent Device

Current

I

V

GND

or

0

6

-

8

-

80

-

160

µA

CC

4

CD74HC138, CD74HCT138, CD74HC238, CD74HCT238

DC Electrical Speciﬁcations (Continued)

TEST

CONDITIONS

o

25 C

-40 C TO 85 C -55 C TO 125 C

V

CC

PARAMETER

HCT TYPES

SYMBOL

V (V)

I

(mA)

(V)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNITS

O

High Level Input

Voltage

V

-

4.5 to

5.5

2

-

0.8

-

2

-

0.8

-

2

-

0.8

-

V

IH

Low Level Input

Voltage

V

4.5 to

5.5

IL

High Level Output

Voltage

CMOS Loads

V

or V

-0.02

4.5

4.4

OH

IH

IL

High Level Output

Voltage

TTL Loads

-4

3.98

-

3.84

-

3.7

-

V

Low Level Output

Voltage

CMOS Loads

V

or V

0.02

4

-

0.1

0.26

-

0.1

0.33

-

0.1

0.4

OL

IL

Low Level Output

Voltage

TTL Loads

Input Leakage

Current

I

V

and

0

-

5.5

-

±0.1

8

-

±1

80

-

±1

µA

I

CC

GND

Quiescent Device

Current

I

V

or

-

160

490

CC

GND

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

(Note 4)

∆I

V

4.5 to

5.5

100

360

450

CC

-2.1

NOTE:

4. For dual-supply systems theoretical worst case (V = 2.4V, V

I

= 5.5V) specification is 1.8mA.

CC

HCT Input Loading Table

INPUT

UNIT LOADS

A0-A2

E1, E2

1.5

1.25

1

E3

NOTE: Unit Load is ∆I

360µA max at 25 C.

limit speciﬁed in DC Electrical Table, e.g.,

CC

o

Switching Speciﬁcations Input t , t = 6ns

r

f

o

-40 C TO

85 C

o

25 C

-55 C TO 125 C

TEST

SYMBOL CONDITIONS

PARAMETER

HC TYPES

V

(V) MIN

TYP MAX

MIN

MAX

MIN

MAX UNITS

CC

Propagation Delay

Address to Output

t

C = 50pF

2

-

150

30

-

190

38

-

225

45

-

ns

PLH, PHL

L

4.5

5

-

C = 15pF

13

-

L

C = 50pF

6

26

33

38

L

5

Switching Speciﬁcations Input t , t = 6ns (Continued)

r

f

o

-40 C TO

85 C

o

25 C

-55 C TO 125 C

TEST

SYMBOL CONDITIONS

PARAMETER

V

(V) MIN

TYP MAX

MIN

MAX

MIN

MAX UNITS

CC

Enable to Output

HC/HCT138

t

C = 50pF

2

-

150

30

26

75

15

13

-

190

38

33

95

19

16

-

265

53

45

110

22

19

-

ns

pF

PLH, PHL

L

4.5

6

-

Output Transition Time

(Figure 1)

t

, t

TLH THL

C = 50pF

2

-

L

4.5

6

-

Power Dissipation

C

C = 15pF

L

5

67

PD

Capacitance, (Notes 5, 6)

Input Capacitance

C

-

10

-

10

-

10

pF

IN

HCT TYPES

Propagation Delay

Address to Output

t

, t

PLH PHL

C = 50pF

4.5

5

-

14

-

35

-

44

-

53

-

ns

L

C = 15pF

L

Enable to Output

HC/HCT138

t , t

PLH PHL

C = 50pF

4.5

35

44

53

L

Enable to Output

HC/HCT238

t

C = 15pF

4.5

5

-

40

15

-

50

19

-

60

22

-

ns

pF

PLH, PHL

L

Output Transition Time

(Figure 2)

t

, t C = 50pF

TLH THL L

Power Dissipation

Capacitance, (Notes 5, 6)

C

C = 15pF

L

67

-

PD

Input Capacitance

NOTES:

C

-

10

IN

5. C

PD

is used to determine the dynamic power consumption, per gate.

2

6. P = V

CC

f (C

PD

+ C ) where: f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.

CC

D

i

L

i

L

Test Circuits and Waveforms

t = 6ns

f

r

t = 6ns

f

t = 6ns

r

V

CC

3V

90%

50%

10%

2.7V

1.3V

0.3V

INPUT

GND

t

TLH

THL

t

THL

TLH

90%

1.3V

90%

50%

10%

INVERTING

OUTPUT

INVERTING

OUTPUT

10%

t

PLH

PHL

FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

型号:	CD74HCT138E
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	THOMSON CONSUMER ELECTRONICS
Reach Compliance Code：	unknown
风险等级：	5.81
Is Samacsys：	N
JESD-30 代码：	R-PDIP-T16
负载电容（CL）：	50 pF
逻辑集成电路类型：	OTHER DECODER/DRIVER
最大I（ol）：	0.004 A
功能数量：	1
端子数量：	16
最高工作温度：	125 °C
最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
电源：	5 V
Prop。Delay @ Nom-Sup：	53 ns
认证状态：	Not Qualified
子类别：	Decoder/Drivers
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	MILITARY
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
Base Number Matches：	1

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