CDC2509BPWR应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

当前位置：IC37首页_>C字母起始型号索引_>C字母起始型号索引第670页更新时间：2024-10-25 17:37:24

产品型号CDC2509BPWR的概述

CDC2509BPWR概述 CDC2509BPWR是一款由Texas Instruments（德州仪器）生产的高性能时钟驱动器，专门设计用于提供高质量时钟信号，并能有效降低时钟信号的抖动。这款芯片通常用于各种电子设备中，如数据通信、网络设备、数字信号处理等领域，帮助实现精确的时序控制和信号同步。详细参数 CDC2509BPWR的主要技术参数包括： - 工作电压范围：3.0V至5.5V - 工作温度范围：-40°C至85°C - 输入频率范围：1MHz至200MHz - 输出频率：依据输入频率进行分频，提供稳定输出 - 输出驱动能力：具有低输出抖动，能够驱动多达10个负载 - 输出信号类型：兼容TTL和差分信号输出 - 功耗：典型功耗小于100mW - 封装类型：TQFP-32 CDC2509BPWR的特性表明，它是一款非常适合高精度应用的时钟驱动器。其性能良好，且适用于各种严苛环境，...

产品型号CDC2509BPWR的Datasheet PDF文件预览

ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢆ

ꢇ ꢈꢇ ꢉꢊ ꢋꢌꢍ ꢎꢏꢉꢐ ꢑ ꢀꢒ ꢐ ꢑꢑ ꢋ ꢀꢐ ꢑ ꢀꢒ ꢁ ꢓꢔ ꢊ ꢏꢓ

ꢕ

SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004

PW PACKAGE

(TOP VIEW)

Use CDCVF2509A as a Replacement for

this Device

Designed to Meet PC SDRAM Registered

DIMM Specification

AGND

CLK

Spread Spectrum Clock Compatible

1Y0

1Y1

1Y2

GND

1Y3

Operating Frequency 25 MHz to 125 MHz

2Y0

2Y1

GND

2Y2

2Y3

Phase Error Time Minus Jitter at 66 MHz to

100 MHz Is 150 ps

Jitter (peak − peak) at 66 MHz to 100 MHz Is

80 ps

1Y4

Jitter (cycle − cycle) at 66 MHz to 100 MHz

Is |100 ps|

FBOUT

FBIN

Available in Plastic 24-Pin TSSOP

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

Distributes One Clock Input to One Bank of

Five and One Bank of Four Outputs

Separate Output Enable for Each Output

Bank

External Feedback (FBIN) Terminal Is Used

to Synchronize the Outputs to the Clock

Input

On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3 V

description

The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock drivers. They use a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

They are specifically designed for use with synchronous DRAMs. The CDC2509B operates at 3.3-V V . They

also provide integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output

signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled

or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in

phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2509B does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2509B requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback

signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ꢋ

ꢓ

ꢑ

ꢨ

ꢁ

ꢣ

ꢖ

ꢀ

ꢡ

ꢗ

ꢢ

ꢔ

ꢜ

ꢑ

ꢚ

ꢘ

ꢛ

ꢁ

ꢍ

ꢗ

ꢍ

ꢙ

ꢚ

ꢤ

ꢛ

ꢜ

ꢢ

ꢝ

ꢞ

ꢟ

ꢠ

ꢙ

ꢜ

ꢚ

ꢙ

ꢡ

ꢥ

ꢢ

ꢣ

ꢝ

ꢤ

ꢚ

ꢠ

ꢟ

ꢞ

ꢡ

ꢜ

ꢛ

ꢥ

ꢗꢤ

ꢣ

ꢦ

ꢡ

ꢧ

ꢙ

ꢢ

ꢟ

ꢡ

ꢠ

ꢙ

ꢠ

ꢜ

ꢝ

ꢚ

ꢣ

ꢨ

ꢟ

ꢚ

ꢠ

ꢤ

ꢡ

ꢈ

ꢝ

ꢜ

ꢢ

ꢠ

ꢜ

ꢝ

ꢞ

ꢠ

ꢜ

ꢡ

ꢥ

ꢙ

ꢛ

ꢙ

ꢢ

ꢤ

ꢝ

ꢠ

ꢩ

ꢠ

ꢤ

ꢝ

ꢜ

ꢛ

ꢪ

ꢟ

ꢔ

ꢚ

ꢞ

ꢤ

ꢡ

ꢠ

ꢟ

ꢚ

ꢨ

ꢟ

ꢝ

ꢨ

ꢫ

ꢟ

ꢠ ꢤ ꢡ ꢠꢙ ꢚꢭ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢈ

ꢝ

ꢟ

ꢚ

ꢠ

ꢬ

ꢈ

ꢋ

ꢝ

ꢜ

ꢨ

ꢣ

ꢢ

ꢠ

ꢙ

ꢜ

ꢚ

ꢥ

ꢝ

ꢜ

ꢢ

ꢤ

ꢡ

ꢙ

ꢚ

ꢭ

ꢨ

ꢜ

ꢤ

ꢡ

ꢚ

ꢜ

ꢠ

ꢚ

ꢤ

ꢢ

ꢤ

ꢡ

ꢟ

ꢝ

ꢙ

ꢧ

ꢬ

ꢙ

ꢚ

ꢢ

ꢧ

ꢣ

ꢨ

ꢤ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢅ ꢆ

ꢇꢈ ꢇꢉꢊ ꢋꢌ ꢍ ꢎꢏꢉꢐ ꢑꢀ ꢒ ꢐꢑ ꢑ ꢋ ꢀꢐ ꢑꢀ ꢒ ꢁꢓ ꢔ ꢊ ꢏꢓ

ꢕ

SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004

description (continued)

The CDC2509B is characterized for operation from 0°C to 70°C.

For application information refer to application reports High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread

Spectrum Clocking (SSC) (literature number SCAA039).

FUNCTION TABLE

INPUTS

OUTPUTS

(0:4)

CLK

FBOUT

(0:3)

functional block diagram

1Y0

1Y1

1Y2

1Y3

1Y4

2Y0

2Y1

2Y2

CLK

PLL

2Y3

FBIN

FBOUT

AVAILABLE OPTIONS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢆ

ꢇ ꢈꢇ ꢉꢊ ꢋꢌ ꢍꢎꢏꢉꢐ ꢑ ꢀꢒ ꢐ ꢑꢑ ꢋ ꢀꢐ ꢑ ꢀꢒ ꢁ ꢓꢔ ꢊ ꢏꢓ

ꢕ

SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004

PACKAGE

SMALL OUTLINE

(PW)

0°C to 70°C

CDC2509BPWR

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Clock input. CLK provides the clock signal to be distributed by the CDC2509B and the CDC2510B clock

drivers. CLK is used to provide the reference signal to the integrated PLL that generates the clock output

signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the

circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to

phase lock the feedback signal to its reference signal.

CLK

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to

FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally

zero phase error between CLK and FBIN.

FBIN

Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are

disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same

frequency as CLK.

Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are

disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same

frequency as CLK.

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK.

When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an

integrated 25-Ω series-damping resistor.

FBOUT

1Y (0:4)

2Y (0:3)

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the

1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each

output has an integrated 25-Ω series-damping resistor.

3, 4, 5, 8, 9

16, 17, 20, 21

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the

2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each

output has an integrated 25-Ω series-damping resistor.

Analog power supply. AV

provides the power reference for the analog circuitry. In addition, AV

can

is strapped to ground, PLL is bypassed and

Power be used to bypass the PLL for test purposes. When AV

CLK is buffered directly to the device outputs.

AGND

Ground Analog ground. AGND provides the ground reference for the analog circuitry.

GND

2, 10, 15, 22

6, 7, 18, 19

Power Power supply

Ground Ground

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢅ ꢆ

ꢇꢈ ꢇꢉꢊ ꢋꢌ ꢍ ꢎꢏꢉꢐ ꢑꢀ ꢒ ꢐꢑ ꢑ ꢋ ꢀꢐ ꢑꢀ ꢒ ꢁꢓ ꢔ ꢊ ꢏꢓ

ꢕ

SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range: AV

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

< V

+0.7 V

Input voltage range, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

Voltage range applied to any output in the high or low state,

(see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Output clamp current, I

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Continuous current through each V

(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

O O CC

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Maximum power dissipation at T = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W

stg

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. AV

must not exceed V .

2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. This value is limited to 4.6 V maximum.

4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data

Book, literature number SCBD002.

recommended operating conditions (see Note 5)

MIN

MAX

UNIT

Supply voltage, V , AV

CC CC

3.6

High-level input voltage, V

Low-level input voltage, V

0.8

Input voltage, V

High-level output current, I

−12

°C

Low-level output current, I

Operating free-air temperature, T

NOTE 5: Unused inputs must be held high or low to prevent them from floating.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢆ

ꢇ ꢈꢇ ꢉꢊ ꢋꢌ ꢍꢎꢏꢉꢐ ꢑ ꢀꢒ ꢐ ꢑꢑ ꢋ ꢀꢐ ꢑ ꢀꢒ ꢁ ꢓꢔ ꢊ ꢏꢓ

ꢕ

SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

TYP

PARAMETER

TEST CONDITIONS

, AV

MIN

MAX

UNIT

I = −18 mA

3 V

−1.2

= −100 µA

= −12 mA

= −6 mA

= 100 µA

= 12 mA

= 6 mA

MIN to MAX

3 V

−0.2

2.1

2.4

3 V

MIN to MAX

3 V

0.2

0.8

0.55

3 V

V = V

or GND

or GND,

3.6 V

µA

‡

V = V

I = 0, Outputs: low or high

3.6 V

∆I

One input at V

− 0.6 V,

Other inputs at V

or GND

3.3 V to 3.6 V

3.3 V

500

V = V

or GND

= V

O CC

3.3 V

†

‡

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

For I of AV , and I vs Frequency (see Figures 7 and 8).

CC CC CC

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

125

60%

UNIT

Clock frequency

MHz

clk

Input clock duty cycle

40%

Stabilization time

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a

fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,

and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under

SSC application.

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C = 30 pF (see Note 6 and Figures 1 and 2)

, AV

= 3.3 V

0.165 V

, AV = 3.3 V

FROM

(INPUT)/CONDITION

(OUTPUT)

0.3 V

PARAMETER

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

t , − jitter

phase error

(see Notes 7 and 8,

Figures 3, 4, and 5)

CLKIN↑ = 66 MHz to100 MHz

FBIN↑

−150

150

−200

200

Any Y or FBOUT

200

sk(o)

Jitter

(see Figure 6)

(pk-pk)

−80

CLKIN = 66 MHz to 100 MHz

F(CLKIN > 60 MHz)

Jitter

(cycle-cycle)

(see Figure 6)

Any Y or FBOUT

|100|

Duty cycle

Any Y or FBOUT

45%

0.8

55%

2.1

1.3

1.7

1.9

2.5

1.2

2.7

These parameters are not production tested.

The t

specification is only valid for equal loading of all outputs.

sk(o)

NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

7. This is considered as static phase error.

8. Phase error does not include jitter. The total phase error is −230 ps to 230 ps for the 5% V

range.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢅ ꢆ

ꢇꢈ ꢇꢉꢊ ꢋꢌ ꢍ ꢎꢏꢉꢐ ꢑꢀ ꢒ ꢐꢑ ꢑ ꢋ ꢀꢐ ꢑꢀ ꢒ ꢁꢓ ꢔ ꢊ ꢏꢓ

ꢕ

SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004

PARAMETER MEASUREMENT INFORMATION

3 V

0 V

Input

50% V

From Output

Under Test

2 V

0.4 V

2 V

Output

500 W

50% V

0.4 V

30 pF

LOAD CIRCUIT FOR OUTPUTS

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

NOTES: A.

includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, Z = 50 Ω, t ≤ 1.2 ns, t ≤ 1.2 ns.

C. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

CLKIN

FBIN

phase error

FBOUT

Any Y

sk(o)

Any Y

sk(o)

Figure 2. Phase Error and Skew Calculations

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢆ

ꢇ ꢈꢇ ꢉꢊ ꢋꢌ ꢍꢎꢏꢉꢐ ꢑ ꢀꢒ ꢐ ꢑꢑ ꢋ ꢀꢐ ꢑ ꢀꢒ ꢁ ꢓꢔ ꢊ ꢏꢓ

ꢕ

SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS

PHASE ADJUSTMENT SLOPE AND PHASE ERROR

LUMPED FEEDBACK CAPACITANCE AT FBIN

250

= 3.3 V

= 100 MHz

200

150

100

= 30 pF

= 25°C

Phase Error

Phase Error Measured

from CLK to Y

−10

−20

−30

−50

−100

−150

Phase Adjustment Slope

−40

−50

−200

−250

45 50

10 15 20 25 30 35 40

CLF − Lumped Feedback Capacitance at FBIN − pF

Figure 3

PHASE ERROR

CLOCK FREQUENCY

400

= 3.3 V

CLY = CLF = 30 pF

= 25°C

300

200

Phase Error Measured

from CLK to FBIN

100

−100

35 45

85 95 105 115 125

− Clock Frequency − MHz

Figure 4

NOTES: A. CLY = Lumped capacitive load at Y

B. CLF = Lumped feedback capacitance at FBIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢅ ꢆ

ꢇꢈ ꢇꢉꢊ ꢋꢌ ꢍ ꢎꢏꢉꢐ ꢑꢀ ꢒ ꢐꢑ ꢑ ꢋ ꢀꢐ ꢑꢀ ꢒ ꢁꢓ ꢔ ꢊ ꢏꢓ

ꢕ

SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS

PHASE ERROR

JITTER

CLOCK FREQUENCY

SUPPLY VOLTAGE

400

350

300

250

400

350

300

= 100 MHz

= 3.3 V

= 25°C

CLY = CLF = 30 pF

Phase Error Measured

from CLK to FBIN

= 25°C

250

200

150

200

150

100

Peak to Peak

100

−50

Cycle to Cycle

−100

35 45

65 75

85 95 105 115 125

2.9

3.0

3.1 3.2

3.3

3.4

3.5

3.6 3.7

− Clock Frequency − MHz

− Supply Voltage − V

Figure 5

Figure 6

SUPPLY CURRENT

ANALOG SUPPLY CURRENT

CLOCK FREQUENCY

250

= 3.6 V

= 25°C

= 3.6 V

CLY = CLF = 30 pF

Bias = 0/3 V

CLY = CLF = 30 pF

200

150

100

= 25°C

100

120

140

100

120

140

− Clock Frequency − MHz

clk

− Clock Frequency − MHz

Figure 7

Figure 8

NOTES: A. CLY = Lumped capacitive load at Y

B. CLF = Lumped feedback capacitance at FBIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

3-Jul-2009

PACKAGING INFORMATION

Orderable Device

CDC2509BPW

Status ⁽¹⁾

NRND

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CDC2509BPWG4

CDC2509BPWR

CDC2509BPWRG4

TSSOP

60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDC2509BPWR

TSSOP

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 24

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

CDC2509BPWR

2000

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Medical

Logic

Security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CDC2509BPWR相关文章

配单直通车

柒号芯城电子商务（深圳）有限公司服务专线: 0755-83209937 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

CDC2509BPWR产品参数

型号:	CDC2509BPWR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Not Recommended
零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP24,.25
针数：	24
Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01
风险等级：	5.72
系列：	2509
输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e4
长度：	7.8 mm
负载电容（CL）：	30 pF
逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.012 A
湿度敏感等级：	1
功能数量：	1
反相输出次数：
端子数量：	24
实输出次数：	9
最高工作温度：	70 °C
最低工作温度：
输出特性：	SERIES-RESISTOR
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP24,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：	TR
峰值回流温度（摄氏度）：	260
电源：	3.3 V
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.2 ns
座面最大高度：	1.2 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	BICMOS
温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
最小 fmax：	125 MHz
Base Number Matches：	1

电子百科

产品导航

产品型号CDC2509BPWR的概述

产品型号CDC2509BPWR的Datasheet PDF文件预览

CDC2509BPWR相关产品

CDC2509BPWR相关文章

IC37:专业IC行业平台