CDC3S04YFFR应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

当前位置：IC37首页_>C字母起始型号索引_>C字母起始型号索引第670页更新时间：2024-10-25 17:21:16

产品型号CDC3S04YFFR的概述

芯片 CDC3S04YFFR 概述 CDC3S04YFFR 是一款集成电路，广泛应用于数字电路系统的设计中。此芯片属于一类通用的逻辑器件，具体功能为数据转换、信号调节以及时钟管理等。它的设计使其能够在多种应用场景中表现出色，例如通信设备、自动化控制系统以及消费电子产品等。芯片 CDC3S04YFFR 的详细参数 CDC3S04YFFR 的主要技术参数包括： - 工作电压：通常在 2.7V 至 5.5V 区间内，适应性强。 - 工作温度范围：芯片的工作温度范围通常为 -40℃ 至 +85℃，适合工业级别的应用需求。 - 封装类型：CDC3S04YFFR 通常采用 TSSOP 封装，外形尺寸小，有利于空间受限的设计。 - 引脚数量：该芯片通常有 16 个引脚，其中包括电源引脚、地引脚以及输入输出引脚。 - 最大输出电流：在满载条件下，输出电流可达 ±20mA。 - 转速：具有高达 50M...

产品型号CDC3S04YFFR的Datasheet PDF文件预览

CDC3S04

www.ti.com

SCAS883B –OCTOBER 2009–REVISED MAY 2011

Quad Sine-Wave Clock Buffer With LDO

Check for Samples: CDC3S04

FEATURES

DESCRIPTION

The CDC3S04 is a four-channel low-power low-jitter

sine-wave clock buffer. It can be used to buffer a

single master clock to multiple peripherals. The four

sine-wave outputs (CLK1–CLK4) are designed for

minimal channel-to-channel skew and ultralow

additive output jitter.

•

1:4 Low-Jitter Clock Buffer

Single-Ended Sine-Wave Clock Input and

Outputs

•

Ultralow Phase Noise and Standby Current

Individual Clock Request Inputs for Each

Output

Each output has its own clock request inputs which

enables the dedicated clock output. These clock

requests are active-high (can also be changed to be

active-low via I²C), and an output signal is generated

that can be sent back to the master clock to request

the clock (MCLK_REQ). MCKL_REQ is an

open-source output and supports the wired-OR

function (default mode). It needs an external pulldown

resistor. MCKL_REQ can be changed to wired-AND

or push-pull functionality via I²C.

The CDC3S04 also provides an I²C interface

(Hs-mode) that can be used to enable or disable the

outputs, select the polarity of the REQ inputs, and

allow control of internal decoding.

•

On-Chip Low-Dropout Output (LDO) for

Low-Noise TCXO Supply

Serial I²C Interface (Compatible With

High-Speed Mode, 3.4 Mbit/s)

•

1.8-V Device Power Supply

Wide Temperature Range, –30°C to 85°C

ESD Protection: 2 KV HBM, 750 V CDM, and

100 V MM

•

Small 20-Pin Chip-Scale Package: 0.4-mm

Pitch WCSP (1.6 mm × 2 mm)

APPLICATIONS

The CDC3S04 features an on-chip high-performance

LDO that accepts voltages from 2.3 V to 5.5 V and

outputs a 1.8-V supply. This 1.8-V supply can be

used to power an external 1.8-V TCXO. It can be

enabled or disabled for power saving at the TCXO.

•

Cellular Phones

Smart Phones

Mobile Handsets

Portable Systems

Wireless Modems Including GPS, WLAN,

W-BT, D-TV, DVB-H, FM Radio, WiMAX, and

System Clock

VDD_DIG

VDD_ANA

WCSP

LDO

VBAT

VLDO

REQ2

REQ1

CLK2

CLK1

REQ1

CLK1

Reset

RESET

MCLK_

VDD_ GND_

ANA

RESET

REQ2

CLK2

MCLK_IN

REQ4 CLK4 REQ3 CLK3

REQ3

CLK3

VDD_ GND_ MCLK_ ADR_

REQ

MCLK_REQ

DIG

REQ4

CLK4

VLDO VBAT SDAH SCLH

I²C

SCLH

SDAH

Control

Top View

(Solder Ball Underneath)

ADR_A0

Decoder

GND_DIG

GND_ANA

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

A low signal at the RESET input switches the outputs CLK1 and CLK4 into the default state. In this configuration,

CLK1 and CLK4 are ON (see Table 1); the remaining device function is not affected. Also, the RESET input

provides a glitch filter which rejects spikes of typical 300 ns on the RESET line to preserve false reset. A

complete device reset to the default condition can be initiated by a power-up cycle of V_{DD_DIG}

The CDC3S04 operates from two 1.8-V supplies. There is a core supply (VDD_DIG/GND_DIG) for the core logic

and a low-noise analog supply (VDD_ANA/GND_ANA) for the sine-wave outputs. The CDC3S04 is designed for

sequence-less power up. Both supply voltages may be applied in any order.

The CDC3S04 is offered in a 0.4-mm pitch WCSP package (1.6 mm × 2 mm) and is optimized for low standby

current (0.5 µA). It is characterized for operation from –30°C to 85°C.

DEVICE INFORMATION

PIN FUNCTIONS

NAME

ADR_A0

CLK1

BALL NO.

TYPE

Input

FUNCTION

Selectable address bit A0 of slave-address register; internal 500-kΩ pulldown resistor

Output

Ground

Input

Clock output 1

CLK2

Clock output 2

CLK3

Clock output 3

CLK4

Clock output 4

GND_ANA

GND_DIG

MCLK_IN

Ground for sine-wave buffer

Ground for core logic

Master clock input

MCLK_RE

Clock request to the master clock source; active-high; open-source output for wired-OR

connection (default condition). Can be changed to push-pull output or wired-AND output via I²C.

Output

REQ1

REQ2

REQ3

REQ4

Input

Clock request from peripheral 1; internal 500-kΩ pulldown resistor

Clock request from peripheral 2; internal 500-kΩ pulldown resistor

Clock request from peripheral 3; internal 500-kΩ pulldown resistor

Clock request from peripheral 4; internal 500-kΩ pulldown resistor

Peripheral reset signal provided by application processor. The signal is active-low and switches

CLK1 and CLK4 outputs to ON (see Table 1). On-chip LDO is enabled. Internal 1-MΩ pullup

resistor and 300-ns (typ) glitch filter.

I²C clock input – Hs-mode. Internal 1-MΩ pullup resistor

RESET

Input

SCLH

SDAH

Input/output I²C data input/output – Hs-mode. Internal 1-MΩ pullup resistor

VBAT

Power

Supply pin to internal LDO

VDD_ANA

1.8-V power supply for sine-wave buffer

1.8-V power supply for core logic. Power up of VDD_DIG resets the whole device to the default

condition.

VDD_DIG

VLDO

Power

Output

1.8-V supply for external TCXO; LDO is enabled if RESET (default mode) or REQx is active.

LDO is not enabled if only VBAT is on.

CDC3S04

www.ti.com

SCAS883B –OCTOBER 2009–REVISED MAY 2011

FUNCTION SELECTION TABLES

Table 1. Reset and Request (REQx) Conditions for Clock Outputs⁽¹⁾

RESET⁽²⁾

PRIORITY BIT⁽³⁾

CLK1

CLK2

CLK3

CLK4

Controlled by REQ2

Controlled by REQ2INT

Controlled by REQ2

Controlled by REQ2INT

Controlled by REQ3

Controlled by REQ3INT

Controlled by REQ3

Controlled by REQ3INT

Controlled by REQ1

Controlled by REQ4

Controlled by REQ1INT

Controlled by REQ4INT

(1) Shaded cells show the default setting after power up.

(2) RESET resets REQ1PRIO/REQ4PRIO and REQ1INT/REQ4INT bits to their default values (CLK1/4 is ON) but does not change the

remaining internal SW bits. During RESET, any I²C operation is blocked until RESET is deactivated. A minimum pulse duration of

500 ns must be applied to activate RESET (the internal glitch-filter suppresses spikes of typical 300 ns).

(3) Priority bit defines if the external control pins (HW controlled) or the SW bits (SW controlled) have priority. It can be set in the

configuration register, Byte 2, Bits 0–3.

Table 2. Request Signal Condition for Clock Outputs⁽¹⁾

REQx

(REQ1/2/3/4)

CLKx

(CLK1/2/3/4)

REQ-Signals⁽²⁾

MCLK_REQ

LDO⁽³⁾

Active-low

Clock

High

Disabled to high

Disabled to high⁽⁴⁾

Clock⁽⁴⁾

Low (if all REQx are high) Off (if all REQx are high)

Low (if all REQx are low)

High

Off (if all REQx are low)

Active-high

(1) Shaded cells show the default setting after power up.

(2) Polarity of REQ1, REQ2, REQ3, and REQ4 are register-configurable via I²C (see Table 3, Byte 0, Bits 0–3). Default setting is

active-high.

(3) The LDO is controlled by an on-chip decoder, but can also be SW controlled (see Table 3, Byte 2, Bits 4–5).

(4) CLK1 and CLK4 are ON after device power up (default condition). CLK2 and CLK3 are controlled by external REQ2 and REQ3,

respectively.

POWER GROUPS

NAME

VBAT

DESCRIPTION

Supply pin for LDO provided by main battery. LDO is not working if only VBAT is on.

1.8-V low-drop output voltage for external TCXO. LDO is enabled if VBAT and VDD_DIG are on and REQx or RESET is

active (see Table 2).

VLDO

1.8-V power supply for core logic and I²C logic. VDD_DIG must be supplied for correct device operation. Power up of

VDD_DIG resets the whole device to the default condition.

VDD_DIG

1.8-V power supply for sine-wave buffers. For correct sine-wave buffer function, all three power supplies (VBAT, V_{DD_DIG}

and V_{DD_ANA}) must be on. But, V_{DD_ANA}can be switched on and off at any time. If off, the sine-wave outputs are switched

to high-impedance.

VDD_ANA

POWER-UP SEQUENCE

The CDC3S04 is designed for sequence-less power up. VBAT, V_{DD_DIG}, and V_{DD_ANA}may be applied in any

order. Recommended power-on sequence is VBAT first, followed by V_{DD_DIG}and V_{DD_ANA}. Recommended

power-off sequence is in reverse order.

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

UNIT

V_{DD_ANA}

Supply voltage range

V_{DD_DIG}

–0.5 to 2.5

V_BAT

V_I

Battery supply voltage range

Input voltage range^{(2) (3)}

Output voltage range^{(2) (3)}

Output voltage range

–0.5 to 6.5

–0.5 to V_DD+ 0.5

–0.5 to V_BAT+ 0.5

±20

V_O

V_LDO

Input current (V_i< 0, V_i> V_DD

Continuous output current

Storage temperature range

)

°C

I_O

±20

I_LDO

T_stg

±20

–65 to 150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) The input V_Iand output V_Opositive voltages are limited to the absolute maximum rating for V_DD= 2.5 V.

THERMAL CHARACTERISTICS for 20-pin WCSP (YFF)⁽¹⁾

AIRFLOW

(lfm)

20-PIN

WCSP

PARAMETER

UNIT

200

400

–

T_JA

Thermal resistance, junction-to-ambient

°C/W

T_JC

T_JB

T_J

Thermal resistance, junction-to- case

Thermal resistance, junction-to-board

Maximum junction temperature

17.5

20.5

125

°C/W

°C

–

(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

RECOMMENDED OPERATING CONDITIONS

MIN

1.65

NOM

1.8

MAX

UNIT

V_{DD_ANA}

V_{DD_DIG}

V_IH

Device supply voltage

1.95

1.65

1.8

0.65 V_{DD_DIG}

Input voltage ADR_A0, REQx, RESET

V_IL

0.35 V_{DD_DIG}

V_IS

Sine-wave input voltage – MCLK_IN; ac-coupled amplitude

Sine-wave output load⁽¹⁾

0.5

1.2

V_PP

µF

°C

C_L

C_OUT

T_A

LDO output capacitance (stabilize the internal control loop)

Operating free-air temperature

0.8

2.2

–30

(1) 10 pF is the typical load-driving capability. The drive capability can be optimized for 30 pF by the I²C register (Byte 3, Bits 7–4).

CDC3S04

www.ti.com

SCAS883B –OCTOBER 2009–REVISED MAY 2011

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OVERALL PARAMETER

V_BAT= 5.5 V;

V_{DD_ANA}= 1.95 V;

LDO is on; V_IS= 1 V_PP

Off (no REQ)

0.1

0.2

2.6

Analog supply current⁽¹⁾

(seeFigure 8 through Figure 12)

I_{DD_ANA}

;

Per output

f_{MCLK_IN}= 38.4 MHz;

R_L= 10 kΩ; C_L= 10 pF⁽²⁾

V_BAT= 5.5 V; V_{DD_DIG}= 1.95 V; V_{DD_ANA}

= off;

Digital supply current

(see Figure 8 through

Figure 12)

I_{DD_DIG}

0.1

LDO = off; V_IS= 1 Vpp; f_{MCLK_IN}= 38.4

MHz;

C_L= 10 pF; R_L= 10 kΩ

V_BAT= 5.5 V; V_{DD_DIG}/V_{DD_ANA}= 1.95 V;

All outputs disabled (no input clock; LDO

off; no REQ; RESET is inactive; I²C is in

idle mode); includes 1-MΩ pullup at I²C

and RESET

I_SB

Standby current

Input frequency

0.5

µA

f_{MCLK_IN}

Sine wave

0.01

38.4

MHz

Wired-OR output;

I_OH= –2 mA; V_{DD_DIG}= 1.65 V (See

Figure 3.)

_{DD_DIG}– 0.45

MCLK_REQ high-level output

voltage

V_OH

Push-pull output; V_{DD_DIG}= 1.65 V,

I_OH= –2 mA

V_{DD_DIG}– 0.45

Wired-AND output; I_OL= 2 mA

V_{DD_DIG}= 1.65 V

0.45

MCLK_REQ low-level output

voltage

V_OL

V_IK

I_IH

Push-pull output; V_{DD_DIG}= 1.65 V,

I_OL= 2 mA

0.45

–1.2

LVCMOS input voltage

V_{DD_DIG}= 1.65 V; I_I= –18 mA

Input current ADR_A0, REQx

(500-kΩ pulldown)

V_I= V_{DD_DIG}; V_{DD_DIG}= 1.95 V

µA

Input current RESET (1-MΩ

pullup)

Input current ADR_A0, REQx

(500-kΩ pulldown)

–2

–3

I_IL

C_I

V_I= 0 V; V_{DD_DIG}= 1.95 V

µA

Input current RESET (1-MΩ

pullup)

Input capacitance ADR_A0,

REQx, RESET

V_I= 0 V or V_{DD_DIG}

SDAH/SCLH PARAMETER (Hs-Mode)

V_{DD_DIG}= 1.65 V; I_I= –18 mA

0.1 V_{DD_DIG}< V_I< 0.9 V_{DD_DIG}

SCLH/SDAH input clamp

voltage

V_IK

–1.2

I_I

SCLH/SDAH input current

SDA/SCL input high voltage

SDAH/SCLH input low voltage

µA

V_IH

V_IL

0.7 V_{DD_DIG}

0.3 V_{DD_DIG}

Hysteresis of Schmitt-trigger

inputs

V_hys

V_OL

0.1 V_{DD_DIG}

SDAH low-level output voltage

SCLH input capacitance

SDAH input capacitance

I_OL= 3 mA, V_{DD_DIG}= 1.65 V

0.2 V_{DD_DIG}

(3)

V_I= 0 V or V_I= V_{DD_DIG}

C_I

(3)

V_I= 0 V or V_I= V_{DD_DIG}

(1) The total current consumption when no output is active is calculated by I_{DD_ANA}(off) + I_{DD_DIG}

(2) For C_L= 30 pF, the typical current for one output is 2.2 mA (see Figure 8).

(3) The I²C standard specifies a maximum C_Iof 10 pF.

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SINE-WAVE PARAMETER (MCLK_IN is sine-wave signal, C_L= 10 pF)

f_OUT

V_OS

Output frequency

MHz

Output gain level

(see Figure 17)

0.5 ≤ V_IS≤

1.2 V_PP

MCLK_IN-to-CLKx; 10 kΩ,

10 pF; ac-coupled;

–1

–0.3

_{MCLK_IN}> 1 MHz

Output voltage

V_IS= 0.5 V_PP

445

490

0.3

500

0.6

mV_PP

10 Hz to 10 MHz; f_OUT= 38.4 MHz

10 kHz to 10 MHz; f_OUT= 38.4 MHz

At offset = 1 kHz

t_jitadd(rms)Additive rms jitter⁽⁴⁾

ps_RMS

0.1

0.2

–142

–152

–157

–135

–145

–150

Additive phase noise at f_OUT

pn_add

At offset = 10 kHz

dBc/Hz

38.4 MHz⁽⁵⁾

At offset = 100 kHz

R_IN

C_IN

Input resistance

At dc level

kΩ

Input capacitance

f_{MCLK_IN}= 38.4 MHz

ELECTRICAL CHARACTERISTIC of LDO (C_OUT= 0.8 to 2.7 µF)⁽⁶⁾

V_BAT

V_LDO

Input voltage range

LDO output voltage⁽⁷⁾

2.3

5.5

1.9

2.3 V < V_BAT< 5.5 V, l_LOAD= 5 mA

2.3 V < V_BAT≤ 5.5 V, l_LOAD= 5 mA

1.72

1.8

Maximum line regulation

0.5%

ΔV_LDO

0 < I_LOAD< 5 mA, V_BAT= 2.3 V or 5.5 V;

T_J= 25°C

Maximum load regulation

0.5%

I_LOAD

I_LCL

I_LGND

I_LSHDN

Load current

C_OUT= 0.8 µF to 2.7 µF

V_LDO= 0.9 × V_LDO(TYP)

V_BAT= 3.6 V; 0 < I_LOAD< 5 mA

2.3 V < V_BAT< 5.5 V

100 Hz

µA

LDO output current limit

LDO ground pin current⁽⁸⁾

LDO shutdown current

150

0.2

µA

1 kHz

V_BAT= 2.3 V (for min)

V_BAT= 2.5 V (for typ)

V_LDO= 1.8 V

I_LOAD= 5 mA

V_ripple= 0.1 Vpp

10 kHz

100 kHz

1 MHz

10 MHz

Power-supply rejection ratio

(ripple rejection) (see Figure 20)

PSRR

Output noise voltage (see

Figure 21)

BW = 10 Hz to 100 kHz; V_LDO= 1.8 V;

I_LOAD= 5 mA

V_N

µV_RMS

(4) Additive rms jitter is the integrated rms jitter that the device adds to the signal chain. It is calculated by

- t

)

jitin(rms)

jitout(rms)

jitadd(rms)

. Specified with the supply ripple noise of 30 µV(rms) from 10 Hz to 100 kHz.

(5) Additive phase noise is the amount of phase noise that the device adds to the signal chain. It is calculated by

L_add(dB) = 10 log (10^{0.1 Lout}– 10^{0.1 Lin}).

(6) Minimum C_OUTshould be 100 nF to allow for stable LDO operation.

(7) LDO output voltage includes maximum line and load regulation.

(8) LDO ground pin current does not change over V_BAT

CDC3S04

www.ti.com

SCAS883B –OCTOBER 2009–REVISED MAY 2011

TIMING REQUIREMENTS

over operating free-air temperature range (unless otherwise noted) V_LDO= 1.8 V; C_L= 10 pF; R_L= 10 kΩ

PARAMETER

TEST CONDITIONS

TIMING PARAMETER

MIN TYP⁽¹⁾

MAX

UNIT

t_PD

t_LH

Propagation delay time

MCLK_IN-to-CLKx; f_{MCLK_IN}= 38.4 MHz

REQx-to-MCLK_REQ (wired-OR, C_L= 15 pF,

R_L= 10 kΩ);

Propagation delay time, low-to-high

CLKx on-time – REQ-to-CLKx

CLKx on-time – RESET-to-CLKx⁽³⁾

CLKx off-time – REQ-to-CLKx

CLKx on-time – V_{DD_ANA}to-CLKx

0.3

0.6

0.4

0.8

µs

f_{MCLK_IN}= 38.4 MHz; V_{VDD_ANA}is on;

V_IS= 1 V; V_OS= –1 dB (see Figure 5 and

Figure 6)

(2)

t_CLK

f_{MCLK_IN}= 38.4 MHz ; V_IS= 1 V;

µs

V_OS= –1 dB; measurement starts when

V_{DD_ANA}is 90% of 1.7 V (see Figure 7)

Pulse duration of spikes that must be

suppressed by the input filter for

RESET

Output skew⁽⁴⁾

LDO on-time⁽⁵⁾

– REQ-to-LDO;

– RESET-to-LDO

t_SP

t_sk(o)

t_LDO

100

µs

(3)

f_{MCLK_IN}= 38.4 MHz; CLK1-to-CLK4

V_LDO= 1.7 V, I_LDO= 5 mA,

2.3 V < V_BAT< 5.5 V; C_OUT= 2.7 µF

100

300

(1) All typical values are at nominal V_{DD_ANA}and V_{DD_DIG}

(2) CLK on-time is measured with valid input signal (V_IS= 1 Vpp). In case a TXCO is used, the LDO and TCXO are already on.

(3) Pulses above 500 ns are interpreted as a valid reset signal. Total time from RESET-to-CLKx is the sum of t_SP+ t_{CLK_/RESET}

(4) Output skew is calculated as the greater of the difference between the fastest and the slowest t_PLHor the difference between the fastest

and the slowest t_PHL

(5) LDO off-time depends on the discharge time of the R-C components (seeFigure 4).

PARAMETER

MIN

MAX

UNIT

SDAH/SCLH TIMING REQUIREMENTS, Hs-Mode (C_BUS= 100 pF for each I²C line; see Figure 24 and Figure 25)

f_SCLH

SCLH clock frequency

160

3.4

MHz

t_su(START)

t_h(START)

t_LOW

START setup time (SCLH high before SDAH low)

START hold time (SCLH low after SDAH low)

Low period of the SCLH clock

High period of the SCLH clock

SDAH hold time (SDAH valid after SCLH low)

SDAH setup time

t_HIGH

t_h(SDAH)

t_su(SDAH)

0⁽¹⁾

SCLH rise time

t_r

t_f

SDAH rise time

SCLH fall time

SDAH fall time

t_su(STOP)

t_SP

STOP setup time

160

Pulse duration of spikes that must be suppressed by the input filter for SDAH and

SCLH

(1) A device must internally provide a data hold time to bridge the undefined period between V_IHand V_ILof the falling edge of the SCLH

signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

PARAMETER MEASUREMENT INFORMATION

Measuring Point

10 nF

100 nF

15 K

TCXO

10 kW

10 pF

Figure 1. Input Circuit

Figure 2. Output Circuit

LDO

VLDO

TCXO

2.2 mF

10 kW

i.e. time constant(RxC) is 440 ms for 63% discharge.

Figure 3. Wired OR

Figure 4. LDO Output Circuit

CDC3S04

www.ti.com

SCAS883B –OCTOBER 2009–REVISED MAY 2011

TYPICAL CHARACTERISTICS

CLKx on Time

RESET

CLKx

90% of Final Amplitude

Figure 5. CLKx On-Time From RESET Off-to-On

REQx

CLKx on Time

CLKx

90% of Final Amplitude

Figure 6. CLKx On-Time From REQ Off-to-On

90% of 1.7 V

VDD_ANA

CLKx on Time

CLKx

90% of Final Amplitude

100 ms

200 ms

300 ms

400 ms

500 ms

600 ms

700 ms

800 ms

900 ms

Figure 7. CLKx On-Time From V_{DD_ANA}Off-to-On

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

SUPPLY CURRENT (IDD_ANA, IDD_DIG)

OUTPUT LOAD (CL) AT 38.4 MHz INPUT CLOCK

IDD_ANA / CLK1&CLK2&CLK3&CLK4

IDD_ANA / CLK1&CLK2&CLK3

IDD_ANA / CLK1&CLK2

IDD_ANA / CLK1

IDD_ANA / CLKx off

IDD_DIG

15 20

Output Load – pF

Figure 8.

SUPPLY CURRENT (IDD_ANA, IDD_DIG)

OUTPUT LOAD (CL) AT 26 MHz INPUT CLOCK

IDD_ANA / CLK1&CLK2&CLK3&CLK4

IDD_ANA / CLK1&CLK2&CLK3

IDD_ANA / CLK1&CLK2

IDD_ANA / CLK1

IDD_ANA / CLKx off

IDD_DIG

15 20

Output Load – pF

Figure 9.

SUPPLY CURRENT (IDD_ANA, IDD_DIG)

INPUT FREQUENCY (MCLK_IN)

IDD_ANA / CLK1&CLK2&CLK3&CLK4

IDD_ANA / CLK1&CLK2&CLK3

IDD_ANA / CLK1&CLK2

IDD_ANA / CLK1

IDD_ANA / CLKx off

IDD_DIG

100

Input Frequency – MHz

Figure 10.

CDC3S04

www.ti.com

SCAS883B –OCTOBER 2009–REVISED MAY 2011

TYPICAL CHARACTERISTICS (continued)

SUPPLY CURRENT (IDD_ANA, IDD_DIG)

INPUT VOLTAGE LEVEL AT 38.4 MHz INPUT CLOCK

IDD_ANA / CLK1&CLK2&CLK3&CLK4

IDD_ANA / CLK1&CLK2&CLK3

IDD_ANA / CLK1&CLK2

IDD_ANA / CLK1

IDD_ANA / CLKx off

0.5 0.6

IDD_DIG

0.7

0.8

0.9

1.0

1.1

1.2

Input Voltage Level – V_PP

Figure 11.

SUPPLY CURRENT (IDD_ANA, IDD_DIG)

INPUT VOLTAGE LEVEL AT 26 MHz INPUT CLOCK

IDD_ANA / CLK1&CLK2&CLK3&CLK4

IDD_ANA / CLK1&CLK2&CLK3

IDD_ANA / CLK1&CLK2

IDD_ANA / CLK1

IDD_ANA / CLKx off

0.5 0.6

IDD_DIG

0.7

0.8

0.9

1.0

1.1

1.2

Input Voltage Level – V_PP

Figure 12.

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

TCXO INPUT CLOCK

OUTPUT CLOCK AT 38.4 MHz

MCLK_IN input signal from TCXO

CDC3S04 output signal at CLKx

Figure 13.

TCXO INPUT CLOCK

OUTPUT CLOCK AT 26 MHz

MCLK_IN input signal from TCXO

CDC3S04 output signal at CLKx

Figure 14.

CDC3S04

www.ti.com

SCAS883B –OCTOBER 2009–REVISED MAY 2011

TYPICAL CHARACTERISTICS (continued)

SINE WAVE INPUT CLOCK

OUTPUT CLOCK AT 38.4 MHz

MCLK_IN sinusoidal input signal

CDC3S04 output signal at CLKx

Figure 15.

SINE WAVE INPUT CLOCK

OUTPUT CLOCK AT 26 MHz

MCLK_IN sinusoidal input signal

CDC3S04 output signal at CLKx

Figure 16.

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

OUTPUT GAIN

INPUT FREQUENCY (MCLK_IN)

VIS = 1 V_PP

V_{DD_ANA}= 1.8 V

-1

–2

–3

–4

–5

–6

–7

10k

100k

10M

100M

Input Frequency – Hz

Figure 17.

INPUT

OUTPUT PHASE-NOISE PERFORMANCE WITH 38.4-MHz TCXO

CLKx Output

CLKx Output Highdrive

MCLK_IN Input

Figure 18.

CDC3S04

www.ti.com

SCAS883B –OCTOBER 2009–REVISED MAY 2011

TYPICAL CHARACTERISTICS (continued)

INPUT

OUTPUT PHASE-NOISE PERFORMANCE WITH 26-MHz TCXO

CLKx Output

CLKx Output Highdrive

MCLK_IN Input

Figure 19.

LDO POWER SUPPLY REJECTION

FREQUENCY (PSRR)

REF 50.000 dB

5.000 dB/div

80 dB

75 dB

70 dB

65 dB

60 dB

55 dB

50 dB

45 dB

40 dB

START 100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

STOP 10 MHz

Figure 20.

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

LDO OUTPUT SPECTRAL NOISE DENSITY

FREQUENCY

1800

1600

1400

1200

1000

800

600

400

200

100

10k

100k

Frequency – Hz

Figure 21.

CDC3S04

www.ti.com

SCAS883B –OCTOBER 2009–REVISED MAY 2011

DETAILED DESCRIPTION

SDAH/SCLH SERIAL INTERFACE (Hs-Mode)

This section describes the SDAH/SCLH interface of the CDC3S04 device. The CDC3S04 operates as a slave

device of the two-wire serial SDAH/SCLH bus, compatible with the popular I²C specification (UM10204-I²C-bus

specification and user manual Rev. 03–19 June 2007). It operates in the high-speed mode (up to 3.4 Mbit/s) and

supports 7-bit addressing. The CDC3S04 is fully downward compatible with fast- and standard-mode (F/S)

devices for bidirectional communication in a mixed-speed bus system.

Data Protocol

The device supports byte-write and byte-read operations only. There is no block-write or block-read operation

supported; therefore, no command code byte is needed.

When a byte has been sent, it is written into the internal register and is immediately effective.

Slave Receiver Address (7 bits)

Device

A0⁽¹⁾

R/W

1/0

CDC3S04

(1) Address bit A0 is selectable by the ADR_A0 input (pin D1). This allows addressing of two devices

connected to the same I²C bus. The default value is 0, set by an internal pulldown resistor.

Byte-Write Programming Sequence

F/S-Mode

Master Code

Hs-Mode

Slave Address

Data

R/W

0000 1XXX

(Hs-Mode Master Code)

0 (Write)

Data Transferred

(n Bytes + Acknowledge)

A = Acknowledge (SDAH LOW)

A = Acknowledge (SDAH HIGH)

S = START Condition

From Master to Slave

From Slave to Master

P = STOP Condition

Figure 22. Byte-Write Protocol

Byte-Read Programming Sequence

F/S-Mode

Hs-Mode

Master Code

Slave Address

Data

R/W

0000 1XXX

(Hs-Mode Master Code)

1 (Read)

Data Transferred

(n Bytes + Acknowledge)

A = Acknowledge (SDAH LOW)

A = Acknowledge (SDAH HIGH)

S = START Condition

From Master to Slave

From Slave to Master

P = STOP Condition

Figure 23. Byte-Read Protocol

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

t_f(DA)

t_r(DA)

SDAH

t_su(STA)

t_h(DAT)

t_h(STA)

t_su(DAT)

t_su(STO)

SCLH

(1)

t_(Low)

t_(High)

t_r(CL)

t_(Low)

t_r(CL1)

(1)

t_f(CL)

t_r(CL1)

t_(High)

= MCS current source pull-up

= Rp resistor pull-up

T0451-01

(1) First rising edge of the SCLH signal after Sr and after each acknowledge bit.

Figure 24. Definition of Timing for a Complete Hs-Mode Transfer

The following diagram shows how the CDC3S04 clock buffer is connected to the SDAH/SCLH serial interface

bus. Multiple devices can be connected to the bus, but the speed may need to be reduced (3.4 MHz is the

maximum) if many devices are connected.

Note that the pullup resistors (R_P) depend on the supply voltage, bus capacitance, and number of connected

devices. For more details, see the I²C bus specification.

CDC3S04

R_p

Master

SDAH

Slave

SCLH

C_BUSC_BUS

Figure 25. SDAH/SCLH Hardware Interface

SDAH/SCLH Configuration Registers

The output stages are user configurable. Table 3 explains the programmable functions of the CDC3S04.

CDC3S04

www.ti.com

Offset

SCAS883B –OCTOBER 2009–REVISED MAY 2011

Table 3. Configuration Register (Shaded Cells Marks Power-Up/Default Setting)

(3)

BIT⁽¹⁾

Acronym

REQ4INT

REQ3INT

REQ2INT

REQ1INT

REQ4POL

REQ3POL

REQ2POL

REQ1POL

Default⁽²⁾

RESET

Description

CLK4 off/on⁽⁴⁾

CLK3 off/on⁽⁴⁾

CLK2 off/on⁽⁴⁾

Type

–

Off

–

Off

–

CLK1 off/on⁽⁴⁾

Off

00h

R/W

Selects polarity of REQ4

Selects polarity of REQ3

Selects polarity of REQ2

Selects polarity of REQ1

Active-low

Active-high

–

Defines if REQ4 is used to decode

MCLK_REQ

MREQ4

MREQ3

MREQ2

–

Defines if REQ3 is used to decode

MCLK_REQ

Not used for

decoding

Used for

decoding

Defines if REQ2 is used to decode

MCLK_REQ

01h

R/W

Defines if REQ1 is used to decode

MCLK_REQ

MREQ1

MCLKOUT1

Selects MCLK_REQ output type

00 = wired-OR (default setting)

01 = wired-AND

00b

–

MCLKOUT0

1x = push-pull

0–1

–

Reserved

MREQCTRL1

MCLK_REQ generation (see Figure 27)

0x = decoder controlled (default setting)

10 = low

MREQCTRL0

LDOEN1

11 = high

Switches LDO on or off:

00 = LDO is on (default setting)

01 = LDO is off

00b

–

LDOEN0

02h

R/W

1x = decoder controlled (see Figure 27)

REQ4PRIO

REQ3PRIO

REQ2PRIO

REQ1PRIO

HIGHDRIVE4

HIGHDRIVE3

HIGHDRIVE2

HIGHDRIVE1

–

Defines external vs internal REQ4 priority

Defines external vs internal REQ3 priority

Defines external vs internal REQ2 priority

Defines external vs internal REQ1 priority

Enables high-drive capability CLK4

Enables high-drive capability CLK3

Enables high-drive capability CLK2

Enables high-drive capability CLK1

Reserved

REQ4

REQ3

REQ2

REQ1

Typical

REQ4INT

REQ3INT

REQ2INT

REQ1INT

High

–

High

03h

–

High

R/W

–

High

0–3

–

04h–Bh⁽⁵⁾

–

Reserved

(1) All data is transferred with the MSB first.

(2) A device reset to default condition is initiated by a V_{DD_DIG}power-up sequence.

(3) "–" means that dedicated bits do not change at RESET.

(4) Inactive as long as the REQxPRIO bit is low, external REQx pins are valid (see Figure 26)

(5) Writing data beyond 03h may affect device function.

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

REQ1PRIO

REQ1

REQ1POL

‘1’

XNOR

REQ1

CLK1 enabled

REQ1INT

‘1’

active-high

REQ2PRIO

REQ2

signal from externel pin

REQ2POL

‘1’

‘x’

REQ2

CLK2

enabled if REQ2=’1'

disabled if REQ2=’0'

REQ2INT

internal signals or

active-high

bits from configuration register

REQ3PRIO

REQ3

REQ3POL

‘1’

XNOR

‘x’

REQ3

CLK3

enabled if REQ3=’1'

disabled if REQ3=’0'

REQ3INT

active-high

REQ4PRIO

REQ4

REQ4POL

‘1’

REQ4

CLK4 enabled

REQ4INT

‘1’

active-high

Figure 26. Clock Output Enable Signal

(Shaded Line Marks Power-Up/Default Setting)

signal from/to

externel pin

REQ1PRIO

REQ1

MREQ1

‘1’

REQ1POL

‘1’

internal signals or

bits from configuration register

XNOR

AND

REQ1

REQ1INT

‘1’

active-high

REQ2PRIO

REQ2

REQ2POL

‘1’

MREQ2

‘1’

LDOEN1

LDOEN0

‘0’

REQ2

‘x’

‘1’

REQ2INT

LDO is

enabled

active-high

REQ3PRIO

REQ3

MREQ3

‘1’

REQ3POL

‘1’

‘x’

REQ3

MCLK_REQ

MREQ

CTRL0

REQ3INT

active-high

REQ4PRIO

REQ4

MREQ4

‘1’

REQ4POL

‘1’

MREQCTRL1

REQ4

REQ4INT

‘1’

active-high

Figure 27. Decoding Scheme for MCLK_REQ and LDOEN

(Shaded Line Marks Power-Up/Default Setting)

CDC3S04

www.ti.com

SCAS883B –OCTOBER 2009–REVISED MAY 2011

APPLICATION INFORMATION

VDD_DIG VDD_ANA

Battery

VLDO

LDO

VBAT

REQ1

CLK1

Peripheral 1

Peripheral 2

Peripheral 3

Peripheral 4

TCXO

38.4MHz

REQ2

CLK2

MCLK_IN

MCLK_REQ

REQ3

CLK3

RESET

REQ4

CLK4

I²C (Hs-mode)

GND_DIG

GND_ANA

Figure 28. Clock Distribution Scheme

CDC3S04

SCAS883B –OCTOBER 2009–REVISED MAY 2011

www.ti.com

REVISION HISTORY

Changes from Original (October 2009) to Revision A

Page

•

Changed the format on page 1 (moved 2 paragraphs from page 2 to page 1) .................................................................... 1

Changed the X axis from 0.1us to 100us....900us ............................................................................................................... 9

Changed Offset 00h Bit 4 Default value from 0h to 1b ....................................................................................................... 19

Changes from Revision A (July 2010) to Revision B

Page

•

Changed Table 3 "Offset" values listed in "Default" and "RESET" columns from "h" to "b". ............................................. 19

PACKAGE OPTION ADDENDUM

www.ti.com

12-Apr-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

CDC3S04YFFR

ACTIVE

DSBGA

YFF

3000

Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Nov-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDC3S04YFFR

DSBGA

YFF

3000

180.0

8.4

1.63

2.08

0.69

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Nov-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

DSBGA YFF 20

SPQ

Length (mm) Width (mm) Height (mm)

210.0 185.0 35.0

CDC3S04YFFR

3000

Pack Materials-Page 2

D: Max = 1.99 mm, Min = 1.93 mm

E: Max = 1.59 mm, Min = 1.53 mm

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Medical

Logic

Security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CDC3S04YFFR相关文章

配单直通车

柒号芯城电子商务（深圳）有限公司服务专线: 0755-83209937 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

CDC3S04YFFR产品参数

型号:	CDC3S04YFFR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	BGA
包装说明：	VFBGA, BGA20,4X5,16
针数：	20
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	1.74
系列：	CDC
输入调节：	STANDARD
JESD-30 代码：	R-XBGA-B20
JESD-609代码：	e1
长度：	2.305 mm
负载电容（CL）：	10 pF
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
最大I（ol）：	0.003 A
湿度敏感等级：	1
功能数量：	1
反相输出次数：
端子数量：	20
实输出次数：	4
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED
封装代码：	VFBGA
封装等效代码：	BGA20,4X5,16
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
包装方法：	TR
峰值回流温度（摄氏度）：	260
电源：	1.8 V
Prop。Delay @ Nom-Sup：	3 ns
传播延迟（tpd）：	3 ns
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.05 ns
座面最大高度：	0.625 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	1.95 V
最小供电电压 (Vsup)：	1.65 V
标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL
端子节距：	0.4 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	1.905 mm
最小 fmax：	52 MHz
Base Number Matches：	1

电子百科

产品导航

产品型号CDC3S04YFFR的概述

产品型号CDC3S04YFFR的Datasheet PDF文件预览

CDC3S04YFFR相关产品

CDC3S04YFFR相关文章

IC37:专业IC行业平台